Semiconductor device, memory device, and electronic apparatus

Abstract

Provided is a semiconductor device having a high storage density. The semiconductor device includes a first layer and a second layer over the first layer. The first layer includes first to fourth conductors, first to fifth insulators, and a first semiconductor, and the second layer includes fifth to seventh conductors, sixth and seventh insulators, and a second semiconductor. A first insulator, a second conductor, a second insulator, and a third conductor are sequentially formed on the first conductor, and each of the first insulator, the second conductor, the second insulator, and the third conductor is provided with a first opening with the first conductor as a bottom surface. A first semiconductor, a fourth insulator and a fourth conductor are sequentially formed in the first opening. The third insulator is located on the side surface of the third conductor and the top surface of the second insulator. The fifth conductor is located on the top surface of the fourth conductor and the top surface of the fifth insulator. A sixth insulator and a sixth conductor are sequentially formed on the fifth conductor, and each of the sixth insulator and the sixth conductor is provided with a second opening with the fifth conductor as the bottom surface. A second semiconductor, a seventh insulator and a seventh conductor are sequentially formed in the second opening.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device, a storage device, and an electronic device.

[0002] In addition, one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a working method or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, a product or a composition. Therefore, specifically, as examples of the technical field of one embodiment of the present invention disclosed in this specification, semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, storage devices, signal processing devices, sensors, processors, electronic devices, systems, their driving methods, their manufacturing methods or their inspection methods can be cited. Background Art

[0003] In recent years, with the increasing amount of data used, there has been a demand for storage devices with larger storage capacities. To increase storage capacity per unit area, stacking memory cells, as in 3D NAND memory devices, is effective (see Patent Documents 1 to 3). By stacking memory cells, the storage capacity per unit area can be increased by the number of stacked memory cells. [Prior technical literature] [Patent Document]

[0004] [Patent Document 1] U.S. Patent Application Publication No. 2011 / 0065270 [Patent Document 2] U.S. Patent Application Publication No. 2016 / 0149004 [Patent Document 3] U.S. Patent Application Publication No. 2013 / 0069052 Summary of the Invention Technical problem to be solved by the invention

[0005] To create memory devices with large storage capacities, memory cells are being miniaturized. While miniaturization of memory cells is possible by reducing the size of capacitors or eliminating them, this also reduces the electrostatic capacitance of the memory cell, making it difficult to write, retain, and read data. Furthermore, low electrostatic capacitance makes it susceptible to noise, causing the value of the stored data to fluctuate.

[0006] One object of one embodiment of the present invention is to provide a semiconductor device with a small circuit area. Another object of one embodiment of the present invention is to provide a semiconductor device with a large storage capacity. Another object of one embodiment of the present invention is to provide a semiconductor device with a high storage density. Another object of one embodiment of the present invention is to provide a novel semiconductor device, etc. Another object of one embodiment of the present invention is to provide a storage device including the above-mentioned semiconductor device. Another object of one embodiment of the present invention is to provide an electronic device including the above-mentioned storage device.

[0007] Note that the purpose of one embodiment of the present invention is not limited to the purpose described above. The purpose described above does not preclude the existence of other purposes. In addition, other purposes are purposes not mentioned above but will be described in the following description. Those skilled in the art can derive and appropriately extract the purposes not mentioned above from the description in the specification or drawings, etc. In addition, one embodiment of the present invention achieves at least one of the above-mentioned purposes and other purposes. In addition, one embodiment of the present invention does not necessarily achieve all of the above-mentioned purposes and other purposes. Means of solving technical problems

[0008] One embodiment of the present invention provides a semiconductor device for the above purpose, comprising two stacked transistors having gate electrodes and channel formation regions arranged in a height direction. This transistor can have a smaller installation area than a planar transistor (with a channel formation region arranged in a planar direction).

[0009] Furthermore, since the gate electrode is arranged along the height direction, a capacitor can be formed by providing a conductive layer around the opening. In other words, the two transistors and the capacitor overlap with each other.

[0010] Hereinafter, a typical configuration example of a processing device according to one embodiment of the present invention will be described. (1) One embodiment of the present invention is a semiconductor device including a first layer having a first opening and a second layer having a second opening, wherein the second layer is located above the first layer.

[0012] The first layer includes a first conductor, a second conductor, a third conductor, a fourth conductor, a first insulator, a second insulator, a third insulator, a fourth insulator, a fifth insulator, and a first semiconductor. Furthermore, the second layer includes a fifth conductor, a sixth conductor, a seventh conductor, a sixth insulator, a seventh insulator, and a second semiconductor.

[0013] The first opening is located above the first conductor, the first insulator is located on the top surface of the first conductor and on the side surfaces outside the first opening, the second conductor is located on the top surface of the first insulator and on the side surfaces outside the first opening, the second insulator is located on the top surface of the second conductor and on the side surfaces outside the first opening, and the third conductor is located on the top surface of the second insulator and on the side surfaces outside the first opening. Furthermore, the third insulator is located on the top surface of the second insulator and on the side surfaces of the third conductor. Furthermore, the first semiconductor is located within the first opening, on the top surface of the first conductor, on the side surfaces of the first insulator, on the side surfaces of the second conductor, on the side surfaces of the second insulator, and on the side surfaces of the third conductor. The fourth insulator is located on the top surface of the third insulator, on the top surface of the third conductor, and on the top surface of the first semiconductor. The fourth conductor is located within the first opening on the top surface of the fourth insulator and above the first opening. Furthermore, the fifth insulator is located above the fourth insulator and on the side surfaces of the fourth conductor, and the fifth conductor is located on the top surface of the fourth conductor and on the top surface of the fifth insulator.

[0014] The second opening is located above the fifth conductor. Furthermore, the sixth insulator is located on the top surface of the fifth insulator, the top surface of the fifth conductor, and the side surfaces outside the second opening, and the sixth conductor is located on the top surface of the sixth insulator and the side surfaces outside the second opening. Furthermore, the second semiconductor is located within the second opening on the top surface of the fifth conductor, the side surfaces of the sixth insulator, and the side surfaces of the sixth conductor, and outside the second opening on the top surface of the sixth conductor. The seventh insulator is located on the top surface of the sixth insulator, the top surface of the sixth conductor, and the top surface of the second semiconductor, and the seventh conductor is located on the top surface of the seventh insulator including the interior of the second opening. (2) Another embodiment of the present invention is a semiconductor device having a structure different from that of (1) above, including a first layer having a first opening and a second layer having a second opening. The second layer is located above the first layer.

[0016] The first layer includes a first conductor, a second conductor, a third conductor, a fourth conductor, a first insulator, a second insulator, a third insulator, a fourth insulator, a fifth insulator, and a first semiconductor. Furthermore, the second layer includes a sixth conductor, a seventh conductor, a sixth insulator, a seventh insulator, and a second semiconductor.

[0017] The first opening is located above the first conductor, the first insulator is located on the top surface of the first conductor and on the side surfaces outside the first opening, the second conductor is located on the top surface of the first insulator and on the side surfaces outside the first opening, the second insulator is located on the top surface of the second conductor and on the side surfaces outside the first opening, and the third conductor is located on the top surface of the second insulator and on the side surfaces outside the first opening. Furthermore, the third insulator is located on the top surface of the second insulator and on the side surfaces of the third conductor. Furthermore, the first semiconductor is located within the first opening, on the top surface of the first conductor, on the side surfaces of the first insulator, on the side surfaces of the second conductor, on the side surfaces of the second insulator, and on the side surfaces of the third conductor. The fourth insulator is located on the top surface of the third insulator, on the top surface of the third conductor, and on the top surface of the first semiconductor. The fourth conductor is located within the first opening on the top surface of the fourth insulator and above the first opening. Furthermore, the fifth insulator is located above the fourth insulator and on the side surfaces of the fourth conductor.

[0018] The second opening is located above the fourth conductor. Furthermore, the sixth insulator is located on the top surface of the fifth insulator, the top surface of the fourth conductor, and the side surface outside the second opening, and the sixth conductor is located on the top surface of the sixth insulator and the side surface outside the second opening. Furthermore, the second semiconductor is located within the second opening on the top surface of the fourth conductor, the side surface of the sixth insulator, and the side surface of the sixth conductor, and outside the second opening on the top surface of the sixth conductor. The seventh insulator is located on the top surface of the sixth insulator, the top surface of the sixth conductor, and the top surface of the second semiconductor, and the seventh conductor is located on the top surface of the seventh insulator including the interior of the second opening. (3) In the above (1) or (2), one embodiment of the present invention may have a structure in which each of the first semiconductor and the second semiconductor contains one or more selected from indium, zinc, and element M.

[0020] The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium and antimony. (4) In addition, in the above (3), one embodiment of the present invention may have a structure in which the taper angle of the side surface of the second opening is not less than 45° and not more than 90°. (5) In the above (4), one embodiment of the present invention may have a structure in which the first conductor and the sixth conductor extend in the first direction, and the second conductor, the third conductor, and the seventh conductor extend in the second direction. (6) In addition, one embodiment of the present invention is a memory device including the semiconductor device described in any one of (1) to (5) above and a driver circuit. The driver circuit is located below the semiconductor device. The driver circuit is formed on a semiconductor substrate containing silicon. The driver circuit includes a transistor having a channel formation region containing silicon. (7) Furthermore, one embodiment of the present invention is an electronic device including the storage device described in (6) above and a housing. Effects of the Invention

[0025] As described above, by adopting a structure in which two transistors and the capacitor overlap each other, the installation area can be reduced. This can improve storage density. In addition, by adopting this structure, the capacitor can be installed without increasing the circuit area.

[0026] According to one embodiment of the present invention, a semiconductor device with a small circuit area can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with a large storage capacity can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with a high storage density can be provided. Furthermore, according to one embodiment of the present invention, a novel semiconductor device can be provided. Furthermore, according to one embodiment of the present invention, a storage device including the aforementioned semiconductor device can be provided. Furthermore, according to one embodiment of the present invention, an electronic device including the aforementioned storage device can be provided.

[0027] Note that the effects of one embodiment of the present invention are not limited to the effects described above. The effects described above do not preclude the existence of other effects. Furthermore, other effects are effects not mentioned above but will be described below. Those skilled in the art can derive and appropriately extract effects not mentioned above from the description in the specification or drawings. Furthermore, one embodiment of the present invention may have at least one of the effects described above and other effects. Therefore, depending on the circumstances, one embodiment of the present invention may not have the effects described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figures 1A to 1C is a circuit diagram showing an example of a semiconductor device. Figure 2A is a schematic plan view showing a structural example of a semiconductor device, Figure 2B and Figure 2C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 3A and Figure 3B is a block diagram showing an example of a storage device. Figure 4A and Figure 4B 2 is a schematic plan view showing an example of a cell array. Figure 5A and Figure 5B 2 is a schematic plan view showing an example of a cell array. Figure 6A and Figure 6B 2 is a schematic plan view showing an example of a cell array. Figure 7A and Figure 7B 2 is a schematic plan view showing an example of a cell array. Figure 8A and Figure 8B is a timing chart showing an operation example of the semiconductor device. Figure 9A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 9B and Figure 9C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 10A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 10B and Figure 10C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 11A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 11B and Figure 11C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 12A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 12B and Figure 12C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 13A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 13B and Figure 13C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 14A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 14B and Figure 14C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 15A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 15B and Figure 15C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 16A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 16B and Figure 16C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 17A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 17B and Figure 17C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 18A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 18B and Figure 18C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 19A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 19B and Figure 19C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 20A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 20B and Figure 20C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 21A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 21B and Figure 21C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 22A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 22B and Figure 22C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 23A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 23B and Figure 23C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 24A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 24B and Figure 24C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 25A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 25B and Figure 25C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 26Ais a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 26B and Figure 26C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 27A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 27B and Figure 27C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 28A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 28B and Figure 28C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 29A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 29B and Figure 29C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 30A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 30B and Figure 30C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 31A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 31B and Figure 31C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 32A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 32B and Figure 32C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 33A is a schematic plan view showing a structural example of a semiconductor device, Figure 33B and Figure 33C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 34A is a schematic plan view showing a structural example of a semiconductor device, Figure 34B and Figure 34C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 35A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 35B and Figure 35C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 36A is a schematic plan view showing a structural example of a semiconductor device, Figure 36B and Figure 36C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 37A is a schematic plan view showing a structural example of a semiconductor device, Figure 37B and Figure 37C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 38A is a schematic plan view showing a structural example of a semiconductor device, Figure 38B and Figure 38C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 39A is a schematic plan view showing a structural example of a semiconductor device, Figure 39B and Figure 39C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 40A is a schematic plan view showing a structural example of a semiconductor device, Figure 40B and Figure 40C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 41A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 41B and Figure 41C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 42A is a schematic plan view showing a structural example of a semiconductor device, Figure 42B and Figure 42C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 43A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 43B and Figure 43C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 44A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 44B and Figure 44C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 45A is a schematic plan view showing a structural example of a semiconductor device, Figure 45B and Figure 45C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 46A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 46B and Figure 46C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 47A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 47B and Figure 47C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 48A is a schematic plan view showing a structural example of a semiconductor device, Figure 48B and Figure 48C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 49A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 49B and Figure 49C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 50A is a schematic plan view showing a structural example of a semiconductor device, Figure 50B and Figure 50C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 51A is a schematic plan view showing a structural example of a semiconductor device, Figure 51B and Figure 51C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 52A is a schematic plan view showing a structural example of a semiconductor device, Figure 52B and Figure 52C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 53A is a schematic plan view showing a structural example of a semiconductor device, Figure 53B and Figure 53C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 54A is a schematic plan view showing a structural example of a semiconductor device, Figure 54B and Figure 54C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 55A is a schematic plan view showing a structural example of a semiconductor device, Figure 55B and Figure 55C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 56A is a schematic plan view showing a structural example of a semiconductor device, Figure 56B and Figure 56C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 57A is a schematic plan view showing a structural example of a semiconductor device, Figure 57B and Figure 57C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 58A is a schematic plan view showing a structural example of a semiconductor device, Figure 58B and Figure 58C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 59A is a schematic plan view showing a structural example of a semiconductor device, Figure 59B and Figure 59C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 60A is a schematic plan view showing a structural example of a semiconductor device, Figure 60B and Figure 60C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 61A is a schematic plan view showing a structural example of a semiconductor device, Figure 61B and Figure 61C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 62A is a schematic plan view showing a structural example of a semiconductor device, Figure 62B and Figure 62C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 63A is a schematic plan view showing a structural example of a semiconductor device, Figure 63B and Figure 63C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 64A is a schematic plan view showing a structural example of a semiconductor device, Figure 64B and Figure 64C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 65A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 65B and Figure 65C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 66A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 66B and Figure 66C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 67A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 67B and Figure 67C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 68A is a schematic plan view showing a structural example of a semiconductor device, Figure 68B and Figure 68C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 69A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 69B and Figure 69C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 70A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 70B and Figure 70C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 71A is a schematic plan view showing a structural example of a semiconductor device, Figure 71B and Figure 71C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 72A is a schematic plan view showing a structural example of a semiconductor device, Figure 72B and Figure 72C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 73A is a schematic plan view showing a structural example of a semiconductor device, Figure 73B and Figure 73C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 74 2 is a schematic plan view showing an example of a cell array. Figure 75A is a schematic plan view showing a structural example of a semiconductor device, Figure 75B and Figure 75C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 76 2 is a schematic plan view showing an example of a cell array. Figure 77A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 77B and Figure 77C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 78A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 78B and Figure 78C1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 79A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, Figure 79B and Figure 79C 1 is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device. Figure 80A is a schematic plan view showing a structural example of a semiconductor device, Figure 80B and Figure 80C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 81A is a schematic plan view showing a structural example of a semiconductor device, Figure 81B and Figure 81C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 82A is a plan view schematically showing an example of a cell array, Figure 82B is a perspective schematic diagram showing a structural example of a transistor. Figure 83A is a schematic plan view showing a structural example of a semiconductor device, Figure 83B and Figure 83C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 84 2 is a schematic plan view showing an example of a cell array. Figure 85A is a schematic plan view showing a structural example of a semiconductor device, Figure 85B and Figure 85C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 86A is a plan view schematically showing an example of a cell array, Figure 86B is a perspective schematic diagram showing a structural example of a transistor. Figure 87A and Figure 87B 2 is a schematic plan view showing an example of a cell array. Figures 88A to 88C is a circuit diagram showing an example of a semiconductor device. Figure 89A is a schematic plan view showing a structural example of a semiconductor device, Figure 89B and Figure 89C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 90A and Figure 90B is a block diagram showing an example of a storage device. Figure 91A is a schematic plan view showing a structural example of a semiconductor device, Figure 91B and Figure 91C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 92A is a schematic plan view showing a structural example of a semiconductor device, Figure 92B and Figure 92C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 93A is a schematic plan view showing a structural example of a semiconductor device, Figure 93B and Figure 93C is a schematic cross-sectional view illustrating a structural example of a semiconductor device. Figure 94A is a perspective view illustrating an example of the structure of a storage device, Figure 94B This is a block diagram illustrating a structural example of a semiconductor device. Figure 95 This is a block diagram illustrating a structural example of a storage device. Figure 96 A diagram illustrating a configuration example of a storage device. Figure 97A and Figure 97B This is a diagram showing an example of an electronic component. Figure 98A and Figure 98B is a diagram showing an example of an electronic device, Figures 98C to 98E This is a diagram showing an example of a mainframe computer. Figure 99 This is a diagram showing an example of space equipment. Figure 100 This diagram shows an example of a secondary storage system that can be used in a data center. Figure 101A is a perspective schematic diagram showing a structural example of a display device, Figure 101B is a block diagram showing a structural example of a display device. Figure 102 is a circuit diagram illustrating a structural example of a pixel circuit included in a display device. Figure 103 It is a perspective schematic diagram showing a structural example of a stacked structure of a display device. Figures 104A to 104I It is a perspective view showing an example of an electronic device. Implementation Method

[0029] In this specification, etc., a semiconductor device refers to a device that utilizes semiconductor characteristics, a circuit including a semiconductor element (for example, a transistor, a diode, a photodiode), and a device including the circuit. In addition, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. As an example of a semiconductor device, an integrated circuit can be cited. In addition, as an example of a semiconductor device, a chip having an integrated circuit and an electronic component in which a chip is housed in a package can be cited. In addition, for example, a storage device, a display device, a light-emitting device, a lighting device, and an electronic device are sometimes themselves semiconductor devices, or sometimes include a semiconductor device.

[0030] In this specification, the phrase "X and Y are connected" indicates that the following are disclosed: X and Y are electrically connected; X and Y are functionally connected; and X and Y are directly connected. Therefore, the connection relationships are not limited to those shown in the drawings or text; other connection relationships are also within the scope of the drawings or text. X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, or layers).

[0031] As an example of electrically connecting X and Y, one or more elements capable of electrically connecting X and Y (e.g., switches, transistors, capacitors, inductors, resistors, diodes, display devices, light-emitting devices, loads, etc.) may be connected between X and Y. Furthermore, a switch has the function of controlling whether to turn it on or off. In other words, whether current flows is controlled by placing the switch in a conductive state (on) or a non-conductive state (off).

[0032] Furthermore, if both components and power lines (e.g., VDD (high power supply potential), VSS (low power supply potential), GND (ground potential), or wiring supplying a desired potential) are located between X and Y, then X and Y cannot be said to be electrically connected. Furthermore, if only a power line is located between X and Y, and no other components are located between them, then X and Y can be said to be directly connected. Therefore, even if only a power line is located between X and Y, it can be said that "X and Y are electrically connected." However, if both components and power lines are located between X and Y, it can be said that X is electrically connected to the power line (through the components) and that Y is electrically connected to the power line, rather than that X and Y are electrically connected. Furthermore, if the gate and source of a transistor are located between X and Y, then X and Y cannot be said to be electrically connected. Furthermore, if the gate and drain of a transistor are located between X and Y, then X and Y cannot be said to be electrically connected. That is, with respect to a transistor, if the drain and source of the transistor are located between X and Y, then X and Y can be said to be electrically connected. Furthermore, when a capacitor is placed between X and Y, it may be said that X and Y are electrically connected, but it may not be said that X and Y are electrically connected. For example, in the configuration of a digital circuit or a logic circuit, when a capacitor is placed between X and Y, it may not be said that X and Y are electrically connected. On the other hand, in the configuration of an analog circuit, for example, when a capacitor is placed between X and Y, it may be said that X and Y are electrically connected.

[0033] As an example of a case where X and Y are functionally connected, one or more circuits capable of functionally connecting X and Y (e.g., logic circuits (e.g., inverters, NAND circuits, and NOR circuits), signal conversion circuits (e.g., digital-to-analog conversion circuits, analog-to-digital conversion circuits, and gamma correction circuits), potential level conversion circuits (e.g., power supply circuits such as boost circuits and buck circuits, and level shift circuits that change the potential level of a signal), voltage sources, current sources, switching circuits, amplifier circuits (e.g., circuits that increase signal amplitude or current, operational amplifiers, differential amplifiers, source follower circuits, and buffer circuits), signal generation circuits, storage circuits, and control circuits) may be connected between X and Y. Note that, for example, even if other circuits are interposed between X and Y, when a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0034] Alternatively, for example, it can be expressed as “X, Y, the source of the transistor (sometimes referred to as one of the first and second terminals), and the drain of the transistor (sometimes referred to as the other of the first and second terminals) are electrically connected to each other, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in this order.” Alternatively, it can be expressed as “The source of the transistor is electrically connected to X, the drain of the transistor is electrically connected to Y, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in this order.” Alternatively, it can be expressed as “X is electrically connected to Y via the source and drain of the transistor, and X, the source of the transistor, the drain of the transistor, and Y are connected to each other in this order.” By specifying the connection order in the circuit structure using the same expression method as these examples, the source and drain of the transistor can be distinguished, thereby determining the technical scope. Note that this expression method is only an example and is not limited to the above-mentioned expression method. Here, X and Y are objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films or layers, etc.).

[0035] Furthermore, even when independent components are electrically connected on a circuit diagram, a single component may sometimes perform the functions of multiple components. For example, when a portion of a wiring serves as an electrode, a single conductive film may perform both wiring and electrode functions. Therefore, the term "electrically connected" in this specification also encompasses situations where a single conductive film performs the functions of multiple components.

[0036] In this specification, etc., a "resistor" may be, for example, a circuit element having a resistance value higher than 0Ω or a wiring having a resistance value higher than 0Ω. Therefore, in this specification, etc., a "resistor" includes a wiring having a resistance value, a transistor, a diode, or a coil through which current flows between a source and a drain. Therefore, a "resistor" may sometimes be referred to as a "resistor," a "load," or a "region having a resistance value." In contrast, a "resistor," a "load," or a "region having a resistance value" may sometimes be referred to as a "resistor." As a resistance value, for example, it is preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. In addition, for example, it may be 1 Ω or more and 1×10 9 Ω or less.

[0037] In this specification, etc., a "capacitor" may be, for example, a circuit element having an electrostatic capacitance value higher than 0F, a region of wiring having an electrostatic capacitance value higher than 0F, a parasitic capacitance, or a gate capacitance of a transistor. In addition, a "capacitor", "parasitic capacitance" or "gate capacitance" may sometimes be referred to as a "capacitor". In contrast, a "capacitor" may sometimes be referred to as a "capacitor", "parasitic capacitance" or "gate capacitance". In addition, a "capacitor" (a "capacitor" having three or more terminals) includes an insulator and a pair of conductors that clamp the insulator. Thus, the "pair of conductors" of a "capacitor" may be referred to as a "pair of electrodes", "a pair of conductive regions", "a pair of regions" or "a pair of terminals". In addition, "one of a pair of terminals" and "the other of a pair of terminals" are sometimes referred to as a first terminal and a second terminal, respectively. In addition, the electrostatic capacitance value may be, for example, greater than 0.05fF and less than 10pF. In addition, for example, it may also be greater than 1pF and less than 10μF.

[0038] In this specification, etc., a transistor includes three terminals: a gate, a source, and a drain. The gate is used as a control terminal to control the conduction state of the transistor. The two terminals used as the source or drain are the input and output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel or p-channel) and the level of the potential applied to the three terminals of the transistor, one of the two input and output terminals is used as the source and the other as the drain. Therefore, in this specification, etc., the source and drain can be interchanged. In this specification, etc., when describing the connection relationship of the transistor, the expressions "one of the source and drain" (first electrode or first terminal) and "the other of the source and drain" (second electrode or second terminal) are used. In addition, depending on the structure of the transistor, a back gate is sometimes included in addition to the above three terminals. In this case, in this specification, etc., one of the gate and back gate of the transistor is sometimes referred to as the first gate, and the other of the gate and back gate of the transistor is sometimes referred to as the second gate. Moreover, in the same transistor, "gate" and "back gate" can sometimes be interchanged. In addition, when a transistor includes three or more gates, each gate may be referred to as a first gate, a second gate, a third gate, etc. in this specification and the like.

[0039] For example, in this specification, a multi-gate structure transistor having two or more gate electrodes can be used as an example of a transistor. When a multi-gate structure is adopted, since the channel forming regions are connected in series, a structure in which multiple transistors are connected in series is formed. Therefore, by adopting a multi-gate structure, the off-state current can be reduced, and the voltage resistance of the transistor can be improved (improving reliability). Alternatively, by utilizing a multi-gate structure, when the transistor operates in the saturation region, even if the voltage between the drain and the source changes, the change in the current between the drain and the source is not too large, so that a voltage-current characteristic with a flat tilt angle can be obtained. When utilizing a voltage-current characteristic with a flat tilt angle, an ideal current source circuit or an active load with an extremely high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with good characteristics can be realized.

[0040] In addition, a circuit diagram showing a circuit element sometimes includes a case where the circuit element includes multiple circuit elements. For example, a circuit diagram showing a resistor includes a case where two or more resistors are connected in series. In addition, for example, a circuit diagram showing a capacitor includes a case where two or more capacitors are connected in parallel. In addition, for example, a circuit diagram showing a transistor includes a case where two or more transistors are connected in series and the gates of each transistor are electrically connected to each other. Similarly, for example, a circuit diagram showing a switch includes a case where the switch includes two or more transistors, and the two or more transistors are electrically connected in series or in parallel and the gates of each transistor are electrically connected to each other.

[0041] In this specification, a node may also be referred to as a terminal, wiring, electrode, conductive layer, conductor, or impurity region depending on the circuit structure or device structure. Terminals, wiring, etc. may also be referred to as nodes.

[0042] In this specification, the terms "voltage" and "potential" may be used interchangeably as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, when the reference potential is ground potential (e.g., ground potential), "voltage" may also be referred to as "potential." Ground potential does not necessarily mean 0V. Furthermore, potential is relative; changes in the reference potential also cause changes in the potential supplied to wiring, applied to circuits, and output from circuits.

[0043] In this specification and other documents, the terms "high-level potential" and "low-level potential" do not necessarily refer to specific potentials. For example, even if two wirings are described as "wirings for supplying a high-level potential," the high-level potentials supplied by the two wirings may be different. Similarly, even if two wirings are described as "wirings for supplying a low-level potential," the low-level potentials supplied by the two wirings may be different.

[0044] In addition, "current" refers to the migration phenomenon of charge (conduction). For example, the description of "conduction occurs in a positively charged body" can be replaced by the description of "conduction occurs in a negatively charged body in the opposite direction". Therefore, in this specification, etc., unless otherwise specified, "current" refers to the migration phenomenon of charge (conduction) when carriers migrate. Here, as carriers, for example, electrons, holes, anions, cations, complex ions, etc. can be cited. The carriers are different depending on the system through which the current flows (for example, semiconductors, metals, electrolytes, and vacuum). In addition, the "direction of current" in wiring, etc. is the direction in which positively charged carriers migrate, and is recorded as a positive current amount. In other words, the direction in which negatively charged carriers migrate is opposite to the direction of current and is recorded as a negative current amount. Therefore, in this specification, etc., unless otherwise specified, regarding the positive and negative of the current (or the direction of the current), the description of "current flows from element A to element B" can be replaced by the description of "current flows from element B to element A". In addition, the description of "current is input to element A" can be replaced by the description of "current is output from element A".

[0045] In addition, in this specification, etc., ordinal numbers such as "first," "second," and "third" are added to avoid confusion between components. Therefore, these ordinal numbers do not limit the number of components. Furthermore, these ordinal numbers do not limit the order of the components. For example, in this specification, etc., the "first" component in one embodiment may be referred to as the "second" component in other embodiments or claims. Furthermore, for example, in this specification, etc., the component referred to as "first" in one embodiment may be omitted in other embodiments or claims.

[0046] In this specification, etc., for the sake of convenience, words and phrases such as "upper" and "lower" that represent configurations are sometimes used to describe the positional relationship of components with reference to the accompanying drawings. In addition, the positional relationship of the components is appropriately changed depending on the direction in which each component is described. Therefore, the wording is not limited to the words and phrases described in the specification, etc., and the wording can be appropriately changed according to the situation. For example, if the expression is "an insulator located on the top surface of the conductor", by rotating the direction of the illustrated drawing by 180 degrees, it can be changed to "an insulator located on the bottom surface of the conductor".

[0047] In addition, the terms "above" or "below" are not limited to the case where the positional relationship of the components is "directly above" or "directly below" and in direct contact. For example, if it is an expression "electrode B on insulating layer A", it is not necessarily necessary that electrode B is formed in direct contact with insulating layer A, and the case where other components are included between insulating layer A and electrode B may also be included. In addition, similarly, for example, if it is an expression "electrode B above insulating layer A", it is not necessarily necessary that electrode B is formed in direct contact with insulating layer A, and the case where other components are included between insulating layer A and electrode B may also be included. In addition, similarly, for example, if it is an expression "electrode B below insulating layer A", it is not necessarily necessary that electrode B is formed in direct contact with below insulating layer A, and the case where other components are included between insulating layer A and electrode B may also be included.

[0048] In addition, in this specification and other documents, terms such as "row" and "column" are sometimes used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships of the components may be appropriately changed depending on the orientation in which the components are described. Therefore, the terms are not limited to those described in this specification and other documents, and may be appropriately changed depending on the circumstances. For example, by rotating the orientation of a drawing by 90 degrees, the term "row direction" may sometimes be replaced with "column direction."

[0049] In this specification, etc., the terms "film" and "layer" may be interchanged depending on the situation. For example, "conductive layer" may be interchanged with "conductive film." Also, "insulating film" may be interchanged with "insulating layer." Furthermore, depending on the situation or circumstances, other terms may be used in place of "film" and "layer." For example, "conductive layer" or "conductive film" may be interchanged with "conductive body." Also, for example, "insulating layer" or "insulating film" may be interchanged with "insulator."

[0050] Note that in this specification, etc., the words "electrode", "wiring" and "terminal" do not functionally limit their constituent elements. For example, sometimes an "electrode" is used as a part of a "wiring", and vice versa. Furthermore, the words "electrode" or "wiring" also include the case where a plurality of "electrodes" or "wirings" are formed into one. In addition, for example, sometimes a "terminal" is used as a part of a "wiring" or "electrode", and vice versa. Furthermore, the words "terminal" also include the case where one or more selected from "electrode", "wiring" and "terminal" are formed into one. Therefore, for example, an "electrode" can be a part of a "wiring" or "terminal", for example, a "terminal" can be a part of a "wiring" or "electrode". In addition, the words "electrode", "wiring" or "terminal" are sometimes replaced with words such as "region" depending on the circumstances.

[0051] In this specification, etc., depending on the situation or circumstances, the words "wiring", "signal line" or "power line" can be interchanged. For example, "wiring" can sometimes be replaced with "signal line". In addition, for example, "wiring" can sometimes be replaced with "power line". Vice versa, "signal line" or "power line" can sometimes be replaced with "wiring". In addition, "power line" can sometimes be replaced with "signal line". Vice versa, "signal line" can sometimes be replaced with "power line". In addition, depending on the situation or circumstances, "potential" applied to the wiring can sometimes be replaced with "signal". Vice versa, "signal" can sometimes be replaced with "potential".

[0052] In addition, in this specification, etc., the working method of the semiconductor device is sometimes described with reference to a timing diagram. In addition, the timing diagram used in this specification, etc. shows an ideal working example, and is not limited to the period, signal (for example, potential or current) and timing shown in the timing diagram unless otherwise specified. In the timing diagram of this specification, etc., the size and timing of the signal (for example, potential or current) of each wiring (including nodes) in the timing diagram can be changed according to the situation. For example, even if two periods of equal intervals are shown in the timing diagram, the lengths of the two periods are sometimes different. In addition, for example, even if one of the two periods is shown to be long and the other is short, the lengths of the two periods may sometimes be the same, or one of the two periods may sometimes be short and the other may be long.

[0053] In this specification, etc., metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors) and oxide semiconductors (Oxide Semiconductor, also referred to as OS), etc. For example, when the channel formation region of a transistor contains a metal oxide, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, when the metal oxide can constitute the channel formation region of a transistor having at least one of an amplification effect, a rectification effect and a switching effect, the metal oxide can be referred to as a metal oxide semiconductor (metal oxide semiconductor). In addition, an OS transistor can be referred to as a transistor containing a metal oxide or an oxide semiconductor.

[0054] In this specification and other documents, metal oxides containing nitrogen may also be referred to as metal oxides (metal oxides). In addition, metal oxides containing nitrogen may also be referred to as metal oxynitrides (metal oxynitrides).

[0055] In addition, in this specification, etc., impurities of a semiconductor refer to substances other than the main components constituting the semiconductor film. For example, an element with a concentration of less than 0.1 at.% is an impurity. For example, when impurities are contained, one or both of the following sometimes occur: an increase in the defect state density in the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor properties include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, or transition metals other than the main components, and in particular, hydrogen (contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc.

[0056] In this specification, etc., a switch refers to an element that has a function of controlling whether or not current flows by changing to a conducting state (on state) or a non-conducting state (off state). Alternatively, a switch refers to an element that has a function of selecting and switching a current path. Therefore, a switch sometimes includes two or more terminals for allowing current to flow in addition to a control terminal. As an example of a switch, an electric switch or a mechanical switch can be used. In other words, a switch is not limited to a specific element as long as it can control current.

[0057] Examples of electrical switches include transistors (e.g., bipolar transistors or MOS transistors), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, metal-insulator-metal (MIM: Metal Insulator Metal) diodes, metal-insulator-semiconductor (MIS: Metal Insulator Semiconductor) diodes, or diode-connected transistors), or logic circuits combining these elements. When a transistor is used as a switch, the "on state" of the transistor refers to, for example, a state in which the source electrode and the drain electrode of the transistor are electrically short-circuited or a state in which current can flow between the source electrode and the drain electrode. In addition, the "non-conducting state" of the transistor refers to a state in which the source electrode and the drain electrode of the transistor are electrically disconnected. When a transistor is used only as a switch, there is no particular restriction on the polarity (conductivity type) of the transistor.

[0058] An example of a mechanical switch is a switch using MEMS (Micro Electro Mechanical System) technology, which has a mechanically movable electrode and operates by controlling conduction and non-conduction by moving the electrode.

[0059] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°. Therefore, this also includes a state where the angle is greater than -5° and less than 5°. "Approximately parallel" refers to a state where the angle formed by two straight lines is greater than -30° and less than 30°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°. Therefore, this also includes a state where the angle is greater than 85° and less than 95°. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than 60° and less than 120°.

[0060] In this specification, etc., the structure shown in each embodiment can be appropriately combined with the structure shown in other embodiments to constitute one mode of the present invention. In addition, when multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0061] In addition, the content (or part thereof) described in a certain embodiment may be applied / combined / replaced with other content (or part thereof) described in that embodiment and at least one of the content (or part thereof) described in one or more other embodiments.

[0062] Note that the contents described in the embodiments refer to the contents described in the various drawings in each embodiment or the contents described in the text described in the specification.

[0063] In addition, more figures can be formed by combining a figure (or part thereof) shown in a certain embodiment with other parts of the figure, other figures (or parts thereof) shown in the embodiment, and at least one figure (or part thereof) shown in one or more other embodiments.

[0064] The embodiments described in this specification are described with reference to the accompanying drawings. However, a person skilled in the art can easily understand the fact that the embodiments can be implemented in a plurality of different forms, and the methods and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments. Note that in the structure of the invention in the embodiments, the same symbols are sometimes used in different drawings to represent the same parts or parts with the same functions, and repeated descriptions are omitted. In stereograms, etc., for the sake of clarity, the illustration of some constituent elements is sometimes omitted.

[0065] In this specification, etc., when the same reference numeral is used for multiple elements and it is necessary to distinguish them, the reference numeral may be appended with an identification symbol such as "_1," "[n]," or "[m,n]." Furthermore, in the drawings, etc., when a reference numeral is appended with an identification symbol such as "_1," "[n]," or "[m,n]," these identification symbols may not be appended if it is not necessary to distinguish them in this specification.

[0066] In the drawings, sizes, layer thicknesses, and regions may be exaggerated for clarity. Therefore, the present invention is not limited to the dimensions shown in the drawings. Furthermore, the drawings schematically illustrate idealized examples and are not limited to the shapes or numerical values ​​shown. For example, variations in signals, voltages, or currents due to noise or timing variations may be included.

[0067] (Implementation 1) In this embodiment, a memory cell as a semiconductor device which is one embodiment of the present invention is described.

[0068] <Circuit Configuration Example of Semiconductor Device> Figure 1A An example of a memory cell of a semiconductor device as one embodiment of the present invention is shown. Memory cell MC is an example of a memory cell called a gain cell and includes a transistor MW, a transistor MR, and a capacitor C1. In particular, in this specification and other documents, a memory cell MC structure using OS transistors as both transistor MW and transistor MR is sometimes referred to as NOSRAM (registered trademark) (Nonvolatile Oxide Semiconductor Random Access Memory).

[0069] The transistor MW is used as, for example, a write transistor in the memory cell MC. In addition, the transistor MR is used as, for example, a read transistor in the memory cell MC.

[0070] The transistor MW and the transistor MR are preferably, for example, OS transistors. In particular, the metal oxide contained in the channel formation region of the OS transistor is preferably, for example, an In-M-Zn oxide containing indium, element M, and zinc (the element M is selected from one or more of aluminum, gallium, silicon, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony). In addition, as the transistor, a transistor containing silicon in the channel formation region (hereinafter referred to as a Si transistor) can also be used. In addition, as silicon, for example, single crystal silicon, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, or polycrystalline silicon can be used. In addition, as transistors other than OS transistors and Si transistors, for example, a transistor including germanium (Ge) in a channel formation region, a transistor including a compound semiconductor such as zinc selenide (ZnSe), cadmium sulfide (CdS), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN) or silicon germanium (SiGe) in a channel formation region, a transistor including carbon nanotubes in a channel formation region, or a transistor including an organic semiconductor in a channel formation region can be used.

[0071] A first terminal of transistor MW is electrically connected to wiring WBL, a second terminal of transistor MW is electrically connected to the gate of transistor MR and the first terminal of capacitor C1, and the gate of transistor MW is electrically connected to wiring WWL. Furthermore, a first terminal of transistor MR is electrically connected to wiring SL, and a second terminal of transistor MR is electrically connected to wiring RBL. Furthermore, a second terminal of capacitor C1 is electrically connected to wiring CL and wiring SL.

[0072] Note that in Figure 1A In FIG, an electrical connection point between the second terminal of the transistor MW, the gate of the transistor MR, and the first terminal of the capacitor C1 is referred to as a node FN.

[0073] The wiring WBL is used as an example as a write data line (sometimes referred to as a write bit line) that transmits write data to be held in the memory cell MC.

[0074] The wiring WWL is used as an example as a wiring (sometimes referred to as a write word line) for selecting a memory cell MC to which data is to be written.

[0075] The wiring RBL is used as an example as a read data line (sometimes referred to as a read bit line) that transmits data read from the memory cell MC.

[0076] As an example, wiring CL and wiring SL are used as wiring (sometimes referred to as read word lines) to select a memory cell from which data is to be read. Note that wiring CL and wiring SL are preferably electrically connected to each other outside memory cell MC so that the same signal is transmitted to wiring CL and wiring SL.

[0077] Note that there is no limitation on the structure of the transistor included in the semiconductor device of one embodiment of the present invention. For example, Figure 1A One or both of the transistor MW and the transistor MR shown may have a structure including a back gate, that is, a multi-gate structure including gates above and below the channel formation region.

[0078] Figure 1B The memory cell MC is Figure 1A A modified example of the memory cell MC. Figure 1B The transistor MW and the transistor MR shown are, for example, n-channel transistors having a multi-gate structure including gates above and below the channel, and both the transistor MW and the transistor MR include a first gate and a second gate. Note that in this specification, etc., for the sake of convenience, for example, the first gate is referred to as the gate (sometimes referred to as the front gate) and the second gate is referred to as the back gate to distinguish them. In addition, in this specification, etc., the first gate and the second gate can be interchanged with each other, so the "gate" can be referred to as the "back gate". Similarly, the "back gate" can be referred to as the "gate". Specifically, the connection structure of "the gate is electrically connected to the first wiring and the back gate is electrically connected to the second wiring" can be replaced with the connection structure of "the back gate is electrically connected to the first wiring and the gate is electrically connected to the second wiring".

[0079] In addition, Figure 1B In the figure, both transistor MW and transistor MR are shown with back gates, but the connection structure of the back gates is not shown. The electrical connection object of the back gate can be determined during the design. For example, in a transistor including a back gate, in order to increase the on-state current of the transistor, the gate and the back gate can be electrically connected. That is, for example, the gate of transistor MW can be electrically connected to the back gate, and the gate of transistor MR can be electrically connected to the back gate. In addition, for example, in a transistor including a back gate, in order to change the threshold voltage of the transistor or reduce the off-state current of the transistor, a wiring for electrically connecting the back gate of the transistor to an external circuit can be provided, and a potential can be applied to the back gate of the transistor through the external circuit.

[0080] Note that except Figure 1B In addition to the transistors shown, transistors described elsewhere in this specification or transistors shown in other drawings may also employ single-gate or multi-gate structures.

[0081] <Example of Cross-Sectional Structure of Semiconductor Device> Next, explain Figure 1A 1 and 2. A planar structure example and a cross-sectional structure example of a memory cell MC.

[0082] Figure 2A The memory cell MC shown is Figure 1AExample of a planar structure of a memory cell MC, Figure 2B and Figure 2C They are Figure 1A An example of a cross-sectional structure of a memory cell MC. Figure 2B It is along Figure 2A A cross-sectional view of the portion indicated by the dashed line A1-A2 of the plan view shown, Figure 2C It is along Figure 2A The cross-sectional view of the portion indicated by the dashed line A3-A4 of the plan view shown. Figure 2A In the plan view, some components are omitted for clarity.

[0083] In addition, due to Figures 2A to 2C The illustrated memory cell MC has a three-dimensional structure, and therefore arrows indicating the x, y, and z directions are shown. Note that, as an example, the x, y, and z directions here represent mutually orthogonal directions. Furthermore, in this specification and other documents, one of the x, y, and z directions may be referred to as the "first direction." Furthermore, another of the x, y, and z directions may be referred to as the "second direction." Furthermore, the remaining direction may be referred to as the "third direction."

[0084] exist Figure 2B and Figure 2C In FIG, the memory cell MC includes a layer L1 and a layer L2. In addition, the layer L2 is located above the layer L1.

[0085] Furthermore, as an example, layer L1 includes insulators IS1, IS2, IS3, IS4, IS5, GI1, conductors ME1, ME2, ME3, ME4, and semiconductor SC1. Furthermore, by forming these materials using a predetermined process, transistor MR and capacitor C1 can be provided in layer L1. Capacitor C1 is located above transistor MR.

[0086] Specifically, for example, the transistor MR and the capacitor C1 can be formed by embedding the semiconductor SC1, the insulator GI1, and the conductor ME4 inside the opening KK1 provided in the insulator IS2, the conductor ME2, the insulator IS3, and the conductor ME3. Figure 1A When the memory cell MC is formed, the opening KK1 is formed in a region where the conductor ME1, the conductive film to become the conductor ME2, and the conductive film to become the conductor ME3 overlap.

[0087] As an example, layer L2 includes insulators IS6, IS7, GI2, conductors ME5, ME6, ME7, and semiconductor SC2. By forming the above materials through a predetermined process, transistor MW can be provided in layer L2.

[0088] Specifically, for example, the transistor MW can be formed by embedding the semiconductor SC2, the insulator GI2, and the conductor ME7 inside the opening KK2 provided in the insulator IS6 and the conductor ME6. Figure 1A When the memory cell MC is formed, the opening KK2 is formed in a region overlapping with the conductor ME5 and the conductive film that becomes the conductor ME6.

[0089] As described above, the memory cell MC has a structure in which the transistor MR, the capacitor C1, and the transistor MW are formed in this order from the bottom.

[0090] As an example, the transistor MR includes a conductor ME1 serving as one of a source electrode and a drain electrode, a conductor ME2 serving as the other of the source electrode and the drain electrode, a semiconductor SC1 serving as a channel formation region, an insulator GI1 serving as a gate insulating film, and a conductor ME4 serving as a gate electrode.

[0091] As an example, the capacitor C1 includes a semiconductor SC1 and an electrical conductor ME3 serving as one of a pair of electrodes, an electrical conductor ME4 serving as the other of the pair of electrodes, and an insulator GI1 serving as a dielectric sandwiched between the pair of electrodes.

[0092] In particular, increasing the contact area between conductor ME3 and semiconductor SC1 can increase the capacitance of capacitor C1. Examples of methods for increasing this contact area include deepening opening KK1 or increasing the area of ​​opening KK1 when viewed from above. Another method for increasing the capacitance of capacitor C1 is to use an insulating material with a high relative dielectric constant for insulator GI1.

[0093] Furthermore, when the capacitance value of capacitor C1 is small, particularly when the parasitic capacitance values ​​of the first and second terminals of capacitor C1 are larger than the capacitance values, there may be effects such as slowing down the write / read speed of memory cell MC and causing the potential applied to the gates of transistor MW or transistor MR to fall below a desired level. Therefore, in memory cell MC, the capacitance value of capacitor C1 is preferably, for example, at least twice the parasitic capacitance value of the first or second terminal of capacitor C1, more preferably at least four times, and even more preferably at least eight times.

[0094] As an example, the transistor MW includes a conductor ME5 serving as one of a source electrode and a drain electrode, a conductor ME6 serving as the other of the source electrode and the drain electrode, a semiconductor SC2 serving as a channel formation region, an insulator GI2 serving as a gate insulating film, and a conductor ME7 serving as a gate electrode.

[0095] In addition, in the structure of the memory cell MC, a transistor may be formed above the transistor MR and below the capacitor C1. Figure 2B and Figure 2C In the embodiment, the transistor is transistor MD. Transistor MD includes, for example, a conductor ME2 serving as one of a source electrode and a drain electrode, a conductor ME3 serving as the other of the source electrode and the drain electrode, a semiconductor SC1 serving as a channel formation region, an insulator GI1 serving as a gate insulating film, and a conductor ME4 serving as a gate electrode.

[0096] In addition, the transistor MD is described in Figure 1A The circuit structure of the memory cell MC is sometimes Figure 1C The circuit structure shown in Figure 1C In the diagram, the first terminal of transistor MD is electrically connected to the second terminal of capacitor C1 and wiring CL, the second terminal of transistor MD is electrically connected to wiring SL and the first terminal of transistor MR, and the gate of transistor MD is electrically connected to the first terminal of capacitor C1, the second terminal of transistor MW, and the gate of transistor MR.

[0097] like Figures 2A to 2C As shown, transistor MD is sometimes formed above transistor MR and below capacitor C1, while Figure 1C When the same signal is transmitted to each of the wiring CL and the wiring SL, the transistor MD does not affect the writing operation and the reading operation of the memory cell MC.

[0098] Note that a memory cell of a semiconductor device as one embodiment of the present invention may be Figure 1C The memory cell MC is shown.

[0099] The conductor ME1 is also used as a wiring RBL as an example. Figures 2A to 2C In addition, the conductor ME2 is also used as a wiring SL as an example. Figures 2A to 2C In addition, the conductor ME3 is also used as a wiring CL as an example. Figures 2A to 2C Extends in the X direction.

[0100] The conductor ME6 is also used as a wiring WBL as an example. Figures 2A to 2C In addition, the conductor ME7 is also used as a wiring WWL as an example. Figures 2A to 2C Extends in the X direction.

[0101] <Configuration Example of Storage Device> Next, the description includes Figure 1A or Figure 1B An example of the structure of a memory device including a memory cell MC.

[0102] Figure 3A The memory device MDV shown is a memory device according to one embodiment of the present invention, and includes a cell array CA, a circuit WBD, a circuit WWD, a circuit CSD, and a circuit RBD.

[0103] Furthermore, the cell array CA includes a plurality of memory cells MC. Specifically, in the cell array CA, the plurality of memory cells MC are arranged in a matrix of m rows and n columns (m is an integer greater than 1, and n is an integer greater than 1). As an example, Figure 3A The cell array CA abstractly shows a memory cell MC[1,1], a memory cell MC[m,1], a memory cell MC[1,n], and a memory cell MC[m,n].

[0104] Note that in Figure 3A In FIG, the memory cell MC located at the x-th row and the y-th column is represented by MC[x, y].

[0105] Figure 3A The memory cells MC[1,1] to MC[m,n] shown can each use Figure 1A The memory cell MC is shown.

[0106] As an example, in the cell array CA, the equivalent of Figure 1A The wiring WWL[1] to the wiring WWL[m] of the wiring WWL extend in the row direction. In addition, as an example, in the cell array CA, the wiring WWL[1] to the wiring WWL[m] are equivalent to Figure 1A The wiring CL[1] to the wiring CL[m] of the cell array CA extend in the row direction. In addition, as an example, in the cell array CA, the wiring SL[1] to the wiring SL[m] corresponding to the wiring SL in FIG. 1 extend in the row direction.

[0107] Note that in Figure 3A In the example, the wiring WWL extending on the x-th row is represented by WWL[x]. Similarly, the wiring CL extending on the x-th row is represented by CL[x]. Similarly, the wiring SL extending on the x-th row is represented by SL[x].

[0108] As an example, in the cell array CA, the equivalent of Figure 1A The wiring WBL[1] to the wiring WBL[n] of the wiring WBL extend in the column direction. In addition, as an example, in the cell array CA, the wiring WBL[1] to the wiring WBL[n] are equivalent to Figure 1A The wirings RBL[1] to RBL[n] of the wirings RBL extend in the column direction, respectively.

[0109] Note that in Figure 3AIn FIG, the wiring WBL extending on the y-th column is represented by the symbol WBL[y]. Similarly, the wiring RBL extending on the y-th column is represented by the symbol RBL[y].

[0110] In addition, Figure 3A In FIG, circuit WWD is electrically connected to wiring WWL[1] through wiring WWL[m]. Circuit CSD is electrically connected to wiring CL[1] through wiring CL[m]. Wiring CL[1] is electrically connected to wiring SL[1], and wiring CL[m] is electrically connected to wiring SL[m]. Circuit WBD is electrically connected to wiring WBL[1] through wiring WBL[n]. Circuit RBD is electrically connected to wiring RBL[1] through wiring RBL[n].

[0111] Circuit WWD, for example, has the function of selecting a memory cell MC in a row to be written in the cell array CA. Specifically, circuit WWD, for example, has the function of sending a select signal to any one of wirings WWL[1] to WWL[m] and sending a non-select signal to the other wirings. Note that when the write transistor included in memory cell MC is an n-channel transistor, the select signal is preferably a high-level potential, and the non-select signal is preferably a low-level potential.

[0112] Circuit CSD, for example, has the function of selecting a memory cell MC in a row to be written or read in cell array CA. Specifically, circuit CSD, for example, has the function of sending a select signal to any one of wirings CL[1] to CL[m] and sending a non-select signal to the other wirings, similar to circuit WWD. In particular, memory cell MC selected by circuit CSD outputs the data written to memory cell MC to wiring RBL as read data. Note that when the read transistor included in memory cell MC is an n-channel transistor, the select signal is preferably a high-level potential, and the non-select signal is preferably a low-level potential. In addition, as an example, circuit CSD may also have the function of supplying a fixed potential to wirings CL[1] to CL[m]. In addition, this fixed potential may be, for example, a high-level potential, a low-level potential, a ground potential, or a negative potential.

[0113] in addition, Figure 3A The memory device MDV has a structure in which the wiring CL and the wiring SL on the same row are electrically connected to each other. Therefore, a selection signal or a non-selection signal sent by the circuit CSD to the wiring CL is also sent to the wiring SL on the same row as the wiring CL.

[0114] Circuit WBD, for example, has the function of transmitting write data to the memory cells MC selected by circuit WWD in cell array CA. Specifically, circuit WBD transmits write data to each of wirings WBL[1] through WBL[n]. Consequently, the write data transmitted to each column is written to the memory cells MC in the row selected by circuit WWD.

[0115] Circuit RBD, for example, has the function of reading data written from memory cells MC in cell array CA. Specifically, memory cells MC in a row selected by circuit CSD output read data to each of wirings RBL[1] to RBL[n]. Circuit RBD then obtains the read data from each of wirings RBL[1] to RBL[n]. Circuit RBD then converts the read data into digital or analog data and outputs it to the outside of circuit RBD.

[0116] Since the circuit RBD converts the read data into digital data or analog data, the circuit RBD preferably includes a current-voltage conversion circuit, an analog-to-digital conversion circuit, or a digital-to-analog conversion circuit.

[0117] Note that the storage device according to one embodiment of the present invention is not limited to Figure 3A The structure of the storage device MDV shown in FIG. The storage device according to one embodiment of the present invention can be appropriately changed. Figure 3A The structure of the storage device MDV. For example, Figure 3B Like the memory device MDV shown in FIG. 1 , the memory device according to one embodiment of the present invention may have a structure in which the wiring CL[ 1 ] and the wiring SL[ 1 ] are not electrically connected, and the wiring CL[m] and the wiring SL[m] are not electrically connected.

[0118] In addition, Figure 3B In the example, the memory device MDV includes a circuit CSE. The circuit CSE is electrically connected to the wiring SL[1] to the wiring SL[m]. The circuit CSE has, for example, a function of selecting the memory cell MC of the row to be read in the cell array CA. Specifically, the circuit CSE has, for example, a function of sending a selection signal to any one of the wirings SL[1] to the wiring SL[m] and sending a non-selection signal to the other wirings, similar to the circuit WWD. Note that when the read transistor included in the memory cell MC is an n-channel transistor, the selection signal is preferably a high-level potential, and the non-selection signal is preferably a low-level potential. In addition, as an example, the circuit CSE may also have a function of supplying a fixed potential to the wirings SL[1] to the wiring SL[m]. In addition, the fixed potential may be, for example, a high-level potential, a low-level potential, a ground potential, or a negative potential.

[0119] <<Example of Cell Array Structure>> Next, explain Figure 3A and Figure 3B A structural example of a cell array CA included in the memory device MDV.

[0120] Figure 4A and Figure 4B Each is a plan view schematically showing a structural example of the cell array CA. In particular, Figure 4A The cell array CA of FIG. 1 shows the conductor ME6, the conductor ME7 and the opening KK2. Figure 4B The cell array CA of FIG. 1 shows the conductor ME1, the conductor ME2, and the materials contained in the opening KK1 (conductor ME4, semiconductor SC1, and insulator GI1). That is, Figure 4A The schematic plan view shows a plurality of transistors MW arranged in a matrix in the cell array CA. Figure 4B The schematic plan view of FIG. 1 shows a plurality of transistors MR arranged in a matrix in the cell array CA.

[0121] exist Figure 4A In the cell array CA shown, the conductor ME6 and the conductor ME7 extend substantially perpendicularly. In addition, an opening KK2 is formed inside the region where the conductor ME6 and the conductor ME7 overlap.

[0122] Likewise, in Figure 4B In the cell array CA shown, the conductor ME1 and the conductor ME2 extend substantially perpendicularly. In addition, an opening KK1 is formed inside the region where the conductor ME1 and the conductor ME2 overlap.

[0123] Note that the configuration example of the cell array CA of the memory device according to one embodiment of the present invention is not limited to Figure 4A and Figure 4B For example, in a structural example of a cell array CA of a memory device according to one embodiment of the present invention, Figure 5A and Figure 5B As shown, the conductors ME6 and ME7 do not need to be approximately perpendicular, and the conductors ME1 and ME2 do not need to be approximately perpendicular. For example, the angle formed by the conductors ME6 and ME7 can be greater than 0° and less than 60°, and the angle formed by the conductors ME1 and ME2 can be greater than 0° and less than 60°. Furthermore, the conductors ME1 and ME6 preferably extend in the same direction, and the conductors ME2 and ME7 preferably extend in the same direction.

[0124] By making the cell array CA have Figure 5A and Figure 5BThe structure shown may increase the number of memory cells MC that can be arranged in the cell array CA, thereby increasing the storage density of the memory device MDV.

[0125] In addition, Figure 4A and Figure 5A In FIG. 1 , the opening KK2 has a quadrangular shape with rounded corners when viewed from a plane, but as shown in FIG. Figure 6A As shown, the opening KK2 may also have a circular shape (including a perfect circle and an ellipse) or a shape close to a circular shape. Figure 6B As shown, the opening KK2 is not only provided in the region where the conductor ME6 and the conductor ME7 overlap when viewed from a plane, but can also be provided in a region that overlaps the conductor ME6 and does not overlap the conductor ME7. Figure 6B In the embodiment, the opening KK2 has, for example, a quadrangular shape with rounded corners when viewed from a plan view. However, the opening KK2 may have a shape other than the quadrangular shape.

[0126] In addition, Figures 4B to 5B In FIG. 1 , the opening KK1 has a circular shape when viewed from a plane, but as Figure 7A As shown in FIG, it may also have a quadrangular shape with rounded corners. Figure 7B As shown, the opening KK1 is not only provided in the region where the conductor ME1 overlaps with the conductor ME2 when viewed from a plane, but can also be provided in the region that overlaps with the conductor ME2 and does not overlap with the conductor ME1. Figure 7B In the embodiment, the opening KK1 has, for example, a quadrangular shape with rounded corners when viewed from a plan view, but the opening KK2 may have a shape other than the quadrangular shape.

[0127] <Operation Example of Semiconductor Device> Next, explain Figure 1A ( Figures 2A to 2C )'s working example of the memory cell MC.

[0128] Figure 8A It shows Figure 1A A timing diagram showing an operation example of the memory cell MC. Figure 8A The timing diagram shows the potential changes of wiring WWL, wiring WBL, wiring CL, wiring SL, wiring RBL, and node FN from time T01 to time T07 and in the vicinity thereof. In particular, memory cell MC performs a write operation from time T01 to time T05, and performs a read operation from memory cell MC from time T06 to time T07.

[0129] in addition, Figure 1A The wiring WWL in FIG3 is electrically connected to the circuit WWD shown in FIG3. Figure 1AThe wiring WBL in FIG3 is electrically connected to the circuit WBD shown in FIG3. Figure 1A The wiring CL in FIG3 is electrically connected to the circuit CSD shown in FIG3. Figure 1A The wiring RBL in FIG. 3 is electrically connected to the circuit RBD shown in FIG. 3 .

[0130] In addition, if Figure 3A As shown in FIG. 1 , the wiring CL and the wiring SL are electrically connected to each other. Therefore, the potential change of the wiring CL is equal to the potential change of the wiring SL.

[0131] Before time T01, the circuit WWD supplies a low-level potential to the wiring WWL (at Figure 8A In addition, the circuit WBD supplies the ground potential V to the wiring WBL. GND In addition, the circuit CSD supplies the potential V to the wiring CL. CL In addition, the circuit RBD supplies V to the wiring RBL as a low-level potential. Low .

[0132] Note that V CL It can also be ground potential V GND The same potential. In addition, V Low Can also be with V CL Or ground potential V GND Equal potential.

[0133] Before time T01, the potential of the node FN is at the ground potential V GND .

[0134] Furthermore, a low-level potential is supplied to the gate of the transistor MW from the wiring WWL, thereby turning off the transistor MW and placing the node FN in a floating state.

[0135] <<Write Work>> During the period from time T01 to time T02, circuit WBD transmits write data to wiring WBL. Note that the potential of wiring WBL at this time is V1 or V0 according to the write data. V1 is a potential higher than V0.

[0136] Note that in Figure 8A In the timing chart of , in the wiring WBL from time T01 to time T04, the case where the potential is V1 is indicated by the solid line, and the case where the potential is V0 is indicated by the dotted line.

[0137] In addition, during the period from time T01 to time T02, the circuit CSD supplies the potential V CH . Note that V CH is higher than V CL The potential.

[0138] Since the node FN is in a floating state, the potential of the wiring CL changes from V CL becomes V CH The potential of the node FN also changes due to the capacitance coupling of the capacitor C1 according to the change in the potential of the wiring CL. Here, the potential of the node FN becomes V GND +(V CH -V CL ). This corresponds to a case where the capacitive coupling coefficient around the node FN is 1.

[0139] During the period from time T02 to time T03, the circuit WWD supplies a high-level potential to the wiring WWL (at Figure 8A As a result, transistor MW is turned on, and conduction occurs between wiring WBL, the first terminal of capacitor C1, and the gate of transistor MR (node ​​FN). Consequently, charge flows between node FN and wiring WBL, and ideally, the potential of node FN becomes equal to the potential (V1 or V0) supplied to wiring WBL.

[0140] Note that in Figure 8A In the timing chart of FIG. 1 , at the node FN after time T02 , the solid line shows the writing of V1 from the wiring WBL to the node FN, and the dotted line shows the writing of V0 from the wiring WBL to the node FN.

[0141] Furthermore, between time T02 and time T03, circuit WWD supplies a high-level potential to wiring WWL. Then, circuit WWD supplies a low-level potential to wiring WWL. This turns transistor MW off, and node FN floats. That is, in memory cell MC, the first terminal of capacitor C1 and the gate of transistor MR (node ​​FN) maintain voltage V1 or V0.

[0142] During the period from time T03 to time T04, the circuit WBD supplies the ground potential V to the wiring WBL. GND .

[0143] During the period from time T04 to time T05, the circuit CSD supplies V to the wiring CL. CL .

[0144] Since the node FN is in a floating state, the potential of the wiring CL changes from V CH becomes V CL When the potential of the node FN also changes due to the capacitance coupling of the capacitor C1 according to the change in the potential of the wiring CL. Here, the potential of the node FN becomes V1-(V CH -V CL ) or V0-(V CH -V CL ).

[0145] In addition, during the period from time T04 to time T05, the circuit RBD supplies V to the wiring RBL. Low .

[0146] As a result, the gate-source voltage (V1-V CH +V CL -V Low or V0-V CH +V CL -V Low ) is lower than the threshold voltage of the transistor MR. That is, the transistor MR becomes off.

[0147] Note that during the period from time T01 to time T04, the circuit RBD supplies the potential V CH By setting the potential of wiring RBL to V CH , the voltage (source-drain voltage) between the first terminal (wiring SL) and the second terminal (wiring RBL) of the transistor MR can be set to 0 V. Consequently, in the transistor MR, no current flows between the source and drain regardless of the gate potential, thereby reducing power consumption during the write operation of the memory cell MC.

[0148] Through the above-described operation, data is written to the memory cell MC.

[0149] <<Reading Work>> During the period from time T06 to time T07, the circuit CSD supplies V to the wiring CL. CH .

[0150] During the period from time T06 to time T07, the node FN is also in a floating state, and the potential of the wiring CL is increased from V CL becomes V CH The potential of the node FN changes due to the capacitive coupling of the capacitor C1 according to the amount of change in the potential of the wiring CL. Here, the potential of the node FN becomes V1 or V0.

[0151] In addition, since the wiring CL is supplied with V CH , so the potential of the wiring SL also becomes V CH Therefore, the first terminal of the transistor MR is supplied with V from the wiring SL. CH In addition, the potential of the gate of the transistor MR is V1 or V0.

[0152] In addition, during the period from time T06 to time T07, the circuit RBD supplies the low-level potential V Low Therefore, the gate-source voltage of transistor MR becomes V1-V Low or V0-VLow A drain current corresponding to the gate-source voltage flows between the source and drain of the transistor MR. As a result, the drain current flows from the wiring SL through the wiring WBL to the circuit RBD.

[0153] Circuit RBD can read data written into memory cell MC based on the amount of drain current flowing through wiring WBL. Specifically, for example, if circuit RBD includes a current-to-voltage conversion circuit, circuit RBD can convert the amount of drain current into a voltage using the current-to-voltage conversion circuit, and thus can process the read data as the voltage.

[0154] Here, the memory cell MC has Figure 1C In the case of a structure in which the potential of the first terminal of the transistor MD becomes the potential supplied by the wiring CL, and the potential of the second terminal of the transistor MD becomes the potential supplied by the wiring SL during the period from time T01 to time T07. That is, the voltage between the first terminal and the second terminal of the transistor MD is 0V, so no charge flows between the first terminal and the second terminal of the transistor MD regardless of the potential of the gate of the transistor MD. In addition, even if a voltage is generated between the first terminal and the second terminal of the transistor MD due to the parasitic resistance of one or the other of the wiring SL and the wiring CL, if the transistor MD is in the on state, the charge is equalized between the wiring SL and the wiring CL through the transistor MD, so the wiring SL and the wiring CL are operated in a manner that has the same potential. Therefore, the voltage between the first terminal and the second terminal of the transistor MD becomes 0V, and then no charge flows between the first terminal and the second terminal of the transistor MD. That is, even if the memory cell MC has Figure 1C The structure and working method can also be Figure 1A The structure is the same.

[0155] The working examples of the semiconductor device according to one embodiment of the present invention are not limited to the above-described working examples. The working examples of the semiconductor device according to one embodiment of the present invention can also be modified as appropriate.

[0156] For example, in the above-mentioned read operation, the circuit RBD supplies V to the wiring RBL. Low The data held in the memory cell MC is read based on the amount of drain current of the transistor MR of the memory cell MC flowing through the wiring RBL. However, the data held in the memory cell MC may be read by a read operation using another method.

[0157] Figure 8B is shown with Figure 8A Timing diagram of different memory cell MC operation examples. Note that Figure 8B The timing diagram and Figure 8AThe difference between the timing diagrams is the readout operation (after time T06). Figure 8B In, V Low and V CL are of equal potential.

[0158] exist Figure 8B In the read operation of the timing diagram, during the period from time T05 to time T06, the circuit RBD raises the potential V to the wiring RBL. CL Then, the circuit RBD and the wiring RBL are placed in a non-conductive state so that the wiring RBL is placed in a floating state.

[0159] In addition, during the period from time T06 to time T07, the circuit CSD supplies V CH , thus with Figure 8A Similarly, during the period from time T06 to time T07 in the timing chart of FIG. 1 , the potential of the node FN becomes V1 or V0 .

[0160] At this time, the transistor MR is turned on, and charge flows from the wiring SL through the transistor MR to the wiring RBL. In addition, since the wiring RBL is in a floating state, the potential of the wiring RBL becomes high until the gate-source voltage of the transistor MR becomes equal to the threshold voltage of the transistor MR (until the transistor MR is turned off). For example, when the threshold voltage of the transistor MR is V th When the potential of wiring RBL finally reaches V1-V th or V0-V th .

[0161] Then, by referring to the potential of the wiring RBL by the circuit RBD, the data held in the memory cell MC can be read.

[0162] Note that although this working example describes the case where binary data is written to or read from a memory cell MC, the data held in the memory cell MC may have three or more values, four or more values, or eight or more values. Alternatively, the data held in the memory cell MC may be an analog potential (analog data).

[0163] By using the semiconductor device described in this embodiment as a memory cell included in a memory device, the area of ​​the memory cell can be reduced. In addition, by reducing the area of ​​the memory cell, the integration of the memory cell can be increased, thereby increasing the storage density of the memory cell. In addition, by increasing the contact area between the conductor ME3 and the semiconductor SC1, the plate area of ​​the capacitor C1 is also increased, thereby increasing the electrostatic capacitance value of the capacitor C1 included in the memory cell. By increasing the electrostatic capacitance value of the capacitor C1, it is easier to maintain the analog voltage (multi-value data) in the memory cell, thereby increasing the storage capacity of the memory cell. In addition, by increasing the electrostatic capacitance value of the capacitor C1, the retention time of the data in the memory cell can be extended.

[0164] The structure described in this embodiment mode can be appropriately combined with other structures described in this embodiment mode. For example, the structure, configuration, and method described in this embodiment mode can be appropriately combined with other structures, configurations, and methods described in this embodiment mode.

[0165] This embodiment mode can be appropriately combined with other embodiment modes described in this specification. For example, the configuration, structure, and method described in this embodiment mode can be appropriately combined with the configuration, structure, and method described in other embodiment modes.

[0166] (Implementation Method 2) In this embodiment, the Figures 2A to 2C An example of a method for manufacturing a memory cell MC and Figures 2A to 2C A modified example of the structure of the memory cell MC is described below.

[0167] <Manufacturing Method Example> Reference Figures 9A to 32C illustrate Figures 2A to 2C An example of a method for manufacturing a memory cell MC.

[0168] exist Figures 9A to 32C , each A is a schematic plan view. Furthermore, B in each drawing is a schematic cross-sectional view taken along the dot-dash line A1-A2 shown in A, also a schematic cross-sectional view in the X direction. Furthermore, C in each drawing is a schematic cross-sectional view taken along the dot-dash line A3-A4 shown in A, also a schematic cross-sectional view in the Y direction. Note that in the schematic plan views of A in each drawing, some components are omitted for clarity.

[0169] Next, by appropriately using a deposition method such as sputtering, CVD (Chemical Vapor Deposition), MBE (Molecular Beam Epitaxy), PLD (Pulsed Laser Depositon), or ALD (Atomic Layer Deposition), an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor can be deposited.

[0170] First, a method for manufacturing the layer L1 of the memory cell MC will be described.

[0171] First, a substrate (not shown) is prepared, and an insulator IS1 and a conductive film ME1A are sequentially formed on the substrate (see Figures 9A to 9C ).

[0172] As the substrate, for example, a semiconductor substrate (for example, a single crystal substrate made of silicon or germanium) can be used. In addition to semiconductor substrates, as substrates, for example, SOI (Silicon On Insulator) substrates, glass substrates, quartz substrates, plastic substrates, sapphire glass substrates, metal substrates, stainless steel substrates, substrates containing stainless steel foil, tungsten substrates, substrates containing tungsten foil, flexible substrates, laminated films, paper containing fibrous materials, or base films can be used. As an example of a glass substrate, barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass can be cited. As flexible substrates, laminated films, and base films, the following examples can be cited. For example, plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE) can be cited. Alternatively, as an example, synthetic resins such as acrylic resins can be cited. In addition, as another example, polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride can be cited. Other examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor-deposited film, and paper. Note that when the manufacturing process of the display device DSP includes heat treatment, a substrate with high heat resistance is preferably selected as the substrate. Alternatively, a substrate with components disposed thereon may be used. Examples of components disposed on the substrate include capacitors, resistors, switching elements, light-emitting elements, and memory elements.

[0173] As an example, the insulator IS1 is used as an interlayer film. Therefore, it is preferable to use an insulating material with a low relative dielectric constant for the insulator IS1. By using an insulating material with a low relative dielectric constant as the interlayer film, the parasitic capacitance generated between the wirings can be reduced.

[0174] For example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride can be used as the insulator IS1. Alternatively, for example, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide with pores can be used as the insulator IS1. Silicon oxide and silicon oxynitride are particularly preferred due to their thermal stability. Silicon oxide, silicon oxynitride, and silicon oxide with pores are particularly preferred because they easily form regions containing oxygen that is released by heating. Alternatively, for example, resin can be used as the insulator IS1. Furthermore, the aforementioned insulating materials may be appropriately combined as the material used for the insulator IS1.

[0175] In the subsequent manufacturing process, the conductor ME1 is formed on the insulator IS1. Therefore, in order to prevent oxidation of the conductor ME1, it is preferable to use silicon nitride, for example, as a barrier insulating film that suppresses oxygen diffusion in the insulator IS1.

[0176] The conductive film ME1A is a film that becomes the conductor ME1 (wiring RBL) in a later step. In addition, a portion of the conductor ME1 is also used as one of the source electrode and the drain electrode of the transistor MR. Therefore, it is preferable to use a highly conductive material for the conductive film ME1A.

[0177] For example, the conductive film ME1A preferably uses a metal element selected from the group consisting of aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum; an alloy containing two or more of these metal elements; or an alloy combining two or more of these metal elements. Alternatively, for example, the conductive film ME1A preferably uses tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. Tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are conductive materials that are not easily oxidized or that maintain conductivity even when absorbing oxygen, and are therefore preferred. Alternatively, as the conductor, a semiconductor having high conductivity, such as polycrystalline silicon containing an impurity element (such as phosphorus or arsenic), or a silicide (such as nickel silicide) may be used.

[0178] Furthermore, a plurality of conductive films formed from the above materials may be stacked. For example, a stacked structure may be formed by combining a material containing the above metal element and a conductive material containing oxygen. Alternatively, a stacked structure may be formed by combining a material containing the above metal element and a conductive material containing nitrogen. Alternatively, a stacked structure may be formed by combining a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0179] For example, the electrical conductor ME1 may include a first electrical conductor and a second electrical conductor surrounded by the first electrical conductor. The first electrical conductor may be made of titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide, which are conductive materials that inhibit oxygen diffusion. The second electrical conductor may be made of a conductive material primarily composed of highly conductive tungsten, copper, or aluminum. By surrounding the second electrical conductor with the first electrical conductor, a decrease in conductivity due to oxidation of the first electrical conductor can be prevented.

[0180] Next, the conductive film ME1A is processed into a strip shape by photolithography to form the conductive body ME1 (see 10A to 10C In particular, the conductor ME1 is formed to extend in a direction parallel to the dot-dash line A3-A4 (Y direction). The above-mentioned processing can be performed by dry etching or wet etching. The processing using dry etching is particularly suitable for micro-processing.

[0181] Note that in photolithography, first, a resist is exposed through a mask. Then, a developer is used to remove or leave the exposed area to form a resist mask. Then, the conductor, semiconductor, or insulator can be processed into a desired shape by etching through the resist mask. For example, a resist mask can be formed by exposing the resist using a KrF excimer laser, an ArF excimer laser, or EUV (Extreme Ultraviolet) light. In addition, an immersion technique can be used in which the exposure is performed in a state where a liquid (for example, water) is filled between the substrate and the projection lens. In addition, an electron beam or an ion beam can be used instead of the above-mentioned light. Note that when an electron beam or an ion beam is used, a mask is not required. In addition, the resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after a dry etching process, or performing a dry etching process after a wet etching process.

[0182] Furthermore, a hard mask made of an insulator or conductor can also be used under the resist mask. When using a hard mask, an insulating film or a conductive film serving as the hard mask material can be formed on the conductive film ME1A, a resist mask formed thereon, and then the hard mask material can be etched to form a hard mask of the desired shape. Etching of the conductive film ME1A and the like can be performed either after removing the resist mask or without removing the resist mask. In the latter case, the resist mask may disappear during etching. The hard mask can be removed by etching after etching the conductive film ME1A and the like. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.

[0183] Next, an insulating film IS2A is deposited on the conductor ME1 (see Figures 11A to 11CWhen depositing the insulating film IS2A, for example, a deposition method such as sputtering, CVD, MBE, PLD, or ALD can be used. Furthermore, after depositing the insulating film IS2A, a planarization process such as CMP can be performed on the insulating film IS2A to planarize the top surface of the insulating film IS2A.

[0184] Insulating film IS2A is a film that becomes insulator IS2 in a later step. Insulator IS2 is used, for example, as an interlayer film. Therefore, insulator IS2 preferably comprises an insulating material with a low relative dielectric constant. Using an insulating material with a low relative dielectric constant as an interlayer film can reduce parasitic capacitance between wiring lines.

[0185] The insulating film IS2A can be made of, for example, a material that can be used for the insulator IS1. In particular, when the semiconductor SC1 formed in a subsequent step is a metal oxide used as an oxide semiconductor, the insulating film IS2A is preferably made of, for example, silicon oxide, silicon oxynitride, or silicon oxide with vacancies. These materials can easily form regions containing oxygen that is released by heating, and this released oxygen can be supplied to the metal oxide. As a result, the carrier concentration of the metal oxide is reduced at and near the interface of the semiconductor SC1 in contact with the insulator IS2, and the interface of the semiconductor SC1 and the vicinity thereof becomes i-type or substantially i-type. Therefore, the interface of the semiconductor SC1 and the vicinity thereof serves as the channel formation region in the transistor MR.

[0186] Next, a conductive film ME2A is deposited on the insulating film IS2A (see Figures 11A to 11C ).

[0187] The conductive film ME2A is a film that becomes the conductor ME2 (wiring SL) in a later step. Furthermore, a portion of the conductor ME2 is also used as the other of the source and drain electrodes of the transistor MR. Therefore, a highly conductive material is preferably used for the conductive film ME2A.

[0188] The conductive film ME2A can use, for example, a material that can be used for the conductor ME1.

[0189] Next, the conductive film ME2A is processed into a strip shape by photolithography to form a conductive film ME2B (see FIG. 12A to 12C ). In particular, the conductive film ME2B is formed so as to extend in a direction parallel to the dot-dash line A1-A2 (X direction) and overlap with the conductive body ME1. Note that regarding the photolithography method, reference can be made to 10A to 10C Photolithography as described.

[0190] Next, an insulating film IS3A is deposited on the conductor ME2B (see 13A to 13CWhen depositing the insulating film IS3A, for example, a deposition method such as sputtering, CVD, MBE, PLD, or ALD can be used. Furthermore, after depositing the insulating film IS3A, a planarization treatment such as CMP can be performed on the insulating film IS3A to planarize the top surface of the insulating film IS3A.

[0191] Insulating film IS3A is a film that becomes insulator IS3 in a later step. Insulator IS3 is used, for example, as an interlayer film. Therefore, insulator IS3 preferably comprises an insulating material with a low relative dielectric constant. Using an insulating material with a low relative dielectric constant as an interlayer film can reduce parasitic capacitance between wirings.

[0192] The insulating film IS3A can be made of, for example, a material that can be used for the insulator IS1.

[0193] Furthermore, in order to reduce the resistance of the interface with the semiconductor SC1 (details will be described later) in contact with the insulator IS3 and in the vicinity of the interface, the insulating film IS3A may contain impurities specific to the semiconductor SC1. For example, when the semiconductor SC1 is a metal oxide such as an In-M-Zn oxide, the insulating film IS3A may contain impurities such as water, hydrogen, nitrogen, or nitrides to reduce the resistance of the In-M-Zn oxide.

[0194] Furthermore, for example, when the semiconductor SC1 is made of a material containing silicon, the insulating film IS3A preferably contains impurities (e.g., elements or ions) for diffusion into the silicon. For example, n-type impurities (donors) such as phosphorus or arsenic can be used as such impurities. Furthermore, p-type impurities (acceptors) such as boron, aluminum, or gallium can be used as such impurities.

[0195] Next, a conductive film ME3A is deposited on the conductive film IS3A (see 13A to 13C ).

[0196] The conductive film ME3A is a film that becomes the conductor ME3 (wiring CL) in a later step. In addition, a portion of the conductor ME3 is also used as one of a pair of electrodes of the capacitor C1. Therefore, it is preferable to use a highly conductive material for the conductive film ME3A.

[0197] The conductive film ME3A can use, for example, a material that can be used for the conductor ME1.

[0198] Furthermore, in order to reduce the resistance of the interface with the semiconductor SC1 (details will be described later) in contact with the conductor ME3 and in the vicinity of the interface, the conductive film ME3A may contain impurities specific to the semiconductor SC1. For example, if the semiconductor SC1 is a metal oxide such as In-M-Zn oxide, the conductive film ME3A may contain impurities such as water, hydrogen, nitrogen, or nitrides to reduce the resistance of the In-M-Zn oxide. In this case, the conductive film ME3A may be made of, for example, a metal film such as aluminum, ruthenium, titanium, tantalum, tungsten, or chromium; a nitride film such as Al-Ti nitride or titanium nitride; or an oxide film such as indium tin oxide or In-M-Zn oxide.

[0199] In addition, for example, when the semiconductor SC1 is a material containing silicon, the conductive film ME3A preferably contains impurities (for example, elements or ions) for diffusing into the silicon. For example, as the impurity, n-type impurities (donors) such as phosphorus or arsenic can be used. In addition, for example, as the impurity, p-type impurities (acceptors) such as boron, aluminum, or gallium can be used. In addition, the conductive film ME3A can also use a material that can form silicon and metal silicides contained in the semiconductor SC1. Examples of such materials include nickel, cobalt, molybdenum, tungsten, or titanium. Alternatively, the conductive film ME3A can also use a material with high electrical conductivity. Specifically, for example, as a material with high electrical conductivity, aluminum, copper, or silver can be mentioned. Alternatively, the conductive film ME3A can also use a material with high heat resistance. Specifically, for example, as a material with high heat resistance, titanium, molybdenum, tungsten, or tantalum can be mentioned.

[0200] Next, the conductive film ME3A is processed into a strip shape including an opening by photolithography, thereby forming the conductive body ME3. In particular, the opening is formed in the region where the conductive body ME1 and the conductive film ME2B overlap (see FIG. 14A to 14C ). This opening is formed in the region where the opening KK1 described in Embodiment 1 is provided. The conductor ME3 is formed so as to extend in a direction (X direction) parallel to the dot-dash line A1-A2. Note that for the photolithography method, reference can be made to 10A to 10C Photolithography as described.

[0201] Next, an insulating film IS4A is deposited on the conductor ME3 and the insulator IS3A (see Figures 15A to 15C ) When depositing the insulating film IS4A, for example, a deposition method such as sputtering, CVD, MBE, PLD, or ALD can be used.

[0202] Insulating film IS4A is a film that becomes insulator IS4 in a later step. Insulator IS4 is used, for example, as an interlayer film. Therefore, insulator IS4 preferably comprises an insulating material with a low relative dielectric constant. Using an insulating material with a low relative dielectric constant as an interlayer film can reduce parasitic capacitance between wirings.

[0203] The insulating film IS4A can be made of, for example, a material that can be used for the insulator IS1.

[0204] Then, the insulating film IS4A is polished by performing a planarization process such as CMP until the conductive body ME3 is exposed. 14A to 14C The area of ​​the conductive film ME3A removed in the process (including 14A to 14C The opening is formed in the manner described (refer to 16A to 16C ) That is, the insulating film IS4B is provided so as to be in contact with the side surface of the conductor ME3 and the top surface of the insulating film IS3A.

[0205] Next, the insulating film IS2A, the conductive film ME2B, the insulating film IS3A, and the insulating film IS4B are processed by photolithography to form the insulator IS2 having the opening KK1, the conductive film ME2, the insulator IS3, and the insulator IS4 (see FIG. 1 ). 17A to 17C ). In particular, the opening KK1 is formed in the 14A to 14C The region where the openings described above overlap is not included. Therefore, this photolithography method can also remove a portion of the conductive body ME3A. Furthermore, the above-described processing can be performed using either dry etching or wet etching, with dry etching being particularly suitable for micromachining. Furthermore, the insulating film IS2A, conductive film ME2B, insulating film IS3A, and insulating film IS4B can also be processed using different conditions.

[0206] In addition, 17A to 17C In the embodiment, by making the side surfaces of the opening KK1 (the side surfaces of the insulator IS2, the conductor ME2, the insulator IS3, and the conductor ME3) have a shape perpendicular to the XY plane, a smaller volume and a higher density can be achieved when setting the memory cell MC.

[0207] In addition, 17A to 17C In the embodiment, the side surfaces of the opening KK1 have a shape perpendicular to the XY plane, but may also have a tapered shape with a taper angle substantially perpendicular. Specifically, for example, each side surface of the insulator IS2, the conductor ME2, the insulator IS3, and the conductor ME3 may also have a tapered shape with a taper angle substantially perpendicular. Alternatively, each side surface of the insulator IS2, the conductor ME2, the insulator IS3, and the conductor ME3 may also have a tapered shape with a taper angle exceeding 0° and less than 60°.

[0208] In this specification, etc., a tapered shape refers to a shape in which at least a portion of the side surface of a component is inclined relative to the substrate surface. Furthermore, the angle formed by the inclined side surface and the substrate surface is referred to as the taper angle. In particular, in this specification, etc., a tapered shape having a taper angle greater than 0° and less than 90° is referred to as a positive taper shape, and a tapered shape having a taper angle greater than 90° and less than 180° is referred to as a negative taper shape.

[0209] Furthermore, byproducts generated during the etching process described above may form in a layered manner on the side surfaces of the opening KK1 (the side surfaces of each of the insulator IS2, the conductor ME2, the insulator IS3, and the conductor ME3). In this case, the layered byproducts are formed between the insulator IS2, the conductor ME2, the insulator IS3, and the conductor ME3 and the semiconductor film SC1A described later. Therefore, it is preferable to remove the layered byproducts formed so as to contact the insulator IS2, the conductor ME2, the insulator IS3, and the conductor ME3.

[0210] Next, the semiconductor film SC1A is deposited on the conductor ME1, the insulator IS2, the conductor ME2, the insulator IS3, the conductor ME3, and the insulator IS4 (see 18A to 18C ). Specifically, inside the opening KK1, the semiconductor film SC1A is deposited on the top surface of the conductor ME1, the side surface of the insulator IS2, the side surface of the conductor ME2, the side surface of the insulator IS3, and the side surface of the conductor ME3. In addition, outside the opening KK1, the semiconductor film SC1A is deposited on the top surface of the conductor ME3 and the top surface of the insulator IS4. That is, the semiconductor film SC1A is deposited on the bottom surface and the inner side surface of the opening KK1, as well as on the conductor ME3 and the insulator IS4. The semiconductor film SC1A can be deposited by a deposition method such as sputtering, CVD, MBE, PLD, or ALD. The semiconductor film SC1A is preferably deposited by the ALD method. As described above, the semiconductor film SC1A is preferably deposited thinly, and the thickness unevenness needs to be small. In this regard, the ALD method is a deposition method that alternately introduces precursors and reactants (for example, oxidants). Since the thickness can be adjusted according to the number of times the cycle is repeated, the thickness can be precisely adjusted. In addition, as Figure 18B and Figure 18C As shown, the semiconductor film SC1A needs to be deposited with high coverage on the bottom surface and inner side surfaces of the opening KK1. In particular, within the opening KK1, the semiconductor film SC1A is preferably deposited with high coverage on the top surface of the conductor ME1, the side surfaces of the conductor ME2, and the top and side surfaces of the conductor ME3. By utilizing the ALD method, atomic layers can be deposited on the bottom surface and inner side surfaces of the opening, thereby allowing the semiconductor film SC1A to be deposited with high coverage within the opening.

[0211] Note that when the side surface of the opening KK1 has a tapered shape, deposition of the semiconductor film SC1A is not limited to the ALD method, and for example, sputtering may be used.

[0212] Semiconductor film SC1A is a film that becomes semiconductor SC1 in a later process. A portion of semiconductor SC1 is used as a channel formation region for transistor MR, which is formed in a later process. Another portion of semiconductor SC1 is sometimes used as one of a pair of electrodes for capacitor C1, which is formed in a later process.

[0213] The semiconductor film SC1A can be, for example, a metal oxide used as an oxide semiconductor. In this case, the transistor MR is an OS transistor. The metal oxide preferably contains at least indium or zinc, for example. In particular, it preferably contains indium and zinc. In addition, it preferably contains element M. As element M, one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and antimony can be used. In particular, element M is preferably one or more of aluminum, gallium, yttrium, and tin. In addition, element M more preferably contains one or both of gallium and tin.

[0214] As an example, the semiconductor film SC1A preferably uses an In-Ga-Zn oxide. In particular, a metal oxide with an atomic ratio of In:Ga:Zn = 1:1:1 or a composition close thereto, a composition close thereto of 4:2:3 or a composition close thereto of 3:1:2 is more preferably used as the In-Ga-Zn oxide. Furthermore, as another example, the semiconductor film SC1A preferably uses an In-Zn oxide. In particular, a metal oxide with an atomic ratio of In:Zn = 4:1 or a composition close thereto is more preferably used as the In-Zn oxide.

[0215] In addition, the metal oxide preferably has a stacked structure of multiple oxide layers having different atomic number ratios of metal atoms. For example, a first metal oxide and a second metal oxide formed on the first metal oxide are considered as metal oxides. In the case where each metal oxide contains at least (In) and element M, the ratio of the number of atoms of element M contained in the first metal oxide relative to the number of atoms of all elements constituting the first metal oxide is preferably higher than the ratio of the number of atoms of element M contained in the second metal oxide relative to the number of atoms of all elements constituting the second metal oxide. In addition, the atomic number ratio of element M contained in the first metal oxide relative to In is preferably greater than the atomic number ratio of element M contained in the second metal oxide relative to In.

[0216] The energy of the conduction band bottom of the first metal oxide is preferably higher than the energy of the conduction band bottom of the second metal oxide. In other words, the electron affinity of the first metal oxide is preferably lower than the electron affinity of the second metal oxide.

[0217] Here, the energy level of the conduction band bottom changes smoothly at the junction of the first metal oxide and the second metal oxide. In other words, the above situation can also be expressed as the energy level of the conduction band bottom at the junction of the first metal oxide and the second metal oxide continuously changing or continuously joining. To this end, it is preferable to reduce the defect state density of the mixed layer formed at the interface between the first metal oxide and the second metal oxide.

[0218] Specifically, by making the first metal oxide and the second metal oxide contain the same element (as a main component) in addition to oxygen, a mixed layer with a low defect state density can be formed. For example, when the second metal oxide is In-Ga-Zn oxide (indium-gallium-zinc oxide), In-Ga-Zn oxide, Ga-Zn oxide, or gallium oxide can be used as the first metal oxide.

[0219] Specifically, the first metal oxide may have a composition of In:Ga:Zn = 1:3:4 [atomic ratio] or a composition close thereto, a composition close thereto of 1:3:2 [atomic ratio] or a composition close thereto of 1:1:0.5 [atomic ratio] or a composition close thereto. Furthermore, the second metal oxide may have a composition of In:Ga:Zn = 1:1:1 [atomic ratio] or a composition close thereto of 4:2:3 [atomic ratio] or a composition close thereto of 3:1:2 [atomic ratio] or a composition close thereto. The composition close thereto may fall within a range of ±30% of the desired atomic ratio.

[0220] In this case, the primary carrier path is through the second metal oxide. By providing the first metal oxide with this structure, the defect state density at the interface between the first and second metal oxides can be reduced. Consequently, the effect of interface scattering on carrier conduction is reduced, enabling the transistor MR to achieve high on-state current and high frequency characteristics.

[0221] Alternatively, the metal oxide may have a stacked structure comprising the second metal oxide and the first metal oxide formed on the second metal oxide. This structure can suppress increases in contact resistance between the conductor ME1 or the conductor ME2 and the metal oxide. Furthermore, deposition damage to the insulator GI1 caused by the second metal oxide can be reduced.

[0222] Furthermore, by using a metal oxide as the semiconductor film SC1A and providing a conductor in contact with the semiconductor SC1 (in 18A to 18CIn the embodiment of the present invention, the oxygen concentration near the conductors of semiconductor SC1 may decrease (corresponding to conductors ME1, ME2, and ME3). Furthermore, a metal compound layer containing the metal in the conductor and components of semiconductor SC1 may form near the conductors of semiconductor SC1. In this case, the carrier density in the region near the conductors of metal semiconductor SC1 increases, and this region becomes a low-resistance region.

[0223] Next, a sacrificial layer (not shown) is formed on the semiconductor film SC1A in such a manner as to embed the opening KK1. Then, a planarization process such as a CMP method is performed, and the sacrificial layer and the semiconductor film SC1A are polished until the conductor ME3 and the insulator IS4 are exposed. Then, the sacrificial layer embedded in the opening KK1 is removed (see FIG. 19A to 19C ) Thus, the semiconductor SC1 is provided in contact with the inner side surface of the opening KK1.

[0224] The semiconductor film SC1A can be made of, for example, a material containing silicon. Examples of this silicon include amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, or single crystal silicon. Furthermore, during the formation of the semiconductor film SC1A in the opening KK1, the interfaces in the semiconductor region forming the semiconductor film SC1A, which are in contact with the conductors ME1, ME2, and ME3, and their vicinities, are preferably converted into low-resistance regions. Thus, a low-resistance region and a semiconductor region are formed in the semiconductor SC1, so that the transistor MW can be a Si transistor.

[0225] Note that in this embodiment, a case where the semiconductor film SC1A includes a metal oxide serving as an oxide semiconductor is described.

[0226] Next, an insulator GI1 and a conductive film ME4A are sequentially formed on the conductor ME3, the insulator IS4, and the semiconductor SC1. In particular, the conductive film ME4A is formed so as to be embedded in the opening KK1 (see FIG. 1 ). 20A to 20C Specifically, the insulator GI1 is formed on the top surfaces of the semiconductor SC1, the conductor ME3, and the insulator IS4, and then the conductive film ME4A is deposited on the top surface of the insulator GI1 in a manner embedded in the opening KK1.

[0227] Thus, a transistor MR is formed in a region including the conductor ME1, the conductor ME2, the semiconductor SC1, the insulator GI1, and the conductive film ME4A. Furthermore, a capacitor C1 is formed in a region including the conductor ME3, the semiconductor SC1, the insulator GI1, and the conductive film ME4A. Furthermore, depending on circumstances, a transistor MD may also be formed in a region including the conductor ME2, the conductor ME3, the insulator IS3, the semiconductor SC1, the insulator GI1, and the conductive film ME4A.

[0228] The insulator GI1 is used as a gate insulating film of the transistor MR and is also used as a dielectric interposed between a pair of electrodes of the capacitor C1.

[0229] Therefore, as the insulator GI1, for example, an insulator composed of a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba, Sr)TiO3 (BST) is preferably used in a single layer or a stacked layer. Alternatively, an insulator having a high relative dielectric constant, such as an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium, may be used as the insulator GI1.

[0230] As transistors become increasingly miniaturized and highly integrated, problems such as leakage current may occur due to thinning of gate insulators. Using high-k materials as gate insulators can reduce the gate potential during transistor operation while maintaining the physical thickness.

[0231] Alternatively, the insulator GI1 may be an insulating layer formed by laminating the above-mentioned high-k material and silicon oxide or silicon oxynitride. This allows a thermally stable insulating layer having a high relative dielectric constant to be used as the gate insulating film of the transistor MR.

[0232] Note that when the semiconductor SC1 includes a metal oxide used as an oxide semiconductor, it is preferable to perform microwave treatment in an atmosphere containing oxygen after forming the insulator GI1 (before depositing the conductive film ME4A). Here, microwave treatment refers to, for example, treatment using an apparatus including a power supply that generates high-density plasma using microwaves. In addition, in this specification, etc., microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less. Note that in the case where the insulating film GI1 has a stacked structure, microwave treatment can also be performed at the stage of depositing a portion of the insulating film GI1. For example, in the case where the insulating film GI1 includes a silicon oxide film or a silicon oxynitride film, the microwave treatment can also be performed at the stage of depositing the silicon oxide film or the silicon oxynitride film.

[0233] In addition, microwave treatment can use high frequencies such as microwaves or RF, oxygen plasma, oxygen free radicals, etc. In addition, when performing microwave treatment, it is preferred to use a microwave processing device that includes a power supply that generates high-density plasma with microwaves. Here, the frequency of the microwave processing device is set to be greater than 300 MHz and less than 300 GHz, preferably greater than 2.4 GHz and less than 2.5 GHz, for example, 2.45 GHz. By using high-density plasma, high-density oxygen free radicals can be generated. In addition, the power of the power supply that applies microwaves of the microwave processing device is greater than 1000 W and less than 10000 W, preferably greater than 2000 W and less than 5000 W. In addition, the microwave processing device may also include a power supply that applies RF to one side of the substrate. In addition, by applying RF to one side of the substrate, the oxygen ions generated by the high-density plasma can be efficiently introduced into the semiconductor SC1 as a metal oxide. Through the action of plasma, microwaves, etc., the V contained in the region of the semiconductor SC1 can be reduced. O H is separated to remove hydrogen from the region. In other words, the V contained in the region can be reduced. O H. Thus, the oxygen vacancies and V O H and thus reduce the carrier concentration. In addition, by supplying oxygen radicals generated in the above-mentioned oxygen plasma to the oxygen vacancies formed in the region, the oxygen vacancies in the region can be further reduced, thereby reducing the carrier concentration.

[0234] The conductive film ME4A is a film that will become the conductor ME4 (node ​​FN or a portion of node FN) in a later step. Furthermore, the conductor ME4 serves as the gate electrode of the transistor MR and the other of the pair of electrodes of the capacitor C1. Therefore, a highly conductive material is preferably used for the conductive film ME4.

[0235] The conductive film ME4A can use, for example, a material that can be used for the conductor ME1.

[0236] Next, the conductive film ME4A is processed by photolithography to form a conductive film ME4B so as to expose a portion of the insulator GI1. In particular, the conductive film ME4B is processed so that the side surface of the conductive film ME4B overlaps with the inside of the opening KK1 (see FIG. 1 ). Figures 21A to 21C ). Note that for photolithography, please refer to 10A to 10C Photolithography as described.

[0237] Next, an insulating film IS5A is deposited on the insulator GI1 and the conductive film ME4B (see Figures 22A to 22C ) When depositing the insulating film IS5A, for example, a deposition method such as sputtering, CVD, MBE, PLD, or ALD can be used.

[0238] Insulating film IS5A is a film that becomes insulator IS5 in a later step. Insulator IS5 is used, for example, as an interlayer film. Therefore, insulator IS5 preferably comprises an insulating material with a low relative dielectric constant. Using an insulating material with a low relative dielectric constant as an interlayer film can reduce parasitic capacitance between wirings.

[0239] The insulating film IS5A can be made of, for example, a material that can be used for the insulator IS1.

[0240] In the subsequent manufacturing process, the conductor ME5 is formed on the insulator IS5. Therefore, in order to prevent oxidation of the conductor ME5, it is preferable to use silicon nitride, for example, as a barrier insulating film that suppresses oxygen diffusion in the insulator IS5.

[0241] Next, the insulating film IS5A and the conductive film ME4B are polished by performing a planarization process such as a CMP method to form an insulator IS5 and a conductor ME4 (see FIG. Figures 23A to 23C ). Thus, circuit elements such as wiring electrically connected to the memory cell MC and the transistor MW can be easily formed above the insulator IS5 and the conductor ME4.

[0242] By the above-described manufacturing method, the transistor MR and the capacitor C1 can be provided in the layer L1. In addition, depending on circumstances, the transistor MD may be provided above the transistor MR and below the capacitor C1.

[0243] Next, a method for manufacturing the layer L2 of the memory cell MC will be described.

[0244] A conductive film ME5A is deposited on the insulator IS5 and the conductive film ME4 (see Figures 24A to 24C ). When depositing the conductive film ME5A, for example, a deposition method such as sputtering, CVD, MBE, PLD, or ALD can be used.

[0245] The conductive film ME5A is a film that becomes the conductor ME5 (node ​​FN or a portion of node FN) in a later step. The conductor ME5 also serves as one of the source and drain electrodes of the transistor MW. Therefore, a highly conductive material is preferably used for the conductive film ME5.

[0246] The conductive film ME5A can use, for example, a material that can be used for the conductor ME1.

[0247] Next, the conductive film ME5A is processed by photolithography to form the conductive body ME5 so as to expose a portion of the insulator IS5. In particular, the conductive body ME5 is processed so as to overlap with the conductive body ME4 (see FIG. 1 ). Figures 25A to 25C ). Note that for photolithography, please refer to 10A to 10C Photolithography as described.

[0248] Next, an insulating film IS6A and a conductive film ME6A are sequentially deposited on the insulator IS5 and the conductive film ME5 (see Figures 26A to 26C ) When depositing each of the insulating film IS6A and the conductive film ME6A, for example, a deposition method such as sputtering, CVD, MBE, PLD, or ALD can be used.

[0249] Insulating film IS6A is a film that becomes insulator IS6 in a later step. Insulator IS6 is used, for example, as an interlayer film. Therefore, insulator IS6 preferably comprises an insulating material with a low relative dielectric constant. Using an insulating material with a low relative dielectric constant as an interlayer film can reduce parasitic capacitance between wirings.

[0250] The insulating film IS6A can be made of, for example, a material that can be used for the insulator IS1. In particular, when the semiconductor SC2 formed in a subsequent step is a metal oxide used as an oxide semiconductor, the insulating film IS6A is preferably made of, for example, silicon oxide, silicon oxynitride, or silicon oxide with vacancies. These materials can easily form a region containing oxygen that is released by heating, and the released oxygen can be supplied to the metal oxide. As a result, the carrier concentration of the metal oxide is reduced at and near the interface of the semiconductor SC2 in contact with the insulator IS6, and the interface of the semiconductor SC2 and the vicinity of the interface become i-type or substantially i-type. Therefore, the interface of the semiconductor SC2 and the vicinity of the interface are used as the channel formation region in the transistor MW.

[0251] The conductive film ME6A is a film that becomes the conductor ME6 (wiring WBL) in a later step. In addition, a portion of the conductor ME6 is also used as the other of the source electrode and the drain electrode of the transistor MW. Therefore, it is preferable to use a highly conductive material for the conductive film ME6.

[0252] The conductive film ME6A can use, for example, a material that can be used for the conductor ME1.

[0253] Next, the conductive film ME6A is processed into a stripe shape by photolithography, thereby forming a conductive film ME6B (see Figures 27A to 27C ). In particular, the conductive film ME6B is formed so as to extend in a direction parallel to the dot-dash line A3-A4 (Y direction) and overlap with the conductor ME5. Note that, regarding the photolithography method, reference can be made to 10A to 10C Photolithography as described.

[0254] Next, the insulating film IS6A and the conductive film ME6B are processed by photolithography to form an insulator IS6 having an opening KK2 and a conductive body ME5 (see FIG. Figures 28A to 28CIn particular, the opening KK2 is formed in the region overlapping with the conductor ME5. That is, the opening KK2 is an opening with the conductor ME5 as its bottom surface. Furthermore, the above-described processing can utilize dry etching or wet etching, with dry etching being particularly suitable for micromachining. Furthermore, the insulator IS6 and the conductive film ME6B can also be processed under different conditions.

[0255] In addition, Figures 28A to 28C Specifically, for example, each side surface of the insulator IS6 and the conductor ME6 may have a tapered shape with a taper angle of 45° or more and 90° or less.

[0256] Next, a semiconductor film SC2A is deposited on the conductor ME5, the insulator IS6, and the conductor ME6 (see Figures 29A to 29C ). Specifically, inside the opening KK2, the semiconductor film SC2A is deposited on the top surface of the conductor ME5, the side surface of the insulator IS6, and the side surface of the conductor ME6. In addition, outside the opening KK2, the semiconductor film SC2A is deposited on the top surface of the conductor ME6 and the top surface of the insulator IS6. In other words, the semiconductor film SC2A is deposited on the bottom surface and inner side surface of the opening KK2, the top surface and side surface of the conductor ME6, and the side surface of the insulator IS6. The semiconductor film SC2A can be deposited using a deposition method such as sputtering, CVD, MBE, PLD, or ALD. The semiconductor film SC2A is preferably deposited using the ALD method. In particular, when the material of the semiconductor film SC2B is the same as that of the semiconductor film SC2A, the description of the ALD method for depositing the semiconductor film SC2B can be referred to the description of the ALD method for depositing the semiconductor film SC1A.

[0257] The semiconductor film SC2A is a film that becomes the semiconductor SC2 in a later step. In addition, a portion of the semiconductor SC2 is used as a channel formation region of the transistor MW formed in a later step.

[0258] The semiconductor film SC2A can be made of a material that can be used for the semiconductor SC1, for example. Therefore, the transistor MW can be an OS transistor or a Si transistor.

[0259] Next, the semiconductor film SC2A is processed by photolithography to form the semiconductor SC2 so as to expose a portion of the insulator IS6 and a portion of the conductor ME6. In particular, the semiconductor SC2 is processed so as to overlap with the conductor ME5 (see FIG. 1 ). Figures 30A to 30C ). Note that for photolithography, please refer to 10A to 10C Photolithography as described.

[0260] Next, an insulator GI2 and a conductive film ME7A are sequentially deposited on the insulator IS6, the conductive film ME6, and the semiconductor SC2 (see Figures 31A to 31C In particular, the conductive film ME7A is deposited so as to fit into the opening KK2. When depositing each of the insulator GI2 and the conductive film ME7A, for example, a deposition method such as sputtering, CVD, MBE, PLD, or ALD can be used.

[0261] The insulator GI2 is used as a gate insulating film of the transistor MW.

[0262] For example, the insulator GI2 can use the same material as that used for the insulator GI1.

[0263] Furthermore, when the semiconductor SC2 includes a metal oxide serving as an oxide semiconductor, the semiconductor SC2A covered by the insulator GI2 may be subjected to microwave treatment, similarly to the semiconductor SC1. In particular, in this case, the conductors ME5 and ME6 shield the layer L1 from the effects of microwaves, high frequencies such as RF, and oxygen plasma, and the like. Therefore, the microwave treatment may not affect the layer L1.

[0264] The conductive film ME7A is a film that becomes the conductor ME7 (wiring WWL) in a later step. In addition, a portion of the conductor ME7 is also used as the gate electrode of the transistor MW. Therefore, it is preferable to use a material with high conductivity for the conductive film ME7.

[0265] The conductive film ME7A can use, for example, a material that can be used for the conductor ME1.

[0266] Next, the conductive film ME7A is processed into a stripe shape by photolithography, thereby forming the conductive film ME7 (see Figures 32A to 32C ). In particular, the conductive film ME7 is formed so as to extend in a direction parallel to the dot-dash line A1-A2 (X direction) and overlap with the conductor ME5. Note that, regarding the photolithography method, reference can be made to 10A to 10C Photolithography as described.

[0267] Next, an insulator IS7 is deposited on the insulator GI2 and the conductor ME7 (see Figures 2A to 2C ).

[0268] Insulator IS7 is used as an interlayer film as an example. Therefore, insulator IS7 preferably includes an insulating material with a low relative dielectric constant. By using an insulating material with a low relative dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

[0269] For example, the insulator IS7 can use the same material as that used for the insulator IS1.

[0270] Furthermore, the conductor ME7 is formed below the insulator IS7. Therefore, in order to prevent oxidation of the conductor ME7, it is preferable to use silicon nitride, for example, as a barrier insulating film that suppresses oxygen diffusion in the insulator IS7.

[0271] By the above manufacturing method, the transistor MW can be provided in the layer L2. In addition, by forming the layer L1 and the layer L2, the transistor MW can be manufactured. Figures 2A to 2C The memory cell MC is shown.

[0272] <Deformation Example> The method for manufacturing a semiconductor device according to one embodiment of the present invention is not limited to the method described above. In manufacturing a semiconductor device according to one embodiment of the present invention, the manufacturing method may be modified as appropriate. Furthermore, even if the structure of the semiconductor device changes due to a modification of the manufacturing method, the semiconductor device may still be considered as one embodiment of the present invention.

[0273] <<Variation Example 1>> Figures 33A to 33C The memory cell MC shown is Figures 2A to 2C A modified example of a memory cell MC, wherein Figures 2A to 2C The taper angle of the opening KK2 in the memory cell MC is 90°.

[0274] Figures 33A to 33C The memory cell MC shown can be realized by, for example, Figures 28A to 28C In the manufacturing process of the memory cell MC described above, the taper angle of the opening KK2 is set to 90° with respect to the substrate (not shown).

[0275] By setting the taper angle of the opening KK2 to 90°, the area for forming the opening KK2 can be reduced, thereby reducing the area of ​​the memory cell MC.

[0276] <<Variation Example 2>> Figures 34A to 34C The memory cell MC shown is Figures 2A to 2C A modified example of the memory cell MC is shown in FIG. 1 , in which the insulator IS6 is planarized in a region other than the opening KK2 .

[0277] Figures 34A to 34C The memory cell MC shown can be obtained, for example, by the following method: Figures 26A to 26C In the manufacturing process of the memory cell MC described above, after the insulating film IS6A is formed, the insulating film IS6A is polished by a planarization process such as the CMP method.

[0278] Specifically, for example, Figures 26A to 26CIn the manufacturing process of the memory cell MC, after forming the insulating film IS6A, the insulating film IS6A is processed into the insulating film IS6B by a planarization process such as a CMP method (see Figures 35A to 35B ). Then, in Figures 26A to 26C In the manufacturing process of the memory cell MC, the conductive film ME6A is deposited and the Figures 27A to 27C The manufacturing process after the process, which can be manufactured Figures 33A to 33C The memory cell MC is shown.

[0279] By flattening the insulator IS6, for example, formation defects of the conductor ME6 and the insulator GI2 on the insulator IS6A caused by steps of the insulator IS6 can be prevented. In other words, the yield of the memory cells MC can be improved.

[0280] <<Variation Example 3>> Figures 36A to 36C The memory cell MC shown is Figures 2A to 2C A modified example of a memory cell MC, wherein the memory cell MC is enlarged when viewed from a plane. Figures 2A to 2C The area of ​​the conductive body ME4 formed on the insulator GI1 in the memory cell MC.

[0281] Figures 36A to 36C The memory cell MC shown can be realized by, for example, Figures 21A to 21C The memory cell MC is manufactured by processing the conductive body ME4 to be formed on the conductive body ME3 and the insulator IS4 in the manufacturing process.

[0282] like Figures 36A to 36C By increasing the overlapping region of the conductors ME3 and ME4 as in the memory cell MC shown, the capacitance of the capacitor C1 can be increased. By increasing the capacitance of the capacitor C1, for example, the data retention time of the memory cell MC can be extended.

[0283] <<Variation Example 4>> Figures 37A to 37C The memory cell MC shown is Figures 2A to 2C A modified example of the memory cell MC is shown in FIG. 1 , in which a conductive body MEP serving as a contact plug is provided between the conductive body ME4 and the conductive body ME5 .

[0284] Figures 37A to 37C The memory cell MC shown is, for example, Figures 23A to 23C It is obtained by performing a process of providing the conductor MEP after the manufacturing process of the memory cell MC.

[0285] Specifically, for example, Figures 23A to 23CAfter the manufacturing process of the memory cell MC, an insulator ISP is formed as an interlayer film. Then, an opening is formed in the region of the insulator ISP that overlaps with the conductor ME4 using photolithography. Then, the conductor MEP is formed so as to fit into the opening, and then a planarization process such as CMP is performed until the insulator ISP is exposed and then polished. Then, a layer L2 is formed so as to provide the conductor ME5 on the conductor MEP, thereby manufacturing Figures 37A to 37C The memory cell MC is shown.

[0286] In particular, by increasing the area of ​​the conductive body MEP serving as the contact plug, the margin for fabricating the transistor MW can be increased. Consequently, even if, for example, the processing area for photolithography deviates, the transistor MW electrically connected to the capacitor C1 can be fabricated as long as the fabrication area for the transistor MW falls within the margin. This improves the yield of the memory cell MC.

[0287] As a deposition method of the conductor MEP, for example, sputtering, CVD, MBE, PLD, or ALD can be used. In addition, the conductor MEP can use, for example, a material that can be used for the conductor ME1. Figure 37B and Figure 37C The middle conductor MEP has a two-layer stacked structure, but the present invention is not limited thereto. The conductor MEP may have a single-layer structure or a stacked structure of three or more layers.

[0288] Insulator ISP is used as an interlayer film as an example. Therefore, insulator ISP preferably contains an insulating material with a low relative dielectric constant. By using an insulating material with a low relative dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

[0289] As a deposition method of the insulator ISP, for example, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. In addition, the insulator ISP can use, for example, a material that can be used for the insulator IS1.

[0290] <<Variation Example 5>> Figures 38A to 38C The memory cell MC shown is Figures 2A to 2C A modified example of the memory cell MC is shown, in which a conductor MS1 serving as a hard mask is provided on the top surface of the conductor ME3.

[0291] Figures 38A to 38C The memory cell MC shown is, for example, 13A to 13C The memory cell MC is obtained by performing a step of providing the conductor MS1 as a hard mask after the manufacturing step of the memory cell MC.

[0292] Specifically, for example, 13A to 13CAfter the manufacturing process of the memory cell MC, the conductor MS1 is formed as a hard mask material used in the subsequent photolithography. 14A to 14C Similarly, the opening KK1 is formed by the photolithography method. Figures 2A to 2C The same steps of the manufacturing method of the memory cell MC can be manufactured Figures 38A to 38C The memory cell MC is shown.

[0293] By providing the conductor MS1 as a hard mask material on the top surface of the conductor ME3, 14A to 14C In the photolithography method, the conductor ME3 is protected from the influence of the chemical solution used for etching processing.

[0294] Furthermore, conductor MS1 may be used as an auxiliary electrode in conductor ME3. In this case, conductor MS1 is preferably made of a material with a lower resistivity than conductor ME3. This reduces the resistance of conductor ME3 (wiring CL), thereby reducing power consumption of memory cell MC.

[0295] In addition, if Figure 38C As shown, the side surface of the conductor MS1 is substantially aligned with the side surface of the conductor ME3. In other words, the conductor MS1 and the conductor ME3 can be considered to constitute a conductor having a stacked structure.

[0296] The conductor MS1 can be deposited by sputtering, CVD, MBE, PLD, ALD, etc. The conductor MS1 is preferably deposited in the same deposition apparatus as the conductor ME3.

[0297] In addition, you can also 14A to 14C In the subsequent process 19A to 19C The conductor MS1 is removed by a planarization process such as a CMP method.

[0298] <<Variation Example 6>> Figures 39A to 39C The memory cell MC shown is Figures 2A to 2C A modified example of the memory cell MC is shown in FIG. 1 , in which the electrical conductor ME5 is formed not only on the electrical conductor ME4 but also on the insulator GI1 .

[0299] Figures 39A to 39C The memory cell MC shown can be replaced by a planarization process such as CMP. Figures 21A to 21C The memory cell MC is manufactured by polishing the conductive film ME4A until the insulator GI1 is exposed using a photolithography method in the manufacturing process.

[0300] Figures 39A to 39C The memory cell MC shown does not require the formation of an insulator IS5, so Figures 2A to 2CThe manufacturing process can be shortened compared to the memory cell MC.

[0301] <<Variation Example 7>> Figures 40A to 40C The memory cell MC shown is Figures 2A to 2C A modified example of the memory cell MC is shown, in which the end of the semiconductor SC1 is located on the top surface of the electrical conductor ME3.

[0302] Figures 40A to 40C The memory cell MC shown can be realized by, for example, 18A to 18C The memory cell MC is manufactured by processing the semiconductor film SC1A by photolithography (see Figures 41A to 41C ). In addition, Figures 41A to 41C After the manufacturing process, continue 20A to 20C The steps after the manufacturing step of the memory cell MC are sufficient.

[0303] Alternatively, a sacrificial layer may be deposited on the semiconductor film SC1A so as to embed the opening KK1 before the photolithography process, and the sacrificial layer may be removed after the photolithography process to form the semiconductor film SC1A. Figures 41A to 41C The semiconductor SC1 is shown.

[0304] exist Figures 2A to 2C In the memory cell MC, the semiconductor film SC1A is processed into the semiconductor SC1 by planarization. Figures 40A to 40C In the memory cell MC, the semiconductor film SC1A is processed into the semiconductor SC1 by photolithography to form a portion of the bottom surface and inner side surface of the opening KK1 and the conductor ME3. The method of processing the semiconductor film SC1A into the semiconductor SC1 is not limited to Figures 2A to 2C The manufacturing method of the memory cell MC can also be changed appropriately.

[0305] <<Variation Example 8>> Figures 42A to 42C The memory cell MC shown is Figures 40A to 40C A modified example of the memory cell MC is shown, in which the end of the insulator GI1 is located on the top surface of the semiconductor SC1.

[0306] As Figures 42A to 42C The manufacturing method of the memory cell MC shown in FIG. 18A to 18C After the manufacturing process of the memory cell MC, an insulator GI1 is deposited on the semiconductor film SC1A (see Figures 43A to 43C Then, the semiconductor film SC1A and the insulator GI1 are processed by photolithography so that the end of the semiconductor SC1 is located on the conductor ME3 or the insulator IS4 (see Figures 44A to 44C ). Then, by continuously 20A to 20CThe memory cell MC manufacturing process and subsequent processes can be manufactured Figures 42A to 42C storage unit MC.

[0307] Alternatively, a sacrificial layer may be deposited on the insulator GI1 in such a manner as to embed the opening KK1 before the photolithography process, and the sacrificial layer may be removed after the photolithography process, thereby forming the insulator GI1. Figures 42A to 42C The semiconductor SC1 and the insulator GI1 are shown.

[0308] <<Variation Example 9>> Figures 45A to 45C The memory cell MC shown is Figures 42A to 42C Another modified example of the memory cell MC is shown, in which the conductor ME4, the insulator GI1, and the semiconductor SC1 located above the opening KK1 are processed by photolithography.

[0309] As Figures 45A to 45C The manufacturing method of the memory cell MC shown in FIG. 18A to 18C After the manufacturing process of the memory cell MC, the insulator GI1 and the conductive film ME4A are sequentially deposited on the semiconductor film SC1A (see Figures 46A to 46C Then, the semiconductor film SC1A, the insulator GI1, and the conductive film ME4A are processed by photolithography so that the end of the semiconductor SC1 is located on the conductor ME3 or the insulator IS4 (see Figures 47A to 47C ). Then, by continuously Figures 22A to 22C The memory cell MC manufacturing process and subsequent processes can be manufactured Figures 45A to 45C storage unit MC.

[0310] <<Variation Example 10>> Figures 48A to 48C The memory cell MC shown is Figures 45A to 45C Another modified example of the memory cell MC is shown, in which an insulator IB3 is provided on the top surface of the conductor ME3, the top surface of the insulator IS4, the side surface of the semiconductor SC1, the side surface of the insulator GI1, and the side surface of the conductor ME4.

[0311] As Figures 48A to 48C The manufacturing method of the memory cell MC shown in FIG. Figures 47A to 47C After the manufacturing process of the memory cell MC, the insulator IB3 is deposited on the top surface of the conductor ME3, the top surface of the insulator IS4, the side surface of the semiconductor SC1, the side surface of the insulator GI1, and the side surface and top surface of the conductor ME4, and the insulator IS5A is deposited on the insulator IB3 (refer to Figures 49A to 49C ). Then, by continuously Figures 23A to 23C The memory cell MC manufacturing process and subsequent processes can be manufactured Figures 48A to 48C storage unit MC.

[0312] For example, insulator IB3 is preferably used as a barrier insulating film to prevent impurities such as water, hydrogen, nitrogen, and oxygen contained in insulator IS5 from infiltrating into conductors ME3, ME4, and semiconductor SC1. Therefore, insulator IB3 is preferably an insulating material that inhibits the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., NO, NO, or NO), and copper atoms (resistance to these impurities). Alternatively, an insulating material that inhibits the diffusion of oxygen (e.g., one or both of oxygen atoms and oxygen molecules) (resistance to these oxygen atoms and molecules) is preferably used.

[0313] As an insulator having the function of inhibiting the permeation of impurities such as water and hydrogen, and oxygen, for example, a single layer or a stack of insulators containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used. Specifically, as an insulator having the function of inhibiting the permeation of impurities such as water and hydrogen, and oxygen, for example, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide can be mentioned. In addition, as an insulator having the function of inhibiting the permeation of impurities such as water and hydrogen, and oxygen, for example, an oxide containing aluminum and hafnium (hafnium aluminate) can be mentioned. In addition, as an insulator having the function of inhibiting the permeation of impurities such as water and hydrogen, and oxygen, for example, metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon oxynitride, and silicon nitride can be mentioned.

[0314] In particular, aluminum oxide or silicon nitride is preferably used for the insulator IB3, thereby suppressing the diffusion of impurities such as water and hydrogen from the insulator IB3 to the capacitor C1 and the transistor MR.

[0315] Note that as a deposition method of the insulator IB3, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method can be used.

[0316] In addition, a barrier insulating film similar to the insulator IB3 may be provided in other parts. Figures 50A to 50C As shown, the insulator IB1 may be provided on the insulator IS1 as a barrier insulating film similar to the insulator IB3. This can prevent impurities such as water, hydrogen, nitrogen, and oxygen contained in the insulator IS1 from entering the conductor ME1, semiconductor SC1, and conductor ME2 located above the insulator IS1.

[0317] In addition, for example, Figures 51A to 51CAs shown, an insulator IB4 can be provided as a barrier insulating film similar to the insulator IB3 on the insulator IS5 and the conductive body ME5. The insulator IB4 includes a region of the opening KK2. This prevents impurities such as water, hydrogen, nitrogen, and oxygen contained in the insulator IS5 from entering the conductive body ME5, the semiconductor SC2, and the conductive body ME6 located above the insulator IS5.

[0318] In addition, for example, Figures 52A to 52C As shown, an insulator IB5 can be provided on the insulator IS6 as a barrier insulating film similar to the insulator IB3. The insulator IB5 includes a region of the opening KK2. This can suppress the intrusion of impurities such as water, hydrogen, nitrogen, and oxygen from below the conductor ME6.

[0319] like Figures 48A to 48C The memory cell MC shown, Figures 50A to 50C The memory cell MC shown, Figures 51A to 51C The memory cell MC shown and Figures 52A to 52C By providing a blocking insulating film as in the memory cell MC shown, diffusion of impurities into the conductor and semiconductor can be suppressed.

[0320] <<Variation Example 11>> Figures 53A to 53C The memory cell MC shown is Figures 2A to 2C In a modified example of the memory cell MC, a conductive body serving as the gate electrode of the transistor MR and the other of the pair of electrodes of the capacitor C1 has a stacked-layer structure of a conductive body ME4 and a conductive body ME4S.

[0321] Specifically, in Figures 53A to 53C In the memory cell MC shown, for example, a highly covering conductor ME4 is formed on the bottom and inner side surfaces of the opening KK1, and a highly conductive conductor ME4S is formed on the conductor ME4. Therefore, the conductor ME4S serves as an auxiliary electrode for the conductor ME4.

[0322] exist Figures 53A to 53C In the memory cell MC, it is preferable to use the ALD method having high coverage as a deposition method for the conductor ME4.

[0323] The conductor ME4S may be deposited by, for example, sputtering, CVD, MBE, PLD, or ALD. The conductor ME4S is preferably a material that has a lower resistivity than the conductor ME4 among the materials that can be used for the conductor ME1.

[0324] In addition, auxiliary electrodes similar to the conductor ME4S may be provided in other parts. Figures 54A to 54CAs shown in FIG. 1 , the conductor ME7S may be provided on the conductor ME7 as an auxiliary electrode similar to the conductor ME4S. Figures 55A to 55C As shown, the conductor ME2S and the conductor ME6S may be provided on the conductor ME2 and the conductor ME6, respectively, as auxiliary electrodes similar to the conductor ME4S.

[0325] The conductors ME2S, ME6S, and ME7S can be deposited using, for example, sputtering, CVD, MBE, PLD, or ALD. Furthermore, for the conductor ME2S, for example, a material that can be used for the conductor ME1 and has a lower resistivity than the conductor ME2 is preferably used. Similarly, for the conductor ME6S, for example, a material that can be used for the conductor ME1 and has a lower resistivity than the conductor ME6 is preferably used. Similarly, for the conductor ME7S, for example, a material that can be used for the conductor ME1 and has a lower resistivity than the conductor ME7 is preferably used.

[0326] like Figures 53A to 53C The memory cell MC shown, Figures 54A to 54C The memory cell MC shown and Figures 55A to 55C As in the memory cell MC shown, by providing an auxiliary electrode on the conductor, the resistance of the wiring including the conductor and the auxiliary electrode can be reduced, thereby reducing the power consumption of the memory cell MC.

[0327] <<Variation Example 12>> Figures 56A to 56C The memory cell MC shown is Figures 2A to 2C A modified example of the memory cell MC in which the conductor ME5 is not provided is different from Figures 2A to 2C The memory cells MC are different.

[0328] exist Figures 56A to 56C In the memory cell MC, for example, an insulating film IS6A and a conductive film ME6A are sequentially formed on the insulator IS5 and the conductor ME4, and an opening KK2 is provided in each of the insulating film IS6A and the conductive film ME6A in a region overlapping with the conductor ME4.

[0329] As mentioned above, with Figures 2A to 2C The storage unit MC is different, Figures 56A to 56C The memory cell MC has a structure in which the conductor ME5 is not provided, so Figures 56A to 56C The manufacturing process of the memory cell MC is Figures 2A to 2C The manufacturing process of the memory cell MC can be shortened compared with the conventional method.

[0330] Furthermore, the above-described modified examples of the memory cell MC may also adopt a structure in which the conductor ME5 is not provided. Figures 36A to 36CThe manufacturing method of the memory cell MC removes the step of forming the conductor ME5, and can manufacture Figures 57A to 57C The memory cell MC is shown.

[0331] In addition, for example, by Figures 37A to 37C The manufacturing method of the memory cell MC removes the step of forming the conductor ME5, and can manufacture Figures 58A to 58C The memory cell MC shown. In addition, for example, by Figures 39A to 39C The manufacturing method of the memory cell MC removes the step of forming the conductor ME5, and can manufacture Figures 59A to 59C The memory cell MC shown. In addition, for example, by Figures 53A to 53C The manufacturing method of the memory cell MC removes the step of forming the conductor ME5, and can manufacture Figures 60A to 60C The memory cell MC is shown.

[0332] Note that when the step of forming the conductor ME5 is removed from the method for manufacturing the memory cell MC, the semiconductor SC2 included in the transistor MW is in direct contact with the conductor ME4. Therefore, in order to facilitate the formation of the semiconductor SC2 on the conductor ME4 (more precisely, in order to facilitate the formation of the opening KK2 in the region of the insulator IS6 that overlaps with the conductor ME4), the conductor ME4 preferably has a large area. For example, Figures 60A to 60C In the memory cell MC, Figures 61A to 61C By increasing the area of ​​the conductor ME4S as in the memory cell MC shown, a connection failure between the conductor ME4 and the semiconductor SC2 can be prevented.

[0333] in addition, Figures 62A to 62C A structural example of a memory cell MC is shown in which the conductor ME5 is not provided and the conductor ME4 and the semiconductor SC2 are easily in contact with each other. Figures 62A to 62C The memory cell MC shown is Figures 2A to 2C A modified example of the memory cell MC is shown, in which a conductor MEQ is provided on the conductor ME4 and the insulator GI1, and a transistor MW is formed on the conductor MEQ.

[0334] As Figures 62A to 62C The manufacturing method of the memory cell MC shown in FIG. Figures 22A to 22C After the manufacturing process of the memory cell MC, an opening is formed in the region including the conductor ME4 in the insulator IS5A. Note that the area of ​​the opening is preferably larger than the area of ​​the conductor ME4 when viewed from a planar perspective (not shown). Next, the conductor MEQ is deposited so as to embed the opening, and then polished until the insulator IS5 is exposed by a planarization process. Then, by continuously performing Figures 26A to 26C The memory cell MC manufacturing process and subsequent processes can be manufactured Figures 62A to 62C storage unit MC.

[0335] In addition, with Figures 61A to 61C Likewise, in Figures 62A to 62C In the memory cell MC, the area of ​​the conductor MEQ is increased when viewed from above, thereby facilitating the formation of the semiconductor SC2 on the conductor MEQ (more precisely, the opening KK2 is easily formed in the region of the insulator IS6 that overlaps with the conductor MEQ). This prevents poor connection between the conductor MEQ and the semiconductor SC2.

[0336] As a deposition method of the conductor MEQ, for example, sputtering, CVD, MBE, PLD, or ALD can be used. In addition, the conductor MEQ can use, for example, the material that can be used for the conductor ME1. Figure 60B and Figure 60C The middle conductor MEQ has a two-layer stacked structure, but the present invention is not limited thereto. The conductor MEQ may have a single-layer structure or a stacked structure of three or more layers.

[0337] <<Variation Example 13>> Figures 63A to 63C The memory cell MC shown is Figures 60A to 60C ( Figures 61A to 61C ) another modification of the memory cell MC, wherein the semiconductor SC2 of the transistor MW is embedded inside the opening KK1 instead of the conductor ME4S, which is similar to Figures 60A to 60C ( Figures 61A to 61C )'s storage cells MC are different.

[0338] As Figures 63A to 63C The manufacturing method of the memory cell MC shown in FIG. 19A to 19C After the manufacturing process of the memory cell MC, conductive films that will become the insulator GI1 and the conductor ME4 are deposited sequentially from below. Then, using photolithography, the conductor ME4 is formed so that this conductive film remains inside the opening KK1, on a portion of the conductor ME3, and on a portion of the conductor IS4. Next, an insulating film that will become the insulator IS6 is deposited on the conductor ME4 and the insulator GI1, and a conductive film that will become the conductor ME6 is deposited on the insulating film that will become the insulator IS6. Next, using photolithography, the conductive film that will become the conductor ME6 is processed into wiring extending in the Y direction. Furthermore, using photolithography, an opening is formed in the conductive film that will become the conductor ME6 and the insulating film that will become the insulator IS6 in the region that overlaps with the opening KK1. Note that this opening corresponds to the bottom and side surfaces of the conductor ME4 in layer L1. Furthermore, this processing forms the insulator IS6 and the conductor ME6. Next, the semiconductor SC1 is deposited in layer L1, embedded in the opening, and located on the side surfaces of the insulator IS6 and the side and top surfaces of the conductor ME6. Then, by continuously Figures 30A to 30CThe memory cell MC manufacturing process and subsequent processes can be manufactured Figures 63A to 63C storage unit MC.

[0339] Figures 63A to 63C The memory cell MC shown does not require the formation of the conductor ME4S and the insulator IS5, so Figures 60A to 60C ( Figures 61A to 61C ) can shorten the manufacturing process compared to the memory cell MC.

[0340] <<Variation Example 14>> Figures 64A to 64C The memory cell MC shown is Figures 2A to 2C A modified example of the memory cell MC is shown in FIG. 1 , in which a conductor MB3 serving as an auxiliary electrode is formed below the conductor ME3.

[0341] As Figures 64A to 64C The manufacturing method of the memory cell MC shown in FIG. 13A to 13C In the manufacturing process of the memory cell MC, a conductive film MB3B (see FIG. 1 ) serving as the conductor MB3 is formed between the insulating film IS3A and the conductive film ME3A. Figures 65A to 65C Note that the conductive film MB3B can be obtained by depositing a conductive film to be the conductive film MB3B on the insulator IS3A and processing the conductive film using photolithography. 14A to 14C Similarly, the conductive film ME3A is processed into a strip shape including an opening, thereby forming the conductive body ME3. In particular, the opening is formed in the region where the conductive body ME1 and the conductive film ME2B overlap (see Figures 66A to 66C ).

[0342] Then, with Figures 15A to 15C Similarly, an insulating film IS4A (not shown) is deposited on the insulating film IS3A and the conductor ME3. 16A to 16C Likewise, the insulating film IS4A is polished by a planarization process using a CMP method or the like until the conductive body ME3 is exposed (not shown).

[0343] Then, with 17A to 17C Similarly, the insulating film IS2A, the conductive film ME2B, the conductor MB3B, the insulating film IS3A, and the insulating film IS4B are processed by photolithography to form the insulator IS2, the conductor ME2, the conductor MB3, the insulator IS3, and the insulator IS4 having the opening KK1 (see FIG. Figures 67A to 67C ). Then, by continuously 18A to 18C The memory cell MC manufacturing process and subsequent processes can be manufactured Figures 64A to 64C storage unit MC.

[0344] Although Figures 64A to 64CThe memory cell MC has a structure in which the conductor MB3 serving as an auxiliary electrode is formed below the conductor ME3. However, the semiconductor device according to one embodiment of the present invention may have a structure in which the auxiliary electrode is formed above the conductor ME3.

[0345] Figures 68A to 68C The memory cell MC shown is Figures 2A to 2C A modified example of the memory cell MC is shown in FIG. 1 , in which a conductor MT3 serving as an auxiliary electrode is formed on the upper portion of the conductor ME3.

[0346] As Figures 68A to 68C The manufacturing method of the memory cell MC shown in FIG. 16A to 16C In the manufacturing process of the memory cell MC, a conductive film MT3B (see FIG. 1 ) serving as the conductive body MT3 is formed on the insulating film IS4B and the conductive body ME3. Figures 69A to 69C Note that the conductive film MT3B can be obtained by depositing a conductive film to be the conductive film MT3B on the insulating film IS4B and the conductive film ME3A and processing the conductive film using a photolithography method.

[0347] Then, with 17A to 17C Similarly, the insulating film IS2A, the conductive film ME2B, the insulating film IS3A, the insulating film IS4B and the conductor MT3B are processed by photolithography to form the insulator IS2, the conductor ME2, the insulator IS3, the conductor MT3 and the insulator IS4 having the opening KK1 (see Figures 70A to 70C ). Then, by continuously 18A to 18C The memory cell MC manufacturing process and subsequent processes can be manufactured Figures 68A to 68C storage unit MC.

[0348] like Figures 64A to 64C The memory cell MC shown and Figures 68A to 68C As in the memory cell MC shown, by providing an auxiliary electrode under or on the conductor, the resistance of the wiring including the conductor and the auxiliary electrode can be reduced, thereby reducing the power consumption of the memory cell MC.

[0349] <<Variation Example 15>> Figures 71A to 71C The memory cell MC shown is Figures 2A to 2C A modified example of the memory cell MC is shown, in which the conductor ME3 sandwiches the opening KK1 in the Y direction.

[0350] Figures 71A to 71C The memory cell MC can be changed by 14A to 14CIn the manufacturing process of the memory cell MC shown, the conductive film ME3A is processed into the shape of the conductor ME3. Specifically, the conductive film ME3A is processed by photolithography so that the opening KK1 is sandwiched between two conductors ME3 in the X direction.

[0351] In addition, the shape of the conductor ME3 located around the opening KK1 can also be Figures 72A to 72C The shape of the memory cell MC shown in FIG. Figures 71A to 71C The shape of the memory cell MC is shown. Figures 72A to 72C In the illustrated memory cell MC, the conductor ME3 forms a U-shape around the opening KK1 when viewed from above.

[0352] like Figures 71A to 71C The memory cell MC shown or Figures 72A to 72C By changing the shape of the conductor ME3 surrounding the opening KK1, as in the memory cell MC shown in FIG. 1 , the capacitance of the capacitor C1 included in the memory cell MC can be increased or decreased. When the capacitance of the capacitor C1 increases, the time for which the memory cell MC retains data is prolonged, sometimes causing the operating speed of the memory cell MC to decrease. During the manufacturing stage of the memory cell MC, if the operating speed of the memory cell MC is to be increased, the capacitance of the capacitor C1 can be decreased. If the data retention time of the memory cell MC is to be prolonged, the capacitance of the capacitor C1 can be increased.

[0353] <<Variation Example 16>> Figures 73A to 73C The memory cell MC shown is Figures 2A to 2C A modified example of the memory cell MC is shown in FIG. 1 , in which the semiconductor SC2 extends in the Y direction.

[0354] Specifically, if Figure 74 As shown, in Figures 73A to 73C In the memory cell MC, the semiconductor SC2 in the cell array CA is located on the side and bottom surfaces of the opening KK2 and is formed on a portion of the conductor ME6 along the same Y direction as the conductor ME6.

[0355] Figures 73A to 73C The memory cell MC shown can be manufactured, for example, by the following method: Figures 30A to 30C In the manufacturing process of the memory cell MC, the semiconductor film SC2A is processed by photolithography to form the semiconductor SC2 so that a portion of the insulator IS6 and a portion of the conductor ME6 are exposed and extend in the Y direction.

[0356] exist Figures 73A to 73CIn the memory cell MC shown, a semiconductor SC2 is formed on a conductor ME6 extending in the Y direction. In this case, in order to reduce the resistance of the interface of the semiconductor SC2 in contact with the conductor ME6 and the vicinity of the interface, the conductor ME6 may also contain impurities specific to the semiconductor SC2. Specifically, for example, if the semiconductor SC2 is a metal oxide (e.g., In-M-Zn oxide), the conductor ME6 may also contain impurities such as water, hydrogen, nitrogen, or nitrides to reduce the resistance of the metal oxide. By reducing the resistance of the region of the semiconductor SC2 located on the conductor ME6, this region of the semiconductor SC2 serves as an auxiliary electrode for the conductor ME6. This reduces the resistance of the wiring WBL including the conductor ME6, thereby reducing the power consumption of the memory cell MC.

[0357] In addition, Figures 73A to 73C In the illustrated memory cell MC, the conductor ME6 and the semiconductor SC2 are formed by photolithography at different timings, but the conductor ME6 and the semiconductor SC2 may be formed simultaneously.

[0358] Figures 75A to 75C The memory cell MC shown is Figures 73A to 73C A modified example of the memory cell MC is shown, in which the conductor ME6 and the semiconductor SC2 are formed simultaneously.

[0359] Therefore, if Figure 76 As shown, in Figures 75A to 75C In the memory cell MC, the semiconductor SC2 in the cell array CA is formed so as to substantially overlap with the conductor ME6.

[0360] As Figures 75A to 75C The manufacturing process of the memory cell MC shown in FIG. Figures 26A to 26C After the manufacturing process of the memory cell MC, the insulating film IS6A and the conductive film ME6A are processed by photolithography to form an insulator IS6 having an opening KK2 and a conductive film ME6C (see Figures 77A to 77C Then, a semiconductor film SC2A is deposited on the side and bottom surfaces of the conductor ME6C and the opening KK2 (see Figures 78A to 78C ). In addition, after the semiconductor film SC2A is deposited, the conductor ME6C and the semiconductor SC2 are processed by photolithography so as to extend in the Y direction, thereby forming the conductor ME6 and the semiconductor SC2 (see Figures 79A to 79C ). Then, by continuously Figures 31A to 31C The memory cell MC manufacturing process and subsequent processes can be manufactured Figures 75A to 75C storage unit MC.

[0361] exist Figures 75A to 75C In the manufacturing process of the memory cell MC shown in FIG. 1 , the insulator IS6 and the conductor ME6C are formed simultaneously. Figures 2A to 2C The memory cell MC can be manufactured in a shorter manufacturing process compared to Figures 75A to 75C The memory cell MC is shown.

[0362] In addition, Figures 75A to 75C In the illustrated memory cell MC, in order to increase the resistance of the interface of the semiconductor SC2 in contact with the conductor ME6 and the vicinity of the interface, the conductor ME6 may also contain a material that promotes the increase in resistance of the semiconductor SC2. Specifically, for example, when the semiconductor SC2 is a metal oxide (e.g., In-M-Zn oxide), the conductor ME6 may also contain oxygen to increase the resistance of the metal oxide. Thus, by supplying oxygen contained in the conductor ME6 to the semiconductor SC2, the resistance of the interface of the semiconductor SC2 in contact with the conductor ME6 and the vicinity of the interface can be increased. By increasing the resistance of the interface of the semiconductor SC2 and the vicinity of the interface, the effective insulator thickness of the semiconductor SC2 and the insulator GI2 located above the conductor ME6 is increased, thereby reducing the parasitic capacitance between the conductor ME6 and the conductor ME7 overlapping the conductor ME6. By reducing this parasitic capacitance, the drive frequency of the transistor MW can be increased, thereby increasing the write speed of the memory cell MC.

[0363] In this case, it is preferable to use a material such as indium oxide or indium tin oxide that has a low resistance value even when containing oxygen as the conductor ME6.

[0364] <<Variation Example 17>> Figures 80A to 80C The memory cell MC shown is Figures 34A to 34C In the modified example of the memory cell MC, the heights of the conductor ME7, the insulator GI2 and the insulator IS8 described later are substantially the same. In addition, the conductor ME7 is formed only inside the opening KK2, so Figures 80A to 80C In the memory cell MC, the conductor ME8 formed on the conductor ME7 and the insulator GI2 is used as the wiring WWL.

[0365] As Figures 80A to 80C The manufacturing method of the memory cell MC shown in FIG. Figures 35A to 35C After the manufacturing process Figures 27A to 31CIn the manufacturing process, the conductive film ME7A is embedded in the opening KK2. Next, the conductive film ME7A is polished using a planarization process such as CMP until the insulator GI2 is exposed, thereby forming the conductive body ME7. An insulating film, which will become the insulator IS8, is then formed over the insulator GI2 and the conductive body ME7, filling the step of the insulator GI2. The insulating film, which will become the insulator IS8, is then polished again using a planarization process such as CMP until the insulator GI2 is exposed, thereby forming the insulator IS8. This results in a memory cell MC in which the heights of the conductive bodies ME7, GI2, and IS8 are substantially uniform.

[0366] In the above-described method of embedding the conductor ME7 in the opening KK2, the conductor ME7 is formed by selecting the conductive film to be the conductor ME7 in self-alignment without using a mask. This allows the conductor ME7 to be formed without requiring any alignment, thus reducing the area occupied by the transistor MW.

[0367] As a deposition method of the conductor ME8, for example, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. can be used. In addition, the conductor ME8 can use the material which can be used for the conductor ME1, for example.

[0368] The insulator IS8 can be deposited by, for example, sputtering, CVD, MBE, PLD, or ALD. The insulator IS8 can be made of, for example, the same material as that used for the insulator IS1.

[0369] In the subsequent manufacturing process, the conductor ME8 is formed on the insulator IS8. Therefore, in order to prevent oxidation of the conductor ME8, it is preferable to use silicon nitride, for example, as a barrier insulating film that suppresses oxygen diffusion in the insulator IS8.

[0370] In addition, with Figures 80A to 80C Similarly, the memory cell MC Figures 81A to 81C The memory cell MC shown has a structure in which the heights of the conductor ME7 and the insulator GI2 are roughly the same after the conductor ME7 is embedded in the opening KK2 through a planarization process such as CMP, but the conductor ME7 is used as the wiring WWL and the conductor ME8 is not used as the wiring WWL.

[0371] Specifically, if Figure 82A As shown, Figures 81A to 81C The memory cell MC has the following structure: in the cell array CA, the opening KK2 is arranged along the row direction (X direction), and the conductor ME7 is formed in such a way as to embed the opening KK2. Therefore, in the cell array CA, the conductor ME6 arranged along the column direction is arranged in the Figure 81B The opening KK3 is included in the middle so as not to be electrically connected to the conductor ME5.

[0372] Figure 82B : is a schematic perspective view showing the conductive body ME5, the conductive body ME6 and the conductive body ME7 around the transistor MW of the memory cell MC. Figure 82B In the embodiment, after the conductor ME5 is formed, an insulator IS6 (not shown) including an opening KK2 is formed. Then, a conductive film to become the conductor ME6 is deposited on the side and bottom surfaces of the opening KK2 and on the insulator IS6.

[0373] Next, a conductive body ME6 is formed by photolithography by providing an opening KK3 in the conductive film to expose the conductive body ME5 and extend in the Y direction. At this time, the conductive bodies ME5 and ME6 are preferably made of different materials to achieve etching selectivity. Specifically, for example, it is preferable to use indium tin oxide as the conductive body ME5 and to use a material other than indium tin oxide, such as tantalum, titanium, or tungsten, as the conductive body ME6.

[0374] Next, a semiconductor SC2 (not shown) is formed in the region including the opening KK2. At this time, the semiconductor SC2 is formed along the X direction. Then, an insulator GI2 (not shown) is formed on the semiconductor SC2 and the conductor ME6.

[0375] Next, a conductive film, which will become the conductor ME7, is formed on the insulator GI2. A planarization process, such as CMP, is then performed to embed the conductor ME7 within the opening KK2. This formation method allows the conductive film, which will become the conductor ME7, to be selected in a self-aligned manner, without the use of a mask. Consequently, the wiring WWL including the conductor ME7 can be formed without requiring alignment, making it less likely to cause misalignment due to mask misalignment. Consequently, the yield of memory cells MC can be improved.

[0376] Notice, Figures 81A to 81C The memory cell MC can also be changed appropriately. For example, Figures 81A to 81C In the memory cell MC, when the conductive body ME7 is formed by planarization, the conductive body ME7 may be polished to the level of the conductive body ME6 instead of being polished to the level of the insulator GI2. In other words, the conductive body ME7 may be polished until the conductive body ME6 is exposed by planarization. Figures 83A to 83C yes Figures 81A to 81C A modified example of the memory cell MC is shown in FIG. 1 , in which the conductive body ME7 is polished by the planarization process until the conductive body ME6 is exposed.

[0377] In addition, if Figure 84 As shown, in Figures 83A to 83C In the memory cell MC, the opening KK2 in the cell array CA is provided along the row direction. In addition, the semiconductor SC2 and the conductor ME7 are provided along the row direction in a manner embedded in the opening KK2. Figure 84 The cell array CA shown is Figure 82A The illustrated cell array CA is different in that the semiconductor SC2 is formed only inside the opening KK2.

[0378] <<Variation Example 18>> Figures 85A to 85C The memory cell MC shown is Figures 2A to 2C A modified example of the memory cell MC is a structural example in which an opening KK2 is formed along the Y direction.

[0379] Specifically, if Figure 86A As shown, Figures 85A to 85C The memory cell MC has a structure in which an opening KK2 is provided along the column direction (Y direction) in the cell array CA, and a semiconductor SC2 is formed along the opening KK2. Therefore, in the cell array CA, for example, two conductive bodies ME6 provided along the column direction form a pair as a wiring WBL extending in the column direction (Y direction).

[0380] Figure 86B 1 is a schematic perspective view showing the conductive body ME6, semiconductor SC2 and conductive body ME7 around the transistor MW of the memory cell MC. Figure 86B In the embodiment, an insulating film that becomes the insulator IS6 (not shown) and a conductive film that becomes the conductor ME6 are formed in sequence. The conductive film extends in the column direction (Y direction). Next, an opening KK2 that reaches the conductor ME5 (not shown) is formed in the region of the conductive film. Thus, the insulating film is formed in the insulator IS6, and the conductive film is formed in the conductor ME6. Next, a semiconductor SC2 is formed on the conductor ME6 and the conductor ME5. The semiconductor SC2 extends in the column direction (Y direction). In addition, an insulator GI2 (not shown) is deposited on the conductor ME6 and the semiconductor SC2. Next, the conductor ME7 is formed along the X direction. Then, an insulator IS7 (not shown) is formed in a manner that covers the conductor ME6, the semiconductor SC2, the insulator GI2, and the conductor ME7.

[0381] in addition, Figures 85A to 85C The memory cell MC may also have a structure in which a conductive film to become the conductor ME6 and a semiconductor film to become the semiconductor SC2 are processed together by photolithography on the insulator IS6. In this case, the ends of the conductor ME6 and the semiconductor film SC2 may overlap when viewed from a plane. For example, Figure 87AAs in the cell array CA shown, a conductive film to become the conductor ME6 and a semiconductor film to become the semiconductor SC2 are processed together on the insulator IS6 by photolithography, so that the conductor ME6 and the semiconductor SC6 have a shape overlapping each other.

[0382] also, Figures 85A to 85C The memory cell MC can also adopt a structure in which the semiconductor SC2 covers the conductor ME6. Figure 87B As in the cell array CA shown in the figure, the semiconductor SC2 may have a shape longer than the width of the conductor ME6 extending in the Y direction and covering the conductor ME6.

[0383] In addition, the insulators, conductors, and semiconductors disclosed in this specification and other materials can be formed using PVD (Physical Vapor Deposition) or CVD. Examples of PVD methods include sputtering, resistance heating evaporation, electron beam evaporation, MBE (Molecular Beam Epitxy), and PLD. Examples of CVD methods include plasma CVD and thermal CVD. In particular, examples of thermal CVD methods include MOCVD (Metal Organic Chemical Vapor Deposition) and ALD.

[0384] Since the thermal CVD method is a deposition method that does not use plasma, it has the advantage of not causing defects caused by plasma damage.

[0385] Deposition using thermal CVD can be performed as follows: source gas and oxidant are simultaneously supplied into a process chamber, the pressure in the process chamber is set to atmospheric pressure or reduced pressure, and a reaction occurs near or on the substrate to deposit on the substrate.

[0386] In addition, deposition using the ALD method can also be performed in the following way: the pressure in the processing chamber is set to atmospheric pressure or reduced pressure, the source gases used for the reaction are introduced into the processing chamber in sequence, and the gases are repeatedly introduced in this order. For example, two or more source gases are supplied into the processing chamber in sequence by switching each switch valve (also called a high-speed valve). In order to prevent the mixing of multiple source gases, an inert gas (for example, argon or nitrogen) is introduced at the same time as or after the introduction of the first source gas, and then the second source gas is introduced. Note that when the inert gas is introduced at the same time, the inert gas is used as a carrier gas. In addition, the inert gas can be introduced at the same time as the introduction of the second source gas. In addition, the first source gas can be discharged by vacuum pumping without introducing an inert gas, and then the second source gas can be introduced. The first source gas adheres to the surface of the substrate to deposit a first thinner layer, and the second source gas introduced thereafter reacts with the first thinner layer, whereby the second thinner layer is stacked on the first thinner layer to form a thin film. By repeatedly introducing gases in this order until the desired thickness is obtained, a thin film with good step coverage can be formed. Since the thickness of the film can be adjusted by the number of times the gas is introduced in sequence, the ALD method can accurately adjust the thickness and is suitable for manufacturing micro FETs.

[0387] Thermal CVD methods such as MOCVD and ALD can be used to form various films such as the metal films, semiconductor films, and inorganic insulating films disclosed in the above-described embodiments. For example, when depositing an In-Ga-Zn-O film, trimethylindium (In(CH3)3), trimethylgallium (Ga(CH3)3), and dimethylzinc (Zn(CH3)2) are used. Furthermore, without being limited to the above combinations, triethylindium (In(C2H5)3) may be used instead of trimethylindium, triethylgallium (Ga(C2H5)3) may be used instead of trimethylgallium, and diethylzinc (Zn(C2H5)2) may be used instead of dimethylzinc.

[0388] For example, when forming a hafnium oxide film using an ALD deposition apparatus, two gases are used: a source gas obtained by vaporizing a liquid containing a solvent and a hafnium precursor compound (e.g., hafnium alkoxide or hafnium amide such as tetrakisdimethylamide (TDMAH, Hf[N(CH3)2]4)); and ozone (O3) as an oxidizing agent. Other examples of the material include hafnium tetrakis(ethylmethylamide).

[0389] For example, when forming an aluminum oxide film using a deposition apparatus utilizing the ALD method, two gases are used: a source gas obtained by vaporizing a liquid containing a solvent and an aluminum precursor compound (e.g., trimethylaluminum (TMA, Al(CH3)3)), and H2O serving as an oxidant. Other materials include tris(dimethylamide)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedione).

[0390] For example, when forming a silicon oxide film using a deposition apparatus utilizing the ALD method, hexachlorodisilane is deposited on the deposition surface, and radicals of an oxidizing gas (eg, O 2 or nitrous oxide) are supplied to react with the deposited material.

[0391] For example, when depositing a tungsten film using an ALD deposition apparatus, WF6 gas and B2H6 gas are repeatedly introduced sequentially to form an initial tungsten film, and then WF6 gas and H2 gas are repeatedly introduced sequentially to form a tungsten film. Note that SiH4 gas can also be used instead of B2H6 gas.

[0392] For example, when an In-Ga-Zn-O film is deposited as an oxide semiconductor film using a deposition apparatus utilizing an ALD method, a precursor (generally, for example, sometimes referred to as a precursor or metal precursor) and an oxidant (generally, for example, sometimes referred to as a reactant, reactant, or non-metallic precursor) are repeatedly introduced in sequence to form the film. Specifically, for example, an In(CH3)3 gas as a precursor and an O3 gas as an oxidant are introduced to form an In-O layer, then a Ga(CH3)3 gas as a precursor and an O3 gas as an oxidant are introduced to form a GaO layer, and then a Zn(CH3)2 gas as a precursor and an O3 gas as an oxidant are introduced to form a ZnO layer. Note that the order of these layers is not limited to the above example. In addition, these gases can also be used to form mixed oxide layers such as an In-Ga-O layer, an In-Zn-O layer, or a Ga-Zn-O layer. Note that although H2O gas obtained by bubbling water with an inert gas (e.g., argon) can also be used instead of O3 gas, it is preferred to use O3 gas that does not contain H. Alternatively, In(C2H5)3 gas may be used instead of In(CH3)3 gas. Alternatively, Ga(C2H5)3 gas may be used instead of Ga(CH3)3 gas. Alternatively, Zn(C2H5)2 gas may be used instead of Zn(CH3)2 gas.

[0393] The structure described in this embodiment mode can be appropriately combined with other structures described in this embodiment mode. For example, the structure, configuration, and method described in this embodiment mode can be appropriately combined with other structures, configurations, and methods described in this embodiment mode.

[0394] This embodiment mode can be appropriately combined with other embodiment modes described in this specification. For example, the configuration, structure, and method described in this embodiment mode can be appropriately combined with the configuration, structure, and method described in other embodiment modes.

[0395] (Implementation 3) In this embodiment, a modification example of the memory cell MC of the semiconductor device described in the above embodiment will be described.

[0396] <Memory Cell Modification Example 1> Figure 88A A semiconductor device as one embodiment of the present invention is shown. Figure 1A A modified example of a memory cell MC. Figure 1A Similarly, the memory cell MC Figure 88A The memory cell MCA is an example of a memory cell called a gain cell, which includes a transistor MW, a transistor MR, and a capacitor C1. Note that Figure 88A The memory cell MCA is connected to Figure 1A The memory cell MC is different in that it is not electrically connected to the wiring SL.

[0397] In particular, in this specification and the like, the structure of the memory cell MCA in which the transistor MW and the transistor MR each use an OS transistor may be different from Figure 1A The memory cell MC is similarly called a NOSRAM (registered trademark).

[0398] Next, explain Figure 88A Examples of the planar structure and cross-sectional structure of the memory cell MCA.

[0399] Figure 89A The memory cell MCA shown is Figure 88A Example of a planar structure of a memory cell MCA, Figure 89B and Figure 89C They are Figure 88A An example of a cross-sectional structure of a memory cell MCA. Figure 89B It is along Figure 89A A cross-sectional view of the portion indicated by the dashed line A1-A2 of the plan view shown, Figure 89C It is along Figure 89A The cross-sectional view of the portion indicated by the dashed line A3-A4 of the plan view shown. Figure 89A In the plan view, some components are omitted for clarity.

[0400] Notice, Figures 89A to 89C The memory cell MCA shown is Figures 2A to 2C The memory cell MC shown is a modified example, so Figures 89A to 89C The memory cell MCA is Figures 2A to 2C The same structure of the memory cell MC can be referred to Figures 2A to 2C The following describes the memory cell MC. Figures 89A to 89C The memory cell MCA is Figures 2A to 2C The memory cell MC has a different structure.

[0401] Figures 89A to 89C The memory cell MCA is shown with Figures 2A to 2C The difference between the memory cell MC shown in FIG. 1 and FIG. 2 is that the conductor ME2 does not extend in the Y direction but is formed only on the side surface outside the opening KK1. Figures 2A to 2C The memory cell MC shown is different. Figures 89A to 89C The memory cell MCA is not electrically connected to the wiring SL.

[0402] exist Figures 89A to 89C In the example, the conductor ME1 is also used as the wiring RBL. Figures 89A to 89C In addition, the conductor ME3 is also used as a wiring CL as an example. Figures 89A to 89C Extends in the X direction.

[0403] The conductor ME6 is also used as a wiring WBL as an example. Figures 89A to 89C In addition, the conductor ME7 is also used as a wiring WWL as an example. Figures 89A to 89C Extends in the X direction.

[0404] In addition, Figures 89A to 89C The structure of the memory cell MCA, with Figures 2A to 2C Similarly to the memory cell MC, a transistor MD may be formed above the transistor MR and below the capacitor C1. For the transistor MD, reference can be made to the transistor MD described in Embodiment 1.

[0405] In addition, the transistor MD is described in Figure 88A The circuit structure of the memory cell MC is sometimes Figure 88B The circuit structure shown in Figure 88B In the circuit, the first terminal of transistor MD is electrically connected to the second terminal of capacitor C1 and wiring CL, the second terminal of transistor MD is electrically connected to the first terminal of transistor MR, and the gate of transistor MD is electrically connected to the first terminal of capacitor C1, the second terminal of transistor MW, and the gate of transistor MR.

[0406] like Figures 89A to 89C As shown, a transistor MD is sometimes formed above the transistor MR and below the capacitor C1. As described in Embodiment 2, when the semiconductor SC1 is a metal oxide used as an oxide semiconductor, when impurities are added to the semiconductor SC1 from the insulator IS3 at the interface of the semiconductor SC1 in contact with the insulator IS3 and in the vicinity of the interface, the interface of the semiconductor SC1 and the vicinity of the interface become low-resistance, thereby allowing the transistor MD to be regarded as a wiring (or a normally-on transistor) rather than a switching element. In other words, Figure 88B The circuit structure shown is considered as Figure 88Acircuit structure.

[0407] Next, the description includes Figure 88A or Figure 88B A structural example of a storage device of the memory cell MCA.

[0408] Figure 90A The memory device MDVA shown is a memory device according to one embodiment of the present invention, and includes a cell array CA, a circuit WBD, a circuit WWD, a circuit CSD, and a circuit RBD. Figure 3A A modification example of the storage device MDV is that the storage device MDVA is Figure 3A The difference between the memory device MDV and the memory device MDV is that: the cell array CA includes memory cells MCA[1,1] to memory cells MCA[m,n] but does not include memory cells MC[1,1] to memory cells MC[m,n]; and the wiring SL[1] to wiring SL[m] are not set.

[0409] In addition, Figure 90A In the example, the cell array CA includes a plurality of memory cells MCA. Specifically, in the cell array CA, the plurality of memory cells MCA are arranged in a matrix of m rows and n columns. As an example, Figure 90A The cell array CA abstractly shows a memory cell MCA[1,1], a memory cell MCA[m,1], a memory cell MCA[1,n], and a memory cell MCA[m,n].

[0410] Note, about Figure 90A The storage device MDVA is Figure 3A The same structure of the storage device MDV can be referred to Figure 3A Therefore, in Figure 90A In the storage device MDVA, the work of writing to the storage unit MCA can be done with Figure 3A The same is done for the memory device MDV. In addition, regarding the operation of reading from the memory cell MCA, when the transistor MD is regarded as a wiring (when the transistor MD is in a normally open state), it can be performed in the same manner as Figure 3A The same is done for the storage device MDV.

[0411] in addition, Figures 89A to 89C The structure of the memory cell MCA shown can be changed to Figures 91A to 91C The structure of the memory cell MCA is shown.

[0412] Figures 91A to 91C The memory cell MCA shown has Figures 89A to 89C The conductive body ME2 and the insulator IS3 are not provided in the memory cell MCA. Figures 91A to 91CThe memory cell MCA shown does not have a transistor MD formed therein, so Figures 91A to 91C The memory cell MCA can be read stably.

[0413] <Memory Cell Modification Example 2> Figure 88C A semiconductor device as one embodiment of the present invention is shown. Figure 1A A modified example of the memory cell MC. Figure 88C The memory cell MCB is an example of a memory cell called DRAM (Dynamic Random Access Memory), which includes a transistor MW and a capacitor C1. Note that Figure 88C The memory cell MCB and Figure 1A The memory cell MC is different in that: the transistor MR is not provided; and the memory cell MC is not electrically connected to the wiring SL.

[0414] In particular, in this specification and the like, a structure of a memory cell MCB using an OS transistor as the transistor MW may be referred to as DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory).

[0415] Figure 88C The memory cell MCB includes a transistor MW and a capacitor C1. Note that regarding the transistor MW and the capacitor C1, reference can be made to Figure 1A The memory cell MC includes a transistor MW and a capacitor C1.

[0416] A first terminal of transistor MW is electrically connected to wiring BL, a second terminal of transistor MW is electrically connected to a first terminal of capacitor C1, and a gate of transistor MW is electrically connected to wiring WL. A second terminal of capacitor C1 is electrically connected to wiring CL.

[0417] The wiring BL is used as a data line (sometimes referred to as a bit line) as an example, which transmits write data held in the memory cell MC or data read from the memory cell MC.

[0418] The wiring WL is used as a wiring (sometimes referred to as a word line) for selecting a memory cell MC to be written into or read from data.

[0419] As an example, wiring CL is used as a wiring for supplying a fixed potential to the second terminal of capacitor C1. This fixed potential can be, for example, a high-level potential, a low-level potential, a ground potential, or a negative potential. Alternatively, wiring CL can be used to supply a variable potential (sometimes referred to as a pulse potential or pulse voltage) rather than a fixed potential.

[0420] Next, explain Figure 88C Examples of the planar structure and cross-sectional structure of the memory cell MCB.

[0421] Figure 92A The memory cell MCB shown is Figure 88C Example of the planar structure of the memory cell MCB, Figure 92B and Figure 92C They are Figure 88C An example of a cross-sectional structure of a memory cell MCB. Figure 92B It is along Figure 92A A cross-sectional view of the portion indicated by the dashed line A1-A2 of the plan view shown, Figure 92C It is along Figure 92A The cross-sectional view of the portion indicated by the dashed line A3-A4 of the plan view shown. Figure 92A In the plan view, some components are omitted for clarity.

[0422] Notice, Figures 92A to 92C The memory cell MCB shown is Figures 2A to 2C The memory cell MC shown is a modified example, so Figures 92A to 92C The memory cell MCB is Figures 2A to 2C The same structure of the memory cell MC can be referred to Figures 2A to 2C The following describes the memory cell MC. Figures 92A to 92C The memory cell MCB is Figures 2A to 2C The memory cell MC has a different structure.

[0423] Figures 92A to 92C The memory cell MCB is shown with Figures 2A to 2C The memory cell MC shown is different in that the electrical conductor ME1 , the electrical conductor ME2 , and the insulator IS3 are not provided.

[0424] exist Figures 92A to 92C In the example, the conductor ME3 is used as the wiring CL. Figures 92A to 92C In addition, the conductor ME7 is also used as a wiring WL as an example. Figures 92A to 92C In addition, the conductor ME6 is also used as a wiring BL as an example. Figures 92A to 92C Extends in the Y direction.

[0425] Next, the description includes Figure 88C A structural example of a storage device of the memory cell MCB.

[0426] Figure 90B The memory device MDVB shown is a memory device according to one embodiment of the present invention, and includes a cell array CA, a circuit WD, and a circuit BD.

[0427] Furthermore, the cell array CA includes a plurality of memory cells MCB. Specifically, in the cell array CA, the plurality of memory cells MCB are arranged in a matrix of m rows and n columns (m is an integer greater than 1, and n is an integer greater than 1). As an example, Figure 90B The cell array CA abstractly shows a memory cell MCB[1,1], a memory cell MCB[m,1], a memory cell MCB[1,n], and a memory cell MCB[m,n].

[0428] Note that in Figure 90B In FIG, the symbol of the memory cell MCB located at the x-th row and the y-th column is represented as MCB[x, y].

[0429] Figure 90B The memory cells MCB[1,1] to MCB[m,n] shown can each use Figure 88C The memory cell MCB is shown.

[0430] As an example, in the cell array CA, the equivalent of Figure 88C The wiring WL[1] to the wiring WL[m] of the wiring WL extend in the row direction. In addition, as an example, in the cell array CA, the wiring WL[1] to the wiring WL[m] are equivalent to Figure 1C The wiring CL[1] to the wiring CL[m] of the wiring CL extend in the row direction respectively.

[0431] Note that in Figure 90B In FIG, the wiring WL extending on the x-th row is represented by the symbol WL[x]. Similarly, the wiring CL extending on the x-th row is represented by the symbol CL[x].

[0432] As an example, in the cell array CA, the equivalent of Figure 88C The wirings BL[1] to BL[n] of the wirings BL extend in the column direction, respectively.

[0433] Note that in Figure 90B In FIG. 1 , the wiring BL extending on the y-th column is represented by BL[y].

[0434] In addition, Figure 90B In FIG, the circuit WD is electrically connected to the wiring WL[1] to the wiring WL[m]. In addition, the circuit BD is electrically connected to the wiring BL[1] to the wiring BL[n].

[0435] Circuit WD, for example, has the function of selecting a memory cell MC in a row to be written or read in the cell array CA. Specifically, circuit WD, for example, has the function of sending a select signal to any one of wirings WL[1] to WL[m] and sending a non-select signal to the other wirings. Note that when the write transistor included in memory cell MCB is an n-channel transistor, the select signal is preferably a high-level potential, and the non-select signal is preferably a low-level potential.

[0436] Circuit BD, for example, has the function of sending write data to the memory cell MCB selected by circuit WD in the cell array CA, and the function of reading read data from the memory cell MCB. Specifically, circuit BD, for example, sends write data to each of wirings BL[1] to BL[n] during a write operation. Thus, the write data sent to each column is written to the memory cell MC of the row selected by circuit WD. In addition, circuit BD, for example, obtains data read from memory cell MCB from each of wirings BL[1] to BL[n] during a read operation. Then, circuit BD amplifies the read data using a sense amplifier or the like (converting the data into digital data) or converts the data into analog data using a current-voltage conversion circuit or the like, and outputs the data to the outside of circuit BD.

[0437] Since circuit BD converts read data into digital data or analog data, circuit BD preferably includes a current-voltage conversion circuit, an analog-to-digital conversion circuit, a digital-to-analog conversion circuit, or a sense amplifier.

[0438] In addition, you can Figures 92A to 92C The structure of the memory cell MCB shown is changed to Figures 93A to 93C The structure of the memory cell MCB is shown.

[0439] Figures 93A to 93C The memory cell MCB shown has Figures 92A to 92C The insulator IS2 is not provided in the memory cell MCB. Figures 93A to 93C The memory cell MCB shown does not require a process for forming the insulator IS2, so it is similar to Figures 92A to 92C Compared with the memory cell MCB, Figures 93A to 93C The memory cell MCB can shorten the manufacturing process.

[0440] The structure described in this embodiment mode can be appropriately combined with other structures described in this embodiment mode. For example, the structure, configuration, and method described in this embodiment mode can be appropriately combined with other structures, configurations, and methods described in this embodiment mode.

[0441] This embodiment mode can be appropriately combined with other embodiment modes described in this specification. For example, the configuration, structure, and method described in this embodiment mode can be appropriately combined with the configuration, structure, and method described in other embodiment modes.

[0442] (Implementation 4) In this embodiment, a structural example of a memory device including the semiconductor device described in the above embodiment will be described.

[0443] Figure 94A 1 is a perspective schematic diagram showing a structural example of the storage device 100 . Figure 94B 1 is a block diagram showing a structural example of a memory device 100. The memory device 100 includes a drive circuit layer 50 and N layers (N is an integer greater than or equal to 1) of memory layers 60. In addition, each memory layer 60 includes a plurality of memory cells 10 arranged in a matrix of m rows and n columns. Figure 94B An example is shown in which the storage layer 60_k is configured with storage cell 10[1,1], storage cell 10[m,1] (here, m is an integer greater than 1), storage cell 10[1,n] (here, n is an integer greater than 1), storage cell 10[m,n], and storage cell 10[i,j] (here, i is an integer greater than 1 and less than m, and j is an integer greater than 1 and less than n).

[0444] Note that the memory layer 60 can be, for example, the cell array CA described in Embodiment 1. Alternatively, the memory cell 10 may be the memory cell MC described in Embodiments 1 to 3.

[0445] The N-layer memory layer 60 is provided on the driver circuit layer 50. By providing the N-layer memory layer 60 on the driver circuit layer 50, the occupied area of ​​the memory device 100 can be reduced. In addition, the storage capacity per unit area can be increased.

[0446] In this embodiment and other embodiments, the first storage layer 60 is referred to as storage layer 60_1, the second storage layer 60 is referred to as storage layer 60_2, and the third storage layer 60 is referred to as storage layer 60_3. Furthermore, the k-th storage layer 60 (k is an integer greater than or equal to 1 and less than or equal to N) is referred to as storage layer 60_k, and the N-th storage layer 60 is referred to as storage layer 60_N. Furthermore, in this embodiment and other embodiments, when describing matters relating to the entire N-layer storage layer 60 or matters common to each layer of the N-layer storage layer 60, they may be simply referred to as "storage layer 60."

[0447] <Structural Example of Driving Circuit Layer 50> The driving circuit layer 50 includes a PSW 22 (power switch), a PSW 23 , and a peripheral circuit 31 . The peripheral circuit 31 includes a peripheral circuit 41 , a control circuit 32 , and a voltage generating circuit 33 .

[0448] In storage device 100, various circuits, signals, and voltages can be appropriately selected as needed. Alternatively, other circuits or signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, while signal RDA is an external output signal. Signal CLK is a clock signal.

[0449] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may also be generated in control circuit 32.

[0450] The control circuit 32 is a logic circuit that controls the overall operation of the memory device 100. For example, the control circuit performs logical operations on signals CE, GW, and BW to determine the operating mode (e.g., write operation and read operation) of the memory device 100. Alternatively, the control circuit 32 generates control signals for the peripheral circuit 41 to implement the aforementioned operating mode.

[0451] Voltage generating circuit 33 generates a negative voltage. Signal WAKE controls the input of signal CLK to voltage generating circuit 33. For example, when signal WAKE is at an H level, signal CLK is input to voltage generating circuit 33, and voltage generating circuit 33 generates a negative voltage.

[0452] The peripheral circuit 41 is a circuit for writing and reading data from the memory cell 10 and includes a row decoder 42 , a column decoder 44 , a row driver 43 , a column driver 45 , an input circuit 47 , an output circuit 48 , and a sense amplifier 46 .

[0453] The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying a row to be accessed, and the column decoder 44 is a circuit for specifying a column to be accessed.

[0454] The row driver 43 has a function to select a write word line or a read word line (for example, a line described later) designated by the row decoder 42. Figure 95The row driver 43 may be a circuit including the circuit WWD and the circuit CSD described in Embodiment 1. Alternatively, the row driver 43 may be a circuit WD described in Embodiment 3.

[0455] The column driver 45 has the function of writing data to the memory cell 10, reading data from the memory cell 10, and holding the read data. The column driver 45 has the function of selecting a write bit line or a read bit line (for example, a bit line described later) designated by the column decoder 44. Figure 95 The column driver 45 may function as any one of the wirings BL[1] to BL[n] shown in the figure. Specifically, for example, the column driver 45 may be a circuit including the circuit WBD and the circuit RBD described in Embodiment 1. Alternatively, for example, the column driver 45 may be the circuit BD described in Embodiment 3.

[0456] Input circuit 47 holds signal WDA. The data held in input circuit 47 (first data in the above embodiment) is output to column driver 45. The output data from input circuit 47 is the data (Din) written to memory cell 10. The data (Dout) read from memory cell 10 by column driver 45 is output to output circuit 48. In the above embodiment, the read data (Dout) is processed as the result of the calculation. Output circuit 48 holds Dout. Furthermore, output circuit 48 outputs Dout to the outside of memory device 100. The data output from output circuit 48 is signal RDA.

[0457] PSW22 has the function of controlling the supply of VDD to the peripheral circuit 31. PSW23 has the function of controlling the supply of VHM to the row driver 43. Here, the high power supply voltage of the memory device 100 is VDD, and the low power supply voltage is GND (ground potential). In addition, VHM is a high power supply voltage for making the word line high, which is higher than VDD. The signal PON1 is used to switch the open state and closed state of PSW22, and the signal PON2 is used to switch the open state and closed state of PSW23. Figure 94B In the embodiment, the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but it may be more than one. In this case, a power switch may be provided for each power domain.

[0458] Next, the electrical connection between the peripheral circuit 41 and the memory layer 60 will be described.

[0459] Figure 95 4 is a block diagram showing an example of the structure of the peripheral circuit 41 and the memory layer 60_k. Figure 95In the embodiment, the row decoder 42 and the row driver 43 are electrically connected to the wiring WL[1] to the wiring WL[m], and the column decoder 44, the column driver 45 and the read amplifier 46 are electrically connected to the wiring BL[1] to the wiring BL[n].

[0460] Note that the wirings WL[1] to WL[m] are equivalent to the wirings WWL[1] to WWL[m], the wirings CL[1] to CL[m], and the wirings SL[1] to SL[m] described in Embodiment 1. That is, the wirings WL[1] to WL[m] serve as word lines.

[0461] Furthermore, wiring BL[1] to wiring BL[n] are equivalent to wiring WBL[1] to wiring WBL[n] and wiring RBL[1] to wiring RBL[n] described in Embodiment 1. In other words, wiring BL[1] to wiring BL[n] serve as bit lines.

[0462] The memory cell 10[i,j] arranged in the i-th row and the j-th column is electrically connected to the wiring WL[i] and the wiring BL[j].

[0463] like Figure 95 As shown, by electrically connecting the memory layer 60_k and the peripheral circuit 41, data can be written to the memory layer 60_k and data can be read from the memory layer 60_k.

[0464] then, Figure 96 An example of a cross-sectional structure of a storage device 100 according to one embodiment of the present invention is shown. Figure 96 The memory device 100 shown includes a plurality of memory layers 60 (described in Embodiment 1) above the driver circuit layer 50. Figure 3A To avoid repeated description, description of the memory layer 60 is omitted in this embodiment.

[0465] in addition, Figure 96 The transistor 300 included in the driver circuit layer 50 is shown as an example. Transistor 300 is provided on a substrate 301 and includes an element isolation layer 312, a conductor 316, an insulator 315, an insulator 317, a semiconductor region 313 formed as a portion of the substrate 301, and low-resistance regions 314a and 314b that serve as source and drain regions. Substrate 301 can be, for example, a semiconductor substrate, particularly a single-crystal substrate made of silicon. If substrate 301 is a single-crystal substrate made of silicon, transistor 300 can be a Si transistor. Alternatively, an SOI substrate can be used as substrate 301. In this case, the transistor can be provided by processing the SOI substrate to form a convex semiconductor film.

[0466] For example, by adopting a structure in which the top surface and the side surfaces in the channel width direction of the semiconductor region 313 are covered with the conductor 316 via an insulator 315 serving as a gate insulator, the transistor 300 can have a fin structure. By forming a fin-type transistor 300, the effective channel width can be increased, thereby improving the on-state characteristics of the transistor 300. In addition, since the influence of the electric field of the gate electrode can be increased, the off-state characteristics of the transistor 300 can be improved. In addition, the transistor 300 can also have a planar structure instead of a fin structure.

[0467] Alternatively, the plurality of transistors 300 included in the driver circuit layer 50 may each be either a p-channel transistor or an n-channel transistor. In this case, the circuit included in the driver circuit layer 50 is a unipolar circuit. Alternatively, the plurality of transistors 300 included in the driver circuit layer 50 may each be either a p-channel transistor or an n-channel transistor. In this case, the circuit included in the driver circuit layer 50 is a CMOS circuit.

[0468] In the transistor 300, the channel formation region of the semiconductor region 313 and the region near it, as well as the low resistance region 314a and the low resistance region 314b used as the source region or the drain region preferably include a silicon-based semiconductor, specifically, preferably include single crystal silicon. Alternatively, the above-mentioned regions can also be formed using, for example, germanium, silicon germanium, gallium arsenide, aluminum gallium arsenide, or gallium nitride. Alternatively, the transistor 300 can also use silicon that applies stress to the lattice to change the interplanar spacing and control the effective mass. Alternatively, the transistor 300 can also be a HEMT (High Electron Mobility Transistor) using gallium arsenide and aluminum gallium arsenide, for example.

[0469] As the conductor 316 used as the gate electrode, a semiconductor material such as silicon containing an element imparting n-type conductivity, such as arsenic or phosphorus, or an element imparting p-type conductivity, such as boron or aluminum, can be used. Alternatively, as the conductor 316, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used.

[0470] Furthermore, since the material of the conductor 316 determines the work function, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, one or both of titanium nitride and tantalum nitride are preferably used as the conductor. To achieve both conductivity and embedding properties, a stack of one or both of tungsten and aluminum is preferably used as the conductor, with tungsten being particularly preferred for its heat resistance.

[0471] Furthermore, since the material of the conductor determines the work function, the threshold voltage of the transistor can be adjusted by selecting the conductor material. Specifically, titanium nitride or tantalum nitride, or both, is preferably used as the conductor. To achieve both conductivity and embeddability, a laminate of one or both tungsten and aluminum is preferably used as the conductor, with tungsten being particularly preferred for its heat resistance.

[0472] An element isolation layer 312 is provided to isolate a plurality of transistors formed on the substrate 301. The element isolation layer can be formed using, for example, a LOCOS (Local Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, or a mesa isolation method.

[0473] Notice, Figure 96 The structure of the transistor 300 shown is only an example and is not limited to the above structure. An appropriate transistor may be used according to the circuit structure or driving method.

[0474] A wiring layer, including interlayer films, wiring, and plugs, may be provided between the various structures. Furthermore, the wiring layer may be provided in multiple layers depending on the design. Furthermore, in this specification and other contexts, wiring and plugs electrically connected to the wiring may be considered a single component. This means that a portion of a conductor may function as wiring, and a portion of the conductor may function as a plug.

[0475] For example, an insulator 320, an insulator 321, an insulator 324, and an insulator 326 are sequentially stacked as interlayer films on the transistor 300. Furthermore, a conductor 328 and the like are embedded in the insulators 320 and 321. Furthermore, a conductor 330 is embedded in the insulators 324 and 326. Furthermore, the conductors 328 and 330 function as contact plugs or wiring.

[0476] As the insulator 320 , the insulator 321 , and the insulator 326 , for example, one or more selected from silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, and aluminum nitride can be used.

[0477] In this specification, etc., "oxynitride" refers to a material containing more oxygen than nitrogen, while "oxynitride" refers to a material containing more nitrogen than oxygen. For example, "silicon oxynitride" refers to a material containing more oxygen than nitrogen, while "silicon oxynitride" refers to a material containing more nitrogen than oxygen.

[0478] The insulator 321 can also be used as a planarization film for planarizing steps generated by the transistor 300 and the like covered by the insulator 320. For example, to improve the flatness of the top surface of the insulator 321, the top surface can be planarized by a planarization process using a chemical mechanical polishing (CMP) method.

[0479] As the insulator 324, it is preferable to use an insulating film (referred to as a blocking insulating film) having a barrier property that can prevent impurities such as water and hydrogen from diffusing from the substrate 301 or the transistor 300 into the region above the insulator 324 (for example, the cell array CA in which the transistors MW and MR are provided). Therefore, as the insulator 324, it is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, and water molecules (not allowing these impurities to pass through easily). In addition, depending on the circumstances, it is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (for example, N2O, NO, or NO2), and copper atoms (not allowing the above oxygen to pass through easily) as the insulator 324. Alternatively, it is preferable to have a function of suppressing the diffusion of oxygen (for example, one or both of oxygen atoms and oxygen molecules).

[0480] As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD method can be used.

[0481] The amount of hydrogen released can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, when the amount of hydrogen released is converted to the amount per unit area of ​​the insulator 324 when the film surface temperature in TDS is within the range of 50°C to 500°C, the amount of hydrogen released from the insulator 324 is 10×10 15 atoms / cm 2 Below, preferably 5×10 15 atoms / cm 2 The following is enough.

[0482] Note that the dielectric constant of the insulator 326 is preferably lower than that of the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably lower than 4, more preferably lower than 3. For example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using an insulating material with a low dielectric constant for the insulator 326, parasitic capacitance generated between wirings can be reduced.

[0483] Furthermore, conductors 328 and 330 are embedded in insulators 320, 321, 324, and 326, and are connected to memory cells MC and the like disposed above insulator 324. Furthermore, conductors 328 and 330 function as plugs or wiring. Note that the same symbol may be used to represent multiple conductors functioning as plugs or wiring. Furthermore, in this specification and other documents, a wiring and a plug connected to the wiring may be considered a single component. That is, a portion of a conductor may function as wiring, and a portion of a conductor may function as a plug.

[0484] As the material for each plug and wiring (for example, conductor 328 and conductor 330), a single layer or a stack of one or more conductive materials selected from metal materials, alloy materials, metal nitride materials, and metal oxide materials can be used. Preferably, a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity is used, with tungsten being particularly preferred. Alternatively, it is preferably formed using a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0485] Alternatively, a wiring layer may be formed on the insulator 326 and the conductor 330. For example, Figure 96 The structure shown is a structure in which a plurality of wiring layers are provided on an insulator 326 and a conductor 330. In addition, the wiring layer is provided with a plurality of conductors 340 serving as contact plugs or wirings.

[0486] Specifically, in Figure 96 In the embodiment, an insulator 334, an insulator 336, and an insulator 338 are stacked in this order on the insulator 326 and the conductor 330 as one wiring layer. Furthermore, a conductor 340 is embedded in the insulators 334, 336, and 338. For example, the transistor 300 is electrically connected to any one of the wirings WL[1] to WL[m] or any one of the wirings BL[1] to BL[n] via the conductors 328, 330, and 340.

[0487] The insulator 334 can use, for example, the material that can be used for the insulator 324 .

[0488] The insulator 336 and the insulator 338 can use, for example, a material that can be used for the insulator 320 , the insulator 321 , or the insulator 326 .

[0489] The conductor 340 can use, for example, a material that can be used for the conductor 328 or the conductor 330 .

[0490] Next, the structure of the memory layer 60 located above the driver circuit layer 50 will be described. Figure 96In FIG. 5 , as an example, the memory layer 60_1 and the memory layer 60_2 are provided above a wiring layer provided with a plurality of conductors 340 serving as contact plugs or wirings.

[0491] exist Figure 96 In the storage layer 60_1 shown, multiple Figures 2A to 2C The memory cells MC are arranged in a matrix. Figure 96 In FIG. 1 , a structure in which three memory cells MC are arranged in the X direction is shown as an example.

[0492] like Figures 2A to 2C As described, memory cell MC includes transistor MW, transistor MR, and capacitor C1. In some cases, memory cell MC also includes transistor MD. Memory cell MC is electrically connected to conductors ME1, ME2, ME3, ME6, and ME7, all of which serve as wiring.

[0493] Conductor ME2 is shared as a wiring SL with multiple memory cells MC extending in the X direction and located in the same row. Similarly, conductor ME3 is shared as a wiring CL with multiple memory cells MC extending in the X direction and located in the same row. Similarly, conductor ME7 is shared as a wiring WWL with multiple memory cells MC extending in the X direction and located in the same row.

[0494] The conductor ME1 is connected to a plurality of memory cells (in the same column) extending in the Y direction as the wiring RBL. Figure 96 Similarly, the conductor ME6 is shared with a plurality of memory cells (not shown) extending in the Y direction and located in the same column as the wiring WBL. Figure 96 (not shown) shared.

[0495] exist Figure 96 In the embodiment, as an example, conductors 350a and 350b are embedded in insulator IS1. Conductors 350a and 350b serve as contact plugs or wirings, and can use, for example, the same material as conductor 328 or conductor 330. Furthermore, conductors 350a and 350b are electrically connected to conductor 340 of the wiring layer below memory layer 60_1.

[0496] For example, a conductor ME1a is formed on the insulator IS1 and the conductor 350a. Also, for example, a conductor ME1b is formed on the insulator IS1 and the conductor 350b. The conductor ME1a and the conductor ME1b can be formed simultaneously in the formation step of the conductor ME1.

[0497] exist Figure 96As an example, in the region overlapping with the conductor ME1a, the conductor MV1 is embedded in the insulators IS2, ME2, IS3, ME3, GI1, and IS5. For example, the insulators IS2, ME2, IS3, ME3, and GI1 can be processed to form an opening in the region overlapping with the conductor ME1a, and then the conductor MV1 can be deposited so as to be embedded in the opening.

[0498] In addition, Figure 96 As an example, in the region overlapping with the conductor ME1b, the conductor MV2 is embedded in the insulators IS2, IS3, IS4, GI1, and IS5. For example, the insulators IS2, IS3, IS4, GI1, and IS5 may be processed to form an opening in the region overlapping with the conductor ME1b, and then the conductor MV2 may be deposited so as to be embedded in the opening.

[0499] Furthermore, the conductors MV1 and MV2 may be deposited simultaneously in the deposition step of the conductor ME4. Alternatively, after the conductors MV1 and MV2 are deposited, they may be processed simultaneously with the processing of the conductor ME4 and the insulator IS5.

[0500] The conductor MV1 is electrically connected to the conductors ME2 and ME3. That is, the wiring SL and the wiring CL in the cell array CA of the memory layer 60_1 are electrically connected to the transistor 300 of the driver circuit layer 50 through the conductor MV1, the conductor ME1a, the conductor 350a, and the conductor 340.

[0501] In addition, Figure 96 In the example, an opening is provided in the region of each of the insulator IS6 and the insulator GI2 that overlaps with the conductor MV2. In addition, the conductor ME7 is embedded in the opening.

[0502] Thus, the conductor MV2 is electrically connected to the conductor ME7 . That is, the wiring WWL in the cell array CA of the memory layer 60_1 is electrically connected to the transistor 300 of the driver circuit layer 50 through the conductor MV2 , the conductor ME1 b , the conductor 350 b , and the conductor 340 .

[0503] In addition, although Figure 96 Although not shown in the figure, the conductor ME1 (wiring RBL) and the conductor ME6 (wiring WBL) are also electrically connected to the transistor 300 of the driving circuit layer 50 through contact plugs or wirings.

[0504] By having Figure 96The memory layer 60_1 can be provided above the driver circuit layer 50. Similarly, the memory layers 60_2 to 60_N can be provided above the driver circuit layer 50 and the memory layer 60_1 by using contact plugs or wiring.

[0505] With the above-described structure, a memory device including the memory cell MC described in Embodiments 1 and 2 can be manufactured.

[0506] This embodiment mode can be appropriately combined with other embodiment modes described in this specification. For example, the configuration, structure, and method described in this embodiment mode can be appropriately combined with the configuration, structure, and method described in other embodiment modes.

[0507] (Implementation 5) In this embodiment, a transistor including an oxide semiconductor in a channel formation region (OS transistor) is described. The OS transistor is briefly described in comparison with a transistor including silicon in a channel formation region (also referred to as a Si transistor).

[0508] [OS transistor] It is preferable to use an oxide semiconductor with a low carrier concentration for the OS transistor. For example, the carrier concentration of the channel formation region of the oxide semiconductor is 1×10 18 cm -3 Below, preferably below 1×10 17 cm -3 , more preferably less than 1×10 16 cm -3 , more preferably less than 1×10 13 cm -3 , and further preferably less than 1×10 10 cm -3 , and is 1×10 -9 cm -3 When the carrier concentration of the oxide semiconductor film is to be reduced, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In this specification, etc., a state with a low impurity concentration and a low defect state density is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0509] Because high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors have a low defect state density, they sometimes also have a low trap state density. Furthermore, charges trapped in the trap states of the oxide semiconductor take a long time to disappear, sometimes acting like fixed charges. Consequently, transistors with channel formation regions formed in oxide semiconductors with a high trap state density sometimes experience unstable electrical characteristics.

[0510] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. Examples of impurities include hydrogen and nitrogen. Note that impurities in an oxide semiconductor refer to, for example, elements other than the main components that constitute the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0511] In an OS transistor, when impurities and oxygen vacancies exist in the channel formation region of an oxide semiconductor, the electrical characteristics are easily changed, which may reduce reliability. In addition, in an OS transistor, hydrogen enters the oxygen vacancies in the oxide semiconductor to form defects (hereinafter sometimes referred to as V O H), electrons that become carriers may be generated. In addition, when V O When the voltage is V, the donor concentration in the channel formation region may increase. As the donor concentration in the channel formation region increases, the threshold voltage may become uneven. Therefore, when oxygen vacancies are included in the channel formation region of the oxide semiconductor, the transistor is often turned on (a state in which a channel exists even when a voltage is not applied to the gate electrode and current flows in the transistor). Therefore, in the channel formation region of the oxide semiconductor, it is preferable to minimize impurities, oxygen vacancies, and V. O H.

[0512] In addition, the band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and more preferably 3.0 eV or more. By using an oxide semiconductor with a larger band gap than silicon, the off-state current (also called off-state leakage current or Ioff) of the transistor can be reduced.

[0513] Furthermore, in Si transistors, as transistors become increasingly miniaturized, a short channel effect (SCE) occurs. Therefore, miniaturization of Si transistors is difficult. One reason for the short channel effect is the small band gap of silicon. On the other hand, OS transistors use oxide semiconductors, which are semiconductor materials with large band gaps, to suppress the short channel effect. In other words, OS transistors have no short channel effect or very little short channel effect.

[0514] The short-channel effect refers to the degradation of electrical properties that occurs with transistor miniaturization (reduction in channel length). Specific examples of the short-channel effect include a decrease in threshold voltage, an increase in the subthreshold swing value (sometimes referred to as the S value), and an increase in leakage current. The S value refers to the change in gate voltage in the subthreshold region that causes a single-digit change in drain current at a fixed drain voltage.

[0515] Characteristic length is widely used as an indicator of resistance to short channel effects. Characteristic length refers to the curvature of the potential in the channel formation region. The smaller the characteristic length, the more steeply the potential rises, and therefore it can be said that the resistance to short channel effects is high.

[0516] OS transistors are accumulation-mode transistors, while Si transistors are inversion-mode transistors. Therefore, the characteristic lengths between the source region and the channel formation region, and the characteristic lengths between the drain region and the channel formation region, are smaller in OS transistors than in Si transistors. Consequently, OS transistors are more resistant to short-channel effects than Si transistors. In other words, when manufacturing transistors with short channel lengths, OS transistors are more suitable than Si transistors.

[0517] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region is i-type or substantially i-type, the conduction band bottom of the channel formation region is lowered due to the conduction-band-lowering (CBL) effect in the short channel transistor. Therefore, the energy difference in the conduction band bottom between the source region or the drain region and the channel formation region is likely to be reduced to 0.1 eV or more and 0.2 eV or less. Therefore, the OS transistor can be regarded as having n + / n - / n + The accumulation type junction-less transistor structure or n + / n - / n + The accumulation type non-junction transistor structure, in which the channel forming region is n - Type region, source region and drain region are n + Type area.

[0518] When the above structure is adopted as an OS transistor, good electrical characteristics can be achieved even if the semiconductor device is miniaturized or highly integrated. For example, even if the gate length of the OS transistor is less than 20nm, less than 15nm, less than 10nm, less than 7nm or less than 6nm and greater than 1nm, greater than 3nm or greater than 5nm, good electrical characteristics can be obtained. On the other hand, in Si transistors, it is sometimes difficult to have a gate length of less than 20nm or less than 15nm due to the occurrence of a short channel effect. Therefore, compared with Si transistors, OS transistors are more suitable for use as transistors with a small channel length. The gate length is the length of the gate electrode in the direction of the carrier movement channel formation region when the transistor is working, and is also the width of the bottom surface of the gate electrode when the transistor is viewed from a plane.

[0519] Furthermore, miniaturizing the OS transistor can improve the transistor's high-frequency characteristics. Specifically, the transistor's cutoff frequency can be increased. When the gate length of the OS transistor is within the above range, for example, at room temperature, the transistor's cutoff frequency can be above 50 GHz, preferably above 100 GHz, and more preferably above 150 GHz.

[0520] As described above, OS transistors have advantages superior to Si transistors, such as small off-state current and the ability to manufacture transistors with small channel lengths.

[0521] This embodiment mode can be appropriately combined with other embodiment modes described in this specification. For example, the configuration, structure, and method described in this embodiment mode can be appropriately combined with the configuration, structure, and method described in other embodiment modes.

[0522] (Implementation 6) This embodiment mode describes electronic components, electronic devices, mainframe computers, space equipment, and data centers (also referred to as DCs) that can use the semiconductor devices described in the above embodiment modes. Electronic components, electronic devices, mainframe computers, space equipment, and data centers that use a semiconductor device according to one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0523] [Electronic components] Figure 97A A perspective view of a substrate (circuit board 704 ) on which an electronic component 700 is mounted is shown. Figure 97A The electronic component 700 shown includes a semiconductor device 710 within a mold 711. Figure 97A700 is partially omitted to illustrate its interior. Electronic component 700 includes lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, which are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. By combining multiple electronic components and electrically connecting them on printed circuit board 702, a circuit board 704 is completed.

[0524] In addition, the semiconductor device 710 includes a driver circuit layer 715 and a memory layer 716. The memory layer 716 has a structure in which a plurality of memory cell arrays are stacked. The structure in which the driver circuit layer 715 and the memory layer 716 are stacked can adopt a monolithic stacked structure. In a monolithic stacked structure, it is possible to connect the layers without using through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. When the driver circuit layer 715 and the memory layer 716 adopt a monolithic stacked structure, for example, a so-called on-chip memory structure can be realized in which a memory is directly formed on a processor. By adopting an on-chip memory structure, high-speed operation of the interface between the processor and the memory can be achieved.

[0525] Furthermore, the use of an on-chip memory structure reduces the size of interconnects and other components compared to technologies using through-hole electrodes such as TSVs, allowing for a larger number of pins. This increased number of pins allows for parallel operation, thereby increasing the memory bandwidth (also known as memory bandwidth).

[0526] In addition, it is preferred to use OS transistors to form multiple memory cell arrays in the memory layer 716, and stack the multiple memory cell arrays in a monolithic manner. When multiple memory cell arrays are stacked in a monolithic manner, either or both of the bandwidth of the memory and the access delay of the memory can be improved. Bandwidth refers to the amount of data transmitted per unit time, and access delay refers to the time between access and the start of data exchange. When Si transistors are used in the memory layer 716, it is more difficult to achieve a monolithic stacked structure compared to OS transistors. Therefore, in a monolithic stacked structure, OS transistors are superior to Si transistors.

[0527] In addition, the semiconductor device 710 may be referred to as a bare die. In this specification, etc., a bare die refers to a chip obtained by forming a circuit pattern on a disk-shaped substrate (also called a wafer) during the manufacturing process of a semiconductor chip, for example, and then cutting it into rectangular pieces. Examples of semiconductor materials that can be used for bare chips include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a bare die obtained from a silicon substrate (also called a silicon wafer) is sometimes referred to as a silicon chip.

[0528] then, Figure 97B A perspective view of an electronic component 730 is shown. Electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board). A semiconductor device 735 and a plurality of semiconductor devices 710 are provided on interposer 731.

[0529] Electronic component 730 illustrates an example of using semiconductor device 710 as a high-bandwidth memory (HBM). Alternatively, semiconductor device 735 can be used in integrated circuits such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or an FPGA (Field Programmable Gate Array).

[0530] The package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate, and the interposer 731 may be, for example, a silicon interposer or a resin interposer.

[0531] The interposer 731 has a plurality of wirings and has the function of electrically connecting a plurality of integrated circuits with different terminal spacings. The plurality of wirings are composed of a single layer or multiple layers. In addition, the interposer 731 has the function of electrically connecting the integrated circuit provided on the interposer 731 to the electrodes provided on the package substrate 732. Therefore, the interposer is sometimes also referred to as a "rewiring substrate" or "intermediate substrate". In addition, sometimes a through electrode is provided in the interposer 731, and the integrated circuit is electrically connected to the package substrate 732 through the through electrode. In addition, when a silicon interposer is used, TSV can also be used as a through electrode.

[0532] To achieve a wide memory bandwidth in HBM, numerous wiring connections are required. Therefore, the interposer on which HBM is mounted must be able to form fine wiring at a high density. Therefore, a silicon interposer is preferred for HBM mounting.

[0533] Furthermore, SiPs and MCMs using silicon interposers are less susceptible to reliability degradation caused by differences in thermal expansion coefficients between the integrated circuits and the interposer. Furthermore, due to the high surface flatness of the silicon interposer, poor connections between the integrated circuits mounted on the silicon interposer and the silicon interposer are less likely to occur. Silicon interposers are particularly well-suited for 2.5D packaging (2.5D assembly), in which multiple integrated circuits are arranged horizontally on the interposer.

[0534] On the other hand, when using silicon interposers and TSVs to electrically connect multiple integrated circuits with different terminal pitches, space is required, such as the width of the terminal pitch. Therefore, when reducing the size of the electronic component 730, the width of the terminal pitch becomes a problem, and it is sometimes difficult to provide the large amount of wiring required to achieve a wider memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferred. Alternatively, a composite structure combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array can be used.

[0535] Alternatively, a heat sink (heat dissipation plate) may be provided overlapping the electronic component 730. When a heat sink is provided, it is preferable to make the heights of the integrated circuits provided on the interposer 731 uniform. For example, in the electronic component 730 shown in this embodiment, it is preferable to make the heights of the semiconductor device 710 and the semiconductor device 735 uniform.

[0536] In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom of the package substrate 732 . Figure 97B The example of electrodes 733 formed using solder balls is shown. By arranging solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, electrodes 733 can be formed using conductive pins. Arranging conductive pins in a matrix on the bottom of the package substrate 732 enables PGA (Pin Grid Array) mounting.

[0537] The electronic component 730 can be mounted on another substrate using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded Package), and QFN (Quad Flat Non-leaded Package).

[0538] [Electronic equipment] then, Figure 98A A perspective view of electronic device 6500 is shown. Figure 98AThe electronic device 6500 shown is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. The control device 6509 may include, for example, one or more of a CPU, a GPU, and a storage device. The semiconductor device according to one embodiment of the present invention can be used for the display portion 6502, the control device 6509, and the like.

[0539] Figure 98B The electronic device 6600 shown is an information terminal that can be used as a notebook personal computer. The electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display unit 6615, and a control unit 6616. The control unit 6616 includes, for example, one or more of a CPU, a GPU, and a storage device. A semiconductor device according to one embodiment of the present invention can be used for the display unit 6615, the control unit 6616, and the like. Furthermore, using a semiconductor device according to one embodiment of the present invention in the control unit 6509 and the control unit 6616 is preferred because it can reduce power consumption.

[0540] [Mainframe computer] then, Figure 98C A perspective view of a mainframe computer 5600 is shown. Figure 98C In the illustrated mainframe computer 5600, a plurality of rack-mount computers 5620 are housed in a rack 5610. The mainframe computer 5600 may also be referred to as a supercomputer.

[0541] Computer 5620 may have, for example, Figure 98D The structure of the stereogram shown. Figure 98D In the embodiment, computer 5620 includes a motherboard 5630, which includes multiple slots 5631 and multiple connection terminals. A personal computer card 5621 is inserted into slots 5631. Furthermore, personal computer card 5621 includes connection terminals 5623, 5624, and 5625, which are connected to motherboard 5630.

[0542] Figure 98E The illustrated personal computer card 5621 is an example of a processing board including a CPU, a GPU, a storage device, etc. The personal computer card 5621 includes a board 5622. In addition, the board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Figure 98ESemiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 are shown. For descriptions of these semiconductor devices, refer to the descriptions of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 described below.

[0543] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630 and is used as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of the standard of the connection terminal 5629 include PCIe.

[0544] Each of the connection terminals 5623, 5624, and 5625 can be used, for example, as an interface for supplying power to the PC card 5621 or inputting signals. Furthermore, for example, each can be used as an interface for outputting signals calculated by the PC card 5621. Examples of the standards for each of the connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Furthermore, when outputting video signals from the connection terminals 5623, 5624, and 5625, examples of the standards include HDMI (registered trademark).

[0545] The semiconductor device 5626 includes terminals (not shown) for inputting and outputting signals. By inserting the terminals into sockets (not shown) included in the board 5622 , the semiconductor device 5626 and the board 5622 can be electrically connected.

[0546] The semiconductor device 5627 includes a plurality of terminals. For example, by soldering these terminals to wiring included in the board 5622 using reflow soldering, the semiconductor device 5627 and the board 5622 can be electrically connected. Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0547] The semiconductor device 5628 includes a plurality of terminals. For example, by soldering these terminals to wiring included in the board 5622 by reflow soldering, the semiconductor device 5628 and the board 5622 can be electrically connected. Examples of the semiconductor device 5628 include a memory device. For example, the electronic component 700 can be used as the semiconductor device 5628.

[0548] The mainframe computer 5600 can be used as a parallel computer. By using the mainframe computer 5600 as a parallel computer, for example, large-scale calculations required for learning and inference of artificial intelligence can be performed.

[0549] [Space Equipment] The semiconductor device of one embodiment of the present invention can be applied to space equipment, which is one example of equipment that processes and stores information.

[0550] A semiconductor device according to one embodiment of the present invention may include an OS transistor. This OS transistor exhibits minimal fluctuations in electrical characteristics due to exposure to radiation. In other words, it exhibits high resistance to radiation and can be suitably used in environments where radiation is likely to enter. For example, an OS transistor can be suitably used in space.

[0551] exist Figure 99 , an artificial satellite 6800 is shown as an example of a space device. The artificial satellite 6800 includes a main body 6801, a solar cell panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Figure 99 An example of a planet 6804 in outer space is shown. Note that outer space refers to an altitude of 100 km or higher, for example, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0552] In addition, although Figure 99 Although not shown, a battery management system (also called BMS) or a battery control circuit may be provided in the secondary battery 6805. When an OS transistor is used for the battery management system or the battery control circuit, power consumption is low and high reliability is achieved even in outer space, which is preferable.

[0553] Furthermore, outer space is an environment with a radiation dose over 100 times greater than that on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, and particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and muon rays.

[0554] When sunlight hits the solar panels 6802, they generate the electricity necessary to operate the satellite 6800. However, if sunlight does not reach the solar panels, or if the amount of sunlight hitting the solar panels is low, the amount of electricity generated decreases. Consequently, there is a possibility that the required electricity for the operation of the satellite 6800 may not be generated. To enable the satellite 6800 to operate even when the generated electricity is low, a secondary battery 6805 is preferably provided in the satellite 6800. Solar panels are sometimes referred to as solar cell modules.

[0555] Satellite 6800 can generate a signal. This signal is transmitted via antenna 6803 and can be received by a receiver on the ground or another satellite. By receiving the signal transmitted by satellite 6800, the position of the receiver receiving the signal can be measured. Thus, satellite 6800 can form a satellite positioning system.

[0556] Furthermore, control device 6807 has the function of controlling artificial satellite 6800. Control device 6807 is configured using, for example, one or more of a CPU, a GPU, and a storage device. Furthermore, a semiconductor device according to one embodiment of the present invention is preferably used for control device 6807. Compared to Si transistors, OS transistors exhibit less variation in electrical characteristics due to exposure to radiation. This means that OS transistors are highly reliable and can be suitably used even in environments where radiation is likely to be incident.

[0557] Additionally, artificial satellite 6800 may include sensors. For example, by including a visible light sensor, artificial satellite 6800 may be capable of detecting sunlight reflected from objects on the ground. Alternatively, by including a thermal infrared sensor, artificial satellite 6800 may be capable of detecting thermal infrared radiation emitted from the Earth's surface. Thus, artificial satellite 6800 may be used, for example, as an Earth observation satellite.

[0558] Note that although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited thereto. For example, a semiconductor device according to one embodiment of the present invention can be suitably applied to space equipment such as a spacecraft, a space capsule, and a space probe.

[0559] As described above, OS transistors have superior effects compared to Si transistors, such as achieving a wider memory bandwidth and having high radiation resistance.

[0560] [Data Center] For example, a semiconductor device according to one embodiment of the present invention can be applied to auxiliary storage systems used in data centers and the like. Data centers are required to ensure data immutability and other aspects of long-term data management. This long-term data management requires large-scale facilities, such as auxiliary storage and servers to store large amounts of data, ensuring a stable power supply to maintain data, and ensuring the cooling equipment required for data storage.

[0561] By using a semiconductor device according to one embodiment of the present invention in a secondary storage system employed in a data center, it is possible to reduce the power required for data retention and miniaturize the semiconductor device that retains data. Consequently, it is possible to miniaturize the secondary storage system, the power supply required for data retention, and the cooling equipment required. This, in turn, allows for space savings in the data center.

[0562] Furthermore, the semiconductor device according to one embodiment of the present invention consumes low power, thereby reducing circuit heat generation. This reduces the negative impact of heat generation on the circuit itself, peripheral circuits, and modules. Furthermore, the use of the semiconductor device according to one embodiment of the present invention enables the realization of a data center that can operate stably even in high-temperature environments. Consequently, the reliability of the data center can be improved.

[0563] Figure 100 A secondary storage system that can be used in a data center is shown. Figure 100 The auxiliary storage system 7000 shown includes a plurality of servers 7001sb as a host 7001 and a plurality of storage devices 7003md as an auxiliary storage 7003. The host 7001 and the auxiliary storage 7003 are connected via an auxiliary storage area network 7004 and an auxiliary storage control circuit 7002.

[0564] The host computer 7001 is equivalent to a computer that accesses data stored in the auxiliary storage 7003. The hosts 7001 may be connected to each other via a network.

[0565] In auxiliary storage 7003, the use of flash memory reduces data access speed, thereby shortening the time required to store and output data. However, this time is significantly longer than the time required by DRAM (Dynamic Random Access Memory), which can be used as a cache memory in auxiliary storage. To address the issue of the slower access speed of auxiliary storage 7003, a cache memory is typically incorporated into the auxiliary storage to shorten the time required to store and output data.

[0566] The cache memory is used in the auxiliary storage control circuit 7002 and the auxiliary storage 7003. Data exchanged between the host 7001 and the auxiliary storage 7003 is stored in the cache memory in the auxiliary storage control circuit 7002 and the auxiliary storage 7003 and then output to the host 7001 and the auxiliary storage 7003.

[0567] When OS transistors are used as transistors for storing data in the cache memory to hold a potential corresponding to the data, the refresh frequency can be reduced to reduce power consumption. In addition, miniaturization can be achieved by stacking memory cell arrays.

[0568] Note that by using a semiconductor device according to one embodiment of the present invention in any one or more of electronic components, electronic devices, mainframe computers, space equipment, and data centers, it is expected that power consumption can be reduced. Therefore, it is currently believed that as energy requirements increase with the performance and integration of semiconductor devices, the use of a semiconductor device according to one embodiment of the present invention can also reduce greenhouse gas emissions such as carbon dioxide (CO2). In addition, the semiconductor device according to one embodiment of the present invention has low power consumption and is therefore also effective as a measure to combat global warming.

[0569] This embodiment mode can be appropriately combined with other embodiment modes described in this specification. For example, the configuration, structure, and method described in this embodiment mode can be appropriately combined with the configuration, structure, and method described in other embodiment modes.

[0570] (Implementation 7) In this embodiment, a structural example in which the stacked structure described in the above embodiment is applied to a display device and an electronic device using the display device will be described.

[0571] <Configuration Example of Display Device> Figure 101A FIG. 1 is a perspective view showing a structural example of a display device DSP adopting the stacked structure. Figure 101B It is a block diagram of the DSP of the display device.

[0572] The display device DSP includes a memory circuit area MEMA, a driver circuit area DRVA, a circuit layer CIRL, and a display area EMA. The memory circuit area MEMA and the driver circuit area DRVA are located below the circuit layer CIRL, while the display area EMA is located above the circuit layer CIRL. In other words, in the display device DSP, the memory circuit area MEMA and the driver circuit area DRVA, the circuit layer CIRL, and the display area EMA are stacked in this order from the bottom.

[0573] The memory circuit area MEMA has a function of storing image data for displaying an image on the display area EMA. As an example, the memory circuit area MEMA may also include DRAM, SRAM, FeRAM, ReRAM, MRAM, or PRAM. Figure 101B In the embodiment, the memory circuit area MEMA includes, for example, a plurality of memory cells that store image data as digital data, and each of the plurality of memory cells transmits data of one bit or a plurality of bits to the circuit layer CIRL.

[0574] For example, the memory circuit area MEMA has the function of reading image data from the memory cells included in the memory circuit area MEMA and transmitting the image data to the drive circuit area DRVA described later. Furthermore, the memory cells may be capable of processing data smaller than 8 bits, such as 1 bit, 2 bits, or 4 bits. Furthermore, data larger than 8 bits, such as 8 bits, 16 bits, 32 bits, 64 bits, 128 bits, or 256 bits, may also be processed.

[0575] The drive circuit area DRVA includes, for example, a shift register and multiple digital-to-analog conversion circuits. The shift register sequentially distributes image data sent from the memory circuit area MEMA to the rows or columns of the display area EMA. Furthermore, the digital-to-analog conversion circuit converts digital image data read from the memory cells in the memory circuit area MEMA into analog data. Furthermore, the drive circuit area DRVA transmits the converted analog data to the circuit layer CIRL.

[0576] The display area EMA includes, for example, a plurality of light-emitting portions EP. In particular, the light-emitting portion EP is preferably arranged in an array in the display area EMA. The light-emitting portion EP includes, for example, a light-emitting device. In addition, as the light-emitting device, for example, a light-emitting device including an organic EL element (OLED (Organic Light Emitting Diode)), an inorganic EL element, an LED (including a micro-LED), a QLED (Quantum-dot Light Emitting Diode: quantum dot light-emitting diode) and a semiconductor laser can be cited. Note that in this embodiment, the case where the light-emitting portion EP adopts a light-emitting device including an organic EL is described. In particular, the brightness of the light emitted from the light-emitting device capable of emitting light with high brightness can be, for example, 500 cd / m 2 Above, preferably 1000 cd / m 2 Above and 10000cd / m 2 Below, more preferably 2000 cd / m 2 Above and 5000cd / m 2 the following.

[0577] Alternatively, the display area EMA may include, for example, a liquid crystal display device (e.g., a transmissive liquid crystal device or a reflective liquid crystal device). Alternatively, the display area EMA may include, for example, a display device using an electrophoretic element, an electronic powder fluid (registered trademark), or an electrowetting display device.

[0578] The circuit layer CIRL includes, for example, a plurality of driving parts DP, one of which has a function of driving a light emitting device included in a corresponding light emitting part EP.

[0579] The driving portion DP, for example, holds image data sent from the driving circuit area DRVA and sends current corresponding to the image data to the light emitting portion EP, whereby the light emitting device included in the light emitting portion EP can emit light having brightness corresponding to the current.

[0580] By configuring the display device DSP as described above, the display device DSP can select image data held by each of the plurality of memory cells in the memory circuit area MEMA and display the selected image data on one of the plurality of pixel circuits PX in the display area EMA.

[0581] Next, a configuration example of the pixel circuit PX will be described.

[0582] Figure 102 FIG. 4 shows a configuration example of a light emitting section EP and a driving section DP that may be included in a pixel circuit PX. Figure 102 1 is a diagram showing the connection of each circuit element included in the pixel circuit PX.

[0583] The driver DP includes a transistor 500A, a transistor 500B, a transistor 500C, and a capacitor 600. For example, the transistors 500A, 500B, and 500C that can be used as the transistor MW or the transistor MR described in Embodiment 1 can be used as each of the transistors 500A, 500B, and 500C. In particular, the transistors 500A, 500B, and 500C are preferably OS transistors.

[0584] Note that in Figure 102 Although the transistor 500A, the transistor 500B, and the transistor 500C do not have back gate electrodes, a structure in which a back gate electrode is provided in each transistor and the same or different signal as that of the gate electrode is supplied to the back gate electrode may be adopted.

[0585] The transistor 500B includes a gate electrode electrically connected to the transistor 500A, a first electrode electrically connected to the light emitting device 130 , and a second electrode electrically connected to a wiring ANO. The wiring ANO is a wiring of a potential for supplying current to the light emitting device 130 .

[0586] The transistor 500A includes a first terminal electrically connected to the gate electrode of the transistor 500B, a second terminal electrically connected to the wiring DL serving as a source line, and a gate electrode having a function of controlling switching between an on state and an off state according to the potential of the wiring G1 serving as a gate line.

[0587] The wiring DL is used as a source line in the pixel circuit PX, and thus image data transmitted to the wiring DL is image data output from the above-described circuit layer CIRL.

[0588] Transistor 500C includes a first terminal electrically connected to wiring V0, a ​​second terminal electrically connected to light-emitting device 130, and a gate electrode having a function of controlling switching between an on state and an off state according to the potential of wiring G2 serving as a gate line. Wiring V0 serves as a wiring for supplying a reference potential and also as a wiring for outputting current flowing through driver portion DP to driver circuit region DRVA.

[0589] The capacitor 600 includes a conductive film electrically connected to the gate electrode of the transistor 500B and a conductive film electrically connected to the second electrode of the transistor 500C.

[0590] The light emitting device 130 in the light emitting portion EP includes a first electrode electrically connected to the first electrode of the transistor 500B and a second electrode electrically connected to a wiring VCOM. The wiring VCOM is a wiring for supplying a potential for supplying current to the light emitting device 130.

[0591] Thus, the intensity of light emitted by the light emitting device 130 can be controlled according to the image signal supplied to the gate electrode of the transistor 500B. In addition, the reference potential of the wiring V0 supplied through the transistor 500C can suppress variations in the gate-source voltage of the transistor 500B.

[0592] In addition, a current value that can be used when setting pixel parameters can be output from the wiring V0. More specifically, the wiring V0 can be used as a monitoring line that outputs the current flowing through the transistor 500B or the current flowing through the light-emitting device 130 to the outside. The current output to the wiring V0 is converted into a voltage by, for example, a source follower circuit and output to the outside. Alternatively, the current can be converted into a digital signal by, for example, an analog-to-digital conversion circuit and output to a circuit that performs dimming and color adjustment processing. The above-mentioned source follower circuit, analog-to-digital conversion circuit, or circuit that performs dimming and color adjustment processing can each be included in the drive circuit area DRVA, for example.

[0593] Note that as part of the circuit elements included in the driver DP, the circuit elements described in Embodiment 1 can be used. Figure 1A and Figures 2A to 2C The memory cell MC shown in FIG. 1 includes circuit elements. For example, transistor 500A may be Figure 1A and Figures 2A to 2C The transistor MW shown, the transistor 500B can be Figure 1A and Figures 2A to 2C The transistor MR shown, the capacitor 600 can be Figure 1A and Figures 2A to 2C The transistor C1 is shown. In addition, the wiring DL can be Figure 1A and Figures 2A to 2C The wiring WBL shown, the wiring G1 can be Figure 1A and Figures 2A to 2CThe wiring WWL and wiring ANO shown can be Figure 1A and Figures 2A to 2C The wiring RBL is shown. In addition, Figure 1A and Figures 2A to 2C The wiring SL and wiring CL shown in FIG. Figure 102 The wiring in the middle is connected to the first electrode of the light emitting device 130 or the second electrode of the transistor 500C. That is, Figure 1A and Figures 2A to 2C The memory cell MC shown can be used as a part of the driver DP described in this embodiment.

[0594] Figure 103 Schematically illustrates the vertical relationship between the driver circuit region DRVA, the memory circuit region MEMA, the circuit layer CIRL, and the driver portion DP having a plurality of transistors and the light emitting portion EP having the light emitting device 130 included in the pixel circuit PX. As an example, Figure 103 The display area EMA of the display device DSP shown includes a light emitting portion EP, and the circuit layer CIRL includes a driving portion DP.

[0595] In addition, Figure 103 In the structure shown as an example, the wiring used to electrically connect the driving part DP to the driving circuit area DRVA can be shortened, so the wiring resistance of the wiring can be reduced. Therefore, data can be written at high speed, so the display device DSP can be driven at high speed. Thus, even if the number of pixel circuits PX included in the display device DSP is large, sufficient frame periods can be ensured, so the pixel density of the display device DSP can be increased. In addition, by increasing the pixel density of the display device DSP, the clarity of the image displayed by the display device DSP can be improved. For example, the pixel density of the display device DSP can be 500ppi or more, preferably 1000ppi or more, more preferably 3000ppi or more, further preferably 5000ppi or more, and further preferably 6000ppi or more. Therefore, the display device DSP can be, for example, a display device for XR (Extended Reality or Cross Reality) such as AR (Augmented Reality) and VR (Virtual Reality), which can be appropriately used in electronic devices such as HMD (Head-Mounted Display) in which the display part is close to the user.

[0596] <Structure Example of Electronic Equipment> Next, an example of electronic equipment that can use the above-mentioned display device DSP will be described.

[0597] The electronic device includes, for example, a display device and one or more selected from an antenna, a battery, a housing, a camera, a speaker, a microphone, a touch sensor, and an operation button.

[0598] Furthermore, the electronic device may include a secondary battery, and the secondary battery is preferably charged by contactless power transmission.

[0599] Examples of secondary batteries include lithium ion secondary batteries (e.g., lithium polymer batteries using a gel electrolyte (lithium ion polymer battery)), nickel hydrogen batteries, nickel cadmium batteries, organic radical batteries, lead storage batteries, air secondary batteries, nickel zinc batteries, and silver zinc batteries.

[0600] Furthermore, the electronic device may include an antenna. By using the antenna to receive signals, images, information, etc. can be displayed on the display unit. In addition, when the electronic device includes an antenna and a secondary battery, the antenna can be used for contactless power transmission.

[0601] On the display area of ​​the electronic device, for example, images with full HD, 4K2K, 8K4K, 16K8K or higher resolution can be displayed.

[0602] Examples of electronic devices include those with large screens, such as televisions, notebook personal computers, display devices, digital signage, pinball machines, and game consoles. Furthermore, examples of electronic devices include digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, and audio reproduction devices.

[0603] The electronic device can be assembled along the flat or curved surface of the inner or outer wall of a building such as a house or a high-rise building. In addition, the electronic device can be assembled along the flat or curved surface of the interior or exterior of a car or the like.

[0604] [Mobile phone] Figure 104A The illustrated information terminal 5500 is a mobile phone (smartphone) which is one type of information terminal. The information terminal 5500 includes a housing 5510 and a display portion 5511 . The display portion 5511 includes a touch panel as an input interface, and the housing 5510 is provided with buttons.

[0605] [Wearable Terminal] Figure 104B 59 is an external view of an information terminal 5900 , which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901 , a display portion 5902 , operation buttons 5903 , a crown 5904 , and a strap 5905 .

[0606] [Information Terminal] in addition, Figure 104C As an example, a notebook information terminal 5300 is shown. Figure 104CIn the illustrated notebook information terminal 5300 , a housing 5330 a includes a display portion 5331 , and a housing 5330 b includes a keyboard portion 5350 .

[0607] Note that in the above example, Figures 104A to 104C While smartphones, wearable devices, and notebook-type information terminals are shown as examples of electronic devices, the present invention is also applicable to information terminals other than smartphones, wearable devices, and notebook-type information terminals. Examples of information terminals other than smartphones, wearable devices, and notebook-type information terminals include PDAs (Personal Digital Assistants), desktop information terminals, and workstations.

[0608] [camera] Figure 104D 8100 is an external view of a camera 8000 equipped with a viewfinder 8100. The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, and a shutter button 8004. The camera 8000 also includes a detachable lens 8006. The viewfinder 8100 includes a housing 8101, a display unit 8102, and buttons 8103.

[0609] In the camera 8000 , the lens 8006 and the housing may be formed integrally.

[0610] The camera 8000 can take a picture by pressing a shutter button 8004 or touching the display portion 8002 serving as a touch panel.

[0611] The housing 8001 includes an inserter having electrodes, and can be connected to the viewfinder 8100 as well as a flash device.

[0612] The housing 8101 is attached to the camera 8000 via an inserter that is fitted into the inserter of the camera 8000. The viewfinder 8100 can display an image received from the camera 8000 on the display portion 8102.

[0613] Button 8103 is used as a power button.

[0614] The display device according to one embodiment of the present invention can be used for the display portion 8002 of the camera 8000 and the display portion 8102 of the viewfinder 8100. Alternatively, the camera 8000 may include a built-in viewfinder.

[0615] [Game console] Figure 104E 5200 is an external view showing an example of a portable game machine 5200. The portable game machine 5200 includes a housing 5201, a display portion 5202, and buttons 5203.

[0616] Furthermore, the images of the portable game console 5200 can be output by a display device such as a television, a personal computer monitor, a game monitor, or a head-mounted display.

[0617] By using the display device described in the above embodiment in the portable game console 5200, a low-power portable game console 5200 can be realized. Furthermore, low power consumption can reduce heat generated by the circuit, thereby reducing the negative effects of heat on the circuit itself, peripheral circuits, and modules.

[0618] exist Figure 104E In the description, a portable game console is shown as an example of a game console, but the electronic device of one embodiment of the present invention is not limited thereto. Examples of the electronic device of one embodiment of the present invention include stationary game consoles, arcade game consoles installed in entertainment facilities (e.g., game centers, amusement parks, etc.), and batting practice pitching machines installed in sports facilities.

[0619] [TV device] Figure 104F 9000 includes a housing 9002, a display unit 9001, a speaker 9003, an operation key 9005 (for example, including a power switch or an operation switch), a connection terminal 9006, and a sensor 9007 (the sensor, for example, has a function of measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, number of rotations, distance, light (for example, visible light or invisible light), liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow rate, humidity, inclination, vibration, or odor). Alternatively, the sensor, for example, has a function of detecting or measuring odor or light). A storage device according to one embodiment of the present invention can be assembled in a television device. A display unit 9001 having a size of, for example, 50 inches or more or 100 inches or more can be assembled in a television device.

[0620] By applying the display device described in the above embodiment to the television set 9000, a low-power television set 9000 can be realized. Furthermore, low power consumption can reduce heat generated by the circuit, thereby reducing the negative effects of heat on the circuit itself, peripheral circuits, and modules.

[0621] [Mobile Object] The display device according to one embodiment of the present invention can be used near a driver's seat of a vehicle as a moving object.

[0622] Figure 104G This is a diagram showing the vicinity of the front windshield inside a vehicle interior. Figure 104GDisplay panels 5701, 5702, and 5703 installed on the instrument panel and 5704 installed on the pillar are shown.

[0623] Display panels 5701 through 5703 can display one or more of navigation information, a speedometer, a tachometer, distance traveled, fuel level, gear status, and air conditioning settings. Furthermore, users can modify the display content and layout of the display panels to suit their preferences, enhancing design. Display panels 5701 through 5703 can also function as lighting devices.

[0624] By displaying images captured by a camera unit installed on the vehicle body on display panel 5704, it is possible to supplement the field of view (blind spots) blocked by pillars. In other words, by displaying images captured by a camera unit installed on the outside of the vehicle, blind spots can be supplemented, thereby improving safety. Furthermore, by displaying images that supplement the unseen areas, safety confirmation can be made more natural and comfortable. Display panel 5704 can...

Claims

1. A semiconductor device comprising: a first layer having a first opening; as well as a second layer having a second opening, wherein the second layer is located above the first layer, The first layer includes a first conductor, a second conductor, a third conductor, a fourth conductor, a first insulator, a second insulator, a third insulator, a fourth insulator, a fifth insulator and a first semiconductor. The second layer includes a fifth conductor, a sixth conductor, a seventh conductor, a sixth insulator, a seventh insulator and a second semiconductor. The first opening is located above the first conductor, The first insulator is located on the top surface of the first conductor and the side surface outside the first opening. The second conductor is located on the top surface of the first insulator and the side surface outside the first opening. The second insulator is located on the top surface of the second conductor and the side surface outside the first opening. The third conductor is located on the top surface of the second insulator and the side surface outside the first opening. The third insulator is located on the top surface of the second insulator and the side surface of the third conductor. The first semiconductor is located inside the first opening on the top surface of the first conductor, the side surface of the first insulator, the side surface of the second conductor, the side surface of the second insulator, and the side surface of the third conductor. The fourth insulator is located on the top surface of the third insulator, the top surface of the third conductor, and the top surface of the first semiconductor. The fourth conductor is located inside the first opening and above the first opening in the top surface of the fourth insulator. The fifth insulator is located above the fourth insulator and on the side of the fourth conductor. The fifth conductor is located on the top surface of the fourth conductor and the top surface of the fifth insulator, The second opening is located above the fifth conductor, The sixth insulator is located on the top surface of the fifth insulator, the top surface of the fifth conductor, and the side surface outside the second opening. The sixth conductor is located on the top surface of the sixth insulator and the side surface outside the second opening. The second semiconductor is located inside the second opening on the top surface of the fifth conductor, the side surface of the sixth insulator, and the side surface of the sixth conductor. The second semiconductor is located on the top surface of the sixth conductor outside the second opening. The seventh insulator is located on the top surface of the sixth insulator, the top surface of the sixth conductor, and the top surface of the second semiconductor. Furthermore, the seventh conductor is located on a top surface of the seventh insulator including an interior of the second opening.

2. The semiconductor device according to claim 1, wherein the first semiconductor and the second semiconductor each contain one or more selected from indium, zinc and element M, The element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium and antimony.

3. The semiconductor device according to claim 2, The taper angle of the side surface of the second opening is greater than or equal to 45° and less than or equal to 90°.

4. The semiconductor device according to claim 3, The first conductor and the sixth conductor extend in a first direction. And the second electrical conductor, the third electrical conductor and the seventh electrical conductor extend in a second direction.

5. A semiconductor device comprising: a first layer having a first opening; as well as a second layer having a second opening, wherein the second layer is located above the first layer, The first layer includes a first conductor, a second conductor, a third conductor, a fourth conductor, a first insulator, a second insulator, a third insulator, a fourth insulator, a fifth insulator and a first semiconductor. The second layer includes a sixth conductor, a seventh conductor, a sixth insulator, a seventh insulator and a second semiconductor, The first opening is located above the first conductor, The first insulator is located on the top surface of the first conductor and the side surface outside the first opening. The second conductor is located on the top surface of the first insulator and the side surface outside the first opening. The second insulator is located on the top surface of the second conductor and the side surface outside the first opening. The third conductor is located on the top surface of the second insulator and the side surface outside the first opening. The third insulator is located on the top surface of the second insulator and the side surface of the third conductor. The first semiconductor is located inside the first opening on the top surface of the first conductor, the side surface of the first insulator, the side surface of the second conductor, the side surface of the second insulator, and the side surface of the third conductor. The fourth insulator is located on the top surface of the third insulator, the top surface of the third conductor, and the top surface of the first semiconductor. The fourth conductor is located inside the first opening and above the first opening in the top surface of the fourth insulator. The fifth insulator is located above the fourth insulator and on the side of the fourth conductor. The second opening is located above the fourth conductor, The sixth insulator is located on the top surface of the fifth insulator, the top surface of the fourth conductor, and the side surface outside the second opening. The sixth conductor is located on the top surface of the sixth insulator and the side surface outside the second opening. The second semiconductor is located inside the second opening on the top surface of the fourth conductor, the side surface of the sixth insulator, and the side surface of the sixth conductor. The second semiconductor is located on the top surface of the sixth conductor outside the second opening. The seventh insulator is located on the top surface of the sixth insulator, the top surface of the sixth conductor, and the top surface of the second semiconductor. Furthermore, the seventh conductor is located on a top surface of the seventh insulator including an interior of the second opening.

6. The semiconductor device according to claim 5, wherein the first semiconductor and the second semiconductor each contain one or more selected from indium, zinc and element M, The element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium and antimony.

7. The semiconductor device according to claim 6, The taper angle of the side surface of the second opening is greater than or equal to 45° and less than or equal to 90°.

8. The semiconductor device according to claim 7, The first conductor and the sixth conductor extend in a first direction. And the second electrical conductor, the third electrical conductor and the seventh electrical conductor extend in a second direction.

9. A storage device, comprising: The semiconductor device according to any one of claims 1 to 8; as well as Drive circuit, Wherein, the driving circuit is located below the semiconductor device, The driving circuit is formed on a semiconductor substrate including silicon, Furthermore, the driving circuit includes a transistor including the silicon in a channel formation region.

10. An electronic device, comprising: The storage device according to claim 9; as well as Frame.

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