Substrate structure and method of manufacturing the same

Abstract

The application provides a substrate structure and a preparation method thereof, and the method comprises the following steps: a first through hole is formed through a ceramic core plate; a core plate dielectric layer covers the surface of the ceramic core plate and fills the first through hole; a second through hole is formed through the core plate dielectric layer at a position corresponding to the first through hole; the surface of the core plate dielectric layer is provided with a patterned core plate circuit layer, a build-up dielectric layer with a build-up through hole, and a build-up circuit layer; and the build-up circuit layer is electrically connected with the core plate circuit layer through the build-up through hole. The ceramic core plate is used to reduce the warping degree and loss of the substrate, and the substrate is suitable for a larger size. Meanwhile, the ceramic core plate surface is wrapped by the core plate dielectric layer to avoid the ceramic from being easily broken due to insufficient toughness and improve the product life. In addition, the circuit layer is arranged after the ceramic core plate is wrapped by the core plate dielectric layer to improve the bonding force between the ceramic core plate and the core plate circuit layer and improve the structural stability. Finally, the ceramic core plate is prepared by cooperating with the 3D printing technology to improve the preparation efficiency of the substrate.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing technology, and in particular relates to a substrate structure and its preparation method. Background Technology

[0002] With the rapid development of electronic technology, the number of chip I / O (input / output) pins is constantly increasing, and multi-chip packaging and heterogeneous integration applications are becoming more and more widespread. This places higher demands on the warpage deformation of the packaging substrate. Traditional organic IC (integrated circuit) packaging substrates are made of polymer and glass fiber composites, which are prone to large expansion and contraction deformation and severe warpage. Currently, this problem is solved by increasing the board thickness. However, excessive board thickness will lead to an increase in the overall thickness and weight of the IC packaging substrate, which will cause inconvenience to production operations.

[0003] Ceramics, as a structural material, are widely used in aerospace, industrial manufacturing, and biomedicine due to their high flexural strength, good creep properties, high hardness, and high temperature resistance. If ceramic materials could be used to fabricate packaging substrates, their excellent properties could solve the current problems with packaging substrates. However, ceramics prepared using traditional methods generally suffer from processing difficulties and are challenging to fabricate complex shapes; traditional ceramic preparation techniques cannot meet the requirements of packaging substrate fabrication.

[0004] Therefore, there is an urgent need for a substrate preparation method and substrate structure that can reduce substrate warpage and facilitate preparation.

[0005] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating the understanding of those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because these solutions have been described in the background section of this application. Summary of the Invention

[0006] In view of the shortcomings of the prior art, the purpose of this invention is to provide a substrate structure and its preparation method to solve the problems of large substrate warpage and high preparation difficulty in the prior art.

[0007] To achieve the above objectives, the present invention provides a method for preparing a substrate structure, the method comprising: A ceramic core plate is provided, the ceramic core plate including a first surface and a second surface disposed opposite to each other, and a first through hole is provided on the first surface or the second surface of the ceramic core plate; A core plate dielectric layer is provided on the first and second surfaces of the ceramic core plate, and the core plate dielectric layer covers the first and second surfaces and fills the first through hole; A second through hole is provided at the position between the core plate dielectric layer and the first through hole. The second through hole penetrates the core plate dielectric layer. The diameter of the second through hole is smaller than the diameter of the first through hole, and the wall of the second through hole does not contact the wall of the first through hole. A patterned core board circuit layer is provided on the surface of the core board dielectric layer, and the core board circuit layer fills the second through-hole; A patterned add-on dielectric layer is disposed on the patterned core board circuit layer. The add-on dielectric layer includes add-on vias that penetrate the add-on dielectric layer and expose a portion of the core board circuit layer. The material of the add-on dielectric layer is Ajinomoto film. A patterned augmentation circuit layer is disposed on the patterned augmentation dielectric layer, and the augmentation circuit layer forms an effective electrical connection with a portion of the core board circuit layer through the augmentation via.

[0008] Alternatively, the ceramic core plate including the first through hole can be prepared by 3D printing.

[0009] Optionally, the 3D printing method used includes fused deposition modeling (FDM) or photopolymerization 3D printing.

[0010] Optionally, the method for preparing the core board circuit layer includes: A first seed layer is applied to the surface of the core plate dielectric layer, and the first seed layer covers all exposed surfaces of the core plate dielectric layer. A patterned first photosensitive layer is formed on the surface of the first seed layer; A first conductive layer is filled in the gaps between the patterned first photosensitive layers, and the first conductive layer is also filled with the second via. The first photosensitive layer and the first seed layer below the first photosensitive layer are removed, and the patterned first seed layer and the first conductive layer constitute the core board circuit layer.

[0011] Optionally, the method for preparing the added circuit layer includes: A second seed layer is disposed on the graphical build-up dielectric layer, the second seed layer covering the exposed surfaces of the build-up dielectric layer and the exposed surfaces of the core board circuit layer; A patterned second photosensitive layer is disposed on the second seed layer; A second conductive layer is filled into the gaps between the patterned second photosensitive layers, and the second conductive layer also fills the augmentation vias; The second photosensitive layer and the second seed layer below the second photosensitive layer are removed, and the patterned second seed layer and the second conductive layer constitute the added circuit layer.

[0012] Optionally, the added circuit layer and the added dielectric layer constitute a substrate added layer, and multiple substrate added layers are provided.

[0013] Optionally, a solder mask layer is filled between the augmentation circuit layers on the exposed surface of the substrate structure.

[0014] Optionally, a surface treatment layer is provided on the surface of the exposed augmentation circuit layer of the substrate structure.

[0015] The present invention also provides a substrate structure, which is obtained by any of the above-described preparation methods. The substrate structure includes: a ceramic core board, a core board dielectric layer, a core board circuit layer, a multilayer substrate add-in layer, a solder resist layer, and a surface treatment layer. The ceramic core plate includes a first surface and a second surface disposed opposite to each other, and a first through hole is provided in the ceramic core plate, extending from the first surface to the second surface; The core plate dielectric layer covers all exposed surfaces of the ceramic core plate. The core plate dielectric layer has a second through hole that penetrates the core plate dielectric layer within the first through hole. The diameter of the second through hole is smaller than that of the first through hole, and the wall of the second through hole does not contact the wall of the first through hole. The graphical representation of the core board circuit layer is located on the surface of the core board dielectric layer and fills the second through-hole; Each substrate add-in layer includes a patterned add-in dielectric layer and an add-in circuit layer. The add-in dielectric layer is provided with add-in vias that penetrate the add-in dielectric layer and expose a portion of the underlying core board circuit layer or the add-in circuit layer. The add-in circuit layer is located on the add-in dielectric layer and fills the add-in vias to achieve effective electrical connection with the exposed core board circuit layer or the add-in circuit layer. The solder resist layer is located in the gap between the augmentation circuit layers on the surface of the substrate structure, and the surface treatment layer is located on the surface of the augmentation circuit layers on the surface of the substrate structure.

[0016] Optionally, the material of the ceramic core plate is one or more of silicon carbide ceramics, silicon nitride ceramics, alumina ceramics, or aluminum nitride ceramics.

[0017] As described above, the substrate structure and its preparation method of the present invention have the following beneficial effects: This invention reduces substrate warpage and loss by using a ceramic core plate, making it suitable for larger substrate sizes. This invention wraps the surface of a ceramic core board with a core board dielectric layer, which prevents the ceramic from easily breaking due to insufficient toughness and improves product lifespan. This invention improves the bonding force between the ceramic core board and the core board circuit layer by wrapping the ceramic core board with a core board dielectric layer and then setting a circuit layer, thereby improving the structural stability. This invention utilizes 3D printing technology to prepare ceramic core plates, thereby improving the substrate preparation efficiency. Attached Figure Description

[0018] Figure 1 The diagram shown is a schematic representation of the structure of the ceramic core plate provided in step 1 of Embodiment 1 of the present invention.

[0019] Figure 2 The diagram shows the structure of the core board dielectric layer in step 2 of Embodiment 1 of the present invention.

[0020] Figure 3 The diagram shows the structure of the second through hole set in step 3 of embodiment 1 of the present invention.

[0021] Figure 4 The diagram shows the structure of setting the first seed layer in step 4 of embodiment 1 of the present invention.

[0022] Figure 5 The diagram shows the structure of setting the first photosensitive layer in step 4 of embodiment 1 of the present invention.

[0023] Figure 6 The diagram shows the structure of setting the first conductive layer in step 4 of embodiment 1 of the present invention.

[0024] Figure 7 The diagram shows the structure after removing the first photosensitive layer in step 4 of an optional example of Embodiment 1 of the present invention.

[0025] Figure 8 The diagram shown is a schematic representation of the structure presented in step 5 of Embodiment 1 of the present invention, where an additive dielectric layer is set.

[0026] Figure 9 The diagram shows the structure of setting the second seed layer in step 6 of an optional example of Embodiment 1 of the present invention.

[0027] Figure 10 The diagram shows the structure of setting the second photosensitive layer in step 6 of an optional example of Embodiment 1 of the present invention.

[0028] Figure 11 The diagram shows the structure of setting the second conductive layer in step 6 of embodiment 1 of the present invention.

[0029] Figure 12 The diagram shows the structure after removing the second photosensitive layer in step 6 of an optional example of Embodiment 1 of the present invention.

[0030] Figure 13 The diagram shown is a schematic representation of the structure presented in step 6 of an optional example of the present invention, which involves adding a multilayer substrate.

[0031] Figure 14 The diagram shown is a schematic representation of the structure presented in step 6 of an optional example of the present invention, which involves setting a solder resist layer and a surface treatment layer.

[0032] Figure 15 The diagram shown is a schematic diagram of the substrate structure in Embodiment 2 of the present invention.

[0033] Component designation explanation 1. Ceramic core board; 12. First through-hole; 2. Core board dielectric layer; 21. Second through-hole; 3. Core board circuit layer; 31. First seed layer; 32. First photosensitive layer; 33. First conductive layer; 4. Substrate addition layer; 41. Addition layer dielectric layer; 42. Addition layer through-hole; 43. Addition layer circuit layer; 44. Second seed layer; 45. Second photosensitive layer; 46. Second conductive layer; 5. Solder resist layer; 6. Surface treatment layer. Detailed Implementation

[0034] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0035] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0036] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the accompanying drawings for devices in use or operation.

[0037] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0038] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex. Example 1:

[0039] This invention provides a method for preparing a substrate structure, the method comprising: Step 1: Provide a ceramic core plate, the ceramic core plate including a first surface and a second surface disposed opposite to each other, and provide a first through hole through the ceramic core plate on the first surface or the second surface of the ceramic core plate; Step 2: A core plate dielectric layer is provided on the first and second surfaces of the ceramic core plate, the core plate dielectric layer covering the first and second surfaces and filling the first through hole; Step 3: A second through hole is provided at the position between the core plate dielectric layer and the first through hole. The second through hole penetrates the core plate dielectric layer. The diameter of the second through hole is smaller than the diameter of the first through hole, and the wall of the second through hole does not contact the wall of the first through hole. Step 4: A patterned core board circuit layer is formed on the surface of the core board dielectric layer, and the core board circuit layer fills the second through hole; Step 5: A patterned add-on dielectric layer is formed on the patterned core board circuit layer. The add-on dielectric layer includes add-on vias that penetrate the add-on dielectric layer and expose a portion of the core board circuit layer. Step 6: A patterned augmentation circuit layer is formed on the patterned augmentation dielectric layer, and the augmentation circuit layer forms an effective electrical connection with a portion of the core board circuit layer through the augmentation via.

[0040] The method for preparing the substrate structure of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the above order does not strictly represent the order of preparation of the substrate structure protected by the present invention, and those skilled in the art can make changes according to the actual preparation steps.

[0041] First, such as Figure 1 As shown, in step 1, a ceramic core plate 1 is provided. The ceramic core plate 1 includes a first surface and a second surface that are disposed opposite to each other. A first through hole 12 is provided on the first surface or the second surface of the ceramic core plate 1 to penetrate the ceramic core plate 1.

[0042] In one embodiment, the ceramic core plate 1 including the first through hole 12 is prepared by 3D printing.

[0043] This invention uses 3D printing to prepare ceramic substrates, which can achieve higher precision in preparation, thus enabling the obtained substrates to adapt to higher density circuit alignment and meet the requirements of high-density, small-size substrates.

[0044] In one embodiment, the 3D printing method employed includes fused deposition modeling (FDM) or photopolymerization 3D printing.

[0045] Preferably, photopolymer 3D printing technology is used, which has a fast forming speed, a high degree of automation, can form any complex shape, has high dimensional accuracy and excellent surface quality, and can realize the rapid forming of high-precision fine workpieces, further improving the circuit density that the substrate can achieve.

[0046] Then, as Figure 2 As shown, in step 2, a core plate dielectric layer 2 is provided on the first and second surfaces of the ceramic core plate 1. The core plate dielectric layer 2 covers the first and second surfaces and fills the first through hole 12.

[0047] Next, as Figure 3 As shown, in step 3, a second through hole 21 is provided at the position between the core plate dielectric layer 2 and the first through hole 12. The second through hole 21 penetrates the core plate dielectric layer 2. The diameter of the second through hole 21 is smaller than the diameter of the first through hole 12. The wall of the second through hole 21 does not contact the wall of the first through hole 12.

[0048] In one embodiment, the second through hole 21 is formed by laser drilling using carbon dioxide or ultraviolet light.

[0049] In one embodiment, after the second through hole 21 is provided, desmear is performed.

[0050] Then, in step 4, a patterned core board circuit layer 3 is formed on the surface of the core board dielectric layer 2, and the core board circuit layer 3 fills the second through hole 21.

[0051] In one embodiment, a method for preparing the core board circuit layer 3 includes: like Figure 4 As shown, a first seed layer 31 is covered on the surface of the core plate dielectric layer 2, and the first seed layer 31 covers all exposed surfaces of the core plate dielectric layer 2; like Figure 5 As shown, a patterned first photosensitive layer 32 is provided on the surface of the first seed layer 31; like Figure 6 As shown, the gaps between the patterned first photosensitive layers 32 are filled with a first conductive layer 33, and the first conductive layer 33 is also filled with the second through-hole 21. like Figure 7As shown, after removing the first photosensitive layer 32 and the first seed layer 31 below the first photosensitive layer 32, the patterned first seed layer 31 and the first conductive layer 33 constitute the core board circuit layer 3.

[0052] In one embodiment, the first seed layer 31 is formed using a plated through hole (PTH) process.

[0053] In one embodiment, the first seed layer 31 is formed by chemical copper plating.

[0054] In one embodiment, the first seed layer 31 beneath the first photosensitive layer 32 is removed by a flash etching process.

[0055] Next, as Figure 8 As shown, in step 5, a patterned add-on dielectric layer 41 is provided on the patterned core board circuit layer 3. The add-on dielectric layer 41 includes an add-on via that penetrates the add-on dielectric layer 41, and the add-on via exposes a portion of the core board circuit layer 3.

[0056] Finally, in step 6, a patterned augmentation layer 43 is formed on the patterned augmentation dielectric layer 41, and the augmentation layer 43 forms an effective electrical connection with a portion of the core board circuit layer 3 through the augmentation via 42.

[0057] In one embodiment, a method for fabricating the augmentation circuit layer 43 includes: like Figure 9 As shown, a second seed layer is provided on the graphical build-up dielectric layer 41, and the second seed layer covers the exposed surface of the build-up dielectric layer 41 and the exposed surface of the core board circuit layer 3. like Figure 10 As shown, a patterned second photosensitive layer 45 is provided on the second seed layer; like Figure 11 As shown, the gaps between the patterned second photosensitive layers 45 are filled with a second conductive layer 46, and the second conductive layer 46 also fills the augmentation vias 42. like Figure 12 As shown, the second photosensitive layer 45 and the second seed layer below the second photosensitive layer 45 are removed, and the patterned second seed layer and the second conductive layer 46 constitute the added circuit layer 43.

[0058] In one embodiment, the second seed layer is set using a plated through hole (PTH) process.

[0059] In one embodiment, the second seed layer is set by chemical copper plating.

[0060] In one embodiment, the second seed layer beneath the second photosensitive layer 45 is removed by a flash etching process.

[0061] In one embodiment, the augmentation via 42 is formed by laser drilling using carbon dioxide or ultraviolet light.

[0062] In one embodiment, after the layering through-hole 42 is provided in the layering medium layer 41, desmearing is performed.

[0063] This invention achieves a large-size packaging substrate with low warpage and low loss by using ceramic as the core material within the substrate. The smaller warpage deformation results in a substrate structure with better coplanarity, thereby achieving better interconnect performance. At the same time, by wrapping the surface of the first through-hole 12 with the core dielectric layer 2, a buffer protection effect is provided for the ceramic core 1, solving the problem of ceramic being fragile due to insufficient toughness, improving the reliability of the substrate structure, and extending the product lifespan. In addition, the higher adhesion of the core dielectric layer 2 improves the bonding force between the ceramic core 1 and the core circuit layer 3, enhancing the structural stability of the substrate structure, thus enabling the ceramic core 1 to be widely used in production lines.

[0064] In one embodiment, such as Figure 13 As shown, the added circuit layer 43 and the added dielectric layer 41 constitute a substrate added layer 4, and multiple layers of the substrate added layer 4 are provided.

[0065] In one embodiment, each of the augmentation circuit layers 43 consists of a seed layer and a conductive layer, with the seed layer in contact with the underlying structural layer.

[0066] In one embodiment, the material of the augmentation medium layer 41 is ABF (Ajinomoto stacked film).

[0067] In one embodiment, such as Figure 14 As shown, the gaps between the augmentation circuit layers 43 on the exposed surface of the substrate structure are filled with solder resist layer 5.

[0068] In one embodiment, the material of the solder resist layer 5 is solder resist ink.

[0069] In one embodiment, such as Figure 14 As shown, a surface treatment layer 6 is provided on the surface of the augmentation circuit layer 43 exposed in the substrate structure. Example 2:

[0070] like Figure 15As shown, the present invention provides a substrate structure, which is obtained by any of the preparation methods in Embodiment 1 above. The substrate structure includes: a ceramic core board 1, a core board dielectric layer 2, a core board circuit layer 3, a multilayer substrate addition layer 4, a solder resist layer 5, and a surface treatment layer 6. The ceramic core plate 1 includes a first surface and a second surface disposed opposite to each other, and a first through hole 12 is provided in the ceramic core plate 1, which extends from the first surface to the second surface. The core plate dielectric layer 2 covers all exposed surfaces of the ceramic core plate 1. The core plate dielectric layer 2 has a second through hole 21 that penetrates the core plate dielectric layer 2 within the first through hole 12. The diameter of the second through hole 21 is smaller than the diameter of the first through hole 12, and the wall of the second through hole 21 does not contact the wall of the first through hole 12. The graphical core board circuit layer 3 is located on the surface of the core board dielectric layer 2 and fills the second through hole 21; Each substrate addition layer 4 includes a patterned addition dielectric layer 41 and an addition circuit layer 43. The addition dielectric layer 41 is provided with an addition via that penetrates the addition dielectric layer 41, and the addition via exposes a portion of the underlying core board circuit layer 3 or the addition circuit layer 43. The addition circuit layer 43 is located on the addition dielectric layer 41 and fills the addition via to achieve effective electrical connection with the exposed core board circuit layer 3 or the addition circuit layer 43. The solder resist layer 5 is located in the gap between the augmentation circuit layers 43 on the surface of the substrate structure, and the surface treatment layer 6 is located on the surface of the augmentation circuit layers 43 on the surface of the substrate structure.

[0071] In one embodiment, the material of the core plate dielectric layer 2 and / or the add-on dielectric layer 41 is ABF (Ajinomoto stacked film).

[0072] In one embodiment, the material of the ceramic core plate 1 is one or more of silicon carbide ceramics, silicon nitride ceramics, alumina ceramics, or aluminum nitride ceramics.

[0073] This invention reduces the weight of the substrate structure and makes the product lighter by using lightweight ceramic materials, while maintaining other excellent properties of the ceramic core board 1, such as low warpage, high density, and large size.

[0074] In summary, the substrate structure and its preparation method of the present invention can reduce the warpage and loss of the substrate by using a ceramic core plate, making it suitable for larger-sized substrates; at the same time, by wrapping the surface of the ceramic core plate with a core plate dielectric layer, the ceramic is prevented from easily breaking due to insufficient toughness, thus improving product life; in addition, the circuit layer is set after wrapping the ceramic core plate with the core plate dielectric layer, which improves the bonding force between the ceramic core plate and the core plate circuit layer, thereby improving structural stability; finally, the ceramic core plate is prepared by using 3D printing technology, which improves the substrate preparation efficiency.

[0075] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0076] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a substrate structure, characterized in that, The preparation method includes: A ceramic core plate is provided, the ceramic core plate including a first surface and a second surface disposed opposite to each other, and a first through hole is provided on the first surface or the second surface of the ceramic core plate; A core plate dielectric layer is provided on the first and second surfaces of the ceramic core plate, and the core plate dielectric layer covers the first and second surfaces and fills the first through hole; A second through hole is provided at the position between the core plate dielectric layer and the first through hole. The second through hole penetrates the core plate dielectric layer. The diameter of the second through hole is smaller than the diameter of the first through hole, and the wall of the second through hole does not contact the wall of the first through hole. A patterned core board circuit layer is provided on the surface of the core board dielectric layer, and the core board circuit layer fills the second through-hole; A patterned add-on dielectric layer is disposed on the patterned core board circuit layer. The add-on dielectric layer includes add-on vias that penetrate the add-on dielectric layer and expose a portion of the core board circuit layer. The material of the add-on dielectric layer is Ajinomoto film. A patterned augmentation circuit layer is disposed on the patterned augmentation dielectric layer, and the augmentation circuit layer forms an effective electrical connection with a portion of the core board circuit layer through the augmentation via.

2. The method for preparing the substrate structure according to claim 1, characterized in that, The ceramic core plate including the first through hole is prepared by 3D printing.

3. The method for preparing the substrate structure according to claim 2, characterized in that, The 3D printing methods used include fused deposition modeling (FDM) or photopolymerization 3D printing.

4. The method for preparing the substrate structure according to claim 1, characterized in that, The method for preparing the core board circuit layer includes: A first seed layer is applied to the surface of the core plate dielectric layer, and the first seed layer covers all exposed surfaces of the core plate dielectric layer. A patterned first photosensitive layer is formed on the surface of the first seed layer; A first conductive layer is filled in the gaps between the patterned first photosensitive layers, and the first conductive layer is also filled with the second via. The first photosensitive layer and the first seed layer below the first photosensitive layer are removed, and the patterned first seed layer and the first conductive layer constitute the core board circuit layer.

5. The method for preparing the substrate structure according to claim 1, characterized in that, The method for preparing the added circuit layer includes: A second seed layer is disposed on the graphical build-up dielectric layer, the second seed layer covering the exposed surfaces of the build-up dielectric layer and the exposed surfaces of the core board circuit layer; A patterned second photosensitive layer is disposed on the second seed layer; A second conductive layer is filled into the gaps between the patterned second photosensitive layers, and the second conductive layer also fills the augmentation vias; The second photosensitive layer and the second seed layer below the second photosensitive layer are removed, and the patterned second seed layer and the second conductive layer constitute the added circuit layer.

6. The method for preparing the substrate structure according to claim 5, characterized in that, The added circuit layer and the added dielectric layer constitute a substrate added layer, and multiple substrate added layers are provided.

7. The method for preparing the substrate structure according to claim 1, characterized in that, A solder resist layer is used to fill the gaps between the augmentation circuit layers on the exposed surface of the substrate structure.

8. The method for preparing the substrate structure according to claim 1, characterized in that, A surface treatment layer is provided on the surface of the exposed augmentation circuit layer of the substrate structure.

9. A substrate structure, characterized in that, The substrate structure is obtained by the substrate structure preparation method according to any one of claims 1-8, and the substrate structure includes: a ceramic core board, a core board dielectric layer, a core board circuit layer, a multilayer substrate add-in layer, a solder resist layer, and a surface treatment layer. The ceramic core plate includes a first surface and a second surface disposed opposite to each other, and a first through hole is provided in the ceramic core plate, extending from the first surface to the second surface; The core plate dielectric layer covers all exposed surfaces of the ceramic core plate. The core plate dielectric layer has a second through hole that penetrates the core plate dielectric layer within the first through hole. The diameter of the second through hole is smaller than that of the first through hole, and the wall of the second through hole does not contact the wall of the first through hole. The graphical representation of the core board circuit layer is located on the surface of the core board dielectric layer and fills the second through-hole; Each substrate add-in layer includes a patterned add-in dielectric layer and an add-in circuit layer. The add-in dielectric layer is provided with add-in vias that penetrate the add-in dielectric layer and expose a portion of the underlying core board circuit layer or the add-in circuit layer. The add-in circuit layer is located on the add-in dielectric layer and fills the add-in vias to achieve effective electrical connection with the exposed core board circuit layer or the add-in circuit layer. The solder resist layer is located in the gap between the augmentation circuit layers on the surface of the substrate structure, and the surface treatment layer is located on the surface of the augmentation circuit layers on the surface of the substrate structure.

10. The substrate structure according to claim 9, characterized in that, The ceramic core plate is made of one or more of silicon carbide ceramics, silicon nitride ceramics, alumina ceramics, or aluminum nitride ceramics.

Images