Display device

Abstract

The application provides a display device, which comprises a display panel, a driving controller and an emission driver, the emission driver outputs a light-emitting control signal to a sub-pixel, the driving controller generates a control signal to control the emission driver to generate the light-emitting control signal, a display period in the display panel comprises a write frame with a first time length, in the write frame, by making a ratio of a number of periods of the light-emitting control signal to the first time length greater than a critical flicker frequency, and a ratio of the first time length to a time length required by the driving controller to control one pixel unit to realize display greater than the number of pixel units, the display panel can balance display performance and endurance performance.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to a display device. Background Technology

[0002] With the continuous upgrading of display devices such as smartphones and smartwatches, users have increasingly higher requirements for display performance and battery life. However, in actual use, achieving higher display performance often increases power consumption, thereby reducing battery life. To improve battery life, display performance must be sacrificed. Therefore, display devices cannot simultaneously meet both display performance and battery life requirements. Summary of the Invention

[0003] This invention provides a display device that can balance display performance requirements and battery life requirements.

[0004] This invention provides a display device, comprising:

[0005] A display panel includes a plurality of sub-pixels, the plurality of sub-pixels forming a plurality of pixel units arranged in an array, each pixel unit including the plurality of sub-pixels; and

[0006] An emission driver configured to output an emission control signal to the sub-pixel;

[0007] A drive controller is configured to generate a control signal to control the transmitter driver to generate the light emission control signal;

[0008] The process of displaying the screen on the display panel includes multiple display cycles. Each display cycle includes the duration of a write frame, which is a first duration. Within the write frame, the light emission control signal has multiple cycles, and the ratio of the number of cycles of the light emission control signal to the first duration is greater than the critical flicker frequency.

[0009] Wherein, the ratio of the first duration to the duration required for the drive controller to control one pixel unit to achieve display is greater than the number of pixel units in the display device.

[0010] This invention provides a display device including a display panel, a drive controller, and an emitter driver. The emitter driver outputs a light emission control signal to sub-pixels. The drive controller is configured to generate a control signal to control the emitter driver to control the display state of multiple sub-pixels. At least one display cycle of the display panel has a write frame. Within a first duration corresponding to the write frame, by ensuring that the ratio of the number of cycles of the light emission control signal to the first duration is greater than a critical flicker frequency, the sub-pixels switch between display and non-display states multiple times within the write frame under the control of the light emission control signal. This reduces the audience's perception of display panel flicker within the total duration corresponding to the write frame, resulting in better display performance. Furthermore, the ratio of the first duration to the duration required for the drive controller to control one pixel unit to achieve display is greater than the number of pixel units in the display device, thereby increasing the duration of each frame to achieve a balance between display performance and battery life. Attached Figure Description

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of the structure of the display device provided in an embodiment of the present invention;

[0013] Figure 2 This is a diagram illustrating the human eye's perception of flickering, provided in an embodiment of the present invention.

[0014] Figure 3 This is a schematic diagram of the sub-pixel structure provided in an embodiment of the present invention;

[0015] Figure 4 This is a timing diagram of the corresponding high-frequency driving mode provided in the embodiments of the present invention;

[0016] Figure 5 This is a schematic diagram illustrating the principle of increasing the duration of each frame as provided in an embodiment of the present invention;

[0017] Figure 6 This is a timing diagram of the write frame corresponding to the ultra-low frequency drive mode provided in the embodiments of the present invention;

[0018] Figure 7 This is a schematic diagram of the measured emission waveform with a brightness of 50 nits provided in the embodiment of the present invention;

[0019] Figure 8 This is a timing diagram of the next display cycle corresponding to the ultra-low frequency driving mode provided in the embodiments of the present invention;

[0020] Figure 9 This is a schematic diagram of power consumption test results provided in an embodiment of the present invention. Detailed Implementation

[0021] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of the present invention and are not intended to limit the present invention. In the present invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0022] Specifically, such as Figure 1 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. The present invention provides a display device, including a display panel and a driving control module.

[0023] Optionally, the display panel includes a self-emissive display panel. Optionally, the self-emissive display panel includes an organic light-emitting diode (OLED) display panel, a sub-millimeter OLED display panel, a micro OLED display panel, a quantum dot display panel, etc.

[0024] The display panel includes multiple sub-pixels SP, multiple scan lines, multiple data lines, and multiple light emission control lines. The multiple sub-pixels SP form multiple pixel units Pi arranged in an array. The multiple scan lines, multiple data lines, and multiple light emission control lines are electrically connected to the multiple sub-pixels SP, so that the multiple sub-pixels SP can realize the display function according to the corresponding scan signal, data signal Data, and light emission control signal EM.

[0025] Optionally, each pixel unit Pi includes three sub-pixels SP. Optionally, the three sub-pixels SP included in each pixel unit Pi emit different colors. The emission colors of the sub-pixels SP include red, green, blue, yellow, white, etc.

[0026] Optionally, the drive control module includes a gate driver, a transmit driver, and a data driver.

[0027] The gate driver is configured to output a scan signal to the display panel. Optionally, the gate driver is electrically connected to multiple scan lines to transmit the scan signal to multiple sub-pixels (SPs) via the multiple scan lines.

[0028] Optionally, the gate driver includes a first gate driving unit and a second gate driving unit. The first gate driving unit is configured to output a first scan signal Pscan1 to the display panel. The second gate driving unit is configured to output a second scan signal Pscan2 to the display panel.

[0029] The emitter driver is configured to output an luminance control signal EM to the display panel. Optionally, the emitter driver is electrically connected to multiple luminance control lines to output the luminance control signal EM to multiple sub-pixels SP via the multiple luminance control lines.

[0030] The data driver is configured to output a data signal (Data) to the display panel. Optionally, the data driver is electrically connected to multiple data lines to output the data signal (Data) to multiple sub-pixels (SP) via the multiple data lines.

[0031] Optionally, the drive controller includes a receiver, registers, a timing controller, a memory controller, random access memory, and a dynamic frame rate module. The principle by which the drive controller controls the gate driver, data driver, and transmit driver to control the display state of multiple pixel units Pi is as follows:

[0032] Phase 1: The receiver outputs instruction c to the register based on the register instruction a sent by the host, and the register is configured according to instruction c.

[0033] Second stage: The host sends image data signal b to the receiver at certain time intervals (e.g., one minute). The receiver outputs image data signal d to the memory controller based on the image data signal b sent by the host. The memory controller outputs image data signal f to the random access memory based on the image data signal d.

[0034] The third stage: The register outputs the instruction e, which sets the corresponding timing control, to the timing controller. The random access memory outputs the image data signal h to the timing controller based on the image data signal f. After the dynamic frame rate module detects that the random access memory has an updated data signal g, it outputs the high-frequency switching instruction i to the timing controller.

[0035] Fourth stage: The timing controller sends the corresponding high-frequency switching command j to the gate driver, transmitter driver and data driver respectively, so as to control the display panel to display multiple sub-pixels SP in high-frequency driving mode through the gate driver, transmitter driver and data driver.

[0036] Fifth stage: The host stops outputting image data signals to the receiver. The dynamic frame rate module detects that the random access memory has no updated data signal g and outputs the low frequency switching command i to the timing controller.

[0037] Sixth stage: The timing controller sends the corresponding low-frequency switching command j to the gate driver, transmitter driver and data driver respectively, so as to control the display panel to display multiple sub-pixels SP in ultra-low frequency driving mode through the gate driver, transmitter driver and data driver.

[0038] To achieve the display function, the display panel can have multiple display cycles. To implement frequency conversion technology, the duration of each display cycle of the display panel can be different. When the display panel uses a high-frequency driving mode, the display cycle may only include one write frame (WF). When the display panel uses a frequency lower than the high-frequency driving mode, the display panel may include one write frame (WF) and at least one hold frame (HF). The data signal Data is written to the sub-pixel SP during the effective pulse duration of the second scan signal Pscan2 in the write frame (WF), and is held in the hold frame (HF) to maintain the data signal Data written to the sub-pixel SP in the write frame (WF), so that when the display panel uses a frequency lower than the high-frequency driving mode, the information displayed by the display panel within the total duration tsu corresponding to a display cycle is the same.

[0039] The lower the frequency at which a display panel achieves its display effect, the better it is for improving the battery life of the display device. Specifically, to further enhance battery life, the display panel can employ an ultra-low frequency, defined as a frequency less than 1Hz. However, using an ultra-low frequency can cause significant flickering issues.

[0040] To enable the display panel to achieve display at ultra-low frequencies while improving flicker issues, thus balancing display performance and battery life, this application provides that each of the write frame (WF) and multiple hold frames (HF) has a first duration (tfr). Within each of the write frame (WF) and multiple hold frames (HF), the light emission control signal (EM) has multiple periods (T). The ratio of the number of periods (Ncft) of the light emission control signal (EM) to the first duration (tfr) is greater than the critical flicker frequency (CFF), i.e., Ncft / tfr > CFF. This allows the sub-pixel (SP) to switch between display and non-display states multiple times within the write frame (WF) and multiple hold frames (HF) under the control of the light emission control signal (EM). This reduces the audience's perception of flicker within the total duration (tsu) of the write frame (WF) and multiple hold frames (HF), resulting in better display performance for the display panel.

[0041] By ensuring that the light emission control signal EM has one valid pulse and one invalid pulse in each cycle, and the first scan signal Pscan1 has one valid pulse during the duration of each invalid pulse of the light emission control signal EM in the write frame WF and multiple hold frames HF, and the second scan signal Pscan2 has one valid pulse during the duration of the invalid pulse in the first cycle of the light emission control signal EM in the write frame WF, the sub-pixel SP, under the control of the light emission control signal EM, the first scan signal Pscan1, and the second scan signal Pscan2, switches between display and non-display states multiple times within the write frame WF and multiple hold frames HF according to the same display content within the total duration tsu corresponding to one display cycle. This ensures that multiple sub-pixel SPs display the same information within the total duration tsu corresponding to the write frame WF and multiple hold frames HF, thereby achieving a balance between display performance and battery life.

[0042] The critical flicker frequency (CFF) is the minimum flicker frequency that the human eye can perceive as stable light. Optionally, the critical flicker frequency (CFF) is greater than or equal to 45 Hz.

[0043] like Figure 2 This is a perceptual diagram of flicker by the human eye provided in an embodiment of the present invention. Since the critical flicker frequency (CFF) is closely related to many factors such as display brightness, ambient brightness, and viewing distance, and is not a constant, according to... Figure 2 It is known that the human eye cannot perceive flicker when the frequency is greater than or equal to 60Hz. Therefore, the ratio of the number of cycles Ncft of the light emission control signal EM in each of the write frame WF and multiple hold frames HF to the first duration tfr can be greater than or equal to 60Hz; that is, Ncft / tfr≥60Hz, to ensure that the human eye cannot perceive any flicker in the display screen during actual application.

[0044] Understandably, the total duration tsu corresponding to one display cycle is the sum of the multiple first durations tfr corresponding to the write frames (WF) and multiple hold frames (HF) included in one display cycle. That is, tsu = m * tfr; where m is the total number of frames, and the total number of frames m is the sum of the number of write frames (WF) and multiple hold frames (HF) included in one display cycle.

[0045] Optionally, to enable the display panel to achieve ultra-low frequency display, the total number of frames m in one display cycle must be less than or equal to the upper limit of frame skipping SKL provided by the drive control module; that is, m ≤ SKL. Correspondingly, the ratio of the total duration tsu to the first duration tfr corresponding to one display cycle is less than or equal to the upper limit of frame skipping SKL provided by the drive control module; that is, tsu / tfr ≤ SKL. Optionally, the upper limit of frame skipping SKL provided by the drive control module is determined by the number of bits in the register controlling the number of frame skips included in the drive control module. Specifically, if the register controlling the number of frame skips is x bits, then the upper limit of frame skipping is equal to 2^x; if the register controlling the number of frame skips is 8 bits, then the upper limit of frame skipping SKL is equal to 2^8 = 256; if the register controlling the number of frame skips is 10 bits, then the upper limit of frame skipping SKL is equal to 2^10 = 1024. Figure 1 The registers shown represent all the registers included in the display device, not just the registers used to control the number of frame skips.

[0046] Optionally, since the data signal Data is written to the sub-pixel SP within the effective pulse duration of the second scan signal Pscan2 in the write frame WF, and the information displayed on the display panel is the same within the total duration tsu corresponding to one display cycle, the target frequency f1 of the second scan signal Pscan2 within the total duration tsu corresponding to one display cycle (i.e., the sum of multiple first durations corresponding to the write frame WF and multiple hold frames HF) can be less than 1Hz, i.e., f1 < 1Hz. This allows the sub-pixel SP to update the display information according to each display cycle, thereby enabling the display panel to achieve ultra-low frequency display. Correspondingly, the total duration tsu corresponding to one display cycle is the reciprocal of the target frequency f1 of the second scan signal Pscan2 in one display cycle; i.e., tsu = 1 / f1.

[0047] Optionally, the target frequency f1 is the frequency used by the display panel when it adopts an ultra-low frequency driving mode to achieve display. That is, the target frequency f1 can be equal to 0.99Hz, 0.98Hz, ..., 0.9Hz, 0.89Hz, ..., 0.75Hz, ..., 0.5Hz, ..., 0.11Hz, 0.1Hz, 0.099Hz, 0.098Hz, ..., 0.09Hz, 0.089Hz, ..., 0.08Hz, 0.079Hz, ..., 0.07Hz, 0.069Hz, ..., 0.064Hz, ..., 0.06Hz, ..., 0.05Hz, ..., 0.04Hz, ..., 0.032Hz, ..., 0.03Hz, ..., 0.02Hz, ..., 0.016Hz, 0.015Hz, ..., 0.01Hz, 0.009Hz, 0.008Hz, ..., 0.006Hz, 0.005Hz, 0.004Hz, ... and so on.

[0048] Optionally, within the write frame WF, the product of the fundamental frequency f3 of the second scan signal Pscan2 and the number of cycles Ncft of the light emission control signal EM is equal to the intermediate frequency f2 of the light emission control signal EM, so that within each corresponding first duration tfr in the write frame WF and the plurality of hold frames HF, the number of cycles Ncft included in the light emission control signal EM meets the requirements, thereby enabling the display panel to meet the display performance requirements.

[0049] Since the data signal Data is written to the sub-pixel SP within the effective pulse duration of the second scan signal Pscan2 in the write frame WF, and the information displayed on the display panel is the same within the total duration tsu corresponding to one display cycle, the first duration tfr corresponding to the write frame WF and each hold frame HF can be made to be the reciprocal of the fundamental frequency f3 of the second scan signal Pscan2 in the write frame WF; that is, tfr = 1 / f3, so that the sub-pixel SP displays the same information within one display cycle, thereby enabling the display panel to achieve ultra-low frequency display.

[0050] Optionally, the total number of frames m can be obtained based on the base frequency f3 and the target frequency f1, that is, the ratio of the base frequency f3 to the target frequency f1 is equal to the total number of frames m (that is, the ratio of the base frequency f3 to the target frequency f1 is equal to the sum of the number of written frames WF and multiple hold frames HF); that is, f3 / f1 = m.

[0051] The following will explain the working principles of display panels using high-frequency and low-frequency driving modes, taking into account the specific forms of sub-pixels (SPs). Optionally, such as... Figure 3 This is a schematic diagram of the structure of a sub-pixel SP provided in an embodiment of the present invention. It should be understood that the structure of the sub-pixel SP is not limited to... Figure 3 As shown in the figure.

[0052] Each sub-pixel SP includes a driving transistor Tdr, a first reset transistor Ti1, a second reset transistor Ti2, a data transistor Tda, a light-emitting control transistor, and a light-emitting device D.

[0053] The driving transistor Tdr is configured to generate a driving current based on the data signal Data to drive the light-emitting device D to emit light. Optionally, the driving transistor Tdr includes an input electrode connected to a first node N1, an output electrode connected to a second node N2, and a control electrode connected to a third node N3. The control electrode is the gate, the input electrode is one of the source and drain, and the output electrode is the other of the source and drain.

[0054] The first reset transistor Ti1 is configured to reset the anode potential of the light-emitting device D according to the first scan signal Pscan1. Optionally, the first reset transistor Ti1 includes a control electrode configured to receive the first scan signal Pscan1, an input electrode configured to receive the first reset signal VI1, and an output electrode connected to the fourth node N4.

[0055] The second reset transistor Ti2 is configured to reset the input and output electrode potentials of the drive transistor Tdr according to the first scan signal Pscan1. Optionally, the second reset transistor Ti2 includes a control electrode configured to receive the first scan signal Pscan1, an input electrode configured to receive the second reset signal VI2, and an output electrode connected to the first node N1. The first reset transistor Ti1 and the second reset transistor Ti2 are turned on under the level state corresponding to the valid pulse of the first scan signal Pscan1, and turned off under the level state corresponding to the invalid pulse of the first scan signal Pscan1.

[0056] The data transistor Tda is configured to transmit a data signal Data to the driving transistor Tdr through the first node N1 according to the second scan signal Pscan2. Optionally, the data transistor Tda includes a control electrode configured to receive the second scan signal Pscan2, an input electrode configured to receive the data signal Data, and an output electrode connected to the first node N1. The data transistor Tda is turned on under the level state corresponding to the valid pulse of the second scan signal Pscan2, and turned off under the level state corresponding to the invalid pulse of the second scan signal Pscan2.

[0057] The light-emitting control transistor is configured to control the switching of the drive current path according to the light-emitting control signal EM. Optionally, the light-emitting control transistor includes a first switching transistor Ts1 and a second switching transistor Ts2; the first switching transistor Ts1 includes a control electrode configured to receive the light-emitting control signal EM, an input electrode configured to be connected to a first power supply terminal VDD, and an output electrode connected to a first node N1; the second switching transistor Ts2 includes a control electrode configured to receive the light-emitting control signal EM, an input electrode configured to be connected to a second node N2, and an output electrode connected to a fourth node N4. The first switching transistor Ts1 and the second switching transistor Ts2 are turned on under the level state corresponding to the valid pulse of the light-emitting control signal EM, and turned off under the level state corresponding to the invalid pulse of the light-emitting control signal EM.

[0058] The light-emitting device D includes an anode connected to the fourth node N4 and a cathode configured to be connected to the second power supply terminal VSS. Optionally, the light-emitting device D includes an organic light-emitting diode, a sub-millimeter light-emitting diode, a miniature light-emitting diode, etc.

[0059] Alternatively, please continue reading Figures 1-3 The gate driver also includes a third gate driving unit, which is configured to output a third scan signal Nscan1 and a fourth scan signal Nscan2 to the sub-pixel SP.

[0060] Optionally, the third scan signal Nscan1 and the fourth scan signal Nscan2 each have an effective pulse during the invalid pulse duration of the first cycle of the light emission control signal EM in the write frame WF, so as to initialize the potential of the third node N3 in the write frame WF and transmit the data signal Data to the gate of the driving transistor Tdr in the write frame WF, thereby making the sub-pixel SP maintain the display according to the data signal Data written to the sub-pixel SP in the write frame WF in the hold frame HF.

[0061] The sub-pixel SP also includes a compensation transistor Tc, a third reset transistor Ti3, and a storage capacitor Cst.

[0062] The compensation transistor Tc includes a control electrode configured to receive a third scan signal Nscan1, an input electrode configured to be connected to a third node N3, and an output electrode connected to a second node N2.

[0063] The third reset transistor Ti3 includes a control electrode configured to receive a fourth scan signal Nscan2, an input electrode configured to receive a third reset signal VI3, and an output electrode connected to a third node N3.

[0064] The storage capacitor Cst includes a first electrode configured to be connected to a first power supply terminal VDD and a second electrode configured to be connected to a third node N3.

[0065] Optionally, the active layers of the compensation transistor Tc and the third reset transistor Ti3 both comprise oxide semiconductors, while the active layers of the driving transistor Tdr, the first reset transistor Ti1, the second reset transistor Ti2, the data transistor Tda, and the light-emitting control transistor all comprise silicon semiconductors. Optionally, the silicon semiconductors include materials such as monocrystalline silicon, polycrystalline silicon, and amorphous silicon, and the oxide semiconductors include at least one of materials such as zinc oxide, zinc tin oxide, zinc indium oxide, indium oxide, titanium oxide, indium gallium zinc oxide, and indium zinc tin oxide. Optionally, the driving transistor Tdr, the first reset transistor Ti1, the second reset transistor Ti2, the data transistor Tda, and the light-emitting control transistor are fabricated using a low-temperature polycrystalline silicon process.

[0066] To improve the flickering problem, the potential of the first node N1, the potential of the second node N2, the potential of the third node N3, and the potential of the fourth node N4 are kept equal when the sub-pixel SP is written to the frame WF and each hold frame HF to achieve multiple non-display or display states.

[0067] Optionally, during the duration of multiple invalid pulses of the light emission control signal EM, the potentials of the first node N1, the second node N2, the third node N3, and the fourth node N4 remain equal to improve the flickering problem.

[0068] Optionally, the voltage value of the second reset signal VI2 can be controlled to ensure that the potential of the first node N1 remains equal and the potential of the second node N2 remains equal during the duration of multiple invalid pulses of the light emission control signal EM. Optionally, the driving transistor Tdr is a P-type transistor. During the duration of each valid pulse of the first scan signal Pscan1, the difference between the potential of the third node N3 and the second reset signal VI2 is less than the threshold voltage of the driving transistor Tdr, so that when the second reset transistor Ti2 is turned on, the driving transistor Tdr is also turned on, thereby resetting the input electrode potential (i.e., the potential of the first node N1) and the output electrode potential (i.e., the potential of the second node N2) of the driving transistor Tdr according to the first scan signal Pscan1.

[0069] Figure 4 This is a timing diagram of the corresponding high-frequency driving mode provided in the embodiments of the present invention. Taking a frequency of 60Hz corresponding to the high-frequency driving mode, where the driving transistor Tdr, the first reset transistor Ti1, the second reset transistor Ti2, the data transistor Tda, the first switching transistor Ts1, and the second switching transistor Ts2 are all P-type transistors, and the compensation transistor Tc and the third reset transistor Ti3 are all N-type transistors, the following is an example. Figure 3 The working principle of the sub-pixel SP is explained below. A display cycle consists only of the write frame WF, which includes the initialization phase P1, the data writing phase P2, the node reset phase P3, and the light emission phase P4.

[0070] Initialization Phase P1: The light emission control signal EM, the first scan signal Pscan1, the second scan signal Pscan2, the third scan signal Nscan1, and the fourth scan signal Nscan2 are all at high levels. The third reset transistor Ti3 turns on in response to the fourth scan signal Nscan2. The compensation transistor Tc turns on in response to the third scan signal Nscan1, causing the driving transistor Tdr to form a diode connection. The driving transistor Tdr turns on, and the third reset signal resets the potentials of the third node N3, the second node N2, and the first node N1. The first reset transistor Ti1 and the second reset transistor Ti2 both turn off in response to the first scan signal Pscan1. The data transistor Tda turns off in response to the second scan signal Pscan2. The first switching transistor Ts1 and the second switching transistor Ts2 both turn off in response to the light emission control signal EM.

[0071] In the data writing phase P2: the light emission control signal EM, the first scan signal Pscan1, and the third scan signal Nscan1 are all at high levels, while the second scan signal Pscan2 and the fourth scan signal Nscan2 are at low levels. The data transistor Tda turns on in response to the second scan signal Pscan2, and the compensation transistor Tc turns on in response to the third scan signal Nscan1, causing the driving transistor Tdr to form a diode connection. The driving transistor Tdr then turns on, and the data signal Data is transmitted to the third node N3 via the data transistor Tda, the first node N1, the driving transistor Tdr, the second node N2, and the compensation transistor Tc, thus realizing the writing of the data signal Data and the capture of the threshold voltage of the driving transistor Tdr. The first reset transistor Ti1 and the second reset transistor Ti2 are both turned off in response to the first scan signal Pscan1. The first switching transistor Ts1 and the second switching transistor Ts2 are turned off in response to the light emission control signal EM, and the third reset transistor Ti3 is turned off in response to the fourth scan signal Nscan2.

[0072] During node reset phase P3: the light emission control signal EM and the second scan signal Pscan2 are both at high levels, while the first scan signal Pscan1, the third scan signal Nscan1, and the fourth scan signal Nscan2 are all at low levels. The first reset transistor Ti1 and the second reset transistor Ti2 are both turned on in response to the first scan signal Pscan1, and the first reset signal VI1 resets the potential of the fourth node N4. The second reset signal VI2 has a higher voltage value. The voltage difference between the gate and source of the driving transistor Tdr is the same as the voltage difference between the third node N3 and the first node N1. Therefore, making the voltage difference between the third node N3 and the first node N1 less than the threshold voltage of the driving transistor Tdr will turn on the driving transistor Tdr, thereby resetting the potentials of the first node N1 and the second node N2 with the second reset signal VI2. The data transistor Tda is turned off in response to the second scan signal Pscan2, the compensation transistor Tc is turned off in response to the third scan signal Nscan1, the third reset transistor Ti3 is turned off in response to the fourth scan signal Nscan2, and the first switching transistor Ts1 and the second switching transistor Ts2 are both turned off in response to the light emission control signal EM.

[0073] During the light-emitting stage P4: the light-emitting control signal EM, the third scan signal Nscan1, and the fourth scan signal Nscan2 are all at low levels, while the first scan signal Pscan1 and the second scan signal Pscan2 are at high levels. The first switching transistor Ts1 and the second switching transistor Ts2 are both turned on in response to the light-emitting control signal EM. The driving transistor Tdr remains on due to the storage capacitor. The driving current generated by the driving transistor Tdr according to the data signal Data flows in the path between the first power supply terminal VDD and the second power supply terminal VSS, causing the light-emitting device D to emit light. The first reset transistor Ti1 and the second reset transistor Ti2 are both turned off in response to the first scan signal Pscan1. The data transistor Tda is turned off in response to the second scan signal Pscan2. The compensation transistor Tc is turned off in response to the third scan signal Nscan1, and the third reset transistor Ti3 is turned off in response to the fourth scan signal Nscan2.

[0074] Table 1 shows the potential changes of the first node N1, second node N2, third node N3, and fourth node N4 in the sub-pixel SP during each working stage of the corresponding high-frequency driving mode. In Table 1, Vth is the threshold voltage of the driving transistor Tdr, and Lum.vo indicates that the actual potential is affected by the charging and discharging state in the circuit and has a certain degree of fluctuation.

[0075]

[0076] To improve the flickering problem caused by the ultra-low frequency drive mode while realizing the display function of the ultra-low frequency drive mode, the duration of each frame in the next display cycle of the corresponding ultra-low frequency drive mode is increased, and then frame skipping is used to realize the display function of the ultra-low drive mode.

[0077] like Figure 5 This is a schematic diagram illustrating the principle of increasing the duration of each frame according to an embodiment of the present invention. Figure 5 In this context, VBP represents the vertical rear porch, VFP represents the vertical front porch, HBP represents the horizontal rear porch, and HFP represents the horizontal front porch. y1, y3, and y5 all represent the number of rows in pixel unit Pi, while y2, y4, and y6 all represent the number of columns in pixel unit Pi. y1≠y3≠y5; y2≠y4≠y6.

[0078] Since the resolution of the display panel is fixed after manufacturing, if you want to increase the duration of each frame, you can make the drive control module think that the number of scan lines V-proch and the number N to be controlled need to be increased. V-porch The number of rows greater than the number of pixel units Pi, and / or the number of scans N of pixel units Pi that need to be controlled per row. H-line The number of columns greater than the number of pixel units Pi. This means the number of scans N of pixel units Pi that need to be controlled in each row. H-line Without changing the number of scan lines V-proch required for control, increase the number N. V-porch This increases the number of rows required to scan per frame, thereby increasing the duration of each frame; alternatively, the number of scan rows V-proch and the number N-proch can be controlled. V-porch Without changing the parameters, increase the scan time N of the pixel units Pi that need to be controlled per row. H-line / f osc This allows for an increase in the duration of each frame; it can also increase the number of scan lines V-proch required for control, N. V-porch And the scan time N for the number of pixel units Pi that need to be controlled per row. H-line / f osc This increases the duration of each frame, thus achieving the desired increase in duration. Where f osc This represents the crystal oscillator frequency of the drive control module, 1 / f osc This indicates the time required for the drive control module to control one pixel unit Pi to achieve display.

[0079] The duration T of each frame frame =N V-porch *N H-line / f osc However, due to the functional limitations of the drive control module, N H-line and N V-porch The values ​​of N all have an upper limit; for example, the register that controls the number of skipped frames is 10 bits.H-line The maximum value for N is 1024. V-porch The maximum value can be VAA + 1028, where VAA is N. V-porch Minimum possible value.

[0080] After increasing the duration of each frame, the ratio of the first duration tfr corresponding to the write frame WF and each hold frame HF in a display cycle to the duration required for the drive controller to control one pixel unit Pi to achieve display (i.e., t1*f) is calculated. osc =N V-porch *N H-line It is greater than the number of pixel units Pi of the display device.

[0081] Because flickering occurs when each frame is displayed at a frequency below the critical flicker frequency (CFF), timing optimization is implemented. Specifically, during the initialization phase P1, data writing phase P2, and node reset phase P3 of the frame WF, the working principle of the display panel using high-frequency driving mode and ultra-low-frequency driving mode is similar. When using ultra-low-frequency driving mode, the light-emitting phase P4 includes multiple light-emitting sub-phases and multiple non-light-emitting sub-phases. In each light-emitting sub-phase, the light-emitting control signal EM has a valid pulse, while the first scan signal Pscan1, the second scan signal Pscan2, the third scan signal Nscan1, and the fourth scan signal Nscan2 all have corresponding invalid pulses. This causes the first switching transistor Ts1 and the second switching transistor Ts2 to turn on in response to the light-emitting control signal EM, and the driving transistor Tdr, based on the driving current generated by the data signal Data, flows through the path between the first power supply terminal VDD and the second power supply terminal VSS to control the light-emitting device D to emit light. In each non-light-emitting stage, the light-emitting control signal EM, the third scan signal Nscan1, and the fourth scan signal Nscan2 all have corresponding invalid pulses. The first scan signal Pscan1 has an effective pulse during the duration of the invalid pulse in the light-emitting control signal EM, and the duration of the effective pulse in the first scan signal Pscan1 is less than or equal to the duration of the invalid pulse in the light-emitting control signal EM. This causes the first reset transistor Ti1 and the second reset transistor Ti2 to be turned on in response to the first scan signal Pscan1. This allows the first reset signal VI1 to reset the potential of the fourth node N4. The second reset signal VI2, with its higher voltage value, turns on the driving transistor Tdr, thereby resetting the potentials of the first node N1 and the second node N2. By switching the sub-pixel SP between the display state and the non-display state during the light-emitting stage, the display frequency is increased, thereby improving the flicker problem.

[0082] Specifically, let's first explain the timing diagram of the write frame WF in the corresponding ultra-low frequency drive mode. Figure 6 This is a timing diagram of the write frame WF in the ultra-low frequency driving mode provided in this embodiment of the invention; taking the first duration tfr corresponding to the write frame WF, where the second scan signal Pscan2 has a base frequency f3 of 16Hz, and the driving transistor Tdr, the first reset transistor Ti1, the second reset transistor Ti2, the data transistor Tda, the first switching transistor Ts1, and the second switching transistor Ts2 are all P-type transistors, while the compensation transistor Tc and the third reset transistor Ti3 are all N-type transistors, for example... Figure 3 The working principle of the light-emitting stage P4 in the corresponding ultra-low frequency driving mode of the sub-pixel SP is explained. The light-emitting stage P4 includes the first light-emitting sub-stage P41, the first non-light-emitting sub-stage P42, the second light-emitting sub-stage P43, the second non-light-emitting sub-stage P44, the third light-emitting sub-stage P45, the third non-light-emitting sub-stage P46, and the fourth light-emitting sub-stage P47.

[0083] In the first light-emitting stage P41, the second light-emitting stage P43, the third light-emitting stage P45, and the fourth light-emitting stage P47: the light-emitting control signal EM, the third scan signal Nscan1, and the fourth scan signal Nscan2 are all in a low-level state, and the first scan signal Pscan1 and the second scan signal Pscan2 are both in a high-level state. The first switching transistor Ts1 and the second switching transistor Ts2 are both turned on in response to the light-emitting control signal EM. The driving transistor Tdr is kept on under the action of the storage capacitor Cst. The driving current generated by the driving transistor Tdr according to the data signal Data flows in the path between the first power supply terminal VDD and the second power supply terminal VSS, so that the light-emitting device D emits light.

[0084] In the first non-emitting phase P42, the second non-emitting phase P44, and the third non-emitting phase P46: the emission control signal EM and the second scan signal Pscan2 are both at a high level, while the third scan signal Nscan1 and the fourth scan signal Nscan2 are both at a low level. The first scan signal Pscan1 has a low level for a certain duration within the time period during which the emission control signal EM is at a high level. The first reset transistor Ti1 and the second reset transistor Ti2 are both turned on in response to the first scan signal Pscan1, and the first reset signal VI1 resets the potential of the fourth node N4. The second reset signal VI2 has a higher voltage value, causing the driving transistor Tdr to turn on, and the second reset signal VI2 resets the potentials of the first node N1 and the second node N2.

[0085] Table 2 shows the potential changes of the first node N1, the second node N2, the third node N3, and the fourth node N4 in the sub-pixel SP during each working stage in the corresponding high-frequency driving mode.

[0086] As shown in Table 2, in the multiple non-emitting sub-stages, the potentials of the first node N1, the second node N2, the third node N3, and the fourth node N4 remain equal. In the multiple emitting sub-stages, the potentials of the first node N1, the second node N2, the third node N3, and the fourth node N4 remain equal, thus ensuring that the display brightness of the sub-pixel SP remains consistent in each emitting sub-stage.

[0087]

[0088] Figure 7 This is a schematic diagram of the measured results of the light emission waveform with a brightness of 50 nits provided in the embodiment of the present invention. By making the light emission stage include multiple light emission sub-stages and multiple non-light emission sub-stages, the display brightness of the sub-pixel SP can be kept consistent in each light emission sub-stage, and the flicker problem can also be improved.

[0089] exist Figure 6 In the illustrated embodiment, within the first duration tfr corresponding to the write frame WF, the second scan signal Pscan2 has a fundamental frequency f3 of 16Hz, while the number of cycles Ncft of the light emission control signal EM is 4. Therefore, the intermediate frequency f2 of the light emission control signal EM is 64Hz. The number of cycles Ncft of the light emission control signal EM can be determined based on the sum of the number of light-emitting sub-stages and the number of non-light-emitting sub-stages included in the write frame WF. That is, the stages corresponding to the initialization stage P1, data writing stage P2, and node reset stage P3 of the write frame WF also belong to a non-light-emitting sub-stage. The sum of the non-light-emitting sub-stages formed by the initialization stage P1, data writing stage P2, and node reset stage P3, the light-emitting sub-stages included in the light-emitting stage, and the non-light-emitting sub-stages is equal to twice the number of cycles Ncft of the light emission control signal EM; that is, each cycle T of the light emission control signal EM actually corresponds to one non-light-emitting sub-stage and one light-emitting sub-stage.

[0090] Optionally, the number of cycles Ncft of the light emission control signal EM is an integer so that when subsequent frame skipping is performed to achieve the ultra-low frequency display mode, the number of light-emitting sub-stages and non-light-emitting sub-stages included in each frame can be kept equal.

[0091] To achieve the display function of the ultra-low frequency driving mode, within the hold frame HF, the light-emitting stage also has multiple light-emitting sub-stages and multiple non-light-emitting sub-stages. Optionally, the number of light-emitting sub-stages included in each hold frame HF is equal to the number of light-emitting sub-stages included in the write frame WF, and the number of non-light-emitting sub-stages included in each hold frame HF is equal to the number of non-light-emitting sub-stages included in the write frame WF, so that both the write frame WF and each hold frame HF have a first duration tfr.

[0092] Based on the already achieved increase in frame duration, this paper explains the number of frame skips per display cycle when using the ultra-low frequency drive mode. Figure 8 This is a timing diagram of a display cycle in the ultra-low frequency driving mode provided in this embodiment of the invention; within the total duration tsu corresponding to one display cycle, the target frequency f1 of the second scan signal Pscan2 is 0.016Hz; within the first duration tfr corresponding to the write frame WF, the fundamental frequency f3 of the second scan signal Pscan2 is 16Hz, combined with... Figure 3 The sub-pixels shown illustrate the number of frame skips per display cycle when using the ultra-low frequency driving mode.

[0093] Within each hold frame HF, the sub-pixel SP switches between a non-display state and a display state under the control of the emission control signal EM. The total number of frames m = 16 / 0.016 = 1000 (i.e., the sum of the number of write frames WF and multiple hold frames HF included in one display cycle equals 16 / 0.016 = 1000), meaning one display cycle includes one write frame WF (i.e., corresponding to...). Figure 8 1 in st 16Hz) and 999 hold frames HF (i.e., corresponding to Figure 8 2 in nd ~999 th 16Hz and 1000 th (16Hz). The frame skipping number SKF is equal to the number of hold frames HF included in one display cycle, that is, the frame skipping number SKF is equal to 999.

[0094] Optionally, the frame skipping number SKF is an integer, so that the number of write frames (WF) and hold frames (HF) included in each display cycle is an integer. Optionally, the frame skipping number SKF is less than the frame skipping limit SKL, so that the display device can achieve the desired target frequency.

[0095] By including a write frame (WF) and multiple hold frames (HF) in a display cycle, the display panel displays the same content within the total duration (tsu) of the display cycle. Since the sub-pixel SP switches between display and non-display states multiple times within the first duration (tfr) of each write frame (WF) and each hold frame (HF), the human eye can not perceive any flickering problem in the display panel within the total duration (tsu) of the display cycle.

[0096] Understandably, in addition to achieving a display with a target frequency f1 of 0.016Hz, more corresponding ultra-low frequency displays can be obtained based on the relationship between the target frequency f1, intermediate frequency f2, fundamental frequency f3, the number of cycles Ncft of the light emission control signal EM, the total number of frames m, the first duration tfr, and the total duration tsu. Table 3 only shows some examples when the corresponding frame skipping limit SKL is equal to 2^10 = 1024, and is not intended to limit this application.

[0097] As shown in Table 3, there can be multiple fundamental frequencies f3 used to achieve the target frequency f1, and there can also be multiple intermediate frequencies f2 used to achieve the target frequency f1. Among the multiple fundamental frequencies f3, there is a maximum fundamental frequency fmax, and among the multiple intermediate frequencies f2, there is a minimum intermediate frequency fmin. Specifically, within the first duration tfr corresponding to the write frame WF and each hold frame HF included in a display cycle, the number of cycles Ncft of the light emission control signal EM is greater than or equal to the ratio of the minimum intermediate frequency to the maximum fundamental frequency; that is, Ncft ≥ fmin / fmax.

[0098]

[0099] The maximum base frequency fmax can be determined based on the frame skipping limit SKL and the target frequency f1. For example, by subtracting the frame skipping limit SKL from the ratios of multiple base frequencies f3 and target frequencies f1, multiple first differences are obtained. The base frequency f3 corresponding to the smallest of these first differences is the maximum base frequency fmax. Note that the ratios of multiple base frequencies f3 to target frequencies f1 are all less than the frame skipping limit SKL.

[0100] The minimum intermediate frequency fmin can be determined by multiplying the critical scintillation frequency CFF and the number of cycles Ncft. Alternatively, multiple intermediate frequencies f2 can be subtracted from the critical scintillation frequency CFF to obtain multiple second difference values. The intermediate frequency f2 corresponding to the smallest of these second difference values ​​is the minimum intermediate frequency fmin. Note that all intermediate frequencies f2 are greater than the critical scintillation frequency CFF.

[0101] If the frame skipping limit SKL is equal to 2^10 = 1024 and the target frequency f1 is 0.016Hz, then the minimum intermediate frequency fmin is 64Hz and the maximum fundamental frequency fmax is 16Hz. Therefore, within the first duration tfr corresponding to the write frame WF and each hold frame HF included in a display cycle, the number of cycles Ncft of the light emission control signal EM is greater than or equal to 4.

[0102] Understandably, in ultra-low frequency drive display mode, depending on the target frequency f1 to be achieved, the timing of writing frame WF and the timing of one display cycle will differ. Figure 6 and Figure 8The timing will also differ, and those skilled in the art can obtain the write frame WF timing and a display cycle timing corresponding to the target frequency f1 to be achieved based on this application. In this application, other embodiments will not be described in detail to save space.

[0103] Table 4 shows the flicker test results obtained with a base frequency f3 of 16Hz, an intermediate frequency f2 of 64Hz, and a target frequency f1 of 0.016Hz.

[0104]

[0105] As shown in Table 4, when the display panel uses an ultra-low frequency driving mode with a target frequency f1 of 0.016Hz to achieve the display, the flicker of the display panel is still less than the specified value. Therefore, when the display panel achieves ultra-low frequency display, the human eye can not perceive the flicker problem, thus giving the display panel better display performance.

[0106] like Figure 9 This is a schematic diagram of power consumption test results provided in an embodiment of the present invention. Wherein, 25% OPR means that 25% of the display area of ​​the screen emits light, and 10% OPR means that 25% of the display area of ​​the screen emits light. Figure 9 It is evident that, compared to existing displays using low-frequency driving modes, the display implemented in this application using ultra-low-frequency driving modes reduces power consumption by 14.1% at 25% OPR and by 18.4% at 10% OPR. Therefore, the goal of reducing power consumption can be achieved, enabling the display device to have better battery life.

[0107] Understandably, display devices include portable display devices (such as laptops, mobile phones, etc.), fixed terminals (such as desktop computers, televisions, etc.), measuring devices (such as fitness trackers, thermometers, etc.), etc.

[0108] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A display device, characterized in that, include: The display panel includes a plurality of sub-pixels, which form a plurality of pixel units arranged in an array. Each pixel unit includes a plurality of sub-pixels, and each sub-pixel includes a light-emitting device, a driving transistor, and a data transistor. The driving transistor is configured to generate a driving current according to a data signal to drive the light-emitting device to emit light, and the data transistor is configured to transmit the data signal to the driving transistor according to a second scan signal. as well as, A drive control module includes an emission driver and a drive controller, wherein the emission driver is configured to output an emission control signal to the sub-pixel; The drive controller is configured to generate a control signal to control the emitter driver to generate the light emission control signal; The process of displaying the image on the display panel includes multiple display cycles, at least one of the display cycles includes a write frame and multiple hold frames, the duration of each of the write frame and multiple hold frames is equal to a first duration; within each of the write frame and multiple hold frames, the light emission control signal has multiple cycles, and the ratio of the number of cycles of the light emission control signal to the first duration is greater than the critical flicker frequency. Wherein, the ratio of the first duration to the duration required for the drive controller to control one pixel unit to achieve display is greater than the number of pixel units in the display device, and the target frequency corresponding to at least one display cycle is less than 1Hz, f1=f2 / [Ncft×(SKF+1)]; f1 ​​represents the target frequency corresponding to the display cycle, f2 represents the intermediate frequency of the light emission control signal in the write frame; in the write frame, the product of the base frequency of the second scan signal and the number of cycles of the light emission control signal is equal to the intermediate frequency of the light emission control signal; Ncft represents the number of cycles of the light emission control signal, SKF represents the number of frame skips included in the display cycle, and the number of frame skips is less than the upper limit of frame skips that the drive control module can provide.

2. The display device according to claim 1, characterized in that, The ratio of the first duration to the duration required for the drive controller to control one pixel unit to achieve display is equal to N. H-line With N V-porch The product of N H-line The number of columns greater than the number of pixel units, and / or N V-porch The number of rows is greater than the number of pixels.

3. The display device according to claim 1 or 2, characterized in that, Also includes: A gate driver includes a first gate driving unit and a second gate driving unit, wherein the first gate driving unit is configured to output a first scan signal to the sub-pixel, and the second gate driving unit is configured to output a second scan signal to the sub-pixel; Each of the sub-pixels includes: The first reset transistor is configured to reset the anode potential of the light-emitting device according to the first scan signal; A light-emitting control transistor is configured to control the on / off state of the flow path of the drive current according to the light-emitting control signal; The data transistor is configured to be controlled by the second scan signal to transmit the data signal to the driving transistor through the first node; The light emission control signal has one valid pulse and one invalid pulse in each cycle. The first scan signal has one valid pulse during the duration of each invalid pulse of the light emission control signal in the write frame. The second scan signal has one valid pulse during the duration of the invalid pulse in the first cycle of the light emission control signal in the write frame.

4. The display device according to claim 3, characterized in that, The first scan signal has a valid pulse during the duration of each invalid pulse of the light emission control signal in the write frame and the plurality of hold frames, and the second scan signal has a valid pulse during the duration of the invalid pulse in the first period of the light emission control signal in the write frame.

5. The display device according to claim 4, characterized in that, Within the total duration corresponding to the write frame and the plurality of hold frames, the second scan signal has a frequency of the target frequency, and the target frequency of the second scan signal is less than 1 Hz.

6. The display device according to claim 1, characterized in that, The ratio of the base frequency to the target frequency is equal to the sum of the number of the write frames and the number of the plurality of hold frames.

7. The display device according to claim 1, characterized in that, The base frequency is 16Hz, the intermediate frequency is 64Hz, and the target frequency is 0.016Hz.

8. The display device according to claim 3, characterized in that, Each of the sub-pixels further includes: The second reset transistor is configured to reset the potential of the input electrode and the potential of the output electrode of the driving transistor according to the first scan signal.

9. The display device according to claim 8, characterized in that, The driving transistor includes an input electrode connected to the first node, an output electrode connected to the second node, and a control electrode connected to the third node. The data transistor includes a control electrode configured to receive the second scan signal, an input electrode configured to receive the data signal, and an output electrode connected to the first node. The light-emitting control transistor includes a first switching transistor and a second switching transistor; the first switching transistor includes a control electrode configured to receive the light-emitting control signal, an input electrode connected to a first power supply terminal, and an output electrode connected to the first node; the second switching transistor includes a control electrode configured to receive the light-emitting control signal, an input electrode connected to the second node, and an output electrode connected to the fourth node. The first reset transistor includes a control electrode configured to receive the first scan signal, an input electrode configured to receive the first reset signal, and an output electrode connected to the fourth node; The second reset transistor includes a control electrode configured to receive the first scan signal, an input electrode configured to receive a second reset signal, and an output electrode connected to the first node; as well as The light-emitting device includes an anode connected to the fourth node and a cathode connected to the second power supply terminal; During the duration of the multiple invalid pulses of the light emission control signal, the potentials of the first node, the second node, the third node, and the fourth node remain equal.

10. The display device according to claim 9, characterized in that, The driving transistor is a P-type transistor. During the duration of each effective pulse of the first scan signal, the difference between the potential of the third node and the second reset signal is less than the threshold voltage of the driving transistor.

11. The display device according to claim 9, characterized in that, The gate driver further includes a third gate driving unit, which is configured to output a third scan signal and a fourth scan signal to the sub-pixel; The sub-pixel also includes a compensation transistor, a third reset transistor, and a storage capacitor; The compensation transistor includes a control electrode configured to receive the third scan signal, an input electrode connected to the third node, and an output electrode connected to the second node; The third reset transistor includes a control electrode configured to receive the fourth scan signal, an input electrode configured to receive the third reset signal, and an output electrode connected to the third node. The storage capacitor includes a first electrode configured to be connected to the first power supply terminal and a second electrode configured to be connected to the third node; The third scan signal and the fourth scan signal each have an effective pulse during the duration of the invalid pulse in the first period of the light emission control signal in the write frame.

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