Display panel and display device

Abstract

This application provides a display panel and a display device. The display panel includes: R rows of pixel circuits; a first scan driving circuit scans one row of pixel circuits for a duration of t; a first light-emitting driving circuit provides the pixel circuit rows with first light-emitting control signals including S first sub-segments; wherein the duration of the first sub-segment is m*t, and m is a positive integer; the pixel circuit includes a first data writing transistor, the first terminal of the first data writing transistor is electrically connected to a data line, the control terminal of the first data writing transistor is electrically connected to the first scan driving line, and the first scan driving circuit is electrically connected to the first scan driving line; the one-frame scan time T of the display panel includes a display scan period and a front and back corridor period, the duration of the display scan period is M, and the duration of the front and back corridor periods is N; M = R*t, N = P*t, T = M + N; wherein S = (R + P) / m, S is a positive integer, and R / m is a positive integer. According to this application embodiment, the performance of the display panel can be optimized.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0002] With the development of the information society, the demand for display panels used to display images has increased. Examples of such display panels include micro light-emitting diodes (micro LEDs) and organic light-emitting diodes (OLEDs).

[0003] However, with the continuous development of display technology, users' performance requirements for display panels are gradually increasing. Therefore, how to optimize the performance of display panels is an important issue facing those skilled in the art. Summary of the Invention

[0004] This application provides a display panel and a display device that can optimize the performance of the display panel.

[0005] In a first aspect, embodiments of this application provide a display panel, comprising: a pixel circuit, wherein a plurality of pixel circuits are arranged in a pixel circuit row in a first direction, and R pixel circuit rows are arranged in a second direction, the first direction and the second direction intersecting; a first scanning driving circuit, wherein the first scanning driving circuit provides a first scanning driving signal to the pixel circuit row; wherein the duration of scanning a row of pixel circuits by the first scanning driving circuit is t; a first light-emitting driving circuit, wherein the first light-emitting driving circuit provides a first light-emitting control signal including S first sub-segments to the pixel circuit row; wherein the duration of the first sub-segment is m*t, and m is a positive integer; the pixel circuit includes a first data writing transistor, the first terminal of the first data writing transistor is electrically connected to a data line, the control terminal of the first data writing transistor is electrically connected to the first scanning driving line, and the first scanning driving circuit is electrically connected to the first scanning driving line; the one-frame scanning time T of the display panel includes a display scanning period and a front and back corridor period, the duration of the display scanning period is M, and the duration of the front and back corridor period is N; M = R*t, N = P*t, T = M + N; wherein S = (R + P) / m, S is a positive integer, and R / m is a positive integer.

[0006] Secondly, embodiments of this application provide a display device, including a display panel as described in the first aspect embodiment.

[0007] According to the display panel and display device provided in the embodiments of this application, a frame scan time includes not only the display scan period but also the front and back corridor periods, so that the multiple emission of the light-emitting element can be distributed throughout the entire frame scan time. This allows the light-emitting element to emit light not only during the display scan period but also during the front and back corridor periods, thereby avoiding the multiple emission of the light-emitting element being concentrated in the display scan period. This ensures that the number of pixel circuit rows driven by the first light-emitting driving circuit is the same at each moment, reducing the load difference of the first light-emitting driving circuit and improving the display effect. Attached Figure Description

[0008] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals denote the same or similar features, and the drawings are not drawn to scale.

[0009] Figure 1 This illustration shows a structural schematic diagram of a display panel provided in an embodiment of this application;

[0010] Figure 2 This illustration shows a schematic diagram of a pixel circuit provided in an embodiment of this application;

[0011] Figure 3 This illustration shows another structural diagram of the pixel circuit provided in an embodiment of this application;

[0012] Figure 4 This illustration shows yet another structural schematic of the pixel circuit provided in an embodiment of this application;

[0013] Figure 5 This illustration shows a timing diagram of a first light-emitting driving signal for a display panel provided in an embodiment of this application.

[0014] Figure 6a This invention provides a timing diagram of the first scan drive signal for a display panel according to an embodiment of the present application.

[0015] Figure 6b This illustration shows a timing diagram of a display panel provided in an embodiment of this application.

[0016] Figure 7 This illustration shows another timing diagram of the first light-emitting driving signal of the display panel provided in an embodiment of this application;

[0017] Figure 8 This diagram illustrates yet another timing sequence of the first light-emitting driving signal for the display panel provided in an embodiment of this application.

[0018] Figure 9 This diagram illustrates yet another timing sequence of the first light-emitting driving signal for the display panel provided in an embodiment of this application.

[0019] Figure 10 This diagram illustrates a timing schematic of a display panel provided in an embodiment of this application.

[0020] Figure 11 This diagram illustrates yet another timing schematic of a display panel provided in an embodiment of this application;

[0021] Figure 12 This diagram illustrates yet another timing schematic of a display panel provided in an embodiment of this application;

[0022] Figure 13 This is a schematic diagram of a first light-emitting driving circuit in a display panel provided in an embodiment of this application;

[0023] Figure 14 This illustration shows a schematic diagram of a first shift register in a display panel provided in an embodiment of this application;

[0024] Figure 15 Show Figure 14 A corresponding timing diagram;

[0025] Figure 16 Show Figure 14 Another corresponding timing diagram;

[0026] Figure 17 A timing diagram illustrating a comparative example is shown;

[0027] Figure 18 This diagram illustrates yet another timing schematic of a display panel provided in an embodiment of this application;

[0028] Figure 19 Show Figure 4 A corresponding timing diagram;

[0029] Figure 20 This is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation

[0030] The features and exemplary embodiments of various aspects of this application will now be described in detail. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain this application and are not configured to limit this application. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples of this application.

[0031] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0032] It should be understood that when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it can mean that it is directly above the other layer or region, or that it contains other layers or regions between it and the other layer or region. Furthermore, if the component is flipped over, that layer or region will be located "below" or "under" the other layer or region.

[0033] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0034] In the embodiments of this application, the term "electrical connection" can refer to a direct electrical connection between two components, or it can refer to an electrical connection between two components via one or more other components. The term "drive" can refer to "control" or "operation." The display panel can be a display device or a module / part of a display device.

[0035] Various modifications and variations can be made to this application without departing from its spirit or scope, which will be apparent to those skilled in the art. Therefore, this application is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided in this application can be combined with each other without contradiction.

[0036] This application provides a display panel and a display device. The following description, in conjunction with the accompanying drawings, will illustrate various embodiments of the display panel and the display device.

[0037] like Figure 1As shown, the display panel 100 provided in this embodiment includes a pixel circuit 1, a first scanning driving circuit 21, and a first light-emitting driving circuit 31.

[0038] Pixel circuit 1 is electrically connected to light-emitting element D, and the pixel circuit is used to drive the light-emitting element to emit light. The light-emitting element may include micro LED, minLED, or OLED, etc.

[0039] Multiple pixel circuits 1 are arranged in a pixel circuit row 10 in the first direction X, and R pixel circuit rows 10 are arranged in the second direction Y, where the first direction X and the second direction Y intersect. Figure 1 Rows 1, 2, 3, ..., R represent the 1st pixel circuit row, 2nd pixel circuit row, 3rd pixel circuit row, ..., Rth pixel circuit row, respectively. It is understandable that R is a positive number.

[0040] The first scan drive circuit 21 provides a first scan drive signal Scan1 to the pixel circuit row 10, wherein the first scan drive circuit 21 scans a row of pixel circuits 1 for a duration of t. The first scan drive signal is used to control whether data voltage can be written to the pixel circuit 1. For example, when the first scan drive signal is at an active level, data voltage is written to the pixel circuit 1.

[0041] For example, the first scan driving circuit 21 is electrically connected to multiple pixel circuits 1 in the same row through the first scan driving line 41. In other words, the first scan driving signals connected to multiple pixel circuits in the same pixel circuit row are the same.

[0042] The first light-emitting driving circuit 31 provides a first light-emitting control signal to the pixel circuit row 10. It is understood that the first light-emitting control signal is used to control whether the light-emitting elements of the display panel emit light. Specifically, when the first light-emitting control signal is at an active level (e.g., active level is low), the light-emitting element emits light; when the first light-emitting control signal is at a cutoff level (e.g., cutoff level is high), the light-emitting element does not emit light.

[0043] For example, the first light-emitting driving circuit 31 is electrically connected to multiple pixel circuits 1 in the same row through the first light-emitting control signal line 42. In other words, the first light-emitting control signal connected to multiple pixel circuits in the same pixel circuit row is the same.

[0044] It should be noted that, Figure 1 The example shown only illustrates that the first scanning driving circuit 21 and the first light-emitting driving circuit 31 are provided on one side in the first direction X, and this is not intended to limit the scope of this application. For example, in other examples, the first scanning driving circuit can be provided on both sides in the first direction, and / or the first light-emitting driving circuit can be provided on both sides in the first direction.

[0045] For example, such as Figures 2-4 As shown in any of the attached figures, the pixel circuit 1 includes a first data writing transistor 101. The first terminal of the first data writing transistor 101 is electrically connected to the data line data. The control terminal of the first data writing transistor 101 is electrically connected to the first scan driving line 41. The first scan driving line 41 is electrically connected to the first scan driving circuit 21.

[0046] As an example, the pixel circuit is Figure 2 In the 7T1C architecture shown, transistor T2 writes the data voltage on the data line to the driving transistor T3, which generates the driving current. Transistor T4 compensates for the threshold voltage of the driving transistor T3. Transistor T5 transmits the reset signal on the first reset signal line Vref1 to the gate of the driving transistor T3. Capacitor Cst maintains the gate potential of the driving transistor T3. Transistor T7 transmits the reset signal on the second reset signal line Vref2 to the first terminal of the light-emitting element D. Transistors T1 and T6 control whether the light-emitting element D emits light. Additionally, Scan1 to Scan3 are scan driving signals, transistor T2 is the first data writing transistor 101, and EM1 is the first light-emitting control signal.

[0047] As another example, the pixel circuit is Figure 3 The 13T2C architecture shown, or the pixel circuit, is... Figure 4 The 17T3C architecture shown is in Figure 3 and Figure 4 In the structure shown, the pixel circuit includes a PWM (Pulse Width Modulation) module and a PAM (Pulse Amplitude Modulation) module. The PWM module is electrically connected to the PAM module, and the PAM module is electrically connected to the light-emitting element D.

[0048] The combination of PWM and PAM modules enables control over the intensity and duration of the drive current, thereby controlling the emission state of the light-emitting element (LED). Specifically, the PAM module controls the amplitude of the drive current, while the PWM module adjusts the pulse width of the voltage applied to the first electrode of the LED. By adjusting the pulse width of the voltage applied to the LED, the PWM module adjusts the actual emission period of the drive current applied to the LED. Simultaneously, it maintains a constant drive current level to adjust the grayscale or brightness of the LED display, rather than simply adjusting the magnitude of the drive current. Therefore, the PAM module provides drive current to the LED, ensuring optimal luminous efficiency, and the PWM module adjusts the LED's emission duty cycle (i.e., the emission period) to regulate the grayscale or brightness.

[0049] In this embodiment, the first scanning drive circuit 21 is electrically connected to the PWM module, and the first light-emitting drive circuit 31 is connected to the PAM module.

[0050] For details, please refer to Figure 3 In the PAM module, transistor T15 is used to write the data voltage on the data line PAM_data to the driving transistor T11. The driving transistor T11 is used to generate the driving current. Transistor T13 is used to compensate the threshold voltage of the driving transistor T11. Transistor T14 is used to transmit the reset signal on the reset signal line PAM_REF1 to the gate of the driving transistor T11. Capacitor Cst1 is used to maintain the gate potential of the driving transistor T11. Transistor T16 is used to transmit the reset signal on the reset signal line PAM_REF2 to the first terminal of the light-emitting element D. Transistors T12a and T12b are used to control whether the light-emitting element D emits light. In the PWM module, transistor T25 is used to write the data voltage on the data line PWM_data to the driving transistor T21. The driving transistor T21 is used to generate the driving current. Transistor T23 is used to compensate the threshold voltage of the driving transistor T21. Transistor T24 is used to transmit the reset signal on the reset signal line PWM_REF1 to the gate of the driving transistor T21. Capacitor Cst2 is used to couple the signal from the sweep signal terminal SWEEP to the gate of the driving transistor T21. Transistors T22a and T22b are used to control whether the driving current of the driving transistor T21 is written to the N1 node of the PAM module.

[0051] Figure 4 and Figure 3The similarities will not be repeated here. The differences include: In the PAM module, transistor T27 is used to reset the scan signal terminal SWEEP, and transistors T18, T19, T20 and capacitor C3 are used to eliminate the voltage drop of the power supply signal PVDD.

[0052] Specifically, in the PWM module, transistor T25 serves as the first data write transistor 101, and the scan signal PWM_S2 provided by the first scan drive circuit 21 to the gate of transistor T25 serves as the first scan drive signal. The PAM module includes a light-emitting control transistor T12, and the first light-emitting drive circuit 31 is electrically connected to the gate of the light-emitting control transistor T12 in the PAM module. The light-emitting control signal line PAM_EM provided by the first light-emitting drive circuit 31 to the gate of the light-emitting control transistor T12 serves as the first light-emitting control signal.

[0053] It should be noted that, Figures 2 to 4 These are merely examples and are not intended to limit the specific structure of pixel circuits. For example, pixel circuits can be pixel circuits with other architectures.

[0054] like Figure 5 As shown, during one frame scan time of the display panel, the first light emission control signal EM1 includes S first sub-segments d1, where the duration of the first sub-segment is m*t, and S and m are positive integers.

[0055] One frame scan time of the display panel includes a display scan period f1 and a front and back corridor period f2. The duration of the display scan period is M, and the duration of the front and back corridor periods is N; M = R*t, N = P*t, and the duration of one frame scan time of the display panel is T, T = M + N, where P is a positive integer; where S = (R + P) / m, S is a positive integer, and R / m is a positive integer. In this article, the symbol "*" indicates multiplication.

[0056] Understandably, the total duration of the S first segments d1 is S*m*t, and T = S*m*t. Furthermore, the display scanning period f1 includes R / m first segments, and the front and rear corridor period f2 includes P / m first segments. P is a positive integer, and P / m is a positive integer. The fact that R / m and P / m are both positive integers ensures that the first segments of the first light-emitting control signal can be evenly distributed during the scanning display phase and also evenly distributed within the front and rear corridor phases.

[0057] The front and rear corridor time period f2 is located between the display scanning time periods f1 of adjacent display frames. The front and rear corridor time period f2 can be used to prepare and transmit screen data, so as to provide the display driver chip (IC) with enough time to prepare to receive and process the next frame screen data. This allows the display driver chip to complete the processing and output of the current frame data before receiving the next frame screen data, avoiding problems such as data loss and display abnormalities.

[0058] For example, such as Figure 6a As shown, Scan1_1 to Scan1_R represent the first scan drive signals connected to the first pixel circuit row to the Rth pixel circuit row respectively. During the display scan period f1, the first scan drive signals Scan1_1 to Scan1_R are sequentially active (e.g., active level is low). In other words, during the display scan period f1 of one frame scan time of the display panel, the first scan drive circuit 21 scans the first row of pixel circuits to the Rth row of pixel circuits line by line, and the required scan time for the R pixel circuit rows is R*t.

[0059] Specifically, Figure 6b The diagram shows the first scan drive signal Scan1_1 and the first light emission control signal EM1_1 corresponding to the first pixel circuit row, the first scan drive signal Scan1_j and the first light emission control signal EM1_j corresponding to the j-th pixel circuit row, the first scan drive signal Scan1_j+1 and the first light emission control signal EM1_j+1 corresponding to the j+1-th pixel circuit row, the first scan drive signal Scan1_j+2 and the first light emission control signal EM1_j+2 corresponding to the j+2-th pixel circuit row, and the first scan drive signal Scan1_R and the first light emission control signal EM1_R corresponding to the R-th pixel circuit row.

[0060] During the front and rear corridor period f2, the first scan drive signal S1 remains at a cutoff level (e.g., high level). That is, during the front and rear corridor period f2, the first data write transistor in the pixel circuit remains in a cutoff state.

[0061] The first emission control signal is usually a periodic signal, and a first segment can be understood as one cycle of the first emission control signal. In one frame scan time, the first emission control signal is equivalent to dividing it into S equal cycles, each cycle having a duration of m*t.

[0062] It is understood that in the embodiments of this application, during one frame scan time of the display panel, the first sub-segment d1 is distributed not only during the display scan period f1, but also during the front and back corridor periods f2.

[0063] The first light-emitting control signal is used to control whether the light-emitting element of the display panel emits light. The duty cycle of the effective level of the first light-emitting control signal is greater than 0 in at least one first sub-segment, enabling the light-emitting element to emit light in at least one first sub-segment. For example, in at least one first sub-segment d1 within the display scan period f1, the duty cycle of the effective level of the first light-emitting control signal is greater than 0, and in at least one first sub-segment d1 within the front and rear corridor periods f2, the duty cycle of the effective level of the first light-emitting control signal is greater than 0, enabling the light-emitting element to emit light multiple times within one frame scan time.

[0064] For example, in the S1 first sub-segments, the duty cycle of the effective level of the first light-emitting control signal is greater than 0. It can be understood that the number of times the light-emitting element emits light within one frame scanning time is S1, where S1≤S.

[0065] In related technologies, the scanning time of a frame only includes the display scanning period and does not consider the front and back corridor periods. As a result, the multiple emission of the light-emitting element can only be concentrated in the display scanning period, which can easily lead to uneven load on the first light-emitting driving circuit and affect the display effect.

[0066] In this embodiment, a frame scan time includes not only the display scan period but also the front and back corridor periods, so that the multiple emission of the light-emitting element can be distributed throughout the entire frame scan time. This allows the light-emitting element to emit light not only during the display scan period but also during the front and back corridor periods, thereby avoiding the multiple emission of the light-emitting element being concentrated in the display scan period. This ensures that the number of pixel circuit rows driven by the first light-emitting driving circuit is the same at each moment, reducing the load difference of the first light-emitting driving circuit and improving the display effect.

[0067] In some embodiments, such as Figure 5 As shown, the first sub-segment d1 includes a first type of sub-segment d11. In the first type of sub-segment d11, the duty cycle of the effective level of the first light emission control signal EM1 is greater than 0 and less than 1. During one frame scan time, the number of first type of sub-segments d11 is greater than 1, and the duty cycle of the effective level of the first light emission control signal EM1 is the same in different first type of sub-segments d11.

[0068] As an example, within one frame scan time, the number of first-class sub-segments d11 is S1, S1≤S, and the duty cycle of the effective level of the first light emission control signal EM1 is the same in all S1 first-class sub-segments d11.

[0069] As described in the above embodiments, the duration of different first sub-segments d1 is m*t, that is, the duration of different first sub-segments d11 is m*t. When the duty cycle of the effective level of the first light-emitting control signal EM1 in different first sub-segments d11 is the same, the duration of the effective level of the first light-emitting control signal EM1 in different first sub-segments d11 is the same, and the duration of the cutoff level of the first light-emitting control signal EM1 in different first sub-segments d11 is the same.

[0070] The larger the duty cycle of the effective level of the first light-emitting control signal EM1, the longer the light-emitting duration of the light-emitting element; conversely, the smaller the duty cycle of the effective level of the first light-emitting control signal EM1, the shorter the light-emitting duration of the light-emitting element.

[0071] In this embodiment, the duty ratios of the active levels of the first emission control signals in different first-type subfields are the same, which enables the light-emitting elements to have uniform luminous brightness in different first-type subfields, thereby further reducing the load difference of the first emission driving circuits and improving the display effect.

[0072] Certainly, in other examples, it may also be configured that the duty ratios of the active levels of the first emission control signals in at least two first-type subfields are different.

[0073] In some embodiments, as shown in Figure 5 , the first subfield d1 includes a first-type subfield d11, the duty ratio of the active level of the first emission control signal EM1 in the first-type subfield d11 is a, 0<a<0.5, within one frame scanning time of the display panel, the number of the first-type subfields d11 is S1, and S1=S.

[0074] In each first-type subfield d11, the first emission control signal EM1 includes an active level, so that the light-emitting element emits light once in each first-type subfield d11, the total number of light emission of the light-emitting element within one frame scanning time is S, the total number of light emission of the light-emitting element during the display scanning period is R / m, and the total number of light emission of the light-emitting element during the front and back porch periods is P / m.

[0075] In this embodiment, the S times of light emission of the light-emitting element are averaged over all time of one frame scanning time, which not only enables R / m times of light emission to be evenly distributed in the display scanning period, but also enables P / m times of light emission to be evenly distributed in the front and back porch periods, thereby avoiding multiple times of light emission of the light-emitting element from being concentrated in the display scanning period. Thus, the number of pixel circuit rows driven by the first emission driving circuit at each moment is the same, which reduces the load difference of the first emission driving circuits and improves the display effect.

[0076] In some embodiments, as shown in Figure 7 , the first subfield d1 includes a first-type subfield d11 and a second-type subfield d12, the duty ratio of the active level of the first emission control signal EM1 in the first-type subfield d11 is a, the duty ratio of the active level of the first emission control signal EM1 in the second-type subfield d12 is b, 0≤b<a<0.5. Within one frame scanning time of the display panel, the number of the first-type subfields d11 is S1, the number of the second-type subfields d12 is S2, S1+S2=S. Wherein, both S1 and S2 are positive integers.

[0077] It is understood that the duty cycle of the effective level of the first light-emitting control signal EM1 in the first type of sub-segment d11 is the ratio of the effective level duration to the duration of the first type of sub-segment. In various embodiments of this application, b = 0 means that the duty cycle of the cutoff level of the first light-emitting control signal EM1 in the second type of sub-segment d12 is 1. The duty cycle of the cutoff level of the first light-emitting control signal EM1 in the first type of sub-segment d11 is 1-a, and the duty cycle of the effective level of the first light-emitting control signal EM1 in the second type of sub-segment d12 is 1-b, where 0.5 < 1-a < 1-b ≤ 1.

[0078] As an example, 0 < b < a < 0.5. In this case, the first light emission control signal EM1 includes an effective level in both the first sub-segment d11 and the second sub-segment d12, enabling the light-emitting element to emit light in both sub-segments d11 and d12. Furthermore, since a ≠ b, the light emission duration of the light-emitting element in the first sub-segment d11 and the second sub-segment d12 is different, which in turn results in different brightness levels of the light-emitting element in the first sub-segment d11 and the second sub-segment d12. This is beneficial for improving the grayscale resolution in low grayscale images, thereby enabling a more delicate representation of the brightness and darkness changes in the displayed image.

[0079] As another example, such as Figure 8 As shown, 0 == b < a < 0.5. In this case, the first light-emitting control signal EM1 has an active level in the first sub-segment d11, and remains at a cutoff level in the second sub-segment d12, allowing the light-emitting element to emit light in the first sub-segment d11 and not in the second sub-segment d12. For example, the display panel includes multiplexed electrodes. Since the light-emitting element does not emit light in the second sub-segment, the multiplexed electrodes are used to transmit touch signals in the second sub-segment for touch signal recognition. The multiplexed electrodes in the first sub-segment are used to transmit display drive signals to drive the light-emitting element to emit light.

[0080] In some embodiments, S1 > S2.

[0081] As an example, 0 = b < a < 0.5, and S1 > S2. When b = 0, it is understandable that the larger the value of S1, the more times the light-emitting element emits light within one frame of scanning time. In this embodiment, S1 is designed to be greater than S2, which can ensure that the light-emitting element emits light more times within one frame, thereby better ensuring the light-emitting effect of the light-emitting element within one frame of scanning time.

[0082] As another example, 0 < b < a < 0.5, and S1 > S2.

[0083] In some embodiments, such as Figure 8 As shown, at least one second-class sub-segment d12 is located within the front and rear corridor time period f2.

[0084] As an example, 0 = b < a < 0.5, and at least one second-type segment d12 is located within the front and back corridor time period f2. The display driver chip outputs screen data during the display scanning phase and prepares the screen data during the front and back corridor time periods. When b = 0, for example, touch signal recognition can be performed in the second-type segment, and by setting at least one second-type segment within the front and back corridor time periods, touch recognition and screen data output can be separated to avoid interference between the two, thereby ensuring the accuracy of both the image data output and the touch recognition.

[0085] As another example, 0 < b < a < 0.5, and at least one second-class segment d12 is located within the front and rear corridor time period f2.

[0086] In some embodiments, such as Figure 9 As shown, EM1_1 to EM1_R represent the first light-emitting control signals connected to the first pixel circuit row to the Rth pixel circuit row, respectively. It is understandable that... Figure 9 In the diagram, the first light emission control signal corresponding to the first pixel circuit row is EM_1, the first light emission control signal corresponding to the second pixel circuit row is EM_2, the first light emission control signal corresponding to the m-th pixel circuit row is EM_m, and so on, with the first light emission control signal corresponding to the R-th pixel circuit row being EM_R.

[0087] in addition, Figures 9 to 12 In the diagram, the effective voltage of the first scan drive signal Scan1 corresponding to the first pixel circuit row to the Rth pixel circuit row is indicated by a gray box.

[0088] like Figure 6b As shown, within the same frame scanning time of the display panel, the time interval between the p-th first sub-segment d1_p following the effective level of the first scan drive signal Scan1_j corresponding to the j-th pixel circuit row and the p-th first sub-segment d1_p following the effective level of the first scan drive signal Scan1_j+1 corresponding to the (j+1)-th pixel circuit row is t.

[0089] For example, such as Figure 9As shown, p=1, the interval between the start time of the first first sub-segment d1 of the first emission control signal EM1_1 after the first pixel circuit row is scanned and the start time of the first first sub-segment d1 of the first emission control signal EM1_2 after the second pixel circuit row is scanned is represented as t; the interval between the start time of the first first sub-segment d1 of the first emission control signal EM1_2 after the second pixel circuit row is scanned and the start time of the first first sub-segment d1 of the first emission control signal EM1_3 after the third pixel circuit row is scanned is represented as t; the interval between the start time of the first first sub-segment d1 of the first emission control signal EM1_3 after the third pixel circuit row is scanned and the start time of the first first sub-segment d1 of the first emission control signal EM1_4 after the fourth pixel circuit row is scanned is represented as t; and so on.

[0090] In this embodiment, the interval duration t is set between the emission periods of two adjacent pixel circuit rows to ensure the overall display effect.

[0091] In some embodiments, as Figure 9 shown, within the same frame scanning time of the display panel, the first emission control signal corresponding to each pixel circuit row each includes a second-type sub-segment d12, and the second-type sub-segments d12 in the first emission control signals EM1_1 to EM1_R are all within a target period f3, and the duration of the target period f3 is less than the duration M of the display scanning phase f1.

[0092] For example, the number of second-type sub-segments d12 in the first emission control signal EM1 corresponding to different pixel circuit rows may be the same. The relative positions of the second-type sub-segments d12 corresponding to at least two pixel circuit rows are different, and the relative position refers to the target number of first-type sub-segments d11 spaced between the second-type sub-segment d12 corresponding to the pixel circuit row and the effective level of the first scanning driving signal corresponding to the pixel circuit row.

[0093] As an example, 0 = b < a < 0.5, and the second-type sub-segments of the first emission control signals corresponding to the R pixel circuit rows are respectively within one target period. When b = 0, the light-emitting element does not emit light during the second-type sub-segment. For example, touch signal recognition can be performed during the second-type sub-segment. This embodiment can execute touch recognition and driving of a display image separately, so as to avoid interference between the two, thereby ensuring the accuracy of display driving and the accuracy of touch recognition; in addition, in this embodiment, the non-emitting second-type sub-segments corresponding to the R pixel circuit rows are equivalently controlled within one target period. In this way, display uniformity can be improved.

[0094] As another example, 0 < b < a < 0.5, and the second-type sub-segments of the first emission control signals corresponding to R pixel circuit rows are respectively within one target period.

[0095] In some embodiments, as Figure 9 illustrated, the duration M of the display scanning period f1 is greater than the duration N of the front-porch / back-porch period f2, and the duration of the target period f3 is less than N.

[0096] During the display scanning period f1, the first scanning driving circuit scans R rows of pixel circuits row by row. Setting the duration of the display scanning stage to be greater than the duration of the front-porch / back-porch period can ensure that the scanning duration for each row of pixel circuits is sufficient, thereby ensuring the adequacy of data voltage writing.

[0097] As an example, 0=b<a<0.5, M>N, and the duration of the target period f3 is less than N. In this example, the non-light-emitting second-type sub-segments corresponding to R rows of pixel circuits are controlled within the target period with a shorter duration, which further improves display uniformity.

[0098] As another example, 0<b<a<0.5, M>N, and the duration of the target period f3 is less than N.

[0099] In some embodiments, as Figure 9 illustrated, the second-type sub-segment d12 in the first emission control signal corresponding to the j-th row of pixel circuit is located in the front-porch / back-porch period f2, where 1≤j≤R and j is a positive integer.

[0100] The i-th row of pixel circuit is any one of the first row to the R-th row of pixel circuits, that is, the second-type sub-segment d12 in the first emission control signal corresponding to any row of pixel circuit is located in the front-porch / back-porch period f2.

[0101] For example, the second-type sub-segment d12 in the first emission control signal EM1_1 corresponding to the first row of pixel circuit is located in the front-porch / back-porch period f2; the second-type sub-segment d12 in the first emission control signal EM1_2 corresponding to the second row of pixel circuit is located in the front-porch / back-porch period f2; the second-type sub-segment d12 in the first emission control signal EM1_m corresponding to the m-th row of pixel circuit is located in the front-porch / back-porch period f2, and so on, the second-type sub-segment d12 in the first emission control signal EM1_R corresponding to the R-th row of pixel circuit is located in the front-porch / back-porch period f2.

[0102] It should be noted that, Figure 9 an example is taken in which the number of second-type sub-segments d12 in the first emission control signal corresponding to the i-th row of pixel circuit is 1, the number of second-type sub-segments d12 in the first emission control signal corresponding to the j-th row of pixel circuit may also be multiple, and the plurality of second-type sub-segments d12 in the first emission control signal corresponding to the j-th row of pixel circuit are all located in the front-porch / back-porch period f2.

[0103] As an example, 0==b<a<0.5, and the second-type sub-segment d12 in the first light emission control signal corresponding to the j-th pixel circuit row is located in the front-back porch period f2. The display driving chip outputs frame data during the display scanning period, and prepares the frame data during the front-back porch period. When b=0, the light emitting element does not emit light in the second-type sub-segment. For example, touch signal recognition can be performed in the second-type sub-segment. Arranging the second-type sub-segment d12 in the first light emission control signal corresponding to the i-th pixel circuit row within the front-back porch period f2 can better separate touch recognition and frame data output, so as to avoid interference between the two, thereby ensuring the accuracy of frame data output and the accuracy of touch recognition.

[0104] As another example, 0<b<a<0.5, and the second-type sub-segment d12 in the first light emission control signal corresponding to the j-th pixel circuit row is located in the front-back porch period f2.

[0105] For example, within the same frame scanning time of the display panel, the first light emission control signal corresponding to each pixel circuit row includes the second-type sub-segment d12, the second-type sub-segments d12 in the first light emission control signals EM1_1~EM1_R are all within a target period f3, the duration of the target period f3 is less than the duration N of the front-back porch stage f2, M<N, which can be implemented through the following embodiments. In some embodiments, h pixel circuit rows are arranged into a pixel circuit group in the second direction, and the R pixel circuit rows include a plurality of pixel circuit groups.

[0106] For example, the first pixel circuit row to the h-th pixel circuit row form one pixel circuit group, the (h+1)-th pixel circuit row to the 2h-th pixel circuit row form another pixel circuit group, and so on. Each pixel circuit group includes h pixel circuit rows.

[0107] For example, h==m, the R pixel circuit rows include R / m pixel circuit groups, and R / m is a positive integer.

[0108] as Figure 10 shown, the first light emission control signals corresponding to the first pixel circuit row to the h-th pixel circuit row are respectively marked as EM1_1~EM1_h, the first light emission control signals corresponding to the (h+1)-th pixel circuit row to the 2h-th pixel circuit row are respectively marked as EM1_h+1~EM1_2h, and so on, the first light emission control signal corresponding to the R-th pixel circuit row is marked as EM1_R. The first light emission control signals EM1_1~EM1_h are first light emission control signals respectively corresponding to different pixel circuit rows in the first pixel circuit group, and the first light emission control signals EM1_h+1~EM1_2h are first light emission control signals respectively corresponding to different pixel circuit rows in the second pixel circuit group.

[0109] Within the same frame scan time of the display panel, the relative positions of the second type of sub-segment d12 in the first light emission control signal corresponding to different pixel circuit rows within the same pixel circuit group are the same, and the relative position of the second type of sub-segment d12 in the first light emission control signal corresponding to the j-th pixel circuit row is different from the relative position of the second type of sub-segment d12 in the first light emission control signal corresponding to the (j+h)-th pixel circuit row; the relative position is the target number of the first type of sub-segment b11 between the second type of sub-segment d12 in the first light emission control signal corresponding to the pixel circuit row and the effective level of the first scan drive signal.

[0110] It should be noted that, Figures 10 to 12 To clearly illustrate the arrangement pattern of the second type of sub-segments corresponding to multiple pixel circuit rows, Figures 10 to 12 The rectangle filled with diagonal lines represents the period when the first light-emitting control signal EM1 in the first sub-segment d11 is at an effective level. It can be understood that the rectangle filled with diagonal lines also represents the light-emitting period of the light-emitting element, and all other periods outside the rectangle filled with diagonal lines are the non-light-emitting periods of the light-emitting element. For example, please refer to the reference. Figure 5 and Figure 10 The first type of sub-segment d11 includes an active level segment d111 and a cutoff level segment d112. The first light emission control signal EM1 is active in the active level segment d111 and cutoff in the cutoff level segment d112. Figures 10 to 12 In the diagram, the rectangle filled with diagonal lines represents the active level segment d111, and the interval between adjacent rectangles filled with diagonal lines represents the cutoff level segment d112.

[0111] The first light emission control signal corresponding to the first pixel circuit row is EM1_1, the first scan drive signal corresponding to the first pixel circuit row is Scan1_1, and the target quantity corresponding to the first pixel circuit row is the number of first type sub-segments b11 between the first second type sub-segment d12 of the first light emission control signal EM1_1 and the effective level (low level) of the first scan drive signal Scan1_1.

[0112] The first light emission control signal corresponding to the second pixel circuit row is EM1_2, the first scan drive signal corresponding to the second pixel circuit row is Scan1_2, and the target quantity corresponding to the second pixel circuit row is the number of first type sub-segments b11 between the first second type sub-segment d12 of the first light emission control signal EM1_2 and the effective level (low level) of the first scan drive signal Scan1_2.

[0113] Similarly, the first light emission control signal corresponding to the Rth pixel circuit row is EM1_R, the first scan drive signal corresponding to the second pixel circuit row is Scan1_R, and the target quantity corresponding to the Rth pixel circuit row is the number of the first type of sub-segment b11 between the first second type sub-segment d12 of the first light emission control signal EM1_R and the effective level (low level) of the first scan drive signal Scan1_R.

[0114] Specifically, from the first pixel circuit row to the h-th pixel circuit row, the number of targets corresponding to different pixel circuit rows is the same; from the (h+1)-th pixel circuit row to the 2h-th pixel circuit row, the number of targets corresponding to different pixel circuit rows is the same; from the (2h+1)-th pixel circuit row to the 3h-th pixel circuit row, the number of targets corresponding to different pixel circuit rows is the same; and so on.

[0115] It is understandable that the j-th pixel circuit row and the (j+h)-th pixel circuit row belong to different pixel circuit groups, 1≤j≤R.

[0116] The following explanation uses h==12 as an example:

[0117] From the 1st to the 12th pixel circuit row, the number of targets corresponding to different pixel circuit rows is the same; from the 13th to the 24th pixel circuit row, the number of targets corresponding to different pixel circuit rows is the same; from the 25th to the 36th pixel circuit row, the number of targets corresponding to different pixel circuit rows is the same; and so on.

[0118] In addition, when j=1, the number of targets corresponding to the first pixel circuit row is different from the number of targets corresponding to the 13th pixel circuit row;

[0119] When j=2, the number of targets corresponding to the second pixel circuit row is different from the number of targets corresponding to the fourteenth pixel circuit row;

[0120] And so on;

[0121] When j=12, the number of targets corresponding to the 12th pixel circuit row is different from the number of targets corresponding to the 24th pixel circuit row; and so on.

[0122] In this embodiment, each h pixel circuit rows are considered as a pixel circuit group. Within the same frame scanning time, the relative positions of the second type of sub-segments in the first light emission control signal corresponding to the pixel circuit rows in different pixel circuit groups are different. By adjusting the relative positions of the second type of sub-segments corresponding to different pixel circuit groups, the second type of sub-segments corresponding to multiple pixel circuit groups can be controlled within a target time period to improve display uniformity.

[0123] In some embodiments, within the same frame scan time of the display panel, the effective level of the first scan drive signal corresponding to the j-th pixel circuit row precedes the effective level of the first scan drive signal corresponding to the (j+h)-th pixel circuit row; the target quantity corresponding to the j-th pixel circuit row is j1, and the target quantity corresponding to the (j+h)-th pixel circuit row is j2, where j1 = j2. + h.

[0124] Within the same frame scanning time, the first scanning drive circuit first scans the j-th pixel circuit row, and then scans the (j+h)-th pixel circuit row.

[0125] For example, the following explanation will still use h=12 as an example:

[0126] From the 1st to the 12th pixel circuit row, the target quantity corresponding to each pixel circuit row is j1; from the 13th to the 24th pixel circuit row, the target quantity corresponding to each pixel circuit row is j2. Here, the target quantity corresponding to the 1st pixel circuit row is j1, the target quantity corresponding to the 2nd pixel circuit row is j1, and the same applies to the 3rd to 12th pixel circuit rows. The target quantity corresponding to the 13th pixel circuit row is j2, the target quantity corresponding to the 14th pixel circuit row is j2, and the same applies to the 15th to 24th pixel circuit rows. Here, the meaning of "target quantity" is the same as in the above embodiment, that is, the target quantity corresponding to the first pixel circuit row is the number of first-type sub-segments b11 between the first second-type sub-segment d12 of the first light emission control signal EM1_1 and the effective level (low level) of the first scan drive signal Scan1_1. The first light emission control signal corresponding to the second pixel circuit row is EM1_2, the first scan drive signal corresponding to the second pixel circuit row is Scan1_2, and the target quantity corresponding to the second pixel circuit row is the number of first-type sub-segments b11 between the first second-type sub-segment d12 of the first light emission control signal EM1_2 and the effective level (low level) of the first scan drive signal Scan1_2. And so on, the first light emission control signal corresponding to the Rth pixel circuit row is EM1_R, the first scan drive signal corresponding to the second pixel circuit row is Scan1_R, and the target quantity corresponding to the Rth pixel circuit row is the number of first-type sub-segments b11 between the first second-type sub-segment d12 of the first light emission control signal EM1_R and the effective level (low level) of the first scan drive signal Scan1_R.

[0127] The target number corresponding to the 1st pixel circuit row minus the target number corresponding to the 13th pixel circuit row equals 12, the target number corresponding to the 2nd pixel circuit row minus the target number corresponding to the 14th pixel circuit row equals 12, the target number corresponding to the 3rd pixel circuit row minus the target number corresponding to the 15th pixel circuit row equals 12, and so on, the target number corresponding to the 12th pixel circuit row minus the target number corresponding to the 24th pixel circuit row equals 12.

[0128] It can be understood that in each pixel circuit group, the duration between the start time of the first type-2 sub-segment corresponding to the first pixel circuit row and the end time of the last type-2 sub-segment corresponding to the last pixel circuit row determines the duration occupied by the type-2 sub-segment corresponding to the pixel circuit group.

[0129] In this embodiment, it is equivalent to pulling back the type-2 sub-segment corresponding to the (j+h)th pixel circuit row, so that the type-2 sub-segment corresponding to the (j+h)th pixel circuit row and the type-2 sub-segment corresponding to the jth pixel circuit row tend to be aligned in time, thereby controlling the type-2 sub-segments corresponding to a plurality of pixel circuit groups within a short target period to improve display uniformity.

[0130] Illustratively, 0=b<a<0.5, and h==m, that is, j1=j2+m.

[0131] Within one frame scanning time, the number of first sub-segments included in the first emission control signal is (R+P) / m, and the duration of each first sub-segment is m*t, as Figure 10 shown, the first sub-segment d1 of the first emission control signal EM1_1 corresponding to the 1st pixel circuit row is aligned in time with the first sub-segment d1 of the first emission control signal EM1_h+1 corresponding to the (h+1)th (h=m) pixel circuit row, or in other words, at the same time, the first emission control signal EM1_1 corresponding to the 1st pixel circuit row is the first sub-segment d1, and the first emission control signal EM1_m+1 corresponding to the (m+1)th pixel circuit row is also the first sub-segment d1. For example, Figure 10 taking h=m=12 as an example, in the period c1, the first emission control signal EM1_1 corresponding to the 1st pixel circuit row is at the first sub-segment d1, and the first emission control signal EM1_13 corresponding to the 13th pixel circuit row is at the first sub-segment d1.

[0132] It can be understood that the first sub-segment d1 of the first emission control signal EM1_h corresponding to the hth pixel circuit row is aligned in time with the first sub-segment d1 of the first emission control signal EM1_2h corresponding to the 2hth pixel circuit row, where h=m and m is any value from 1 to R

[0133] In this example, the R pixel circuit rows are divided into R / m pixel circuit groups, with m rows as a group. For the second type of sub-segment d12, it is equivalent to repeating the arrangement with m pixel circuit rows in a periodic manner. This can control the second type of sub-segment corresponding to the R pixel circuit rows within a shorter target time period, thereby improving display uniformity.

[0134] The above examples illustrate some implementation methods that can realize that the second type of sub-segments d12 in the first light emission control signals EM1_1 to EM1_R are all within a target time period f3. However, this is not intended to limit this application. Those skilled in the art can make appropriate modifications to the above embodiments to realize that the second type of sub-segments d12 in the first light emission control signals EM1_1 to EM1_R are all within a target time period f3.

[0135] In some embodiments, such as Figure 10 or Figure 11 As shown, within the same frame scanning time of the display panel, the number of second sub-segments d12 in the first light emission control signals corresponding to different pixel circuit rows is the same.

[0136] For example, the number of second-type sub-segments d12 in the first light emission control signal corresponding to the i1th pixel circuit row is the same as the number of second-type sub-segments d12 in the first light emission control signal corresponding to the i2th pixel circuit row, i1≠i2, and 1≤i1≤R, 1≤i2≤R.

[0137] As an example, S2 = 1. For example... Figure 10 As shown, within one frame scan time of the display panel, the number of second-type sub-segments d12 in the first light emission control signal EM1 corresponding to any pixel circuit row is 1. The fewer the number of second-type sub-segments in the first light emission control signal corresponding to the pixel circuit row, the easier it is to make the duration of the target time period to which the second-type sub-segments corresponding to R pixel circuit rows belong smaller.

[0138] For example, 0 = b < a < 0.5, and S² = 1. Or, 0 < b < a < 0.5, and S² = 1.

[0139] As another example, S² ≥ 2. Figure 11 As shown, within one frame scan time of the display panel, the number of second-type sub-segments d12 in the first light emission control signal EM1 corresponding to any pixel circuit row is 2. Of course, in other examples, the number of second-type sub-segments d12 in the first light emission control signal EM1 corresponding to any pixel circuit row can be greater than 2.

[0140] In some embodiments, when the number of second-type sub-segments in the first light-emitting control signals corresponding to different pixel circuit rows is the same within the same frame scanning time of the display panel, such as Figure 11As shown, within the same frame scan time of the display panel, the relative position of d12_k of the kth second-type sub-segment in the first light emission control signal EM1_j3 corresponding to the j3rd pixel circuit row is the same as the relative position of d12_k of the kth second-type sub-segment in the first light emission control signal EM1_j4 corresponding to the j4th pixel circuit row, 1≤j3<j4≤R. It can be understood that j3 and j4 are both positive integers. Here, the relative position is still the target number of the first-type sub-segments between the second-type sub-segment in the first light emission control signal corresponding to the pixel circuit row and the effective level of the first scan drive signal.

[0141] For example, the target number of the first type of sub-segment d11 between the kth second type sub-segment d12_k in the first light emission control signal EM1_j3 corresponding to the j3rd pixel circuit row and the effective level (e.g., low level) of the first scan drive signal Scan1_j3 corresponding to the j3rd pixel circuit row is the first number, and the target number of the first type of sub-segment d11 between the kth second type sub-segment d12_k in the first light emission control signal EM1_j4 corresponding to the j4th pixel circuit row and the effective level (e.g., low level) of the first scan drive signal Scan1_j4 corresponding to the j4th pixel circuit row is also the first number.

[0142] In this embodiment, within the same frame scanning time of the display panel, the relative positions of the kth second sub-segments in the first light emission control signals corresponding to different pixel circuit rows are set to be the same. In this way, the first light emission control signals corresponding to the first pixel circuit row to the Rth pixel circuit row can be passed sequentially, thereby reducing the complexity of the driving timing.

[0143] For example, if k is less than or equal to S2, taking k==2 as an example, within the same frame scanning time of the display panel, the relative position of d12 of the first second-type sub-segment in the first light emission control signal EM1_j3 corresponding to the j3rd pixel circuit row is the same as the relative position of d12 of the first second-type sub-segment in the first light emission control signal EM1_j4 corresponding to the j4th pixel circuit row; the relative position of d12 of the second second-type sub-segment in the first light emission control signal EM1_j3 corresponding to the j3rd pixel circuit row is the same as the relative position of d12 of the second second-type sub-segment in the first light emission control signal EM1_j4 corresponding to the j4th pixel circuit row.

[0144] In some embodiments, when S2≥2, such as Figure 11 As shown, in the first light emission control signal EM1 corresponding to the pixel circuit row, there is a gap of q first-class sub-segments d11 between two adjacent second-class sub-segments d12. It can be understood that q is an integer greater than or equal to 1.

[0145] As an example, 0 = b < a < 0.5, and q first-type subsegments d11 are spaced between two adjacent second-type subsegments d12 in the first emission control signal EM1 corresponding to the pixel circuit row. In this example, the light-emitting element does not emit light within the second-type subsegments, which is equivalent to dispersing the non-luminous second-type subsegments, thereby avoiding the occurrence of non-luminous phases visible to human eyes.

[0146] As another example, 0 < b < a < 0.5, and q first-type subsegments d11 are spaced between two adjacent second-type subsegments d12 in the first emission control signal EM1 corresponding to the pixel circuit row. In this example, the light-emitting duration of the light-emitting element within the second-type subsegments is shorter than that within the first-type subsegments, which is equivalent to dispersing the second-type subsegments with short non-luminous duration, and can avoid the flicker problem visible to human eyes.

[0147] Of course, in other examples, when S2≥2, no first-type subsegment may be spaced between at least two second-type subsegments of the first emission control signal corresponding to the pixel circuit row.

[0148] In some embodiments, as Figure 11 shown, within one frame scanning time of the display panel, both the display scanning period f1 and the front-back porch period f2 include first-type subsegments d11.

[0149] The light-emitting element emits light within the first-type subsegments d11. In this example, the light-emitting element can emit light in both the display scanning period f1 and the front-back porch period f2, thereby improving the display effect.

[0150] Exemplarily, within one frame scanning time of the display panel, the number of first-type subsegments d11 in the display scanning period f1 is greater than the number of first-type subsegments d11 in the front-back porch period f2, that is, R / m>P / m, R>P. For example, R can be much larger than P. As an example, P=1 m , or P=2m.

[0151] In some embodiments, as Figure 12 shown, at least one first-type subsegment b11 is spaced between the second-type subsegment d12 in the first emission control signal EM1 corresponding to the pixel circuit row and the effective level (for example, low level) of the first scanning driving signal Scan1.

[0152] For example, the first pixel circuit row corresponds to the first emission control signal EM1_1 and the first scanning driving signal Scan1_1, and at least one first-type subsegment b11 is spaced between the second-type subsegment d12 in the first emission control signal EM1_1 in the w-th frame and the effective level of the first scanning driving signal Scan1_1 in the (w+1)-th frame, where w is a positive integer.

[0153] The second pixel circuit row corresponds to the first light emission control signal EM1_ and the first scan drive signal Scan1_2. The second type sub-segment d12 in the first light emission control signal EM1_2 in the w-th frame is at least separated from the effective level of the first scan drive signal Scan1_2 in the w+1-th frame by a first type sub-segment b11.

[0154] Similarly, the Rth pixel circuit row corresponds to the first light emission control signal EM1_R and the first scan drive signal Scan1_R. The second type sub-segment d12 in the first light emission control signal EM1_R in the wth frame is at least separated from the effective level of the first scan drive signal Scan1_R in the w+1th frame by a first type sub-segment b11.

[0155] As an example, when b=0, the light-emitting element does not emit light in the second type of segment. If the effective level of the second type of segment and the first scan drive signal are adjacent, that is, after the light is not emitted, the first scan drive signal immediately writes the corresponding data voltage to the pixel circuit, the stress effect of the driving transistor in the pixel circuit will cause the final written data voltage to change, easily forming a Mura (display unevenness) problem. In this embodiment, the duty cycle of the cutoff level of the first light-emitting control signal EM1 in the second type of segment d12 is 1, and the second type of segment and the effective level of the first scan drive signal are separated by the first type of segment, which can avoid Mura. a question.

[0156] For example, there is at least one first-type sub-segment b11 between the second type sub-segment d12 in the first light emission control signal EM1 corresponding to the pixel circuit row and the effective level (e.g., low level) of the first scan drive signal Scan1. Furthermore, when the number of second-type sub-segments in the first light emission control signals corresponding to different pixel circuit rows is the same during the same frame scan time of the display panel, the relative position of d12_k of the kth second-type sub-segment in the first light emission control signal EM1_j3 corresponding to the j3rd pixel circuit row is the same as the relative position of d12_k of the kth second-type sub-segment in the first light emission control signal EM1_j4 corresponding to the j4th pixel circuit row.

[0157] In any of the above embodiments, the first light-emitting control signal is generated by the first light-emitting driving circuit. The structure of the first light-emitting driving circuit is described below by way of example.

[0158] In some embodiments, such as Figure 13 and Figure 14As shown, the first light-emitting driving circuit 31 includes multiple cascaded first shift registers VSR1. Each first shift register VSR1 includes a first output transistor M14. The first terminal of the first output transistor M14 is connected to the first clock input terminal CLK, and the second terminal of the first output transistor M14 is connected to the output terminal Emi of the first shift register VSR1. The output terminal Emi of the first shift register VSR1 outputs the first light-emitting control signal EM1. The first clock input terminal CLK is electrically connected to the first clock signal line 51. The number of first clock signal lines 51 electrically connected to the first light-emitting driving circuit 31 is n, where n is an integer, R / n is an integer, and m / n is an integer. The effective level duration of the first light-emitting control signal EM1 within the first sub-segment is less than or equal to t*n.

[0159] The first clock signal line 51 includes the first clock signal line 51_1 to the nth first clock signal line 51_n, and the wth first shift register and the w+nth first shift register are connected to the same first clock signal line.

[0160] For example, Figure 13 Taking n=6 as an example, the first shift register VSR1_1 to the sixth shift register VSR1_6 are connected to the first clock signal line 51_1 to the sixth clock signal line 51_6 in sequence. The seventh shift register VSR1_7 to the twelfth shift register VSR1_12 are connected to the first clock signal line 51_1 to the sixth clock signal line 51_6 in sequence. The thirteenth shift register VSR1_13 to the eighteenth shift register VSR1_18 are connected to the first clock signal line 51_1 to the sixth clock signal line 51_6 in sequence, and so on. Understandably, the first first shift register VSR1_1, the seventh first shift register VSR1_7, the thirteenth first shift register VSR1_18, etc., are all connected to the first first clock signal line 51_1, and the second first shift register VSR1_2, the eighth first shift register VSR1_8, the fourteenth first shift register VSR1_14, etc., are all connected to the second first clock signal line 51_2, and so on. They will not be explained one by one.

[0161] like Figure 14 As shown, the first shift register VSR1 includes a driving module 61 and a gating module 62. The gating module 62 includes a first output transistor M14. The output terminal Carry of the driving module 61 is connected to the trigger signal terminal of the next stage first shift register. The output terminal Carry of the driving module 61 is connected to the gate of the first output transistor M14. The output terminal of the gating module 62 outputs the first light emission control signal EM1.

[0162] like Figure 15 As shown, Figure 15 This corresponds to the timing diagram of the first shift register connected to the first clock signal line 51_1. For example, as shown... Figure 15 As shown, the effective level (e.g., low level) of the first clock signal on n first clock signal lines 51 needs to be shifted backward by at least one row scan time t. The effective level on the nth first clock signal line 51_n is shifted backward by the effective level on the 1st first clock signal line 51_1 for a duration n*t.

[0163] In addition, the signal output by the output terminal Carry of the driver module 61 and the signal on the first clock input terminal CLK will jointly control the first light emission control signal EM1 output by the output terminal Emi. That is to say, the effective level duration of the first light emission control signal EM1 is jointly determined by the effective level duration of the signal output by the output terminal Carry of the driver module 61 and the effective level duration of the signal on the first clock input terminal CLK.

[0164] The inventors discovered that if the duration of the effective level of the first light emission control signal EM1 in the first sub-segment is greater than t*n, timing conflicts are likely to occur. In this embodiment, by setting the duration of the effective level of the first light emission control signal EM1 in the first sub-segment to be less than or equal to t*n, timing conflicts can be avoided.

[0165] It should be noted that, Figure 14 and Figure 15 These are merely examples and are not intended to limit this application.

[0166] In some embodiments, the duration of the effective level of the first light-emitting control signal within the first sub-segment is equal to t*n. In this example, the light-emitting duration of the light-emitting element within the first sub-segment can be maximized.

[0167] As an example, such as Figure 5 As shown, the first light emission control signal EM1 includes an effective level (low level) in each first segment d1, and the duration of the effective level of the first light emission control signal EM1 in each first segment d1 can be t*n.

[0168] As an example, such as Figure 10 or Figure 11 As shown, the first sub-segment includes a first type of sub-segment d11 and a second type of sub-segment d12. The first light-emitting control signal EM1 has an effective level (low level) in each of the first type of sub-segments d11, and the duration of the effective level of the first light-emitting control signal EM1 in each of the first type of sub-segments d11 can be t*n. In addition, the first light-emitting control signal EM1 maintains a cutoff level (high level) in the second type of sub-segment d12.

[0169] In some embodiments, such as Figure 15 As shown, during one frame scan time of the display panel, the first clock signal on the first clock signal line 51 includes S second sub-segments d2, and the S second sub-segments d2 and S first sub-segments d1 correspond one-to-one.

[0170] The first clock signal on the first clock signal line 51 is usually a periodic signal. A second sub-segment can be understood as one period of the first clock signal. In one frame scan time, it is equivalent to dividing the first clock signal into S periods on average and dividing the first light emission control signal into S periods on average. The periods of the first clock signal and the periods of the first light emission control signal correspond one-to-one.

[0171] like Figure 14 As shown, when the first output transistor M14 is turned on, the first clock signal on the first clock signal line 51 is transmitted to the output terminal Emi through the first output transistor M14. The output terminal Emi outputs the first light emission control signal EM1. The timing of the first clock signal on the first clock signal line 51 affects the timing of the first light emission control signal EM1.

[0172] In this embodiment, the S second sub-segments of the first clock signal and the S first sub-segments of the first light emission control signal correspond one-to-one, which can avoid timing conflicts.

[0173] In some embodiments, such as Figure 16 As shown, the signal on the first clock signal terminal CLK is the first clock signal. The first sub-segment d1 includes the first type of sub-segment d11. In the first type of sub-segment d11, the duty cycle of the effective level of the first light emission control signal EM1 is a, 0 < a < 0.5. The second sub-segment d2 includes the third type of sub-segment d23. The third type of sub-segment d23 corresponds to the first type of sub-segment d11. In the third type of sub-segment d23, the number of effective pulses (low-level pulses) of the first clock signal is m / n.

[0174] For example, with m=12 and n=6, the first clock signal on the first clock signal terminal CLK includes two low-level pulses in the third sub-segment d23. It is understood that the low levels of the first clock signal on the first clock signal terminal CLK are interspersed with high levels.

[0175] For example, within one frame of scanning time, the first emission control signal EM1 corresponding to each pixel circuit row includes S first segments d1, where S = (R + P) / m. This ensures that the first segment of the first emission control signal corresponding to the first pixel circuit row and the first segment of the first emission control signal corresponding to the (m+1)th pixel circuit row are time-aligned. For example, as... Figure 9An example is shown where m = h = 12, and the first sub-segment d1 of the first light emission control signal EM1_1 corresponding to the first pixel circuit row and the first sub-segment d1 of the first light emission control signal EM1_13 corresponding to the 13th pixel circuit row are time-aligned.

[0176] The first light-emitting driving circuit is connected to n first clock signal lines 51. The effective levels of the first clock signals on different first clock signal lines 51 are staggered in time. The timing of the first clock signals affects the timing of the first light-emitting control signals. Specifically, the first clock signal includes S second sub-segments within one frame of scanning time. The S second sub-segments correspond one-to-one with the S first sub-segments, and the first clock signal in the second sub-segment includes m / n effective pulses, so that the first sub-segment of the first light-emitting control signal corresponding to the first pixel circuit row and the first sub-segment of the first light-emitting control signal corresponding to the (m+1)th pixel circuit row can be aligned in time.

[0177] In some embodiments, such as Figure 16 As shown, the signal on the first clock signal terminal CLK is the first clock signal. The first sub-segment d1 includes the second sub-segment d12, in which the duty cycle of the effective level of the first light emission control signal EM1 is 0. The second sub-segment d2 includes the fourth sub-segment d24, which corresponds to the second sub-segment d12. In the fourth sub-segment d24, the duty cycle of the effective level of the first clock signal is 0. That is, the first clock signal remains at the cutoff level in the fourth sub-segment d24.

[0178] In the second type of sub-segment d12, the duty cycle of the effective level of the first light-emitting control signal EM1 is 0, which means that the duty cycle of the cutoff level of the first light-emitting control signal EM1 in the second type of sub-segment d12 is 1. Similarly, in the fourth type of sub-segment d24, the duty cycle of the effective level of the first clock signal is 0, which means that the duty cycle of the cutoff level of the first clock signal in the fourth type of sub-segment d24 is 1.

[0179] To better explain why the duty cycle of the effective level of the first clock signal in the fourth type of sub-segment is set to 0, please refer to the reference. Figure 13 and Figure 17Taking n=6 and m=12 as an example, the first to sixth first shift registers VSR1_6 are sequentially connected to the first to sixth first clock signal lines 51_1 and 51_6, respectively, and the first to sixth first shift registers VSR1_6 sequentially output the first light-emitting control signals EM1_1 to EM1_6; the seventh to twelfth first shift registers VSR1_12 are sequentially connected to the first to sixth first clock signal lines 51_1 and 51_6, respectively, and the first light-emitting control signals EM1_7 to EM1_12 sequentially output the first light-emitting control signals EM1_7 to EM1_12.

[0180] The timing of the first clock signal on the first clock signal line 511 determines the timing of the first light emission control signals EM1_1 and EM1_7. If the first clock signal on the first clock signal line 51_1 is only changed to the cutoff level (high level) during time period c3, the effective pulse of the first clock signal on the first clock signal line 51_1 during time period c2 is still retained, which will cause the first light emission control signal EM1_1 to remain at the cutoff level in its second type sub-segment d12. However, the first light emission control signal EM1_7 cannot have a second type sub-segment with a cutoff level duty cycle of 1.

[0181] Specifically, if the first clock signal on the first clock signal line 51_1 is only changed to the cutoff level (high level) during time period c3, the effective pulse of the first clock signal on the first clock signal line 51_1 during time period c2 is still retained. The first light-emitting control signals EM1_1 to EM1_6 have a second type of segment with a cutoff level duty cycle of 1; the first light-emitting control signals EM1_7 to EM1_12 cannot have a second type of segment with a cutoff level duty cycle of 1; the first light-emitting control signals EM1_13 to EM1_18 have a second type of segment with a cutoff level duty cycle of 1; the first light-emitting control signals EM1_19 to EM1_24 cannot have a second type of segment with a cutoff level duty cycle of 1; and so on.

[0182] In this embodiment, setting the effective level duty cycle of the first clock signal in the fourth type of sub-segment to 0 enables the effective level duty cycle of the first light emission control signal in the second type of sub-segment to also be 0.

[0183] It should be noted that the accompanying drawings of this application exemplarily show that the duration of an effective level of the first light emission control signal EM1 is equal to the duration of an effective level of the first clock signal on the first clock signal line 51. This is not intended to limit this application, and in other examples, the two may not be equal.

[0184] In some embodiments, such as Figure 13 The first light-emitting driving circuit 31 includes multiple cascaded first shift registers VSR1. The trigger signal terminal STV of the first-stage first shift register VSR1_1 is connected to the trigger signal line 52. The other end of the trigger signal line 52 is connected to the driving chip, and the driving chip provides a trigger signal to the trigger signal terminal STV of the first-stage first shift register VSR1_1.

[0185] like Figure 18 As shown, during one frame scan time of the display panel, the trigger signal on the trigger signal line 52 includes S third sub-segments d3, and the S third sub-segments d3 and S first sub-segments d1 correspond one-to-one.

[0186] The trigger signal on the trigger signal line 52 is usually a periodic signal. A third sub-segment can be understood as one period of the trigger signal. In one frame scan time, it is equivalent to dividing the trigger signal into S periods on average and dividing the first light emission control signal into S periods on average. The period of the trigger signal and the period of the first light emission control signal correspond one-to-one.

[0187] Please refer to the reference. Figure 14 and Figure 15 The trigger signal is used to start the first shift register. The timing of the first light emission control signal output by the first shift register follows the timing of the trigger signal. In this embodiment, the S third segments of the trigger signal and the S first segments of the first light emission control signal correspond one-to-one, which can avoid timing conflicts.

[0188] Understandably, such as Figure 15 As shown, within one frame scan time, relative to the waveform of the trigger signal on the trigger signal terminal STV, the waveform of the first light emission control signal EM1 is shifted backward for a duration, for example, a shift duration t.

[0189] In some embodiments, such as Figure 18 As shown, the first sub-segment d1 includes the first type of sub-segment d11, in which the duty cycle of the effective level of the first light-emitting control signal EM1 is a, 0 < a < 0.5; the third sub-segment d3 includes the fifth type of sub-segment d35, which corresponds to the first type of sub-segment d11, and the number of effective pulses of the trigger signal on the trigger signal line 52 in the fifth type of sub-segment d35 is equal to the number of effective pulses of the first light-emitting control signal EM1 in the first type of sub-segment d11.

[0190] In the corresponding first-class sub-segment d11 and fifth-class sub-segment d35, the first-class sub-segment d11 is shifted to the right relative to the fifth-class sub-segment d35, for example, by a shift time t.

[0191] The timing of the first light emission control signal follows the timing of the trigger signal. In this embodiment, the number of effective pulses of the first light emission control signal in the first type of sub-segment and the number of effective pulses of the trigger signal in the fifth type of sub-segment are set to be the same, which can avoid timing conflicts.

[0192] In some embodiments, such as Figure 18 As shown, the first sub-segment d1 includes the second sub-segment d12, in which the duty cycle of the effective level of the first light-emitting control signal EM1 is 0; the third sub-segment d3 includes the sixth sub-segment d36, which corresponds to the second sub-segment d12, in which the duty cycle of the effective level of the trigger signal on the trigger signal line 52 is 0. The duty cycle of the effective level of the first light-emitting control signal EM1 in the second sub-segment d12 being 0 means that the duty cycle of the cutoff level of the first light-emitting control signal EM1 in the second sub-segment d12 is 1. The duty cycle of the effective level of the trigger signal on the trigger signal line 52 in the sixth sub-segment d36 being 0 means that the duty cycle of the cutoff level of the trigger signal on the trigger signal line 52 in the sixth sub-segment d36 is 1.

[0193] In the corresponding second-class sub-segment d12 and sixth-class sub-segment d36, the second-class sub-segment d12 is shifted to the left relative to the sixth-class sub-segment d36, for example, by a shift time t.

[0194] The timing of the first light emission control signal follows the timing of the trigger signal. In this embodiment, the trigger signal in the fifth sub-segment is set to maintain the cutoff level, which enables the first light emission control signal in the second sub-segment to remain at the cutoff level.

[0195] It should be noted that the accompanying drawings of this application exemplarily show that the duration of an effective level of the first light emission control signal EM1 is equal to the duration of an effective level of the trigger signal on the trigger signal line 52. This is not intended to limit this application, and in other examples, the two may be unequal.

[0196] For example, such as Figure 4 As shown, the pixel circuit includes a PAM module and a PWM module. The first scan drive circuit is electrically connected to the PWM module, and the first light-emitting drive circuit is connected to the PAM module. Figure 19 As shown, within one frame scan time, the first light emission control signal EM1 (PAM_EM) includes multiple first segments d1. In each first segment d1, the scan signal PAM_S2 includes an active level (e.g., low level). The data voltage PAM_data can be written to the driving transistor T11 of PAM in each first segment d1. That is to say, the data voltage PAM_data can be written multiple times within one frame scan time.

[0197] The first scan drive signal Scan1 (i.e. PWM_S2) only includes a low level once within one frame scan time, so the data voltage PWM_data is written to the drive transistor T21 of the PWM module once within one frame scan time.

[0198] It should be noted that this article uses the example of a low level for the effective level and a high level for the cutoff level of each signal. This is not intended to limit this application. Those skilled in the art can make appropriate changes to the embodiments of this application according to their needs, such as changing the effective level to a high level and changing the cutoff level to a low level, etc.

[0199] This application also provides a display device, including the display panel provided in this application. Please refer to... Figure 20 , Figure 20 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 20 The provided display device 1000 includes the display panel 100 provided in any of the above embodiments of this application. Figure 20 This embodiment uses a mobile phone as an example to illustrate the display device 1000. It is understood that the display device provided in this application embodiment can be other display devices with display functions, such as wearable products, computers, televisions, and in-vehicle display devices; this application does not impose specific limitations on these. The display device provided in this application embodiment has the beneficial effects of the display panel provided in this application embodiment. For details, please refer to the specific descriptions of the display panel in the above embodiments; these will not be repeated here.

[0200] The embodiments described above are not exhaustive, nor do they limit the application to the specific embodiments described herein. Clearly, many modifications and variations can be made based on the above description. These embodiments are selected and specifically described in this specification to better explain the principles and practical applications of this application, thereby enabling those skilled in the art to effectively utilize this application and its modifications. This application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized by, Comprising: a pixel circuit, wherein a plurality of said pixel circuits are arranged into pixel circuit rows in a first direction, and R said pixel circuit rows are arranged in a second direction, said first direction intersecting said second direction; a first scanning drive circuit, wherein said first scanning drive circuit provides a first scanning drive signal for said pixel circuit rows; wherein a duration for said first scanning drive circuit to scan one row of said pixel circuits is t; a first emission drive circuit, wherein said first emission drive circuit provides a first emission control signal comprising S first sub-segments for said pixel circuit rows; wherein a duration of said first sub-segment is m*t, and m is a positive integer; said pixel circuit comprises a first data writing transistor, a first pole of said first data writing transistor is electrically connected to a data line, a control terminal of said first data writing transistor is electrically connected to a first scanning drive line, and said first scanning drive circuit is electrically connected to said first scanning drive line; one frame scanning time T of said display panel comprises a display scanning period and a front-back porch period, a duration of said display scanning period is M, and a duration of said front-back porch period is N; M=R*t, N=P*t, T=M+N; wherein, S=(R+P) / m, S is a positive integer, and R / m is a positive integer.

2. The display panel of claim 1, wherein, said first sub-segments comprise first-type sub-segments, in said first-type sub-segments, a duty cycle of an effective level of said first emission control signal is greater than 0, and duty cycles of the effective level of said first emission control signal in different said first-type sub-segments are the same.

3. The display panel according to claim 1, characterized in that, said first sub-segments comprise first-type sub-segments, in said first-type sub-segments, a duty cycle of an effective level of said first emission control signal is a, 0<a<0.5; within one frame scanning time of said display panel, the number of said first-type sub-segments is S1, S1=S.

4. The display panel according to claim 1, characterized in that, said first sub-segments comprise first-type sub-segments and second-type sub-segments, in said first-type sub-segments, a duty cycle of an effective level of said first emission control signal is a, in said second-type sub-segments, a duty cycle of the effective level of said first emission control signal is b, 0≤b<a<0.5; within one frame scanning time of said display panel, the number of said first-type sub-segments is S1, the number of said second-type sub-segments is S2, S=S1+S2.

5. The display panel according to claim 4, characterized in that, b＝0。 6. The display panel according to claim 5, characterized in that, S1>S2.

7. The display panel according to claim 5, characterized in that, at least one of said second-type sub-segments is located in said front-back porch period.

8. The display panel according to claim 5, characterized in that, within the same frame scanning time of the display panel, said second-type sub-segments in said first emission control signals corresponding to R said pixel circuit rows are within a target period, and a duration of said target period is less than M.

9. The display panel according to claim 8, characterized in that, M>N, and a duration of said target period is less than N.

10. The display panel according to claim 7, characterized in that, said second-type sub-segment in said first emission control signal corresponding to the j-th said pixel circuit row is located in said front-back porch period, 1≤j≤R.

11. The display panel according to claim 5, characterized in that, h said pixel circuit rows are arranged into a pixel circuit group in said second direction, and R said pixel circuit rows comprise a plurality of said pixel circuit groups; Within the same frame scan time of the display panel, the relative positions of the second type of sub-segments in the first light emission control signals corresponding to different pixel circuit rows within the same pixel circuit group are the same, and the relative position of the second type of sub-segments in the first light emission control signals corresponding to the j-th pixel circuit row is different from the relative position of the second type of sub-segments in the first light emission control signals corresponding to the (j+h)-th pixel circuit row; the relative position is the target number of the first type of sub-segments between the second type of sub-segments in the first light emission control signals corresponding to the pixel circuit row and the effective level of the first scan drive signal.

12. The display panel according to claim 11, characterized in that, Within the same frame scan time of the display panel, the effective level of the first scan drive signal corresponding to the h-th pixel circuit row is before the effective level of the first scan drive signal corresponding to the j+h-th pixel circuit row. The number of targets corresponding to the j-th pixel circuit row is j1, and the number of targets corresponding to the (j+h)-th pixel circuit row is j2, where j1 = j2 + h.

13. The display panel according to claim 5, characterized in that, Within the same frame scan time of the display panel, the number of the second type of sub-segments in the first light emission control signal corresponding to different pixel circuit rows is the same.

14. The display panel according to claim 13, characterized in that, Within the same frame scan time of the display panel, the relative position of the kth second-type sub-segment in the first light emission control signal corresponding to the j3rd pixel circuit row is the same as the relative position of the kth second-type sub-segment in the first light emission control signal corresponding to the j4th pixel circuit row, 1≤j3<j4≤R; the relative position is the target number of the first-type sub-segments between the second-type sub-segment in the first light emission control signal corresponding to the pixel circuit row and the effective level of the first scan drive signal.

15. The display panel according to claim 5, characterized in that, S2≥2, and there are q first-type sub-segments between two adjacent second-type sub-segments in the first light emission control signal corresponding to the pixel circuit row.

16. The display panel according to claim 15, characterized in that, Within the same frame scanning time of the display panel, both the display scanning period and the front and rear corridor periods include the first type of sub-segment.

17. The display panel according to claim 5, characterized in that, S2＝1。 18. The display panel according to claim 5, characterized in that, There is at least one first-type sub-segment between the second type of sub-segment in the first light emission control signal corresponding to the pixel circuit row and the effective level of the first scan drive signal.

19. The display panel according to claim 1, characterized in that, The first light-emitting driving circuit includes multiple cascaded first shift registers. Each first shift register includes a first output transistor. The first terminal of the first output transistor is connected to a first clock input terminal, and the second terminal of the first output transistor is connected to the output terminal of the first shift register. The output terminal of the first shift register outputs the first light-emitting control signal. The first clock input terminal is electrically connected to the first clock signal line, and the number of the first clock signal lines electrically connected to the first light-emitting driving circuit is n, where n is an integer, R / n is an integer, and m / n is an integer; The duration of the effective level of the first light emission control signal within the first sub-segment is less than or equal to t*n.

20. The display panel according to claim 19, characterized in that, The duration of the effective level of the first light emission control signal within the first sub-segment is equal to t*n.

21. The display panel according to claim 20, characterized in that, During one frame scan time of the display panel, the first clock signal on the first clock signal line includes S second sub-segments, and the S second sub-segments correspond to the S first sub-segments.

22. The display panel according to claim 21, characterized in that, The first sub-segment includes a first type of sub-segment, in which the duty cycle of the effective level of the first light emission control signal is a, 0 < a < 0.5; The second sub-segment includes a third type of sub-segment, which corresponds to the first type of sub-segment. In the third type of sub-segment, the number of effective pulses of the first clock signal is m / n.

23. The display panel according to claim 21, characterized in that, The first sub-segment includes a second type of sub-segment, in which the duty cycle of the effective level of the first light emission control signal is 0; The second sub-segment includes a fourth type of sub-segment, which corresponds to the second type of sub-segment, wherein the duty cycle of the effective level of the first clock signal is 0 in the fourth type of sub-segment.

24. The display panel according to claim 1, characterized in that, The first light-emitting driving circuit includes multiple cascaded first shift registers, and the trigger signal terminal of the first-stage first shift register is connected to a trigger signal line; During one frame scan time of the display panel, the trigger signal on the trigger signal line includes S third sub-segments, and the S third sub-segments correspond to the S first sub-segments.

25. The display panel according to claim 24, characterized in that, The first sub-segment includes a first type of sub-segment, in which the duty cycle of the effective level of the first light emission control signal is a, 0 < a < 0.5; The third sub-segment includes a fifth type of sub-segment, which corresponds to the first type of sub-segment. In the fifth type of sub-segment, the number of effective pulses of the trigger signal on the trigger signal line is equal to the number of effective pulses of the first light emission control signal in the first type of sub-segment.

26. The display panel according to claim 24, characterized in that, The first sub-segment includes a second type of sub-segment, in which the duty cycle of the effective level of the first light emission control signal is 0; The third sub-segment includes a sixth type of sub-segment, which corresponds to the second type of sub-segment. In the sixth type of sub-segment, the duty cycle of the effective level of the trigger signal on the trigger signal line is 0.

27. The display panel according to claim 1, characterized in that, Within the same frame scanning time of the display panel, the time interval between the p-th first sub-segment corresponding to the effective level of the first scan drive signal of the j-th pixel circuit row and the p-th first sub-segment corresponding to the effective level of the first scan drive signal of the (j+1)-th pixel circuit row is t.

28. The display panel according to claim 1, characterized in that, The pixel circuit includes a pulse amplitude modulation module and a pulse width modulation module. The pulse width modulation module is electrically connected to the pulse amplitude modulation module, and the pulse amplitude modulation module is electrically connected to the light-emitting element. The first scan drive circuit is electrically connected to the pulse width modulation module; The first light-emitting driving circuit is electrically connected to the pulse amplitude modulation module.

29. A display device, characterized in that, Includes the display panel as described in any one of claims 1-28.

Images