An amplifier circuit

Abstract

An amplifier circuit includes a preamplifier unit, an amplification unit, a frequency compensation unit and a first slew rate optimization unit. The first slew rate optimization unit includes a first current source circuit and a second current source circuit. When a jump occurs at the input of the amplifier circuit, the first current source or the second current source charges or discharges the output terminal of the amplifier circuit. After the input jump ends, the first current source and the second current source are automatically turned off. The present application optimizes the voltage slew rate of the amplifier circuit while maintaining low power consumption.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to an amplifier circuit. Background Technology

[0002] The display panel in a liquid crystal display (LCD) device consists of multiple pixels arranged in a matrix. The operation of each pixel is controlled by a thin-film transistor (TFT), which is also arranged in a matrix. TFTs in the same row are interconnected via gate lines, while those in the same column are interconnected via data lines. Both the gate lines and data lines are controlled by a display driver chip (DDI).

[0003] To ensure smooth display and avoid stuttering or blurring, the display panel needs to be charged and discharged within a short time, i.e., the signal switching rate of the gate lines and data lines needs to be accelerated. Increasing the voltage slewing rate of the buffer used in DDI (usually implemented using an amplifier) ​​helps to improve the charging and discharging of the display panel. The voltage slewing rate of the buffer refers to how quickly the output signal of the buffer follows changes in the input signal.

[0004] To improve the voltage conversion rate of the buffer, the buffer current can be increased, especially the output stage current. However, increasing the buffer current means increasing its power consumption. Yet, with the rapidly growing demand for low-power, high-resolution display panels, increasing the buffer power is undesirable for battery-powered portable electronic devices such as mobile phones and tablets. Summary of the Invention

[0005] This application provides an amplifier circuit that charges or discharges the output terminal of the amplifier circuit using a charging current source or a discharging current source when the input of the amplifier circuit changes. After the input change ends, the charging current source and the discharging current source are automatically turned off, thereby optimizing the voltage conversion rate of the amplifier circuit while maintaining low power consumption, and meeting the application requirements of low power, high resolution display panels.

[0006] According to an embodiment of the present invention, an amplifier circuit is provided, comprising: a preamplifier unit having a positive differential input terminal and a negative differential input terminal for receiving a positive differential input signal and a negative differential input signal, respectively, and outputting a first converted signal and a second converted signal based on the positive differential input signal and the negative differential input signal; an amplification unit for receiving the first converted signal and the second converted signal, and outputting an output signal of the amplifier circuit at an output terminal based on the first converted signal and the second converted signal; and a frequency compensation unit having a first frequency compensation capacitor and a second frequency compensation capacitor, the first frequency compensation capacitor having a first terminal coupled to a first current shunt point of the preamplifier unit and a second terminal coupled to the output terminal of the amplification unit. The second frequency compensation capacitor has a first end coupled to the second current shunt point of the preamplifier unit and a second end coupled between the output terminals of the amplification unit; and a first slew rate optimization unit, including a first current source circuit and a second current source circuit, the first current source circuit having a first end coupled to a first power supply terminal and a second end coupled to the first end of the first frequency compensation capacitor, and a control terminal receiving the positive differential input signal or a follower signal of the positive differential input signal, the second current source circuit having a first end coupled to a second power supply terminal and a second end coupled to the first end of the second frequency compensation capacitor, and a control terminal receiving the positive differential input signal or a follower signal of the positive differential input signal.

[0007] In one embodiment, the first current source includes a first coupling capacitor having a first end and a second end, the first end being coupled to a first tail current terminal of the preamplifier unit; a first current transistor having a first end coupled to a first power supply terminal, a second end coupled to a first end of the first frequency compensation capacitor, and a control terminal coupled to a second end of the first coupling capacitor; and a pull-up circuit having a first end coupled to the first power supply terminal and a second end coupled to the control terminal of the first current transistor. The second current source includes: a second coupling capacitor having a first end and a second end, the first end being coupled to a second tail current terminal of the preamplifier unit; a second current transistor having a first end coupled to a second power supply terminal, a second end coupled to a first end of the second frequency compensation capacitor, and a control terminal coupled to a second end of the second coupling capacitor; and a pull-down circuit having a first end coupled to the second power supply terminal and a second end coupled to the control terminal of the second current transistor.

[0008] In one embodiment, the first current source includes: a first coupling capacitor having a first end and a second end, the first end being coupled to a positive differential input terminal of a preamplifier unit; a first current transistor having a first end coupled to a first power supply terminal, a second end coupled to a first end of the first frequency compensation capacitor, and a control terminal coupled to a second end of the first coupling capacitor; and a pull-up circuit having a first end coupled to the first power supply terminal and a second end coupled to a control terminal of the first current transistor. The second current source includes: a second coupling capacitor having a first end and a second end, the first end being coupled to a positive differential input terminal of the preamplifier unit; a second current transistor having a first end coupled to a second power supply terminal, a second end coupled to a first end of the second frequency compensation capacitor, and a control terminal coupled to a second end of the second coupling capacitor; and a pull-down circuit having a first end coupled to the second power supply terminal and a second end coupled to a control terminal of the second current transistor. Attached Figure Description

[0009] The above and other objects, features and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings:

[0010] Figure 1 This is a schematic diagram of the circuit structure of an amplifier circuit 100 according to an embodiment of this application;

[0011] Figure 2 This is a schematic diagram of the circuit structure of an amplifier circuit 200 according to an embodiment of this application;

[0012] Figure 3 This is a schematic diagram of the circuit structure of an amplifier circuit 300 according to an embodiment of this application;

[0013] Figure 4 This is a schematic diagram of the circuit structure of an amplifier circuit 400 according to an embodiment of this application;

[0014] Figure 5 This is a schematic diagram of the circuit structure of an amplifier circuit 500 according to an embodiment of this application;

[0015] Figure 6 This is a schematic diagram of the circuit structure of an amplifier circuit 600 according to an embodiment of this application;

[0016] Figure 7 This is a schematic diagram of the circuit structure of an amplifier circuit 700 according to an embodiment of this application;

[0017] Figure 8 This is a schematic diagram of the circuit structure of an amplifier circuit 800 according to an embodiment of this application;

[0018] Figure 9 This is a schematic diagram of the circuit structure of an amplifier circuit 900 according to an embodiment of this application;

[0019] Figure 10 This is a schematic diagram of the circuit structure of an amplifier circuit 1000 according to an embodiment of this application;

[0020] Figure 11 This is a schematic diagram of the circuit structure of an amplifier circuit 1100 according to an embodiment of this application;

[0021] Figure 12 A schematic diagram comparing the voltage conversion rate of the output voltage of a prior art amplifier circuit with the voltage conversion rate of the output voltage of an amplifier circuit 900 according to an embodiment of this application is shown. Detailed Implementation

[0022] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other instances, well-known circuits, materials, or methods have not been specifically described to avoid obscuring the invention.

[0023] The terms "first," "second," etc., used in the following description are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature specified with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "multiple" means two or more.

[0024] Furthermore, in this application, directional terms such as "upper" and "lower" may be defined relative to the orientation in which the components are schematically placed in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly depending on the orientation in which the components are placed in the accompanying drawings.

[0025] In this application, unless otherwise expressly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. Furthermore, the term "coupled" can refer to a method of electrical connection for signal transmission. "Coupled" can be a direct electrical connection or an indirect electrical connection through an intermediate medium.

[0026] To simplify notation and facilitate description, the names of circuit connection nodes or ports will use the same symbols as the voltages or signals on the corresponding nodes or ports in the following text. For example, if the symbols for input terminals are “IN+” and “IN-”, then the input signals will also be represented by “IN+” or “IN-”. Similarly, if the symbol for an output port is “OUT”, then the voltage at the output port will also be represented by “OUT”.

[0027] Figure 1 This is a schematic diagram of the circuit structure of an amplifier circuit 100 according to an embodiment of this application.

[0028] like Figure 1 As shown, the amplifier circuit 100 includes a preamplifier unit 110, an amplification unit 120, a frequency compensation unit 130, and a first slew rate optimization unit 140.

[0029] The front-end unit 110 includes a first input module 111, a second input module 112, a first current mirror module 113, and a second current mirror module 114.

[0030] The first input module 111 is coupled to the positive differential input terminal IN+ and the negative differential input terminal IN- to receive the positive differential input signal IN+ and the negative differential input signal IN-. The second input module 112 is similarly coupled to the positive differential input terminal IN+ and the negative differential input terminal IN- to receive the positive differential input signal IN+ and the negative differential input signal IN-. The first input module 111 and the second input module 112 are respectively provided with a first tail current terminal Pt and a second tail current terminal Nt. Furthermore, the first input module 111 also has a first set of differential current output terminals N1 and N2 coupled to the second current mirror module 114, and the second input module 112 also has a second set of differential current output terminals N3 and N4 coupled to the first current mirror module 113. When the positive and negative differential input signals IN+ and IN- received by the first input module 111 change, the current provided by the first set of differential current output terminals N1 and N2 changes accordingly, thereby adjusting the output of the second current mirror module 114. Similarly, when the positive and negative differential input signals IN+ and IN- received by the second input module 112 change, the current provided by the second set of differential current output terminals N3 and N4 changes accordingly, thereby adjusting the output of the first current mirror module 113.

[0031] The first current mirror module 113 is coupled to the second set of differential current output terminals N3 and N4. The second current mirror module 114 is coupled to the first set of differential current output terminals N1 and N2. Based on the currents at the first set of differential current output terminals N1 and N2 and the second set of differential current output terminals N3 and N4, the first current mirror module 113 and the second current mirror module 114 output a first conversion voltage PD and a second conversion voltage ND, respectively. Figure 1In this embodiment, the first current mirror module 113 includes a first current reference module 115 and a first current follower module 116, and the second current mirror module 114 includes a second current reference module 117 and a second current follower module 118. The first current reference module 115 and the second current reference module 117 are coupled together through a first transmission gate TG1, and the first current follower module 116 and the second current follower module 118 are coupled together through a second transmission gate TG2.

[0032] The amplifier unit 120 receives the first conversion voltage PD and the second conversion voltage ND output by the preamplifier unit, and generates the output voltage OUT at the output terminal OUT.

[0033] The frequency compensation unit 130 includes a first frequency compensation capacitor Co1 and a second frequency compensation capacitor Co2. The first terminal of the first frequency compensation capacitor Co1 is coupled to one of the terminals N3 and N4 in the second set of differential current output terminals (also called the first current shunt point), and the second terminal is coupled to the output terminal OUT of the amplifier circuit 100. The first terminal of the second frequency compensation capacitor Co2 is coupled to one of the terminals N2 in the first set of differential current output terminals N1 and N2 (also called the second current shunt point), and the second terminal is coupled to the output terminal OUT. The first frequency compensation capacitor Co1 and the second frequency compensation capacitor Co2 are used to optimize the frequency characteristics of the output voltage OUT and improve the voltage conversion efficiency of the output voltage OUT.

[0034] The first conversion rate optimization unit 140 includes a first current source circuit 141 and a second current source circuit 142. The first current source circuit 141 has a first terminal coupled to a first power supply terminal VDD, a second terminal coupled to a first terminal of a first frequency compensation capacitor Co1, and a control terminal coupled to a first tail current terminal Pt. The second current source circuit 142 has a first terminal coupled to a second power supply terminal VSS, a second terminal coupled to a first terminal of a second frequency compensation capacitor Co2, and a control terminal coupled to a second tail current terminal Nt.

[0035] exist Figure 1 In the process, when the positive and negative differential input signals received by the positive and negative differential input terminals IN+ and IN- change, the voltages of the first tail current terminal Pt and the second tail current terminal Nt will also change accordingly, thereby controlling the current I1 output by the first current source circuit 141 and the current I2 output by the second current source circuit 142. This causes the current I1 to charge the first frequency compensation capacitor Co1, or the current I2 to discharge the second frequency compensation capacitor Co2, thereby accelerating the change of the output voltage OUT and achieving the purpose of optimizing the conversion rate of the output voltage OUT.

[0036] exist Figure 1In this embodiment, when the negative differential input terminal IN- is connected to the output terminal OUT, the amplifier circuit 100 can be used as a buffer, and the voltage at the output terminal OUT changes with the change at the positive differential input terminal IN+. In the application of a display panel, the amplifier circuit of this embodiment acts as a buffer by connecting the output terminal OUT to the negative differential input terminal IN-, and the voltage at the output terminal OUT follows the voltage at the positive differential input terminal IN+. When the voltage at the positive differential input terminal IN+ changes, the voltage at the output terminal OUT also changes accordingly. However, it should be understood that the amplifier circuit of this embodiment can also be used as an amplifier in other applications.

[0037] Figure 2 This is a schematic diagram of the circuit structure of an amplifier circuit 200 according to an embodiment of this application.

[0038] like Figure 2 As shown, the amplifier circuit 200 includes a preamplifier unit 110, an amplification unit 120, a frequency compensation unit 130, and a first slew rate optimization unit 140. The amplifier circuit 200 and... Figure 1 The amplifier circuit 100 shown in the embodiment has a similar structure and function. The difference is that in the amplifier circuit 200, the control terminal of the first current source circuit 141 and the control terminal of the second current source circuit 142 are both coupled to the positive differential input terminal IN+. The current 11 of the first current source circuit 141 and the current 12 of the second current source circuit 142 are controlled by the positive differential input signal IN+.

[0039] exist Figure 1 In this embodiment, the signals at the first tail current terminal Pt and the second tail current terminal Nt change in response to the changes in the positive differential input signal IN+, and are therefore also referred to as the following signals of the positive differential input signal. It should be understood that, in this embodiment, the rate at which the output terminal OUT follows the change in the positive differential input signal IN+ when IN+ changes is a crucial characteristic of the amplifier circuit. The first current source circuit 141 and the second current source circuit 142 can improve the switching rate of the output terminal OUT, thereby improving the performance of the amplifier circuit. The currents in the first current source circuit 141 and the second current source circuit 142 can be directly controlled by the positive differential input signal IN+, or they can be controlled by the following signals of the positive differential input signal IN+, such as the signals at the first tail current terminal Pt and the second tail current terminal Nt.

[0040] Figure 3 This is a schematic diagram of the circuit structure of an amplifier circuit 300 according to an embodiment of this application.

[0041] like Figure 3 As shown, the amplifier circuit 300 includes a preamplifier unit 310, an amplification unit 320, a frequency compensation unit 330, and a first slew rate optimization unit 340.

[0042] The amplifier circuit 300 includes a plurality of transistors. In this embodiment of the invention, the plurality of transistors includes P-type MOSFETs (metal-oxide-semiconductor field-effect transistors) and N-type MOSFETs. It should be understood that in other embodiments, the plurality of transistors may include other types of controllable switches, such as bipolar transistors.

[0043] The front-end unit 310 includes a first input module 311, a second input module 312, a first current mirror module 313, and a second current mirror module 314.

[0044] The first input module 311 includes transistors M1, M2, and M3. The second input module 312 includes transistors M4, M5, and M6. The first terminal of the first transistor M1 is coupled to the first power supply terminal VDD, and its control terminal receives a reference signal Vp1. The first terminals of the second transistor M2 and the third transistor M3 are coupled to the second terminals of the first transistor M1, and their control terminals receive a negative differential input signal IN- and a positive differential input signal IN+, respectively. Their second terminals are coupled to the first set of differential current output terminals N1 and N2, respectively. The first terminal of the fourth transistor M4 is coupled to the second power supply terminal VSS, and its control terminal receives a reference signal Vn1. The first terminals of the fifth transistor M5 and the sixth transistor M6 are coupled to the second terminal of the fourth transistor M4, and their control terminals receive a negative differential input signal IN- and a positive differential input signal IN+, respectively. Their second terminals are coupled to the second set of differential current output terminals N4 and N3, respectively. Figure 3 In this embodiment, transistors M1-M3 include P-type transistors, and transistors M4-M6 include N-type transistors. The voltage at the first power supply terminal VDD is higher than the voltage at the second power supply terminal VSS.

[0045] The first current mirror module 313 includes a first current reference module 315 and a first current follower module 316. The first current reference module 315 includes a seventh transistor M7 and a ninth transistor M9. The first current follower module 316 includes an eighth transistor M8 and a tenth transistor M10. The first terminal of the seventh transistor M7 is coupled to the first power supply terminal VDD, and the second terminal is coupled to the first terminal of the ninth transistor M9. The second terminal of the ninth transistor M9 is coupled to one end of the first transmission gate TG1. The first terminal of the eighth transistor M8 is coupled to the first power supply terminal VDD, and the second terminal is coupled to the first terminal of the tenth transistor M10. The second terminal of the tenth transistor M10 is coupled to one end of the second transmission gate TG2. The control terminals of the seventh transistor M7 and the eighth transistor M8 are coupled together and are also coupled to the second terminal of the ninth transistor M9. The control terminals of the ninth transistor M9 and the tenth transistor M10 are coupled together and jointly receive the reference signal Vp2.

[0046] The second current mirror module 314 includes a second current reference module 317 and a second current follower module 318. The second current reference module 317 includes an eleventh transistor M11 and a thirteenth transistor M13. The second current follower module 318 includes a twelfth transistor M12 and a fourteenth transistor M14. The first terminal of the thirteenth transistor M13 is coupled to the second power supply terminal VSS, and the second terminal is coupled to the first terminal of the eleventh transistor M11. The second terminal of the eleventh transistor M11 is coupled to the other end of the first transmission gate TG1. The first terminal of the fourteenth transistor M14 is coupled to the second power supply terminal VSS, and the second terminal is coupled to the first terminal of the twelfth transistor M12. The second terminal of the twelfth transistor M12 is coupled to the other end of the second transmission gate TG2. The control terminals of the thirteenth transistor M13 and the fourteenth transistor M14 are coupled together and are also coupled to the second terminal of the eleventh transistor M11. The control terminals of the eleventh transistor M11 and the twelfth transistor M12 are coupled together and both receive the reference signal Vn2.

[0047] The first transmission gate TG1 is coupled between the ninth transistor M9 and the eleventh transistor M11, and its switching is based on reference signals Vp3 and Vn3. The second transmission gate TG2 is coupled between the tenth transistor M10 and the twelfth transistor M12, and its switching is also based on reference signals Vp3 and Vn3. When the second transmission gate TG2 is turned on, the first switching voltage terminal PD and the second switching voltage terminal ND are coupled together, and the voltage difference between them is determined by the on-resistance of the second transmission gate TG2 and the current flowing through it.

[0048] exist Figure 3 In the embodiments, the reference signals Vp1, Vn1, Vp2, Vn2, Vp3, and Vn3 are typically provided by a reference circuit (not shown in the figure) and have constant values ​​to maintain the operation of the amplifier circuit. The setting of the values ​​of the reference signals Vp1, Vn1, Vp2, Vn2, Vp3, and Vn3 is well known to those skilled in the art and will not be described in detail here.

[0049] The first transistor M1 can be considered a current source, and the fourth transistor M4 can be considered a current sink. The current provided by the first transistor M1 flows through the second transistor M2 and the third transistor M3, and then flows into the thirteenth transistor M13 and the fourteenth transistor M14 in the second current mirror circuit 314 through the first set of differential current output terminals N1 and N2, respectively. Meanwhile, the currents in the seventh transistor M7 and the eighth transistor M8 flow through the second set of differential current output terminals N4 and N3, through the second transistor M5 and the sixth transistor M6, respectively, and finally flow into the fourth transistor M4.

[0050] The first current mirror module 313 and the second input module 312 work together to generate the first conversion voltage PD. The second current mirror module 314 and the first input module 311 work together to generate the second conversion voltage ND.

[0051] In the first current mirror module 313, the control terminals (gates) of the seventh transistor M7 and the eighth transistor M8 are connected together, and their first terminals (sources) are also connected to the first power supply terminal VDD, meaning that the source-gate voltages VSG of the seventh transistor M7 and the eighth transistor M8 are the same. Since the aspect ratios of the seventh transistor M7 and the eighth transistor M8 are the same, and the voltages at their second terminals (drains) are approximately the same, their currents are approximately the same. The current of the seventh transistor M7 flows through the fifth transistor M5 and the ninth transistor M9. The current of the eighth transistor M8 flows through the sixth transistor M6 and the tenth transistor M10. That is, the sum of the currents of the fifth transistor M5 and the ninth transistor M9 is approximately the same as the sum of the currents of the sixth transistor M6 and the tenth transistor M10. The dimensions (aspect ratios) of the fifth transistor M5 and the sixth transistor M6 are generally the same. When the voltages of the positive and negative differential input signals IN+ and IN- are the same, the gate-source voltage VGS of the fifth transistor M5 and the sixth transistor M6 are the same, resulting in the same current flowing through them. This means the current flowing through the second set of differential current output terminals N3 and N4 is also the same. When there is a voltage difference between the positive and negative differential input signals IN+ and IN-, the current flowing through the fifth transistor M5 and the sixth transistor M6 differs, meaning the current flowing through the second set of differential current output terminals N3 and N4 is different. Consequently, the current flowing through the seventh transistor M7 is different from the current flowing through the eighth transistor M8.

[0052] In one embodiment, the voltage of the positive differential input signal IN+ is higher than the voltage of the negative differential input signal IN-. The current flowing through the sixth transistor M6 is greater than the current flowing through the fifth transistor M5. In other words, the current flowing from the differential current output terminal N3 into the sixth transistor M6 is greater than the current flowing from the differential current output terminal N4 into the fifth transistor M5. Since the current flowing from the differential current output terminal N4 into the fifth transistor M5 is relatively small, the current flowing through the seventh transistor M7 decreases, causing the voltage at the differential current output terminal N4 and the other end N5 of the ninth transistor M9 to rise. Correspondingly, the voltage at the differential current output terminal N3 decreases, and the first conversion voltage PD decreases accordingly.

[0053] The working principle of the first input module 311 and the second current mirror module 314 is similar to that of the second input module 312 and the first current mirror module 313, and will not be discussed further here.

[0054] The first conversion voltage PD and the second conversion voltage ND will change with the positive and negative differential input voltages IN+ and IN-.

[0055] exist Figure 3 In this embodiment, transistors M7-M10 in the first current mirror module 313 are P-type transistors, and transistors M11-M14 in the second current mirror module 314 are N-type transistors.

[0056] Amplification unit 320 includes a fifteenth transistor M15 and a sixteenth transistor M16. The first terminal of the fifteenth transistor M15 is coupled to a first power supply terminal VDD, and the second terminal is coupled to an output terminal OUT. Its control terminal receives a first conversion voltage PD. The first terminal of the sixteenth transistor M16 is coupled to a second power supply terminal VSS, and the second terminal is coupled to an output terminal OUT. Its control terminal receives a second conversion voltage ND. The output terminal OUT provides the output voltage. When the first conversion voltage PD increases, the output voltage OUT decreases, and vice versa. When the second conversion voltage ND increases, the output voltage OUT decreases, and vice versa.

[0057] exist Figure 3 In this embodiment, the fifteenth transistor M15 is a P-type transistor and the sixteenth transistor M16 is an N-type transistor.

[0058] The frequency compensation unit 330 includes a first frequency compensation capacitor Co1 and a second frequency compensation capacitor Co2. The first terminal of the first frequency compensation capacitor Co1 is coupled to the differential current output terminal N3 (also called the first current shunt point), and the second terminal is coupled to the output terminal OUT. The first terminal of the second frequency compensation capacitor Co2 is coupled to the differential current output terminal N2 (also called the second current shunt point), and the second terminal is coupled to the output terminal OUT.

[0059] The first conversion rate optimization unit 340 includes a first current source circuit 341 and a second current source circuit 342.

[0060] exist Figure 3In this embodiment, the first current source circuit 341 includes a first coupling capacitor Cb1, a first current transistor M18, and a pull-up circuit 343. The first end of the first coupling capacitor Cb1 is coupled to the first tail current terminal Pt, and the second end is coupled to the control terminal of the first current transistor M18. The first end of the first current transistor M18 is coupled to the first power supply terminal VDD, and the second end is coupled to the first end of the first frequency compensation capacitor Co1. The pull-up circuit 343 includes a pull-up transistor, namely the seventeenth transistor M17. The seventeenth transistor M17 has a first end coupled to the first power supply terminal VDD, a second end coupled to the control terminal of the first current transistor M18, and a control terminal that receives a reference signal Vp4. In one embodiment, when the positive differential input signal IN+ transitions, for example from a high level to a low level, the voltage at the first tail current terminal Pt decreases accordingly. The first coupling capacitor Cb1 couples the voltage change at the first tail current terminal Pt to the first current transistor M18, turning on the first current transistor M18. This allows the first power supply terminal VDD to charge the frequency compensation capacitor Co1 through the first current transistor M18, thereby accelerating the decrease in the voltage at the output terminal OUT and improving the voltage transition rate of the output terminal OUT. Before the positive differential input signal IN+ transitions, the reference signal Vp4 turns off the seventeenth transistor M17, allowing the voltage at the control terminal of the first current transistor M18 to be coupled to the voltage at the first tail current terminal Pt through the first coupling capacitor Cb1. After the transition of the positive differential input signal IN+ ends, the reference signal Vp4 turns on the seventeenth transistor M17, pulling the voltage at the control terminal of the first current transistor M18 up to the voltage at the first power supply terminal VDD, thereby turning off the first current transistor M18. The reference signal Vp4 is generated by logic circuitry in an additional control circuit, and its timing is related to the timing of the positive differential input signal IN+. In one embodiment, the reference signal Vp4 has a pulse to turn on the seventeenth transistor M17, the pulse corresponding to the falling edge of the positive differential input signal IN+, and the pulse width is slightly greater than or equal to the falling edge width of the positive differential input signal IN+.

[0061] exist Figure 3In this embodiment, the second current source circuit 342 includes a second coupling capacitor Cb2, a second current transistor M20, and a pull-down circuit 344. The first end of the second coupling capacitor Cb2 is coupled to the second tail current terminal Nt. The first end of the second current transistor M20 is coupled to the second power supply terminal VSS, the second end is coupled to the first end of the second frequency compensation capacitor Co2, and the control terminal is coupled to the second end of the second coupling capacitor Cb2. The pull-down circuit 344 includes a first pull-down transistor, namely the nineteenth transistor M19. The nineteenth transistor M19 has a first end coupled to the second power supply terminal VSS, a second end coupled to the control terminal of the second current transistor M20, and a control terminal that receives a reference signal Vn4. In one embodiment, when the positive differential input signal IN+ transitions, for example from low to high, the voltage at the second tail current terminal Nt increases accordingly. The second coupling capacitor Cb2 couples the voltage change at the second tail current terminal Nt to the second current transistor M20, turning on the second current transistor M20. This allows the second power supply terminal VSS to discharge through the second current transistor M20 to the frequency compensation capacitor Co2, thereby accelerating the increase in the voltage at the output terminal OUT and improving the voltage slew rate of the output terminal OUT. Before the positive differential input signal IN+ transitions, the reference signal Vn4 turns off the nineteenth transistor M19, allowing the voltage at the control terminal of the second current transistor M20 to be coupled to the voltage at the second tail current terminal Nt through the second coupling capacitor Cb2. After the transition of the positive differential input signal IN+ ends, the reference signal Vn4 turns on the nineteenth transistor M19, pulling the voltage at the control terminal of the second current transistor M20 down to the voltage at the second power supply terminal VSS, thereby turning off the second current transistor M20. The reference signal Vn4 is generated by logic circuitry in an additional control circuit, and its timing is related to that of the positive differential input signal IN+. In one embodiment, the reference signal Vn4 has a pulse to turn on the nineteenth transistor M19, the pulse corresponding to the rising and falling edges of the positive differential input signal IN+, and the pulse width is slightly greater than or equal to the rising and falling edge width of the positive differential input signal IN+.

[0062] exist Figure 3 In this embodiment, the first tail current terminal Pt is the source terminal of the two input transistors of the first input module 311, namely the source terminals of the second transistor M2 and the third transistor M3. Similarly, the second tail current terminal Nt is the source terminal of the two input terminals of the second input module 312, namely the source terminals of the fifth transistor M5 and the sixth transistor M6.

[0063] exist Figure 3In the embodiment, the pull-up circuit 343 and the pull-down circuit 344 control the first current transistor M18 and the second current transistor M20 to work when the positive differential signal IN+ transitions, thereby controlling the first current source circuit 341 and the second current source circuit 342 to work only when it is necessary to increase the conversion rate of the output terminal OUT. While increasing the conversion rate of the output terminal OUT, the power of the first current source circuit 341 and the second current source circuit 342 is reduced to a lower level.

[0064] In some embodiments, the reference signal Vp4 and the reference signal Vn4 can also be reference signals with constant values, forming current branches at the control terminals of the first current transistor M18 and the second current transistor M20, respectively, so as to turn off the first current transistor M18 and the second current transistor M20 in a timely manner after the differential input signal IN+ transition ends.

[0065] Figure 4 This is a schematic diagram of the circuit structure of an amplifier circuit 400 according to an embodiment of this application. The amplifier circuit 400 includes a preamplifier unit 310, an amplification unit 320, a frequency compensation unit 330, and a first slew rate optimization unit 440. Figure 3 Compared to the previous embodiment, the first conversion rate optimization unit 440 includes a first current source circuit 441 and a second current source circuit 442. The control terminal of the first current source circuit 441, i.e., the first terminal of the first coupling capacitor Cb1, is coupled to the positive differential input terminal IN+. Similarly, the control terminal of the second current source circuit 442, i.e., the first terminal of the second coupling capacitor Cb2, is also coupled to the positive differential input terminal IN+. The operation of the first current source circuit 441 and the second current source circuit 442 is determined based on the signal at the positive differential input terminal IN+.

[0066] The working principle of amplifier circuit 400 is similar to that of amplifier circuit 300, and will not be discussed further here for the sake of brevity.

[0067] Figure 5 This is a schematic diagram of the circuit structure of an amplifier circuit 500 according to an embodiment of this application. The amplifier circuit 500 includes a preamplifier unit 310, an amplification unit 320, a frequency compensation unit 330, and a first slew rate optimization unit 540. Figure 3 Compared to the previous embodiment, the first conversion rate optimization unit 540 includes a first current source circuit 541 and a second current source circuit 542. The first current source circuit 541 includes a first coupling capacitor Cb1, a pull-up circuit 543, and a first current transistor M18. Figure 5In this embodiment, the pull-up circuit 543 includes a first resistor R1. After the voltage transition at the first tail current terminal Pt ends, the first resistor R1 pulls up the voltage at the control terminal of the first current transistor M18, turning off the first current transistor M18 to reduce the power consumption of the first current source circuit 541. The second current source circuit 542 includes a second coupling capacitor Cb2, a pull-down circuit 544, and a second current transistor M20. The pull-down circuit 544 includes a second resistor R2. After the voltage transition at the second tail current terminal Nt ends, the second resistor R2 pulls down the voltage at the control terminal of the second current transistor M20, turning off the second current transistor M20 to reduce the power consumption of the second current source circuit 542.

[0068] The working principle of amplifier circuit 500 is similar to that of amplifier circuit 300, and will not be discussed further here for the sake of brevity.

[0069] Figure 6 This is a schematic diagram of the circuit structure of an amplifier circuit 600 according to an embodiment of this application. The amplifier circuit 600 includes a preamplifier unit 310, an amplification unit 320, a frequency compensation unit 330, and a first slew rate optimization unit 640. Figure 5 Compared to the previous embodiment, the first conversion rate optimization unit 640 includes a first current source circuit 641 and a second current source circuit 642. The control terminal of the first current source circuit 641, i.e., the first terminal of the first coupling capacitor Cb1, is coupled to the positive differential input terminal IN+. Similarly, the control terminal of the second current source circuit 642, i.e., the first terminal of the second coupling capacitor Cb2, is also coupled to the positive differential input terminal IN+. The operation of the first current source circuit 641 and the second current source circuit 642 is determined based on the signal at the positive differential input terminal IN+.

[0070] The working principle of amplifier circuit 600 is similar to that of amplifier circuit 300, and will not be discussed further here for the sake of brevity.

[0071] Figure 7 This is a schematic diagram of the circuit structure of an amplifier circuit 700 according to an embodiment of this application. The amplifier circuit 700 includes a preamplifier unit 310, an amplification unit 320, a frequency compensation unit 330, and a first slew rate optimization unit 740. Figure 3 Compared to the previous embodiment, the first conversion rate optimization unit 740 includes a first current source circuit 741 and a second current source circuit 742. The first current source circuit 741 includes a first coupling capacitor Cb1, a pull-up circuit 743, and a first current transistor M18. Figure 7In this embodiment, the pull-up circuit 743 includes a seventeenth transistor M17 with a diode connection structure. The seventeenth transistor M17 functions similarly to a resistor; after the voltage transition at the first tail current terminal Pt, it pulls up the voltage at the control terminal of the first current transistor M18, turning off the first current transistor M18 to reduce the power consumption of the first current source circuit 741. The second current source circuit 742 includes a second coupling capacitor Cb2, a pull-down circuit 744, and a second current transistor M20. The pull-down circuit 744 includes a nineteenth transistor M19 with a diode connection structure. After the voltage transition at the second tail current terminal Nt, the nineteenth transistor M19 pulls down the voltage at the control terminal of the second current transistor M20, turning off the second current transistor M20 to reduce the power consumption of the second current source circuit 742.

[0072] The working principle of amplifier circuit 700 is similar to that of amplifier circuit 300, and will not be discussed further here for the sake of brevity.

[0073] Figure 8 This is a schematic diagram of the circuit structure of an amplifier circuit 800 according to an embodiment of this application. The amplifier circuit 800 includes a preamplifier unit 310, an amplification unit 320, a frequency compensation unit 330, and a first slew rate optimization unit 840. Figure 7 Compared to the previous embodiment, the first conversion rate optimization unit 840 includes a first current source circuit 841 and a second current source circuit 842. The control terminal of the first current source circuit 841, i.e., the first terminal of the first coupling capacitor Cb2, is coupled to the positive differential input terminal IN+. Similarly, the control terminal of the second current source circuit 842, i.e., the first terminal of the second coupling capacitor Cb2, is also coupled to the positive differential input terminal IN+. The operation of the first current source circuit 841 and the second current source circuit 842 is determined based on the signal at the positive differential input terminal IN+.

[0074] The working principle of amplifier circuit 800 is similar to that of amplifier circuit 300, and will not be discussed further here for the sake of brevity.

[0075] Figure 9 This is a schematic diagram of the circuit structure of an amplifier circuit 900 according to an embodiment of this application. The amplifier circuit 900 includes a preamplifier unit 310, an amplification unit 320, a frequency compensation unit 330, and a first slew rate optimization unit 940. Figure 3 Compared to the previous embodiment, the first conversion rate optimization unit 940 includes a first current source circuit 941 and a second current source circuit 942.

[0076] The first current source circuit 941 includes a first coupling capacitor Cb1, a pull-up circuit 943, and a first current transistor M18. Figure 9In this embodiment, the pull-up circuit 943 includes a seventeenth transistor M17 (first pull-up transistor) and a twenty-first transistor M21 (second pull-up transistor) connected in series between the first power supply terminal VDD and the control terminal of the first current transistor M18. The control terminals of the seventeenth transistor M17 and the twenty-first transistor M21 receive reference signals Vp4 and Vp5, respectively. In one embodiment, before the positive differential input signal IN+ transitions, the reference signal Vp4 turns off the seventeenth transistor M17, allowing the voltage at the control terminal of the first current transistor M18 to be coupled to the voltage at the first tail current terminal Pt through the first coupling capacitor Cb1. After the transition of the positive differential input signal IN+ ends, the reference signal Vp4 turns on the seventeenth transistor M17, pulling the voltage at the control terminal of the first current transistor M18 up to the voltage of the first power supply terminal VDD, thereby turning off the first current transistor M18. The reference signal Vp4 is generated by logic circuitry in an additional control circuit, and its timing is related to the timing of the positive differential input signal IN+. The reference signal Vp5 has a constant voltage value, which controls the twenty-first transistor M21 to remain on, thereby accelerating the voltage change at the control terminal of the first current transistor M18 and quickly switching the first current transistor M18 on and off to reduce the power consumption of the first current source circuit 941.

[0077] The second current source circuit 942 includes a second coupling capacitor Cb2, a pull-down circuit 944, and a second current transistor M20. Figure 9 In this embodiment, the pull-down circuit 944 includes a nineteenth transistor M19 (first pull-down transistor) and a twenty-second transistor M22 (second pull-down transistor) connected in series between the second power supply terminal VSS and the control terminal of the second current transistor M20. The control terminals of the nineteenth transistor M19 and the twenty-second transistor M22 receive reference signals Vn4 and Vn5, respectively. In one embodiment, before the positive differential input signal IN+ transitions, the reference signal Vn4 turns off the nineteenth transistor M19, allowing the voltage at the control terminal of the second current transistor M20 to be coupled to the voltage at the second tail current terminal Nt through the second coupling capacitor Cb2. After the transition of the positive differential input signal IN+ ends, the reference signal Vn4 turns on the nineteenth transistor M19, pulling the voltage at the control terminal of the second current transistor M20 down to the voltage of the second power supply terminal VSS, thereby turning off the second current transistor M20. The reference signal Vn4 is generated by logic circuitry in an additional control circuit, and its timing is related to the timing of the positive differential input signal IN+. The reference signal Vn5 has a constant voltage value, which controls the twenty-first transistor M21 to remain on, thereby accelerating the voltage change at the control terminal of the second current transistor M20 and quickly switching the second current transistor M20 on and off to reduce the power consumption of the second current source circuit 942.

[0078] The working principle of amplifier circuit 900 is similar to that of amplifier circuit 300, and will not be discussed further here for the sake of brevity.

[0079] Figure 10 This is a schematic diagram of the circuit structure of an amplifier circuit 1000 according to an embodiment of this application. The amplifier circuit 1000 includes a preamplifier unit 310, an amplification unit 320, a frequency compensation unit 330, and a first slew rate optimization unit 1040. Figure 9 Compared to the previous embodiment, the first conversion rate optimization unit 1040 includes a first current source circuit 1041 and a second current source circuit 1042. The control terminal of the first current source circuit 1041, i.e., the first terminal of the first coupling capacitor Cb1, is coupled to the positive differential input terminal IN+. Similarly, the control terminal of the second current source circuit 1042, i.e., the first terminal of the second coupling capacitor Cb2, is also coupled to the positive differential input terminal IN+. The operation of the first current source circuit 1041 and the second current source circuit 1042 is determined based on the signal at the positive differential input terminal IN+.

[0080] The working principle of amplifier circuit 1000 is similar to that of amplifier circuit 300, and will not be discussed further here for the sake of brevity.

[0081] Figure 11 This is a schematic diagram of the circuit structure of an amplifier circuit 1100 according to an embodiment of this application.

[0082] like Figure 11 As shown, the amplifier circuit 1100 includes a preamplifier unit 110, an amplification unit 120, a frequency compensation unit 130, a first slew rate optimization unit 140, and a second slew rate optimization unit 150. Compared to Figure 1 The amplifier circuit 100 of the embodiment further includes a second slew rate optimization unit 150.

[0083] The second conversion rate optimization unit 150 includes a first switch S1 and a second switch S2. The first switch S1 and the second switch S2 are arbitrary controllable switches. The first terminal of the first switch S1 is coupled to the first conversion voltage terminal PD, and the second terminal is coupled to the output terminal OUT. The first terminal of the second switch S2 is coupled to the second conversion voltage terminal ND, and the second terminal is coupled to the output terminal OUT. The control terminals of the first switch S1 and the second switch S2 are connected together and jointly receive the positive differential input signal IN+. The first switch S1 and the second switch S2 switch on and off based on the voltage difference between the positive differential input signal IN+ and the output voltage OUT. When the voltage of the positive differential input signal IN+ jumps, causing the voltage difference between the positive differential input signal IN+ and the output voltage OUT to exceed the conduction threshold of the first switch S1 and the second switch S2, the first switch S1 and the second switch S2 conduct, shorting the first conversion voltage terminal PD and the second conversion voltage terminal ND, thereby accelerating the voltage conversion rate of the output terminal OUT.

[0084] The second conversion rate optimization unit 150 can also be configured in Figures 2-10 The amplifier circuits shown are 200 to 1000.

[0085] Figure 12 A schematic diagram comparing the voltage conversion rate of the output voltage of a prior art amplifier circuit with the voltage conversion rate of the output voltage of an amplifier circuit 900 according to an embodiment of this application is shown.

[0086] exist Figure 12 In the diagram, the thin black line represents the positive differential input signal IN+, the thick black line represents the waveform of the output voltage OUT of amplifier circuit 900 (labeled OUT1), and the dashed line represents the waveform of the output voltage of a prior art amplifier circuit (labeled OUT2). From... Figure 12 It can be clearly seen that when the positive differential input signal IN+ transitions in the positive and negative directions, compared with the existing amplifier circuit, the output voltage OUT of the amplifier circuit 900 with the addition of the first slew rate optimization unit 940 has a higher slope, which means it has a better slew rate.

[0087] The amplifier circuit of this application embodiment can be used as a buffer for the source drive circuit in a liquid crystal display device. The source drive circuit includes the following components: a latch circuit for storing data, and a level shifter for adjusting the data voltage (e.g., processing data output from the latch circuit). The source drive circuit converts the level-shifted data from a digital value to an analog signal and uses a buffer to transmit the analog signal to the data line.

[0088] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0089] The above description is merely a preferred embodiment of this application and is not intended to limit the application in any way. Although this application has disclosed preferred embodiments above, it is not intended to limit the application. Any person skilled in the art can make many possible variations and modifications to the technical solutions of this application using the methods and techniques disclosed above, or modify them into equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of this application. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall still fall within the protection scope of the technical solutions of this application.

Claims

1. An amplifier circuit, comprising: The preamplifier unit has a positive differential input terminal and a negative differential input terminal to receive positive differential input signals and negative differential input signals respectively, and outputs a first conversion signal and a second conversion signal based on the positive differential input signals and negative differential input signals; as well as An amplification unit receives the first conversion signal and the second conversion signal, and outputs the output signal of the amplifier circuit at the output terminal based on the first conversion signal and the second conversion signal; The frequency compensation unit has a first frequency compensation capacitor and a second frequency compensation capacitor. The first frequency compensation capacitor has a first end coupled to a first current shunt point of the preamplifier unit and a second end coupled to the output terminal of the amplification unit. The second frequency compensation capacitor has a first end coupled to a second current shunt point of the preamplifier unit and a second end coupled between the output terminals of the amplification unit. as well as The first conversion rate optimization unit includes a first current source circuit and a second current source circuit. The first current source circuit has a first terminal coupled to a first power supply terminal, a second terminal coupled to a first terminal of the first frequency compensation capacitor, and a control terminal that receives the positive differential input signal or a follower signal of the positive differential input signal. The second current source circuit has a first terminal coupled to a second power supply terminal, a second terminal coupled to a first terminal of the second frequency compensation capacitor, and a control terminal that receives the positive differential input signal or a follower signal of the positive differential input signal. in, The first current source circuit includes: The first coupling capacitor has a first end and a second end, the first end being coupled to the first tail current end of the preamplifier unit. A first current transistor has a first terminal coupled to a first power supply terminal, a second terminal coupled to a first terminal of the first frequency compensation capacitor, and a control terminal coupled to a second terminal of the first coupling capacitor; and A pull-up circuit has a first terminal coupled to a first power supply terminal and a second terminal coupled to a control terminal of the first current transistor. The pull-up circuit is controlled by a reference signal, which is related to the positive differential input signal. The pull-up circuit is turned off before the positive differential input signal transitions from high to low, and turns on after the positive differential input signal transitions from high to low. The second current source includes: The second coupling capacitor has a first end and a second end, the first end being coupled to the second tail current end of the preamplifier unit; The second current transistor has a first terminal coupled to a second power supply terminal, a second terminal coupled to a first terminal of the second frequency compensation capacitor, and a control terminal coupled to a second terminal of the second coupling capacitor; and The pull-down circuit has a first terminal coupled to a second power supply terminal and a second terminal coupled to a control terminal of the second current transistor. The pull-down circuit is controlled by another reference signal, which is related to the positive differential input signal. The pull-down circuit is turned off before the positive differential input signal transitions from low to high, and is turned on after the positive differential input signal transitions from low to high.

2. An amplifier circuit, comprising: The preamplifier unit has a positive differential input terminal and a negative differential input terminal to receive positive differential input signals and negative differential input signals respectively, and outputs a first conversion signal and a second conversion signal based on the positive differential input signals and negative differential input signals; as well as An amplification unit receives the first conversion signal and the second conversion signal, and outputs the output signal of the amplifier circuit at the output terminal based on the first conversion signal and the second conversion signal; The frequency compensation unit has a first frequency compensation capacitor and a second frequency compensation capacitor. The first frequency compensation capacitor has a first end coupled to a first current shunt point of the preamplifier unit and a second end coupled to the output terminal of the amplification unit. The second frequency compensation capacitor has a first end coupled to a second current shunt point of the preamplifier unit and a second end coupled between the output terminals of the amplification unit. as well as The first conversion rate optimization unit includes a first current source circuit and a second current source circuit. The first current source circuit has a first terminal coupled to a first power supply terminal, a second terminal coupled to a first terminal of the first frequency compensation capacitor, and a control terminal that receives the positive differential input signal or a follower signal of the positive differential input signal. The second current source circuit has a first terminal coupled to a second power supply terminal, a second terminal coupled to a first terminal of the second frequency compensation capacitor, and a control terminal that receives the positive differential input signal or a follower signal of the positive differential input signal. in, The first current source circuit includes: A first coupling capacitor has a first end and a second end, the first end being coupled to the positive differential input terminal of the preamplifier unit; A first current transistor has a first terminal coupled to a first power supply terminal, a second terminal coupled to a first terminal of the first frequency compensation capacitor, and a control terminal coupled to a second terminal of the first coupling capacitor; and A pull-up circuit has a first terminal coupled to a first power supply terminal and a second terminal coupled to a control terminal of the first current transistor. The pull-up circuit is controlled by a reference signal, which is related to the positive differential input signal. The pull-up circuit is turned off before the positive differential input signal transitions from high to low, and turns on after the positive differential input signal transitions from high to low. The second current source includes: The second coupling capacitor has a first end and a second end, the first end being coupled to the positive differential input terminal of the preamplifier unit; The second current transistor has a first terminal coupled to a second power supply terminal, a second terminal coupled to a first terminal of the second frequency compensation capacitor, and a control terminal coupled to a second terminal of the second coupling capacitor; and The pull-down circuit has a first terminal coupled to a second power supply terminal and a second terminal coupled to a control terminal of the second current transistor. The pull-down circuit is controlled by another reference signal, which is related to the positive differential input signal. The pull-down circuit is turned off before the positive differential input signal transitions from low to high, and is turned on after the positive differential input signal transitions from low to high.

3. The amplifier circuit as described in any one of claims 1 or 2, wherein, The pull-up circuit includes: The pull-up transistor has a first end coupled to a first power supply terminal, a second end coupled to a control terminal of the first current transistor, and a control terminal that receives the reference signal.

4. The amplifier circuit as described in any one of claims 1 or 2, wherein, The pull-up circuit includes: A first pull-up transistor and a second pull-up transistor are connected in series between the first power supply terminal and the control terminal of the first current transistor. The control terminal of the first pull-up transistor receives a first reference signal, and the control terminal of the second pull-up transistor receives a second reference signal. The first reference signal corresponds to the reference signal.

5. The amplifier circuit as described in any one of claims 1 or 2, wherein, The pull-down circuit includes: The pull-down transistor has a first end coupled to a second power supply terminal, a second end coupled to a control terminal of the second current transistor, and a control terminal that receives the other reference signal.

6. The amplifier circuit as described in any one of claims 1 or 2, wherein, The pull-down circuit includes: A first pull-down transistor and a second pull-down transistor are connected in series between the second power supply terminal and the control terminal of the second current transistor, wherein the control terminal of the first pull-down transistor receives a first reference signal and the control terminal of the second pull-down transistor receives a second reference signal; The first reference signal corresponds to the other reference signal.

7. The amplifier circuit of claim 1 or 2, further comprising a second slew rate optimization unit, the second slew rate optimization unit comprising: The first switch has a first terminal for receiving a first conversion signal, a second terminal coupled to the output terminal of the amplification unit, and a control terminal coupled to the positive differential input terminal. as well as The second switch has a first terminal for receiving a second conversion signal, a second terminal coupled to the output terminal of the amplification unit, and a control terminal coupled to the positive differential input terminal.

8. The amplifier circuit as described in any one of claims 1 or 2, wherein, The front-end unit includes: The first input module has a positive differential input terminal and a negative differential input terminal to receive positive differential input signals and negative differential input signals respectively, and has a first set of differential current output terminals; The second input module has a positive differential input terminal and a negative differential input terminal to receive positive differential input signals and negative differential input signals respectively, and has a second set of differential current output terminals; A first current mirror module is coupled to a second set of differential current output terminals and provides a first conversion voltage based on the current at the second set of differential current output terminals; and The second current mirror module is coupled to the first group of differential current output terminals and provides the first conversion voltage based on the current of the first group of differential current output terminals.

9. The amplifier circuit as described in claim 8, wherein: The first input module includes a first transistor, a second transistor, and a third transistor. The first transistor has a first terminal coupled to a first power supply terminal and a second terminal coupled to a first tail current terminal. The second transistor has a first terminal coupled to the first tail current terminal and a second terminal coupled to one of the first group of differential current output terminals. The third transistor has a first terminal coupled to the first tail current terminal and a second terminal coupled to the other end of the first group of differential current output terminals. The control terminals of the second transistor and the third transistor respectively receive negative differential input signals and positive differential input signals. as well as The second input module includes a fourth transistor, a fifth transistor, and a sixth transistor. The fourth transistor has a first terminal coupled to a second power supply terminal and a second terminal coupled to a second tail current terminal. The fifth transistor has a first terminal coupled to the second tail current terminal and a second terminal coupled to one of the terminals of the second group of differential current output terminals. The sixth transistor has a first terminal coupled to the second tail current terminal and a second terminal coupled to the other terminal of the second group of differential current output terminals. The control terminals of the fifth transistor and the sixth transistor respectively receive negative differential input signals and positive differential input signals. The follower signal of the positive differential input signal represents the voltage at the first tail current terminal or the voltage at the second tail current terminal.

10. The amplifier circuit as claimed in claim 8, wherein: The first current mirror module includes a first current reference module and a first current follower module; and The second current mirror module includes a second current reference module and a second current follower module; in: The first current reference module and the first current follower module are coupled together via a first transmission gate; and The second current reference module and the second current follower module are coupled together through a second transmission gate.

11. The amplifier circuit as claimed in any one of claims 1 or 2, wherein, The amplification unit includes: The fifteenth transistor has a first terminal coupled to a first power supply terminal, a second terminal coupled to the output terminal of the amplifier circuit, and a control terminal receiving a first conversion voltage; and The sixteenth transistor has a first terminal coupled to a second power supply terminal, a second terminal coupled to the output terminal of the amplifier circuit, and a control terminal receiving a second conversion voltage.

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