An operational amplifier with low offset voltage, electronic device

Abstract

The application provides an operational amplifier with low offset voltage and an electronic device, and on one hand, the first offset voltage elimination unit and the second offset voltage elimination unit respectively store and accurately eliminate the offset voltage existing in the first operational amplification unit and the offset voltage existing in the second operational amplification unit, so as to eliminate the error caused by the offset voltage to the first output current unit and the second output current unit respectively generating the first output current and the second output current; on the other hand, by controlling the on-off of the switch, the first operational amplification module and the second operational amplification module are alternately controlled to be in different working stages, so as to ensure that the input end of the operational amplification module in the normal working state in each clock cycle has extremely low offset voltage, thereby ensuring the continuity of the offset voltage elimination.

Description

Technical Field

[0001] This invention relates to the field of high-precision operational amplifiers, and more particularly to an operational amplifier and electronic device with low offset voltage. Background Technology

[0002] During chip manufacturing, operational amplifiers may develop offset voltages at their input terminals due to internal transistor mismatch, process deviations, temperature drift, and mechanical or thermal stress during packaging. In high-precision measurement and control systems, it is often necessary to measure and collect weak analog signals, such as current and voltage. However, the inherent offset voltage of the operational amplifier can affect sampling accuracy.

[0003] To eliminate the offset voltage of operational amplifiers, existing technologies typically employ chopper operational amplifiers and self-stabilizing operational amplifiers.

[0004] For the chopper operational amplifier, please refer to [reference needed]. Figure 1 , Figure 1 This is a circuit diagram of a chopper operational amplifier, specifically composed of a first chopper unit, an operational amplifier, a second chopper unit, and a low-pass filter connected in sequence. The first chopper unit, under the control of a clock signal, can convert the continuous input signal V... in Converted into a high-frequency square wave signal V with a fixed chopping frequency a At this point, the inherent offset voltage Vos at the operational amplifier input, combined with the high-frequency square wave signal Va, is amplified by the operational amplifier to obtain the output signal V. b Output signal V b After passing through the second chopper unit, it is converted into a low-frequency output signal Vout. Since the offset voltage Vos only passes through one chopper unit, its signal is modulated to the chopper frequency by the second chopper unit, even if the input signal V... in The high-frequency offset voltage Vos is separated from the signal. Finally, a low-pass filter is used to filter out the offset voltage Vos that has been modulated to the chopping frequency.

[0005] The problem with this scheme is that, since the chopping process occurs instantaneously, the input signal V... in Before truncation or chopping, there may be rapid changes. When these rapidly changing signals are truncated or chopped, the output signal will exhibit abrupt changes or jumps, resulting in a discontinuity in the output signal in time, which may introduce time-domain errors. Simultaneously, additional harmonic components may appear in the output signal. Therefore, chopper amplifiers cannot be used in scenarios where the input signal frequency is higher than the chopping frequency, thus limiting their application range.

[0006] For self-stabilizing operational amplifiers, please refer to... Figure 2 , Figure 2 This is the circuit diagram of a self-stabilized zero-adjusting operational amplifier, which consists of two operational amplifiers with auxiliary input ports. A1 is the main amplifier, and A2 is the zero-adjusting amplifier. A1 and A2 each have a certain offset voltage, Vos1 and Vos2. The self-stabilized zero-adjusting operational amplifier has two operating modes: a zero-adjustment stage and an amplification stage.

[0007] During the zeroing phase, switches S2 and S4 are closed, while S1 and S3 are open. The input port of A2 is short-circuited, and its output is connected to capacitor CM1. Simultaneously, capacitor CM1 is connected to the auxiliary input of A2 to form a negative feedback structure. Therefore, the input offset voltage of A2 is stored in capacitor CM1. Next, in the amplification phase, switches S2 and S4 are open, while S1 and S3 are closed. Since capacitor voltage cannot change abruptly, the voltage stored in capacitor CM1 remains the offset voltage of A2 itself and serves as the input signal to the auxiliary port of A2. The offset voltage stored in capacitor CM1, combined with the input signal Vin, is input to A2, amplified, and output to capacitor CM2. This signal is then input to the auxiliary input of A1 to cancel the offset voltage Vos1 at the input of A1.

[0008] The problem with this approach is that the self-zeroing operational amplifier needs to store the offset voltage during the zeroing phase before it can cancel the offset voltage during the amplification phase. Therefore, the offset voltage elimination by the self-zeroing operational amplifier is not continuous, which greatly limits its application scenarios.

[0009] Therefore, providing an operational amplifier that can eliminate offset voltage with high precision and continuously without limiting its application scenarios has become a technical problem that the industry urgently needs to solve. Summary of the Invention

[0010] To address the above problems, the present invention provides an operational amplifier and electronic device with low offset voltage.

[0011] According to a first aspect of the present invention, a low offset voltage operational amplifier is provided, comprising: a first operational amplifier module, a second operational amplifier module, and a voltage output module;

[0012] The first operational amplifier module includes a first operational amplifier unit and a first offset voltage cancellation unit; the non-inverting input terminal of the first operational amplifier unit is connected to a first input signal, and the inverting input terminal of the first operational amplifier unit is connected to the first input signal through a second switch or to a second input signal through a first switch; the first terminal of the first operational amplifier unit is coupled to the output terminal of the first offset voltage cancellation unit; the output terminal of the first operational amplifier unit is coupled to the input terminal of the first offset voltage cancellation unit through a third switch, and serves as the output terminal of the first operational amplifier module.

[0013] The second operational amplifier module includes a second operational amplifier unit and a second offset voltage cancellation unit; the non-inverting input terminal of the second operational amplifier unit is connected to a first input signal, and the inverting input terminal of the second operational amplifier unit is connected to the first input signal via a fifth switch or to a second input signal via a fourth switch; the first terminal of the second operational amplifier unit is coupled to the output terminal of the second offset voltage cancellation unit; the output terminal of the second operational amplifier unit is coupled to the input terminal of the second offset voltage cancellation unit via a sixth switch, and serves as the output terminal of the second operational amplifier module.

[0014] The voltage output module includes a first output current unit, a second output current unit, and a first resistor; the control terminal of the first output current unit is coupled to the output terminal of the first operational amplifier module through a seventh switch, the output terminal of the first output current unit is coupled to ground or the first terminal of the first resistor, and the first terminal and the second terminal of the first output current unit are respectively coupled to the second input signal and the power supply voltage; the first output current unit is used to generate and output a first output current according to the voltage output by the first operational amplifier module.

[0015] The control terminal of the second output current unit is coupled to the output terminal of the second operational amplifier module via an eighth switch. The output terminal of the second output current unit is coupled to ground or the first terminal of the first resistor. The first and second terminals of the first output current unit are respectively coupled to the second input signal and the power supply voltage. The second output current unit is used to generate and output a second output current based on the voltage output by the second operational amplifier module. The first terminal of the first resistor serves as the output terminal of the voltage output module, and the second terminal of the first resistor is grounded. The first resistor is used to generate and output a first output voltage or a second output voltage based on the first output current or the second output current. The first output current is the same as the second output current.

[0016] If the first operational amplifier module is in the offset voltage storage stage, then the second switch and the third switch are both turned on, and the first switch and the seventh switch are both turned off; the first offset voltage elimination unit is used to store the voltage output by the first operational amplifier unit, and generate a first offset compensation current and output it to the first operational amplifier unit; if the second operational amplifier module is in the offset voltage storage stage, then the fifth switch and the sixth switch are both turned on, and the fourth switch and the eighth switch are both turned off; the second offset voltage elimination unit is used to store the voltage output by the second operational amplifier unit, and generate a second offset compensation current and output it to the second operational amplifier unit;

[0017] If the first operational amplifier module is in the offset voltage elimination stage, then the second and third switches are both off, and the first and seventh switches are both on; the first offset voltage elimination unit is used to maintain the first offset compensation current according to the stored voltage, so that the first input signal is equal to the second input signal; the output terminal of the first output current unit is coupled to ground; if the second operational amplifier module is in the offset voltage elimination stage, then the fifth and sixth switches are both off, and the fourth and eighth switches are both on; the second offset voltage elimination unit is used to maintain the second offset compensation current according to the stored voltage, so that the first input signal is equal to the second input signal; the output terminal of the second output current unit is coupled to ground.

[0018] If the first operational amplifier module is in normal operation, the second and third switches are still off, and the first and seventh switches are still on; the output terminal of the first output current unit is coupled to the first terminal of the first resistor; if the second operational amplifier module is in normal operation, the fourth and eighth switches are still on, and the fifth and sixth switches are still off; the output terminal of the second output current unit is coupled to the first terminal of the first resistor.

[0019] If the first operational amplifier module is sequentially in the offset voltage storage stage and the offset voltage elimination stage, then the second operational amplifier module is in the normal operation stage; if the second operational amplifier module is sequentially in the offset voltage storage stage and the offset voltage elimination stage, then the first operational amplifier module is in the normal operation stage.

[0020] Optionally, the first offset voltage cancellation unit includes a first capacitor, a first PMOS transistor, a second resistor, a first NMOS transistor, and a second NMOS transistor; the first terminal of the first capacitor is coupled to the gate of the first PMOS transistor and serves as the input terminal of the first offset voltage cancellation unit, and the second terminals of the first capacitor and the second resistor are both coupled to the power supply voltage; the source of the first PMOS transistor is coupled to the first terminal of the second resistor, and the drain of the first PMOS transistor is coupled to the drain of the first NMOS transistor; the gate of the first NMOS transistor is coupled to its own drain and coupled to the gate of the second NMOS transistor, the drain of the second NMOS transistor serves as the output terminal of the first offset voltage cancellation unit, and the sources of the second NMOS transistor and the first NMOS transistor are both grounded.

[0021] Optionally, the first operational amplifier unit includes a first differential input unit, a first amplification path, a second amplification path, a first amplification output unit, and a first bias unit;

[0022] The non-inverting input terminal of the first differential input unit is connected to a first input signal, and the inverting input terminal of the first differential input unit is connected to the first input signal via a second switch or to a second input signal via a first switch; the first terminal of the first amplification path is coupled to the first terminal of the first differential input unit; the first terminal of the second amplification path is coupled to the second terminal of the first differential input unit; the second terminal of the second amplification path is coupled to the first bias terminal of the first amplification output unit and the output terminal of the first offset voltage cancellation unit, respectively; the third terminal of the first differential input unit is coupled to the input terminal of the first bias unit, and the bias terminal of the first bias unit and the second bias terminal of the first amplification output unit are both connected to a bias voltage; the output terminal of the first amplification output unit serves as the output terminal of the first operational amplification unit.

[0023] Optionally, the first differential input unit includes a third NMOS transistor and a fourth NMOS transistor; the gate of the third NMOS transistor and the gate of the fourth NMOS transistor serve as the non-inverting input terminal and the inverting input terminal of the first differential input unit, respectively; the drain of the third NMOS transistor serves as the second terminal of the first differential input unit; and the drain of the fourth NMOS transistor serves as the first terminal of the first differential input unit; the source of the third NMOS transistor serves as the third terminal of the first differential input unit and is coupled to the source of the fourth NMOS transistor.

[0024] Optionally, the first bias unit includes a fifth NMOS transistor; the gate of the fifth NMOS transistor is connected to the bias voltage, the drain of the fifth NMOS transistor serves as the input terminal of the first bias unit, and the source of the fifth NMOS transistor is grounded.

[0025] Optionally, the first amplification path includes a second PMOS transistor, a third PMOS transistor, and a sixth NMOS transistor; the second amplification path includes a fourth PMOS transistor, a fifth PMOS transistor, and a seventh NMOS transistor.

[0026] The gate of the second PMOS transistor is coupled to the gate of the fourth PMOS transistor, and the gate of the second PMOS transistor is also coupled to the drain of the third PMOS transistor. The drain of the second PMOS transistor serves as the first terminal of the first amplification path and is coupled to the source of the third PMOS transistor. The sources of the second PMOS transistor and the fourth PMOS transistor are both coupled to the power supply voltage. The gate of the third PMOS transistor is coupled to the gate of the fifth PMOS transistor, and the drain of the third PMOS transistor is coupled to the drain of the sixth NMOS transistor. The gate of the sixth NMOS transistor is connected to the bias voltage and coupled to the gate of the seventh NMOS transistor. The sources of the sixth NMOS transistor and the seventh NMOS transistor are both grounded.

[0027] The drain of the fourth PMOS transistor serves as the first terminal of the second amplification path and is coupled to the source of the fifth PMOS transistor; the drain of the fifth PMOS transistor serves as the second terminal of the second amplification path and is coupled to the drain of the seventh NMOS transistor.

[0028] Optionally, the first amplification output unit includes a sixth PMOS transistor and an eighth NMOS transistor; the gate of the sixth PMOS transistor serves as the first bias terminal of the first amplification output unit, the source of the sixth PMOS transistor is coupled to the power supply voltage, the drain of the sixth PMOS transistor serves as the output terminal of the first amplification output unit and is coupled to the drain of the eighth NMOS transistor; the gate of the eighth NMOS transistor serves as the second bias terminal of the first amplification output unit, and the source of the eighth NMOS transistor is grounded.

[0029] Optionally, the second offset voltage cancellation unit includes a second capacitor, a seventh PMOS transistor, a third resistor, a ninth NMOS transistor, and a tenth NMOS transistor; the first terminal of the second capacitor is coupled to the gate of the seventh PMOS transistor and serves as the input terminal of the second offset voltage cancellation unit, and the second terminal of the second capacitor and the second terminal of the third resistor are both coupled to the power supply voltage; the source of the seventh PMOS transistor is coupled to the first terminal of the third resistor, and the drain of the seventh PMOS transistor is coupled to the drain of the ninth NMOS transistor; the gate of the ninth NMOS transistor is coupled to its own drain and coupled to the gate of the tenth NMOS transistor, and the drain of the tenth NMOS transistor serves as the output terminal of the second offset voltage cancellation unit, and the sources of the tenth NMOS transistor and the ninth NMOS transistor are both grounded.

[0030] Optionally, the second operational amplifier unit includes a second differential input unit, a third amplification path, a fourth amplification path, a second amplification output unit, and a second bias unit;

[0031] The non-inverting input terminal of the second differential input unit is connected to the first input signal, and the inverting input terminal of the second differential input unit is connected to the first input signal via a fifth switch or to the second input signal via a fourth switch; the first terminal of the third amplification path is coupled to the second terminal of the second differential input unit; the first terminal of the fourth amplification path is coupled to the first terminal of the second differential input unit; the second terminal of the fourth amplification path is coupled to the first bias terminal of the second amplification output unit and the output terminal of the second offset voltage elimination unit, respectively; the third terminal of the second differential input unit is coupled to the input terminal of the second bias unit, and both the bias terminal of the second bias unit and the second bias terminal of the second amplification output unit are connected to a bias voltage; the output terminal of the second amplification output unit serves as the output terminal of the second operational amplification unit.

[0032] Optionally, the second differential input unit includes an eleventh NMOS transistor and a twelfth NMOS transistor; the gate of the eleventh NMOS transistor and the gate of the twelfth NMOS transistor serve as the non-inverting input terminal and the inverting input terminal of the second differential input unit, respectively; the drain of the eleventh NMOS transistor serves as the second terminal of the second differential input unit; and the drain of the twelfth NMOS transistor serves as the first terminal of the second differential input unit; the source of the eleventh NMOS transistor serves as the third terminal of the second differential input unit and is coupled to the source of the twelfth NMOS transistor.

[0033] Optionally, the second bias unit includes a fifteenth NMOS transistor; the gate of the fifteenth NMOS transistor is connected to the bias voltage, the drain of the fifteenth NMOS transistor serves as the input terminal of the second bias unit, and the source of the fifteenth NMOS transistor is grounded.

[0034] Optionally, the third amplification path includes an eighth PMOS transistor, a ninth PMOS transistor, and a thirteenth NMOS transistor; the fourth amplification path includes a tenth PMOS transistor, an eleventh PMOS transistor, and a fourteenth NMOS transistor.

[0035] The gate of the eighth PMOS transistor is coupled to the gate of the tenth PMOS transistor, and the gate of the eighth PMOS transistor is also coupled to the drain of the ninth PMOS transistor. The drain of the eighth PMOS transistor serves as the third terminal of the third amplification path and is coupled to the source of the ninth PMOS transistor. The sources of the eighth PMOS transistor and the tenth PMOS transistor are both coupled to the power supply voltage. The gate of the ninth PMOS transistor is coupled to the gate of the eleventh PMOS transistor, and the drain of the ninth PMOS transistor is coupled to the drain of the thirteenth NMOS transistor. The gate of the thirteenth NMOS transistor is connected to the bias voltage and coupled to the gate of the fourteenth NMOS transistor. The sources of the thirteenth NMOS transistor and the fourteenth NMOS transistor are both grounded.

[0036] The drain of the tenth PMOS transistor serves as the first terminal of the fourth amplification path and is coupled to the source of the eleventh PMOS transistor; the drain of the eleventh PMOS transistor serves as the second terminal of the fourth amplification path and is coupled to the drain of the fourteenth NMOS transistor.

[0037] Optionally, the second amplification output unit includes a twelfth PMOS transistor and a sixteenth NMOS transistor; the gate of the twelfth PMOS transistor serves as the first bias terminal of the second amplification output unit, the source of the twelfth PMOS transistor is coupled to the power supply voltage, the drain of the twelfth PMOS transistor serves as the output terminal of the second amplification output unit and is coupled to the drain of the sixteenth NMOS transistor; the gate of the sixteenth NMOS transistor serves as the second bias terminal of the second amplification output unit, and the source of the sixteenth NMOS transistor is grounded.

[0038] Optionally, the first output current unit includes a thirteenth PMOS transistor and a fourth resistor; the gate of the thirteenth PMOS transistor serves as the control terminal of the first output current unit, the source of the thirteenth PMOS transistor is coupled to the first terminal of the fourth resistor, and the drain of the thirteenth PMOS transistor serves as the output terminal of the first output current unit; the first terminal and the second terminal of the fourth resistor are respectively connected to the second input signal and the power supply voltage.

[0039] Optionally, the second output current unit includes a fourteenth PMOS transistor and a fifth resistor; the gate of the fourteenth PMOS transistor serves as the input terminal of the second output current unit, the source of the fourteenth PMOS transistor is coupled to the first terminal of the fifth resistor, and the drain of the fourteenth PMOS transistor serves as the output terminal of the second output current unit; the first terminal and the second terminal of the fifth resistor are respectively connected to the second input signal and the power supply voltage.

[0040] Optionally, it also includes a switch array; the switch array includes a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth PMOS transistor, and a twentieth PMOS transistor;

[0041] The gate of the fifteenth PMOS transistor is connected to a first control signal, the source of the fifteenth PMOS transistor is coupled to the output terminal of the first output current unit, and the drain of the fifteenth PMOS transistor is coupled to the source of the seventeenth PMOS transistor and the source of the eighteenth PMOS transistor, respectively; the drain of the seventeenth PMOS transistor is grounded, the drain of the eighteenth PMOS transistor is coupled to the first terminal of the first resistor, and the gates of the seventeenth PMOS transistor and the eighteenth PMOS transistor are connected to a second control signal and a third control signal, respectively.

[0042] The gate of the sixteenth PMOS transistor is connected to the fourth control signal, the source of the sixteenth PMOS transistor is coupled to the output terminal of the second output current unit, and the drain of the sixteenth PMOS transistor is coupled to the source of the nineteenth PMOS transistor and the source of the twentieth PMOS transistor, respectively; the drain of the nineteenth PMOS transistor is grounded, the drain of the twentieth PMOS transistor is coupled to the first terminal of the first resistor, and the gates of the nineteenth PMOS transistor and the twentieth PMOS transistor are connected to the fifth control signal and the sixth control signal, respectively.

[0043] Wherein, if the first operational amplifier module is in the offset voltage storage stage or the offset voltage elimination stage, and the second operational amplifier module is in the normal operation stage, then the first control signal is high level or low level, the fourth control signal is low level, the second control signal is low level, the third control signal is high level, the fifth control signal is high level, and the sixth control signal is low level;

[0044] If the second operational amplifier module is in the offset voltage storage stage or the offset voltage elimination stage, and the first operational amplifier module is in the normal operation stage, then the fourth control signal is high or low, the first control signal is low, the fifth control signal is low, the sixth control signal is high, the second control signal is high, and the third control signal is low.

[0045] Optionally, the second control signal and the fifth control signal are two-phase non-overlapping signals; the second control signal is the inverted signal of the third control signal; and the fifth control signal is the inverted signal of the sixth control signal.

[0046] Optionally, a sixth resistor is also included; the sixth resistor is coupled between the drain and ground of the seventeenth PMOS transistor; wherein the resistance value of the sixth resistor is equal to the resistance value of the first resistor.

[0047] According to a second aspect of the present invention, an electronic device is provided, comprising an operational amplifier with low offset voltage provided by the first aspect and alternative embodiments of the present invention.

[0048] The low offset voltage operational amplifier provided by this invention, on the one hand, stores and precisely cancels the offset voltages present in the first operational amplifier unit and the second operational amplifier unit respectively through a first offset voltage cancellation unit and a second offset voltage cancellation unit, thereby eliminating the error caused by the offset voltage in the first output current unit and the second output current unit generating the first output current and the second output current unit respectively. On the other hand, by controlling the on and off of a control switch, the first operational amplifier module and the second operational amplifier module are controlled to alternately be in different operating stages. If the first operational amplifier module is in the offset voltage storage stage and the offset voltage cancellation stage in sequence, the second operational amplifier module is in the normal operating stage; if the second operational amplifier module is in the offset voltage storage stage and the offset voltage cancellation stage in sequence, the first operational amplifier module is in the normal operating stage. This ensures that the input terminal of the operational amplifier module in the normal operating state has an extremely low offset voltage in each clock cycle, thereby ensuring the continuity of offset voltage cancellation. At the same time, the technical solution provided by this invention is not limited by the input signal frequency during the offset voltage cancellation process, thus increasing the application scope of this invention. Attached Figure Description

[0049] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0050] Figure 1 This is a circuit diagram of a chopper operational amplifier in the prior art;

[0051] Figure 2 This is a circuit diagram of a self-stabilizing operational amplifier in the prior art;

[0052] Figure 3 A module structure diagram of an operational amplifier with low offset voltage is provided for the first embodiment of the present invention;

[0053] Figure 4 A circuit diagram of an operational amplifier with low offset voltage is provided for the first embodiment of the present invention;

[0054] Figure 5 A timing diagram of the signals for turning on and off each switch in the operational amplifier provided in the first embodiment of the present invention to control the low offset voltage.

[0055] Figure label:

[0056] 10 - First operational amplifier module; 11 - First operational amplifier unit; 12 - First offset voltage cancellation unit; 20 - Second operational amplifier module; 21 - Second operational amplifier unit; 22 - Second offset voltage cancellation unit; 30 - Voltage output module; 31 - First output current unit; 32 - Second output current unit; S1 - First switch; S2 - Second switch; S3 - Third switch; S4 - Fourth switch; S5 - Fifth switch; S6 - Sixth switch; S7 - Seventh switch; S8 - Eighth switch; VCS - Power supply voltage; VISEN_IN - First input signal; VBUFA - Second input signal; VOUT -; Vos1-; Vos2-; VBIAS-; C1-First capacitor; C2-Second capacitor; R1-First resistor; R2-Second resistor; R3-Third resistor; R4-Fourth resistor; R5-Fifth resistor; NM1-First NMOS transistor; NM2-Second NMOS transistor; NM3-Third NMOS transistor; NM4-Fourth NMOS transistor; NM5-Fifth NMOS transistor; NM6-Sixth NMOS transistor; NM7-Seventh NMOS transistor; NM8-Eighth NMOS transistor; NM9-Ninth NMOS transistor; NM10-Tenth NMOS transistor; NM11-Eleventh NMOS transistor; NM12 - Twelfth NMOS transistor; NM13-Thirteenth NMOS transistor; NM14-Fourteenth NMOS transistor; NM15-Fifteenth NMOS transistor; NM16-Sixteenth NMOS transistor; PM1-First PMOS transistor; PM2-Second PMOS transistor; PM3-Third PMOS transistor; PM4-Fourth PMOS transistor; PM5-Fifth PMOS transistor; PM6-Sixth PMOS transistor; PM7-Seventh PMOS transistor; PM8-Eighth PMOS transistor; PM9-Ninth PMOS transistor; PM10-Tenth PMOS transistor; PM11-Eleventh PMOS transistor; PM12-Twelfth PMOS transistor; P M13 - Thirteenth PMOS transistor; PM14 - Fourteenth PMOS transistor; PM15 - Fifteenth PMOS transistor; PM16 - Sixteenth PMOS transistor; PM17 - Seventeenth PMOS transistor; PM18 - Eighteenth PMOS transistor; PM19 - Nineteenth PMOS transistor; PM20 - Twentieth PMOS transistor; AH - Second control signal; AL - Third control signal; BH - Fifth control signal; BL - Sixth control signal; A1H - Seventh control signal; A2H - Eighth control signal; A2L - First control signal; B1H - Ninth control signal; B2H - Tenth control signal; B2L - Fourth control signal. Detailed Implementation

[0057] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. The terms "first," "second," "third," "fourth," etc. (if present) in the specification, claims, and accompanying drawings of the present invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0058] Please refer to Figure 3 The first embodiment of the present invention provides an operational amplifier with low offset voltage, including: a first operational amplifier module 10, a second operational amplifier module 20, and a voltage output module 30;

[0059] The first operational amplifier module 10 includes a first operational amplifier unit 11 and a first offset voltage cancellation unit 12. The non-inverting input terminal of the first operational amplifier unit 11 is connected to a first input signal VISEN_IN, and the inverting input terminal of the first operational amplifier unit 11 is connected to the first input signal VISEN_IN through a second switch S2 or to a second input signal VBUFA through a first switch S1. The first terminal of the first operational amplifier unit 11 is coupled to the output terminal of the first offset voltage cancellation unit 12. The output terminal of the first operational amplifier unit 11 is coupled to the input terminal of the first offset voltage cancellation unit 12 through a third switch S3, and serves as the output terminal of the first operational amplifier module 10.

[0060] The second operational amplifier module 20 includes a second operational amplifier unit 21 and a second offset voltage cancellation unit 22. The non-inverting input terminal of the second operational amplifier unit 21 is connected to a first input signal VISEN_IN, and the inverting input terminal of the second operational amplifier unit 21 is connected to the first input signal VISEN_IN through a fifth switch S5 or to a second input signal VBUFA through a fourth switch S4. The first terminal of the second operational amplifier unit 21 is coupled to the output terminal of the second offset voltage cancellation unit 22. The output terminal of the second operational amplifier unit 21 is coupled to the input terminal of the second offset voltage cancellation unit 22 through a sixth switch S6, and serves as the output terminal of the second operational amplifier module 20.

[0061] The voltage output module 30 includes a first output current unit 31, a second output current unit 32, and a first resistor R1. The control terminal of the first output current unit 31 is coupled to the output terminal of the first operational amplifier module 10 via a seventh switch S7. The output terminal of the first output current unit 31 is coupled to ground or the first terminal of the first resistor R1. The first and second terminals of the first output current unit 31 are respectively coupled to the second input signal VBUFA and the power supply voltage VCS. The first output current unit 31 is used to generate and output a first output current based on the voltage output by the first operational amplifier module 10. The control terminal of the second output current unit 32 is coupled to the second operational amplifier module 20 via an eighth switch S8. The output terminal of the second output current unit 32 is coupled to ground or the first terminal of the first resistor R1. The first and second terminals of the first output current unit 31 are respectively coupled to the second input signal VBUFA and the power supply voltage VCS. The second output current unit 32 is used to generate a second output current and output it according to the voltage output by the second operational amplifier module 20. The first terminal of the first resistor R1 serves as the output terminal of the voltage output module 30, and the second terminal of the first resistor R1 is grounded. The first resistor R1 is used to generate a first output voltage or a second output voltage and output it according to the first output current or the second output current. The first output current is the same as the second output current.

[0062] If the first operational amplifier module 10 is in the offset voltage storage stage, then the second switch S2 and the third switch S3 are both turned on, and the first switch S1 and the seventh switch S7 are both turned off; the first offset voltage elimination unit 12 is used to store the voltage output by the first operational amplifier unit 11, and generate a first offset compensation current and output it to the first operational amplifier unit 11; if the second operational amplifier module 20 is in the offset voltage storage stage, then the fifth switch S5 and the sixth switch S6 are both turned on, and the fourth switch S4 and the eighth switch S8 are both turned off; the second offset voltage elimination unit is used to store the voltage output by the second operational amplifier unit 21, and generate a second offset compensation current and output it to the second operational amplifier unit 21;

[0063] If the first operational amplifier module 10 is in the offset voltage elimination stage, then the second switch S2 and the third switch S3 are both off, and the first switch S1 and the seventh switch S7 are both on; the first offset voltage elimination unit 12 is used to maintain the first offset compensation current according to the stored voltage, so that the first input signal VISEN_IN is equal to the second input signal VBUFA; the output terminal of the first output current unit 31 is coupled to ground; if the second operational amplifier module 20 is in the offset voltage elimination stage, then the fifth switch S5 and the sixth switch S6 are both off, and the fourth switch S4 and the eighth switch S8 are both on; the second offset voltage elimination unit 22 is used to maintain the second offset compensation current according to the stored voltage, so that the first input signal VISEN_IN is equal to the second input signal VBUFA; the output terminal of the second output current unit 32 is coupled to ground.

[0064] If the first operational amplifier module 10 is in normal operation, the second switch S2 and the third switch S3 are both off, and the first switch S1 and the seventh switch S7 are both on; the output terminal of the first output current unit 31 is coupled to the first terminal of the first resistor R1; if the second operational amplifier module 20 is in normal operation, the fourth switch S4 and the eighth switch S8 are both on, and the fifth switch S5 and the sixth switch S6 are both off; the output terminal of the second output current unit 32 is coupled to the first terminal of the first resistor R1.

[0065] If the first operational amplifier module 10 is in the offset voltage storage stage and the offset voltage elimination stage in sequence, then the second operational amplifier module 20 is in the normal operation stage; if the second operational amplifier module 20 is in the offset voltage storage stage and the offset voltage elimination stage in sequence, then the first operational amplifier module 10 is in the normal operation stage.

[0066] The first embodiment of this invention achieves high-precision and full-cycle elimination of the influence of offset voltage on the accuracy of the first and second output currents through the above-described technical solution. Its principle is as follows:

[0067] For a single operational amplifier module in an operational amplifier, taking the first operational amplifier module 10 as an example, if the first operational amplifier module 10 needs to eliminate the offset voltage at the input terminal of the first operational amplifier unit 11, the first operational amplifier module 10 first enters the offset voltage storage stage and turns on the second switch S2 and the third switch S3, while turning off the first switch S1 and the seventh switch S7. In this stage, both the non-inverting and inverting input terminals of the first operational amplifier unit 11 are connected to the first input signal VISEN_IN, short-circuiting the two input terminals of the first operational amplifier unit 11. Consequently, the first operational amplifier can only amplify the offset voltage at the input terminal and output a first amplified voltage to the first offset voltage elimination unit 12. The first offset voltage elimination unit 12 stores the first amplified voltage in this stage. Specifically, the first offset voltage elimination unit 12 stores the first amplified voltage through an internally configured capacitor. Simultaneously, the first offset voltage elimination unit 12 generates a first offset compensation current based on the first amplified voltage and outputs it to the first operational amplifier unit 11.

[0068] Next, the first operational amplifier module 10 enters the offset voltage cancellation stage, and turns on the first switch S1 and the seventh switch S7, while turning off the second switch S2 and the third switch S3. In this stage, the non-inverting input and inverting input of the first operational amplifier unit 11 are respectively connected to the first input signal VISEN_IN and the second input signal VBUFA. The output of the first operational amplifier unit 11 is connected to the first output current unit 31, so that the first output current unit 31 generates the first output current. Since the capacitor voltage cannot change abruptly, the first offset voltage cancellation unit 12 replaces the original input first amplified voltage with the stored voltage to maintain the first offset compensation current, thereby making the first input signal VISEN_IN input to the non-inverting input of the first operational amplifier module 10 the same as the second input signal VBUFA input to the inverting input. Simultaneously, because the first terminal of the first output current unit 31 is connected to the second input signal VBUFA, the first terminal of the first output current unit 31 is equivalent to being connected to the first input signal VISEN_IN, thus ensuring the accuracy of the first output current.

[0069] Finally, the first operational amplifier module 10 enters the normal operation stage. With the first switch S1 and the seventh switch S7 turned on and the second switch S2 and the third switch S3 turned off, the output terminal of the first output current unit 31 is coupled to the first terminal of the first resistor R1 so that the first output current flows through the first resistor R1, generating the first output voltage and outputting it.

[0070] Since the structure of the second operational amplifier module 20 is the same as that of the first operational amplifier module 10, the working content of the second operational amplifier module 20 in each stage of the offset voltage storage stage, offset voltage elimination stage and normal operation stage is the same as that of the first operational amplifier module 10, and will not be described again here.

[0071] Based on eliminating the impact of offset voltage on output current accuracy using a single operational amplifier module, the first operational amplifier module 10 and the second operational amplifier module 20 are configured to operate alternately. While the first operational amplifier module 10 is in the offset voltage storage phase and the offset voltage elimination phase, the second operational amplifier module 20 is in normal operating condition. After the first operational amplifier module 10 completes the offset voltage elimination phase and enters normal operating condition, the second operational amplifier module 20 then transitions from normal operating condition to the offset voltage storage phase and the offset voltage elimination phase. This ensures that the operational amplifier modules operating normally in each clock cycle have extremely low offset voltage, thereby ensuring the continuity of offset voltage elimination and ensuring that the sampling results of current or voltage are not affected by offset voltage.

[0072] The following provides a detailed description of the various structures and operating principles of the low offset voltage operational amplifier provided in the first embodiment.

[0073] Please refer to Figure 4In one specific embodiment, the first offset voltage cancellation unit 12 includes a first capacitor C1, a first PMOS transistor PM1, a second resistor R2, a first NMOS transistor NM1, and a second NMOS transistor NM2. The first terminal of the first capacitor C1 is coupled to the gate of the first PMOS transistor PM1 and serves as the input terminal of the first offset voltage cancellation unit 12. The second terminals of the first capacitor C1 and the second resistor R2 are both coupled to the power supply voltage VCS. The source of the first PMOS transistor PM1 is coupled to the first terminal of the second resistor R2, and the drain of the first PMOS transistor PM1 is coupled to the drain of the first NMOS transistor NM1. The gate of the first NMOS transistor NM1 is coupled to its own drain and to the gate of the second NMOS transistor NM2. The drain of the second NMOS transistor NM2 serves as the output terminal of the first offset voltage cancellation unit 12. The sources of the second NMOS transistor NM2 and the first NMOS transistor NM1 are both grounded.

[0074] The voltage output by the first operational amplifier unit 11 is applied to the gate of the first PMOS transistor PM1, causing the first PMOS transistor PM1 to generate a source-drain current. The formula for the source-drain current is as follows:

[0075] I DPM6 =g m *V C (1)

[0076] Among them, I DPM6 Used to characterize the source current of the first PMOS transistor PM1; g m Used to characterize the transconductance of the first PMOS transistor PM1; V C Used to characterize the voltage output by the first operational amplifier unit 11.

[0077] Since the drain of the first NMOS transistor NM1 is connected to the drain of the first PMOS transistor PM1 and then to its own gate, the first NMOS transistor NM1 is turned on by the source-drain current output by the first PMOS transistor PM1, and the drain-source current flowing through the first NMOS transistor NM1 is equal to the source current flowing through the first PMOS transistor PM1. Simultaneously, the first NMOS transistor NM1 and the second NMOS transistor NM2 form a current mirror structure, so the drain-source current flowing through the first NMOS transistor NM1 is proportionally mirrored to the second NMOS transistor NM2. Specifically, the current mirroring ratio is controlled by setting the width-to-length ratio of the first NMOS transistor NM1 and the second NMOS transistor NM2. For example, if the width-to-length ratio of the second NMOS transistor NM2 is four times that of the first NMOS transistor NM1, then the drain-source current flowing through the second NMOS transistor NM2 is equal to four times the drain-source current flowing through the first NMOS transistor NM1. Of course, the specific ratio can be set according to actual needs and is not limited here.

[0078] In one specific implementation, the first operational amplifier unit 11 includes a first differential input unit, a first amplification path, a second amplification path, a first amplification output unit, and a first bias unit;

[0079] The non-inverting input terminal of the first differential input unit is connected to the first input signal VISEN_IN, and the inverting input terminal of the first differential input unit is connected to the first input signal VISEN_IN through the second switch S2 or to the second input signal VBUFA through the first switch S1; the first terminal of the first amplification path is coupled to the first terminal of the first differential input unit; the first terminal of the second amplification path is coupled to the second terminal of the first differential input unit; the second terminal of the second amplification path is coupled to the first bias terminal of the first amplification output unit and the output terminal of the first offset voltage cancellation unit 12, respectively; the third terminal of the first differential input unit is coupled to the input terminal of the first bias unit, and the bias terminal of the first bias unit and the second bias terminal of the first amplification output unit are both connected to a bias voltage; the output terminal of the first amplification output unit serves as the output terminal of the first operational amplification unit 11.

[0080] like Figure 4As shown, the first differential input unit includes a third NMOS transistor NM3 and a fourth NMOS transistor NM4. The gates of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 serve as the non-inverting and inverting input terminals of the first differential input unit, respectively. The drain of the third NMOS transistor NM3 serves as the second terminal of the first differential input unit, and the drain of the fourth NMOS transistor NM4 serves as the first terminal of the first differential input unit. The source of the third NMOS transistor NM3 serves as the third terminal of the first differential input unit and is coupled to the source of the fourth NMOS transistor NM4. Specifically, theoretically, when the first operational amplifier unit 11 completes the feedback connection, due to the virtual short principle, the gate voltage of the third NMOS transistor NM3 is equal to the gate voltage of the fourth NMOS transistor NM4. Therefore, the first input signal VISEN_IN applied to the third NMOS transistor NM3 is equal to the second input signal VBUFA applied to the fourth NMOS transistor NM4. However, because there is an offset voltage at the gate of the fourth NMOS transistor NM4, when the gate voltage of the third NMOS transistor NM3 is equal to the gate voltage of the fourth NMOS transistor NM4, the first input signal VISEN_IN is not equal to the second input signal VBUFA, but is equal to the sum of the offset voltage and the second input signal VBUFA. Eliminating the offset voltage and making the first input signal VISEN_IN equal to the second input signal VBUFA is one of the objectives of this embodiment.

[0081] like Figure 4 As shown, the first bias unit includes a fifth NMOS transistor NM5; the gate of the fifth NMOS transistor NM5 is connected to the bias voltage, the drain of the fifth NMOS transistor NM5 serves as the input terminal of the first bias unit, and the source of the fifth NMOS transistor NM5 is grounded.

[0082] like Figure 4 As shown, the first amplification path includes a second PMOS transistor PM2, a third PMOS transistor PM3, and a sixth NMOS transistor NM6; the second amplification path includes a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, and a seventh NMOS transistor NM7.

[0083] The gate of the second PMOS transistor PM2 is coupled to the gate of the fourth PMOS transistor PM4. The gate of the second PMOS transistor PM2 is also coupled to the drain of the third PMOS transistor PM3. The drain of the second PMOS transistor PM2 serves as the first terminal of the first amplification path and is coupled to the source of the third PMOS transistor PM3. The sources of the second PMOS transistor PM2 and the fourth PMOS transistor PM4 are both coupled to the power supply voltage VCS. The gate of the third PMOS transistor PM3 is coupled to the gate of the fifth PMOS transistor PM5. The drain of the third PMOS transistor PM3 is coupled to the drain of the sixth NMOS transistor NM6. The gate of the sixth NMOS transistor NM6 is connected to the bias voltage and coupled to the gate of the seventh NMOS transistor NM7. The sources of the sixth NMOS transistor NM6 and the seventh NMOS transistor NM7 are both grounded.

[0084] The drain of the fourth PMOS transistor PM4 serves as the first terminal of the second amplification path and is coupled to the source of the fifth PMOS transistor PM5; the drain of the fifth PMOS transistor PM5 serves as the second terminal of the second amplification path and is coupled to the drain of the seventh NMOS transistor NM7.

[0085] like Figure 4 As shown, the first amplification output unit includes a sixth PMOS transistor PM6 and an eighth NMOS transistor NM8; the gate of the sixth PMOS transistor PM6 serves as the first bias terminal of the first amplification output unit, the source of the sixth PMOS transistor PM6 is coupled to the power supply voltage VCS, and the drain of the sixth PMOS transistor PM6 serves as the output terminal of the first amplification output unit and is coupled to the drain of the eighth NMOS transistor NM8; the gate of the eighth NMOS transistor NM8 serves as the second bias terminal of the first amplification output unit, and the source of the eighth NMOS transistor NM8 is grounded.

[0086] like Figure 4As shown, in one specific embodiment, the second offset voltage cancellation unit 22 includes a second capacitor C2, a seventh PMOS transistor PM7, a third resistor R3, a ninth NMOS transistor NM9, and a tenth NMOS transistor NM10; the first end of the second capacitor C2 is coupled to the gate of the seventh PMOS transistor PM7 and serves as the input terminal of the second offset voltage cancellation unit 22, and the second end of the second capacitor C2 and the second end of the third resistor R3 are both coupled to the power supply voltage VCS; the source of the seventh PMOS transistor PM7 is coupled to the first end of the third resistor R3, and the drain of the seventh PMOS transistor PM7 is coupled to the drain of the ninth NMOS transistor NM9; the gate of the ninth NMOS transistor NM9 is coupled to its own drain and coupled to the gate of the tenth NMOS transistor NM10, the drain of the tenth NMOS transistor NM10 serves as the output terminal of the second offset voltage cancellation unit 22, and the sources of the tenth NMOS transistor NM10 and the ninth NMOS transistor NM9 are both grounded. The working principle of the second offset voltage elimination unit 22 is the same as that of the first offset voltage elimination unit, and will not be described again here.

[0087] In one specific implementation, the second operational amplifier unit 21 includes a second differential input unit, a third amplification path, a fourth amplification path, a second amplification output unit, and a second bias unit;

[0088] The non-inverting input terminal of the second differential input unit is connected to the first input signal VISEN_IN, and the inverting input terminal of the second differential input unit is connected to the first input signal VISEN_IN through the fifth switch S5 or to the second input signal VBUFA through the fourth switch S4; the first terminal of the third amplification path is coupled to the second terminal of the second differential input unit; the first terminal of the fourth amplification path is coupled to the first terminal of the second differential input unit; the second terminal of the fourth amplification path is coupled to the first bias terminal of the second amplification output unit and the output terminal of the second offset voltage cancellation unit 22, respectively; the third terminal of the second differential input unit is coupled to the input terminal of the second bias unit, and the bias terminal of the second bias unit and the second bias terminal of the second amplification output unit are both connected to a bias voltage; the output terminal of the second amplification output unit serves as the output terminal of the second operational amplification unit 21.

[0089] like Figure 4As shown, the second differential input unit includes an eleventh NMOS transistor NM11 and a twelfth NMOS transistor NM12. The gates of the eleventh NMOS transistor NM11 and the twelfth NMOS transistor NM12 serve as the non-inverting and inverting input terminals of the second differential input unit, respectively. The drain of the eleventh NMOS transistor NM11 serves as the second terminal of the second differential input unit, and the drain of the twelfth NMOS transistor NM12 serves as the first terminal of the second differential input unit. The source of the eleventh NMOS transistor NM11 serves as the third terminal of the second differential input unit and is coupled to the source of the twelfth NMOS transistor NM12. The offset voltage problem between the non-inverting and inverting input terminals of the second differential input unit is the same as that of the first differential input unit and will not be described again here.

[0090] like Figure 4 As shown, the second bias unit includes a fifteenth NMOS transistor NM15; the gate of the fifteenth NMOS transistor NM15 is connected to the bias voltage, the drain of the fifteenth NMOS transistor NM15 serves as the input terminal of the second bias unit, and the source of the fifteenth NMOS transistor NM15 is grounded.

[0091] like Figure 4 As shown, the third amplification path includes the eighth PMOS transistor PM8, the ninth PMOS transistor PM9, and the thirteenth NMOS transistor NM13; the fourth amplification path includes the tenth PMOS transistor PM10, the eleventh PMOS transistor PM11, and the fourteenth NMOS transistor NM14.

[0092] The gate of the eighth PMOS transistor PM8 is coupled to the gate of the tenth PMOS transistor PM10. The gate of the eighth PMOS transistor PM8 is also coupled to the drain of the ninth PMOS transistor PM9. The drain of the eighth PMOS transistor PM8 serves as the third terminal of the third amplification path and is coupled to the source of the ninth PMOS transistor PM9. The sources of the eighth PMOS transistor PM8 and the tenth PMOS transistor PM10 are both coupled to the power supply voltage VCS. The gate of the ninth PMOS transistor PM9 is coupled to the gate of the eleventh PMOS transistor PM11, and the drain of the ninth PMOS transistor PM9 is coupled to the drain of the thirteenth NMOS transistor NM13. The gate of the thirteenth NMOS transistor NM13 is connected to the bias voltage and coupled to the gate of the fourteenth NMOS transistor NM14. The sources of the thirteenth NMOS transistor NM13 and the fourteenth NMOS transistor NM14 are both grounded.

[0093] The drain of the tenth PMOS transistor PM10 serves as the first terminal of the fourth amplification path and is coupled to the source of the eleventh PMOS transistor PM11; the drain of the eleventh PMOS transistor PM11 serves as the second terminal of the fourth amplification path and is coupled to the drain of the fourteenth NMOS transistor NM14.

[0094] like Figure 4 As shown, the second amplification output unit includes a twelfth PMOS transistor PM12 and a sixteenth NMOS transistor NM16; the gate of the twelfth PMOS transistor PM12 serves as the first bias terminal of the second amplification output unit, the source of the twelfth PMOS transistor PM12 is coupled to the power supply voltage VCS, the drain of the twelfth PMOS transistor PM12 serves as the output terminal of the second amplification output unit and is coupled to the drain of the sixteenth NMOS transistor NM16; the gate of the sixteenth NMOS transistor NM16 serves as the second bias terminal of the second amplification output unit, and the source of the sixteenth NMOS transistor NM16 is grounded.

[0095] like Figure 4 As shown, in one specific embodiment, the first output current unit 31 includes a thirteenth PMOS transistor PM13 and a fourth resistor R4; the gate of the thirteenth PMOS transistor PM13 serves as the control terminal of the first output current unit 31, the source of the thirteenth PMOS transistor PM13 is coupled to the first terminal of the fourth resistor R4, and the drain of the thirteenth PMOS transistor PM13 serves as the output terminal of the first output current unit 31; the first and second terminals of the fourth resistor R4 are respectively connected to the second input signal VBUFA and the power supply voltage VCS.

[0096] like Figure 4 As shown, in one specific embodiment, the second output current unit 32 includes a fourteenth PMOS transistor PM14 and a fifth resistor R5; the gate of the fourteenth PMOS transistor PM14 serves as the input terminal of the second output current unit 32, the source of the fourteenth PMOS transistor PM14 is coupled to the first terminal of the fifth resistor R5, and the drain of the fourteenth PMOS transistor PM14 serves as the output terminal of the second output current unit 32; the first and second terminals of the fifth resistor R5 are respectively connected to the second input signal VBUFA and the power supply voltage VCS.

[0097] Please refer to Figure 4 and Figure 5In one specific implementation, the voltage output module 30 further includes a switch array; the switch array includes a fifteenth PMOS transistor PM15, a sixteenth PMOS transistor PM16, a seventeenth PMOS transistor PM17, an eighteenth PMOS transistor PM18, a nineteenth PMOS transistor PM19, and a twentieth PMOS transistor PM20;

[0098] The gate of the fifteenth PMOS transistor PM15 is connected to the first control signal A2L. The source of the fifteenth PMOS transistor PM15 is coupled to the output terminal of the first output current unit 31. The drain of the fifteenth PMOS transistor PM15 is coupled to the source of the seventeenth PMOS transistor PM17 and the source of the eighteenth PMOS transistor PM18, respectively. The drain of the seventeenth PMOS transistor PM17 is grounded. The drain of the eighteenth PMOS transistor PM18 is coupled to the first terminal of the first resistor R1. The gates of the seventeenth PMOS transistor PM17 and the eighteenth PMOS transistor PM18 are connected to the second control signal AH and the third control signal AL, respectively.

[0099] The gate of the sixteenth PMOS transistor PM16 is connected to the fourth control signal B2L. The source of the sixteenth PMOS transistor PM16 is coupled to the output terminal of the second output current unit 32. The drain of the sixteenth PMOS transistor PM16 is coupled to the source of the nineteenth PMOS transistor PM19 and the source of the twentieth PMOS transistor PM20, respectively. The drain of the nineteenth PMOS transistor PM19 is grounded. The drain of the twentieth PMOS transistor PM20 is coupled to the first terminal of the first resistor R1. The gates of the nineteenth PMOS transistor PM19 and the twentieth PMOS transistor PM20 are connected to the fifth control signal BH and the sixth control signal BL, respectively.

[0100] Specifically, if the first operational amplifier module 10 is in the offset voltage storage stage or the offset voltage elimination stage, and the second operational amplifier module 20 is in the normal operation stage, then the first control signal A2L is high or low, the fourth control signal B2L is low, the second control signal AH is low, the third control signal AL is high, the fifth control signal BH is high, and the sixth control signal BL is low. Specifically: if the first operational amplifier module 10 is in the offset voltage storage stage, then the first control signal A2L is high to turn off the fifteenth PMOS transistor PM15. If the first operational amplifier module 10 is in the offset voltage elimination stage, then the first control signal A2L is low to turn on the fifteenth PMOS transistor PM15.

[0101] If the second operational amplifier module 20 is in the offset voltage storage stage or the offset voltage elimination stage, and the first operational amplifier module 10 is in the normal operation stage, then the fourth control signal B2L is high or low, the first control signal A2L is low, the fifth control signal BH is low, the sixth control signal BL is high, the second control signal AH is high, and the third control signal AL is low. Specifically: if the second operational amplifier module 20 is in the offset voltage storage stage, then the fourth control signal B2L is high to turn off the sixteenth PMOS transistor PM16. If the second operational amplifier module 20 is in the offset voltage elimination stage, then the fourth control signal B2L is low to turn on the sixteenth PMOS transistor PM16.

[0102] It should be noted that when high precision is not required, the circuit cost can be reduced by omitting the fifteenth PMOS transistor PM15 and the sixteenth PMOS transistor PM16. Of course, the specific choice can be made according to the requirements, and no limitation is made here.

[0103] like Figure 4 and Figure 5 As shown, in a supplementary embodiment, the second switch S2 and the third switch S3 are both controlled by the seventh control signal A1H, the first switch S1 and the seventh switch S7 are both controlled by the eighth control signal A2H; the fifth switch S5 and the sixth switch S6 are both controlled by the ninth control signal B1H, and the fourth switch S4 and the eighth switch S8 are both controlled by the tenth control signal B2H.

[0104] Wherein, the second control signal AH is the inverted signal of the third control signal AL; and the fifth control signal BH is the inverted signal of the sixth control signal BL.

[0105] The second control signal AH and the fifth control signal BH are also two-phase non-overlapping signals; the seventh control signal A1H and the eighth control signal A2H are two-phase non-overlapping signals; the ninth control signal B1H and the tenth control signal B2H are also two-phase non-overlapping signals. Its beneficial effect is that it can avoid errors caused by accidental charge loss due to simultaneous switching on.

[0106] Specifically, the first switch S1 to the eighth switch S8 include a switching structure composed of NMOS transistors and PMOS transistors connected in parallel. The source of the NMOS transistor is connected to the drain of the PMOS transistor, and the drain of the NMOS transistor is connected to the source of the PMOS transistor. The gates of the NMOS transistor and the PMOS transistor are respectively connected to a pair of signals with opposite phases. For example, if the gate of the NMOS transistor is connected to a high level, the gate of the parallel PMOS transistor is connected to a low level; if the gate of the NMOS transistor is connected to a low level, the gate of the parallel PMOS transistor is connected to a high level. Its beneficial effect is that it improves the accuracy of switching at different stages, thereby improving the accuracy of offset voltage elimination. Of course, in addition to the switching structure composed of NMOS transistors and PMOS transistors connected in parallel, it can also include a single NMOS transistor, a single PMOS transistor, or other circuit devices with switching functions. The specific switching structure can be selected according to actual needs and is not limited here.

[0107] Please refer to Figure 4 and Figure 5 The following describes the operation of the low offset voltage operational amplifier provided in the first embodiment:

[0108] First, the first operational amplifier module 10 enters the offset voltage storage stage, and the second operational amplifier module 20 enters the normal operation stage. The second switch S2 and the third switch S3 are both turned on, while the first switch S1 and the seventh switch S7 are both turned off. The fourth switch S4 and the eighth switch S8 are both turned on, while the fifth switch S5 and the sixth switch S6 are both turned off. It should be noted that since the second operational amplifier module 20 has not yet undergone the offset voltage storage and offset voltage elimination stages, it is still affected by the offset voltage during normal operation. At this time, the voltage output by the first operational amplifier unit 11 acts on the gate of the first capacitor C1 and the first PMOS transistor PM1. This charges the first capacitor C1 and generates a source-drain current in the first PMOS transistor PM1. This source current flows through the first NMOS transistor NM1 and is proportionally mirrored to the second NMOS transistor NM2 by the current mirror structure formed by the first NMOS transistor NM1 and the second NMOS transistor NM2, thereby generating the first offset compensation current. At this time, the current formulas flowing through the second PMOS transistor PM2 and the fourth PMOS transistor PM4 are respectively:

[0109] I DNM6 +I DNM4 =I DPM2 (2)

[0110] I DNM7 +I DNM2 +IDNM3 =I DPM4 (3)

[0111] I DPM1 =I DPM2 (4)

[0112] Among them, I DPM2 Used to characterize the current flowing through the second PMOS transistor PM2; I DPM4 Used to characterize the current flowing through the fourth PMOS transistor PM4; I DNM6 Used to characterize the current flowing through the sixth NMOS transistor NM6; I DNM7 Used to characterize the current flowing through the seventh NMOS transistor NM7; I DNM3 Used to characterize the current flowing through the third NMOS transistor NM3; I DNM4 Used to characterize the current flowing through the fourth NMOS transistor NM4; I DNM2 Used to characterize the first offset compensation current.

[0113] Meanwhile, the gate voltage formulas for the third NMOS transistor NM3 and the fourth NMOS transistor NM4 are as follows:

[0114] V G2 =V ISEV_IN (5)

[0115] V G3 =V os1 +V ISEN_IN (6)

[0116] Among them, V G2 Used to characterize the gate voltage of the third NMOS transistor NM3; V G3 Used to characterize the gate voltage of the fourth NMOS transistor NM4; V ISEN_IN Used to characterize the first input signal VISEN_IN; V os1 Used to characterize the offset voltage.

[0117] The formulas for the current flowing through the third NMOS transistor NM3 and the formulas for the current flowing through the fourth NMOS transistor NM4 are as follows:

[0118]

[0119]

[0120] Among them; V s Used to characterize the source voltages of the third NMOS transistor NM3 and the fourth NMOS transistor NM4; V thThe threshold voltages used to characterize the third NMOS transistor NM3 and the fourth NMOS transistor NM4.

[0121] Next, after the first operational amplifier module 10 enters the offset voltage elimination stage, the second operational amplifier module 20 still operates in the normal operation stage. The second switch S2 and the third switch S3 are both off, while the first switch S1 and the seventh switch S7 are both on; the fourth switch S4 and the eighth switch S8 remain on, and the fifth switch S5 and the sixth switch S6 remain off. Due to the off state of the third switch S3 and the on state of the seventh switch S7, the output voltage of the first operational amplifier unit 11 no longer acts on the gate of the first PMOS transistor PM1, but instead acts on the gate of the thirteenth PMOS transistor PM13. At this time, the voltage stored in the first capacitor C1 is equal to the output voltage of the first operational amplifier unit 11 during the offset voltage storage stage. Since the capacitor voltage does not change abruptly, the gate voltage acting on the first PMOS transistor PM1 will not change, the current flowing through the first PMOS transistor PM1 will not change, and consequently, the first offset compensation current will not change. If the first offset compensation current remains unchanged, and the currents flowing through the second PMOS transistor PM2, the fourth PMOS transistor PM4, the sixth NMOS transistor NM6, and the seventh NMOS transistor NM7 also remain unchanged, then according to formulas (2) and (3) above, the currents flowing through the third NMOS transistor NM3 and the fourth NMOS transistor NM4 also remain unchanged. If the currents flowing through the third NMOS transistor NM3 and the fourth NMOS transistor NM4 also remain unchanged, then according to formulas (7) and (8) above, the gate voltages of the third NMOS transistor NM3 and the fourth NMOS transistor NM4 will also not change. In this case, the formula for the gate voltage of the fourth NMOS transistor NM4 is:

[0122] V G3 '=V os1 +V BUFA (9)

[0123] Among them, V BUFA Used to characterize the second input signal VBUFA.

[0124] Since formula (9) equals formula (8), the first input signal VISEN_IN equals the second input signal VBUFA. Therefore, the second input signal VBUFA connected to the first terminal of the fourth resistor R4 is equivalent to the first input signal VISEN_IN, so that the input signal of the first operational amplifier module 10 equals the output signal. That is, the formula for the first output current flowing through the fourth resistor R4 is:

[0125]

[0126] Simultaneously, during this stage, the second control signal AH and the fifth control signal BH are at low and high levels, respectively. Since the second control signal AH and the third control signal AL are inverted signals, and the fifth control signal BH and the sixth control signal BL are inverted signals, the seventeenth PMOS transistor PM17 and the twentieth PMOS transistor PM20 are both turned on, while the eighteenth PMOS transistor PM18 and the nineteenth PMOS transistor PM19 are both turned off. The first output current flowing through the fourth resistor R4 flows to ground, and the second output current flowing through the fifth resistor R5 flows to the first resistor R1 to generate the second output voltage and output it.

[0127] Next, the first operational amplifier module 10 enters the normal operation stage, and the second operational amplifier module 20 enters the offset voltage storage stage. The second switch S2 and the third switch S3 remain off, while the first switch S1 and the seventh switch S7 remain on; the fourth switch S4 and the eighth switch S8 are both off, and the fifth switch S5 and the sixth switch S6 are both on. Since the circuit structure of the second operational amplifier module 20 is the same as that of the first operational amplifier module 10, the operating principle of the second operational amplifier module 20 in the offset voltage storage stage is the same as that of the first operational amplifier module 10, and will not be described again here.

[0128] Finally, while the first operational amplifier module 10 remains in its normal operating phase, the second operational amplifier module 20 enters the offset voltage elimination phase. The second switch S2 and the third switch S3 remain off, while the first switch S1 and the seventh switch S7 remain on; the fourth switch S4 and the eighth switch S8 are on, and the fifth switch S5 and the sixth switch S6 are off. Since the circuit structure of the second operational amplifier module 20 is the same as that of the first operational amplifier module 10, the operating principle of the second operational amplifier module 20 in the offset voltage elimination phase is the same as that of the first operational amplifier module 10, and will not be described again here.

[0129] Thus, the low offset voltage operational amplifier provided in the first embodiment has completed the first cycle of its workflow. The workflow described above is then repeated continuously to ensure that the input terminal of the operational amplifier has an extremely low offset voltage in all cycles except the first half of the first cycle.

[0130] In summary, the low offset voltage operational amplifier provided in the first embodiment of the present invention, on the one hand, stores and precisely cancels the offset voltages present in the first operational amplifier unit and the second operational amplifier unit respectively through a first offset voltage cancellation unit and a second offset voltage cancellation unit, thereby eliminating the error caused by the offset voltage in the first output current unit and the second output current unit generating the first output current and the second output current unit respectively. On the other hand, by controlling the on and off of a control switch, the first operational amplifier module and the second operational amplifier module are controlled to alternately be in different operating stages. If the first operational amplifier module is in the offset voltage storage stage and the offset voltage cancellation stage in sequence, the second operational amplifier module is in the normal operating stage; if the second operational amplifier module is in the offset voltage storage stage and the offset voltage cancellation stage in sequence, the first operational amplifier module is in the normal operating stage. This ensures that the input terminal of the operational amplifier module in the normal operating state has an extremely low offset voltage in each clock cycle, thereby ensuring the continuity of offset voltage cancellation. Furthermore, as described above, the technical solution provided by the present invention is not limited by the input signal frequency during the offset voltage cancellation process, thus increasing the application scope of the present invention.

[0131] A second embodiment of the present invention provides an electronic device including an operational amplifier with low offset voltage provided in the first embodiment of the present invention.

[0132] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An operational amplifier with low offset voltage, characterized in that, include: First operational amplifier module, second operational amplifier module, voltage output module; The first operational amplifier module includes a first operational amplifier unit and a first offset voltage cancellation unit; the non-inverting input terminal of the first operational amplifier unit is connected to a first input signal, and the inverting input terminal of the first operational amplifier unit is connected to the first input signal through a second switch or to a second input signal through a first switch; The first terminal of the first operational amplifier unit is coupled to the output terminal of the first offset voltage cancellation unit; The output of the first operational amplifier unit is coupled to the input of the first offset voltage cancellation unit through a third switch, and serves as the output of the first operational amplifier module. The second operational amplifier module includes a second operational amplifier unit and a second offset voltage cancellation unit; the non-inverting input terminal of the second operational amplifier unit is connected to a first input signal, and the inverting input terminal of the second operational amplifier unit is connected to the first input signal through a fifth switch or to a second input signal through a fourth switch; The first terminal of the second operational amplifier unit is coupled to the output terminal of the second offset voltage cancellation unit; the output terminal of the second operational amplifier unit is coupled to the input terminal of the second offset voltage cancellation unit through a sixth switch, and serves as the output terminal of the second operational amplifier module. The voltage output module includes a first output current unit, a second output current unit, and a first resistor. The control terminal of the first output current unit is coupled to the output terminal of the first operational amplifier module via a seventh switch. The output terminal of the first output current unit is coupled to ground or the first terminal of the first resistor. The first and second terminals of the first output current unit are respectively coupled to the second input signal and the power supply voltage. The first output current unit generates and outputs a first output current based on the voltage output by the first operational amplifier module. The control terminal of the second output current unit is coupled to the output terminal of the second operational amplifier module via an eighth switch. The output terminal of the second output current unit is coupled to ground or the first terminal of the first resistor. The first and second terminals of the first output current unit are respectively coupled to the second input signal and the power supply voltage. The second output current unit generates and outputs a second output current based on the voltage output by the second operational amplifier module. The first terminal of the first resistor serves as the output terminal of the voltage output module, and the second terminal of the first resistor is grounded. The first resistor generates and outputs a first output voltage or a second output voltage based on the first output current or the second output current. The first output current and the second output current are the same. If the first operational amplifier module is in the offset voltage storage stage, then the second switch and the third switch are both turned on, and the first switch and the seventh switch are both turned off; the first offset voltage elimination unit is used to store the voltage output by the first operational amplifier unit, and generate a first offset compensation current and output it to the first operational amplifier unit; if the second operational amplifier module is in the offset voltage storage stage, then the fifth switch and the sixth switch are both turned on, and the fourth switch and the eighth switch are both turned off; the second offset voltage elimination unit is used to store the voltage output by the second operational amplifier unit, and generate a second offset compensation current and output it to the second operational amplifier unit; If the first operational amplifier module is in the offset voltage elimination stage, then the second and third switches are both off, and the first and seventh switches are both on; the first offset voltage elimination unit is used to maintain the first offset compensation current according to the stored voltage, so that the first input signal is equal to the second input signal; the output terminal of the first output current unit is coupled to ground; if the second operational amplifier module is in the offset voltage elimination stage, then the fifth and sixth switches are both off, and the fourth and eighth switches are both on; the second offset voltage elimination unit is used to maintain the second offset compensation current according to the stored voltage, so that the first input signal is equal to the second input signal; the output terminal of the second output current unit is coupled to ground. If the first operational amplifier module is in normal operation, the second and third switches are still off, and the first and seventh switches are still on; the output terminal of the first output current unit is coupled to the first terminal of the first resistor; if the second operational amplifier module is in normal operation, the fourth and eighth switches are still on, and the fifth and sixth switches are still off; the output terminal of the second output current unit is coupled to the first terminal of the first resistor. If the first operational amplifier module is sequentially in the offset voltage storage stage and the offset voltage elimination stage, then the second operational amplifier module is in the normal operation stage; if the second operational amplifier module is sequentially in the offset voltage storage stage and the offset voltage elimination stage, then the first operational amplifier module is in the normal operation stage.

2. The operational amplifier with low offset voltage according to claim 1, characterized in that, The first offset voltage cancellation unit includes a first capacitor, a first PMOS transistor, a second resistor, a first NMOS transistor, and a second NMOS transistor; the first terminal of the first capacitor is coupled to the gate of the first PMOS transistor and serves as the input terminal of the first offset voltage cancellation unit, and the second terminals of the first capacitor and the second resistor are both coupled to the power supply voltage; the source of the first PMOS transistor is coupled to the first terminal of the second resistor, and the drain of the first PMOS transistor is coupled to the drain of the first NMOS transistor; The gate of the first NMOS transistor is coupled to its own drain and to the gate of the second NMOS transistor. The drain of the second NMOS transistor serves as the output terminal of the first offset voltage cancellation unit. The sources of the second NMOS transistor and the first NMOS transistor are both grounded.

3. The operational amplifier with low offset voltage according to claim 2, characterized in that, The first operational amplifier unit includes a first differential input unit, a first amplification path, a second amplification path, a first amplification output unit, and a first bias unit; The non-inverting input terminal of the first differential input unit is connected to a first input signal, and the inverting input terminal of the first differential input unit is connected to the first input signal via a second switch or to a second input signal via a first switch; the first terminal of the first amplification path is coupled to the first terminal of the first differential input unit; the first terminal of the second amplification path is coupled to the second terminal of the first differential input unit; the second terminal of the second amplification path is coupled to the first bias terminal of the first amplification output unit and the output terminal of the first offset voltage cancellation unit, respectively. The third terminal of the first differential input unit is coupled to the input terminal of the first bias unit, and the bias terminal of the first bias unit and the second bias terminal of the first amplified output unit are both connected to a bias voltage. The output terminal of the first amplification output unit serves as the output terminal of the first operational amplification unit.

4. The operational amplifier with low offset voltage according to claim 3, characterized in that, The first differential input unit includes a third NMOS transistor and a fourth NMOS transistor; the gate of the third NMOS transistor and the gate of the fourth NMOS transistor serve as the non-inverting input terminal and the inverting input terminal of the first differential input unit, respectively; the drain of the third NMOS transistor serves as the second terminal of the first differential input unit; and the drain of the fourth NMOS transistor serves as the first terminal of the first differential input unit; the source of the third NMOS transistor serves as the third terminal of the first differential input unit and is coupled to the source of the fourth NMOS transistor.

5. The operational amplifier with low offset voltage according to claim 3, characterized in that, The first bias unit includes a fifth NMOS transistor; the gate of the fifth NMOS transistor is connected to the bias voltage, the drain of the fifth NMOS transistor serves as the input terminal of the first bias unit, and the source of the fifth NMOS transistor is grounded.

6. The operational amplifier with low offset voltage according to claim 3, characterized in that, The first amplification path includes a second PMOS transistor, a third PMOS transistor, and a sixth NMOS transistor; the second amplification path includes a fourth PMOS transistor, a fifth PMOS transistor, and a seventh NMOS transistor. The gate of the second PMOS transistor is coupled to the gate of the fourth PMOS transistor, and the gate of the second PMOS transistor is also coupled to the drain of the third PMOS transistor. The drain of the second PMOS transistor serves as the first terminal of the first amplification path and is coupled to the source of the third PMOS transistor. The sources of the second PMOS transistor and the fourth PMOS transistor are both coupled to the power supply voltage. The gate of the third PMOS transistor is coupled to the gate of the fifth PMOS transistor, and the drain of the third PMOS transistor is coupled to the drain of the sixth NMOS transistor. The gate of the sixth NMOS transistor is connected to the bias voltage and coupled to the gate of the seventh NMOS transistor. The sources of the sixth NMOS transistor and the seventh NMOS transistor are both grounded. The drain of the fourth PMOS transistor serves as the first terminal of the second amplification path and is coupled to the source of the fifth PMOS transistor; the drain of the fifth PMOS transistor serves as the second terminal of the second amplification path and is coupled to the drain of the seventh NMOS transistor.

7. The operational amplifier with low offset voltage according to claim 3, characterized in that, The first amplification output unit includes a sixth PMOS transistor and an eighth NMOS transistor; the gate of the sixth PMOS transistor serves as the first bias terminal of the first amplification output unit, the source of the sixth PMOS transistor is coupled to the power supply voltage, the drain of the sixth PMOS transistor serves as the output terminal of the first amplification output unit and is coupled to the drain of the eighth NMOS transistor; the gate of the eighth NMOS transistor serves as the second bias terminal of the first amplification output unit, and the source of the eighth NMOS transistor is grounded.

8. The operational amplifier with low offset voltage according to claim 1, characterized in that, The second offset voltage cancellation unit includes a second capacitor, a seventh PMOS transistor, a third resistor, a ninth NMOS transistor, and a tenth NMOS transistor; the first terminal of the second capacitor is coupled to the gate of the seventh PMOS transistor and serves as the input terminal of the second offset voltage cancellation unit; the second terminal of the second capacitor and the second terminal of the third resistor are both coupled to the power supply voltage; the source of the seventh PMOS transistor is coupled to the first terminal of the third resistor, and the drain of the seventh PMOS transistor is coupled to the drain of the ninth NMOS transistor; The gate of the ninth NMOS transistor is coupled to its own drain and to the gate of the tenth NMOS transistor. The drain of the tenth NMOS transistor serves as the output terminal of the second offset voltage cancellation unit. The sources of the tenth NMOS transistor and the ninth NMOS transistor are both grounded.

9. The operational amplifier with low offset voltage according to claim 8, characterized in that, The second operational amplifier unit includes a second differential input unit, a third amplification path, a fourth amplification path, a second amplification output unit, and a second bias unit; The non-inverting input terminal of the second differential input unit is connected to the first input signal, and the inverting input terminal of the second differential input unit is connected to the first input signal via a fifth switch or to the second input signal via a fourth switch; the first terminal of the third amplification path is coupled to the second terminal of the second differential input unit; the first terminal of the fourth amplification path is coupled to the first terminal of the second differential input unit; the second terminal of the fourth amplification path is coupled to the first bias terminal of the second amplification output unit and the output terminal of the second offset voltage cancellation unit, respectively. The third terminal of the second differential input unit is coupled to the input terminal of the second bias unit, and the bias terminal of the second bias unit and the second bias terminal of the second amplification output unit are both connected to a bias voltage. The output terminal of the second amplification output unit serves as the output terminal of the second operational amplification unit.

10. The operational amplifier with low offset voltage according to claim 9, characterized in that, The second differential input unit includes an eleventh NMOS transistor and a twelfth NMOS transistor; the gate of the eleventh NMOS transistor and the gate of the twelfth NMOS transistor serve as the non-inverting input terminal and the inverting input terminal of the second differential input unit, respectively; the drain of the eleventh NMOS transistor serves as the second terminal of the second differential input unit; and the drain of the twelfth NMOS transistor serves as the first terminal of the second differential input unit. The source of the eleventh NMOS transistor serves as the third terminal of the second differential input unit and is coupled to the source of the twelfth NMOS transistor.

11. The operational amplifier with low offset voltage according to claim 9, characterized in that, The second bias unit includes a fifteenth NMOS transistor; the gate of the fifteenth NMOS transistor is connected to the bias voltage, the drain of the fifteenth NMOS transistor serves as the input terminal of the second bias unit, and the source of the fifteenth NMOS transistor is grounded.

12. The operational amplifier with low offset voltage according to claim 9, characterized in that, The third amplification path includes the eighth PMOS transistor, the ninth PMOS transistor, and the thirteenth NMOS transistor; the fourth amplification path includes the tenth PMOS transistor, the eleventh PMOS transistor, and the fourteenth NMOS transistor. The gate of the eighth PMOS transistor is coupled to the gate of the tenth PMOS transistor, and the gate of the eighth PMOS transistor is also coupled to the drain of the ninth PMOS transistor. The drain of the eighth PMOS transistor serves as the third terminal of the third amplification path and is coupled to the source of the ninth PMOS transistor. The sources of the eighth PMOS transistor and the tenth PMOS transistor are both coupled to the power supply voltage. The gate of the ninth PMOS transistor is coupled to the gate of the eleventh PMOS transistor, and the drain of the ninth PMOS transistor is coupled to the drain of the thirteenth NMOS transistor. The gate of the thirteenth NMOS transistor is connected to the bias voltage and coupled to the gate of the fourteenth NMOS transistor. The sources of the thirteenth NMOS transistor and the fourteenth NMOS transistor are both grounded. The drain of the tenth PMOS transistor serves as the first terminal of the fourth amplification path and is coupled to the source of the eleventh PMOS transistor; the drain of the eleventh PMOS transistor serves as the second terminal of the fourth amplification path and is coupled to the drain of the fourteenth NMOS transistor.

13. The operational amplifier with low offset voltage according to claim 9, characterized in that, The second amplification output unit includes a twelfth PMOS transistor and a sixteenth NMOS transistor; the gate of the twelfth PMOS transistor serves as the first bias terminal of the second amplification output unit, the source of the twelfth PMOS transistor is coupled to the power supply voltage, and the drain of the twelfth PMOS transistor serves as the output terminal of the second amplification output unit and is coupled to the drain of the sixteenth NMOS transistor. The gate of the sixteenth NMOS transistor serves as the second bias terminal of the second amplification output unit, and the source of the sixteenth NMOS transistor is grounded.

14. The operational amplifier with low offset voltage according to claim 2, characterized in that, The first output current unit includes a thirteenth PMOS transistor and a fourth resistor; the gate of the thirteenth PMOS transistor serves as the control terminal of the first output current unit, the source of the thirteenth PMOS transistor is coupled to the first terminal of the fourth resistor, and the drain of the thirteenth PMOS transistor serves as the output terminal of the first output current unit; the first terminal and the second terminal of the fourth resistor are respectively connected to the second input signal and the power supply voltage.

15. The operational amplifier with low offset voltage according to claim 14, characterized in that, The second output current unit includes a fourteenth PMOS transistor and a fifth resistor; the gate of the fourteenth PMOS transistor serves as the input terminal of the second output current unit, the source of the fourteenth PMOS transistor is coupled to the first terminal of the fifth resistor, and the drain of the fourteenth PMOS transistor serves as the output terminal of the second output current unit; the first and second terminals of the fifth resistor are respectively connected to the second input signal and the power supply voltage.

16. The operational amplifier with low offset voltage according to claim 15, characterized in that, It also includes a switch array; the switch array includes a fifteenth PMOS transistor, a sixteenth PMOS transistor, a seventeenth PMOS transistor, an eighteenth PMOS transistor, a nineteenth PMOS transistor, and a twentieth PMOS transistor; The gate of the fifteenth PMOS transistor is connected to the first control signal, the source of the fifteenth PMOS transistor is coupled to the output terminal of the first output current unit, and the drain of the fifteenth PMOS transistor is coupled to the source of the seventeenth PMOS transistor and the source of the eighteenth PMOS transistor respectively. The drain of the seventeenth PMOS transistor is grounded, the drain of the eighteenth PMOS transistor is coupled to the first end of the first resistor, and the gates of the seventeenth PMOS transistor and the eighteenth PMOS transistor are respectively connected to the second control signal and the third control signal. The gate of the sixteenth PMOS transistor is connected to the fourth control signal, the source of the sixteenth PMOS transistor is coupled to the output terminal of the second output current unit, and the drain of the sixteenth PMOS transistor is coupled to the source of the nineteenth PMOS transistor and the source of the twentieth PMOS transistor, respectively; the drain of the nineteenth PMOS transistor is grounded, the drain of the twentieth PMOS transistor is coupled to the first terminal of the first resistor, and the gates of the nineteenth PMOS transistor and the twentieth PMOS transistor are connected to the fifth control signal and the sixth control signal, respectively. Wherein, if the first operational amplifier module is in the offset voltage storage stage or the offset voltage elimination stage, and the second operational amplifier module is in the normal operation stage, then the first control signal is high level or low level, the fourth control signal is low level, the second control signal is low level, the third control signal is high level, the fifth control signal is high level, and the sixth control signal is low level; If the second operational amplifier module is in the offset voltage storage stage or the offset voltage elimination stage, and the first operational amplifier module is in the normal operation stage, then the fourth control signal is high or low, the first control signal is low, the fifth control signal is low, the sixth control signal is high, the second control signal is high, and the third control signal is low.

17. The operational amplifier with low offset voltage according to claim 16, characterized in that, The second control signal and the fifth control signal are two-phase non-overlapping signals; the second control signal is the inverted signal of the third control signal; and the fifth control signal is the inverted signal of the sixth control signal.

18. The operational amplifier with low offset voltage according to claim 17, characterized in that, It also includes a sixth resistor; the sixth resistor is coupled between the drain and ground of the seventeenth PMOS transistor; wherein the resistance value of the sixth resistor is equal to the resistance value of the first resistor.

19. An electronic device, characterized in that, The operational amplifier includes the low offset voltage as described in any one of claims 1 to 18.

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