Pin multiplexing circuit and network device
By designing a pin multiplexing circuit, the processor switches signals to the target function pins of the logic device, solving the problem of resource waste and wiring pressure caused by the number of logic device pins. This achieves cost optimization and reduces wiring pressure, while improving the flexibility and programmability of the circuit.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INSPUR SUZHOU INTELLIGENT TECH CO LTD
- Filing Date
- 2025-01-24
- Publication Date
- 2026-07-14
AI Technical Summary
In existing technologies, the increased number of logic device pins leads to resource waste and increased wiring pressure. This is usually solved by packaging multiple logic devices or selecting larger devices, but this increases cost and wiring complexity.
By designing a pin multiplexing circuit, the processor switches the signals of the target function pins, enabling them to transmit different functional signals in different states, thereby achieving the multiplexing of the target function pins and meeting the pin count requirements of logic devices.
It reduces the cost of using logic devices, reduces wiring pressure, improves the flexibility and programmability of circuits, and optimizes resource utilization.
Smart Images
Figure CN120034178B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of network equipment technology, and in particular to a pin multiplexing circuit and network equipment. Background Technology
[0002] Logic devices, as semi-custom integrated circuits, offer advantages such as flexible programming, fast response, and high integration, serving as a crucial hub for information exchange between upper-level systems and lower-level devices. Therefore, they are finding increasingly widespread application in various fields. However, with the increasing prevalence and functional integration of logic devices, the number of pins required also increases.
[0003] To meet the pin requirements of logic devices, related technologies generally package multiple logic devices or select larger logic devices regardless of cost, which not only wastes resources but also increases the wiring pressure of the circuit. Summary of the Invention
[0004] This application provides pin multiplexing circuits and network devices to at least solve the problems of resource waste and increased wiring pressure caused by packaging multiple logic devices or selecting larger logic devices regardless of cost in related technologies.
[0005] In a first aspect, this application provides a pin multiplexing circuit, including: a logic device, a processor, a first functional module, and a second functional module; wherein: the logic device includes a target functional pin, the first functional module includes a first functional pin corresponding to the target functional pin, and the second functional module includes a second functional pin corresponding to the target functional pin;
[0006] The first functional pin of the first functional module is connected to the first terminal of the processor, and is used to transmit the first functional signal to the processor and receive the first result data returned by the processor.
[0007] The second functional module's second functional pin is connected to the second terminal of the processor, and is used to transmit the second functional signal to the processor and receive the second result data returned by the processor.
[0008] The third terminal of the processor is connected to the control signal;
[0009] The fourth terminal of the processor is connected to the target function pin and is used to send the received first function signal to the logic device and receive the first result data returned by the logic device when the control signal is in the first state, so as to return the first result to the first function module; it is also used to send the received second function signal to the logic device and receive the second result data returned by the logic device when the control signal is in the second state, so as to return the second result to the second function module.
[0010] Secondly, this application provides a network device including any of the aforementioned pin multiplexing circuits.
[0011] The pin multiplexing circuit and network device provided in this application multiplex the target function pins, allowing them to function as either a first function pin transmitting a first function signal or a second function pin transmitting a second function signal. The processor switches the actual function signal transmitted by the target function pin based on the received control signal, thus achieving the multiplexing of the target function pins. Therefore, this satisfies the pin count requirements of logic devices, solving the problems of resource waste and increased wiring pressure caused by packaging multiple logic devices or using larger logic devices regardless of cost in related technologies. It reduces the cost of logic devices and alleviates the pressure of wiring for logic devices. Attached Figure Description
[0012] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0013] Figure 1 This is a schematic diagram of the hardware architecture for example in this application;
[0014] Figure 2 Schematic diagram of the pin multiplexing circuit provided in this application Figure 1 ;
[0015] Figure 3 Schematic diagram of the pin multiplexing circuit provided in this application Figure 2 ;
[0016] Figure 4 Schematic diagram of the pin multiplexing circuit provided in this application Figure 3 ;
[0017] Figure 5 Schematic diagram of the pin multiplexing circuit provided in this application Figure 4 ;
[0018] Figure 6 Schematic diagram of the pin multiplexing circuit provided in this application Figure 5 ;
[0019] Figure 7 Schematic diagram of the pin multiplexing circuit provided in this application Figure 6 ;
[0020] Figure 8 Schematic diagram of the pin multiplexing circuit provided in this application Figure 7 ;
[0021] Figure 9 Schematic diagram of the pin multiplexing circuit provided in this application Figure 8 ;
[0022] Figure 10 Schematic diagram of the pin multiplexing circuit provided in this application Figure 9 .
[0023] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation
[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.
[0025] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.
[0026] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0027] Logic devices serve as crucial hubs for information exchange between upper-level systems and lower-level devices, finding increasingly widespread applications across various fields. However, with the proliferation of logic devices and their increasing functional integration, the number of pins required by these devices also grows. To meet the pin requirements, related technologies typically involve packaging multiple logic devices or selecting larger devices regardless of cost, resulting in resource waste and increased circuit wiring complexity.
[0028] Figure 1 This is a schematic diagram of the hardware architecture for example in this application, such as Figure 1As shown, the pin multiplexing circuit provided in this application mainly includes four parts: a logic device, a processing device, a first functional module, and a second functional module. The logic device can be mounted on a circuit board as chip 1, the processing device can be mounted on a circuit board as chip 2, the first functional module can be integrated on chip 3 and chip 3 can be mounted on a circuit board, and the second functional module can be integrated on chip 4 and chip 4 can be mounted on a circuit board. Chip 1 and chip 2 are connected via target functional pins, chip 2 and chip 3 are connected via the first functional pin, and chip 2 and chip 4 are connected via the second functional pin.
[0029] Depend on Figure 1 It can be seen that the processor can receive the first functional signal sent by the first functional module and the second functional signal sent by the second functional module. The processor switches between the first functional signal and the second functional signal so that the processor can transmit the first functional signal or the second functional signal to the logic device, thus realizing the multiplexing of the target functional pin.
[0030] Figure 2 Schematic diagram of the pin multiplexing circuit provided in this application Figure 1 ,like Figure 2 As shown, it includes: a logic device, a processor, a first functional module, and a second functional module; wherein: the logic device includes a target functional pin, the first functional module includes a first functional pin corresponding to the target functional pin, and the second functional module includes a second functional pin corresponding to the target functional pin;
[0031] The first functional pin of the first functional module is connected to the first terminal of the processor, and is used to transmit the first functional signal to the processor and receive the first result data returned by the processor.
[0032] The second functional module's second functional pin is connected to the second terminal of the processor, and is used to transmit the second functional signal to the processor and receive the second result data returned by the processor.
[0033] The third terminal of the processor is connected to the control signal;
[0034] The fourth terminal of the processor is connected to the target function pin and is used to send the received first function signal to the logic device and receive the first result data returned by the logic device when the control signal is in the first state, so as to return the first result to the first function module; it is also used to send the received second function signal to the logic device and receive the second result data returned by the logic device when the control signal is in the second state, so as to return the second result to the second function module.
[0035] Based on scenario examples, the logic functions of a logic device can be edited according to preset requirements. The logic device may include multiple functional pins, from which a target functional pin can be selected from preset functional pins, and the selected target functional pin can be multiplexed. Specifically, the functional signals that the target functional pin can transmit can be determined, such as a first functional signal and a second functional signal. Accordingly, the target functional pin can be multiplexed, serving as the first functional pin and the second functional pin, respectively. The first functional pin is used to transmit the first functional signal, and the second functional pin is used to transmit the second functional signal. The first functional signal can be a functional signal that the target functional pin could originally transmit, and the second functional signal can be a preset functional signal. The first functional signal can be output by the corresponding first functional module, and the second functional signal can be output by the corresponding second functional module.
[0036] The processor can be selected as a Microcontroller Unit (MCU). The control signal received by the processor can be a select signal, which has two states: a first state and a second state. When the processor receives a select signal in the first state, it uses the target function pin as the first function pin, receives the first function signal output by the first function module, and transmits the first function signal to the logic device. The logic device can output first result data based on the first function signal, and then the processor receives the first result data output by the logic device and transmits the first result data to the first function module. When the processor receives a select signal in the second state, it uses the target function pin as the second function pin, receives the second function signal output by the second function module, and transmits the second function signal to the logic device. The logic device can output second result data based on the second function signal, and then the processor receives the second result data output by the logic device and transmits the second result data to the second function module.
[0037] Based on the circuit provided in this example, the target function pins of the logic device can be reused to meet the pin requirements of the logic device, thereby reducing the cost of using the logic device and reducing the pressure on logic device wiring.
[0038] Optionally, the logic device is a complex programmable logic device;
[0039] Accordingly, the target function pins include joint test workgroup pins and serial peripheral interface pins.
[0040] In the scenario example, the logic device is a Complex Programmable Logic Device (CPLD). A CPLD includes various functional pins, such as the Joint Test Action Group (JTAG) pin and the Serial Peripheral Interface (SPI) pin. JTAG is primarily used for internal chip testing, while SPI is a synchronous peripheral interface that allows the microcontroller to communicate serially with various peripheral devices to exchange information.
[0041] By using the circuit provided in this example, identifying the logic device as a CPLD can improve the circuit's flexibility and programmability.
[0042] Optional, Figure 3 Schematic diagram of the pin multiplexing circuit provided in this application Figure 2 ,like Figure 3 As shown, the target function pin is the pin of the joint test group;
[0043] Accordingly, the first functional module is the upper-level system module, and the first functional signal is general information or online upgrade information; the second functional module is the offline update module, and the second functional signal is offline update information.
[0044] Based on a scenario example, when the target function pin is a JTAG pin, the multiplexing design of the JTAG pin includes three parts: connecting the CPLD's JTAG signal to the upper-level system module, connecting the CPLD's JTAG signal to the offline update module, and information interaction between the CPLD and the upper-level system. The upper-level system module includes, but is not limited to, the Baseboard Management Controller (BMC) and the Central Processing Unit (CPU). The first functional signal issued by the upper-level system module can be of two types: general information and online upgrade information. General information includes basic status information, verification information, or control information. When transmitting general information between the upper-level system module and the CPLD, the JTAG pins between the processor MCU and the upper-level system module can be defined as: Load signal, clock signal (CLK), Data-In, and Data-Out. The Load signal is used in digital circuits to control data storage and retrieval operations. It is a control signal used to indicate when to write data to or read data from a storage element (such as a flip-flop); a clock signal is a periodically changing signal used to synchronize the operation of various parts of a digital circuit, ensuring that data is processed and transmitted at the correct time; data input refers to the signal used to input data in a system; data output refers to the signal used to output data in a digital circuit design.
[0045] When the upper-level system module needs to upgrade the CPLD, the JTAG pins between the processor MCU and the upper-level system module can be defined as: Test Mode Select (TMS), Test Clock Input (TCK), Test Data Input (TDI), and Test Data Output (TDO). The offline update information output by the offline update module is used for offline updates of the CPLD. The JTAG pins between the processor MCU and the offline update module can be defined as: TMS, TCK, TDI, and TDO. TCK is used to synchronize operations on the JTAG interface. By sampling and updating data on the rising or falling edge of TCK, synchronous data transmission on the JTAG interface is achieved. TMS is used to control the JTAG state machine transitions. By inputting different values to TMS in each TCK clock cycle, the state of the JTAG state machine can be changed, thereby selecting different test or operation modes. TDI is the channel for sending data to the device under test. Test data, commands, or configuration information can be sent to the device under test (DUT) by inputting data to TDI on each clock cycle of TCK; TDO is the channel for receiving data from the DUT. By reading data from TDO on each clock cycle of TCK, test responses, status information, or output data of the DUT can be obtained. JTAG pins include multiple signal transmission paths, including a first signal transmission path defined as TMS or Load, a second signal transmission path defined as TCK or CLK, a third signal transmission path defined as TDI or Data-In, and a fourth signal transmission path defined as TDO or Data-Out.
[0046] Based on the circuit provided in this example, the multiplexing design of the JTAG pins of the CPLD can be completed.
[0047] Optional, Figure 4 Schematic diagram of the pin multiplexing circuit provided in this application Figure 3 ,like Figure 4 As shown, the complex programmable logic device also includes a first control interface;
[0048] The control terminal of the upper-level system module is connected to the first control interface of the complex programmable logic device. When the first control interface is in a low-level state, the first functional signal sent to the controller is general information, and when the first control interface is in a high-level state, the first functional signal sent to the controller is online upgrade information.
[0049] Based on the scenario example, since the upper-layer system module can output two types of first-function signals, it can determine whether the CPLD needs an upgrade, thus deciding whether to transmit general information or online upgrade information to the CPLD. Specifically, when JTAG-En at the first control interface is low, it can be determined that the CPLD does not need an upgrade, so the upper-layer system module outputs general information. Specifically, the upper-layer system module transmits the output general information to the processor through the first, second, and third signal transmission paths. The processor transmits the general information to the CPLD through the first, second, and third signal transmission paths. The CPLD returns the first processing result to the processor through the fourth signal transmission path, and the processor then returns the first processing result to the upper-layer system module through the fourth signal transmission path.
[0050] When JTAG-En at the first control interface is high, it indicates that the CPLD needs to be upgraded. Therefore, the upper-layer system module outputs online upgrade information, which can be the upgrade image information output by the upper-layer system module. Specifically, the upper-layer system module transmits the output upgrade image information to the processor through the first, second, and third signal transmission paths. The processor then transmits the upgrade image information to the CPLD through the same three paths. The CPLD returns the first processing result to the processor through the fourth signal transmission path, and the processor then returns the first processing result to the upper-layer system module through the fourth signal transmission path.
[0051] Similarly, the offline update module transmits the output offline update information to the processor through the first signal transmission path, the second signal transmission path, and the third signal transmission path. The processor then transmits the offline update information to the CPLD through the first signal transmission path, the second signal transmission path, and the third signal transmission path. The CPLD then returns the second processing result to the processor through the fourth signal transmission path. Finally, the processor returns the second processing result to the upper-level system module through the fourth signal transmission path.
[0052] Based on the circuit provided in this example, the output information can be determined by judging the status information of JTAG-En.
[0053] Optional, Figure 5 Schematic diagram of the pin multiplexing circuit provided in this application Figure 4 ,like Figure 5 As shown, the circuit also includes: a first switch module K1 and a second switch module K2;
[0054] The first terminal of the first switch module K1 is connected to a high level, and the second terminal of the first switch module K1 is grounded.
[0055] The first terminal of the second switch module K2 is connected to a high level, and the second terminal of the second switch module K2 is grounded.
[0056] The first control interface of the complex programmable logic device is connected to the second terminal of the first switch module K1. When the path between the first terminal and the second terminal of the first switch module K1 is disconnected, it is in a low-level state; when the path between the first terminal and the second terminal of the first switch module K1 is connected, it is in a high-level state.
[0057] The third terminal of the controller is connected to the second terminal of the second switch module K2. When the path between the first and second terminals of the second switch module K2 is disconnected, the received control signal is the control signal of the first state; when the path between the first and second terminals of the second switch module K2 is connected, the received control signal is the control signal of the second state.
[0058] In the scenario example, the default state of the first switch module K1 and the second switch module K2 is disconnected, meaning the path between the first and second terminals is not conductive. At this time, [the following text appears to be unrelated and possibly a separate sentence fragment: "by..."] Figure 5 It can be seen that when the path between the first and second terminals of the first switch module K1 is not connected, JTAG-En at the first control interface of the CPLD is at a low level, and when the path between the first and second terminals of the first switch module K1 is connected, JTAG-En at the first control interface of the CPLD is at a high level.
[0059] When the path between the first and second terminals of the second switch module K2 is not open, the control signal received by the MCU is low, i.e., the control signal of the first state. When the path between the first and second terminals of the second switch module K2 is open, the control signal received by the MCU is high, i.e., the control signal of the second state. Specifically, jumpers can be used to short-circuit the first and second terminals of the first switch module K1, and the first and second terminals of the second switch module K1, to achieve the connection between the first and second terminals of the first switch module K1, and the connection between the first and second terminals of the second switch module K1.
[0060] Based on the circuit provided in this example, the level state at the first control interface and the level state of the control signal received by the MCU can be controlled by the first switch module and the second switch module.
[0061] Optional, Figure 6 Schematic diagram of the pin multiplexing circuit provided in this application Figure 5 ,like Figure 6 As shown, the circuit also includes: a first resistor R1 and a second resistor R2;
[0062] The first end of the first resistor R1 is connected to the second end of the first switch module K1, and the second end of the first resistor R1 is grounded to reduce the current in the path.
[0063] The first end of the second resistor R2 is connected to the second end of the second switch module K2, and the second end of the second resistor R2 is grounded to reduce the current in the circuit.
[0064] Based on the scenario example, the resistance value of the second resistor R2 can be determined according to the actual situation. Currently, the second resistor R2 plays the role of current limiting in the circuit to prevent the circuit board from burning out due to excessive current.
[0065] Figure 7 Schematic diagram of the pin multiplexing circuit provided in this application Figure 6 ,like Figure 7 As shown, the complex programmable logic device integrates an interactive information parsing module, and the upper-level system module integrates an interactive information parsing module, a code stream control module, and an upgrade module. The interactive information parsing module is used to parse the received data, the code stream control module is used to control the transmission rate of information interaction, and the upgrade module is used to provide online upgrade information.
[0066] Based on scenario examples, pre-defined functional modules can be integrated into the CPLD and upper-layer system modules, such as an interaction information parsing module, a code stream control module, and an upgrade module. Specifically, the data exchanged between the CPLD and upper-layer system modules can be parsed by the interaction information parsing module, enabling both the CPLD and upper-layer system modules to recognize the data. The code stream control module can control the transmission rate of the upper-layer system modules, and the upgrade module can provide online upgrade information for online upgrades of the CPLD.
[0067] Optional, Figure 8 Schematic diagram of the pin multiplexing circuit provided in this application Figure 7 ,like Figure 8 As shown, the target function pin is the serial peripheral interface pin;
[0068] Accordingly, the first functional module is the Flash module, and the first functional signal is Flash information; the second functional module is the hardware status module, and the second functional signal is hardware status information.
[0069] In a scenario example, when the target function pin is an SPI pin, such as in the Flash•SPI multiplexing design, the CPLD's Flash•SPI pin is connected to an external Flash pin and a general-purpose input / output (GPIO) pin via the MCU. This involves three parts: CPLD logic design and CPLD pin function switching. This enables time-sharing access to the Flash module and hardware status module via the SPI pin. Accessing the Flash module is called Flash access, which refers to the interaction with the server-side database using Flash technology. Specifically, the Flash program sends a request to the server. Upon receiving the request, the server accesses the database to retrieve data and returns it in a specific format. The Flash program then presents this data to the user in different formats. Specifically, when the processor accesses the Flash module, it can obtain the Flash information output by the Flash module via the SPI pin and transmit it to the CPLD. The CPLD returns the first result data to the processor based on the Flash information, and the processor then returns the first result data to the Flash module via the SPI pin. When the processor accesses the hardware status module, it can obtain the hardware status information output by the hardware status module through the SPI pin and transmit the hardware status information to the CPLD. The CPLD returns the second result data to the processor based on the hardware status information, and the processor then returns the second result data to the hardware status module through the SPI pin.
[0070] The SPI pins between the MCU and the Flash module can be defined as Main Clock (MCLK), CSPIN, Master Input Slave Output (MISO), and Master Output Slave Input (MOSI). MCLK is a widely used clock signal in electronic systems, serving as the system's primary time base for synchronizing and driving the operation of various internal and external devices. The MCLK signal is typically generated by a crystal oscillator, providing a stable and accurate frequency output to ensure timing consistency across the system. MISO refers to the process in which the master receives external input data, while the slave processes this data and outputs the results to external devices. MOSI refers to the process in a communication system where the master (usually a control device) sends data or commands to the slave (usually a controlled device), and the slave receives this data or commands and executes the corresponding operations.
[0071] The hardware status module can be a general-purpose input / output (GPIO) control module. The hardware status information can be GPIO information that represents the status of a specific hardware device. Therefore, the SPI pins between the MCU and the general-purpose GPIO control module can be defined as GPIO1, GPIO2, GPIO3 and GPIO4.
[0072] Based on the circuit provided in this example, the multiplexing design of the SPI pins of the CPLD can be completed.
[0073] Optionally, the complex programmable logic device may also include a second control interface;
[0074] The second control interface is connected to a high-level signal;
[0075] The third terminal of the controller is connected to the second control interface, which is used to receive control signals sent by the complex programmable logic device. When the controller receives the control signal of the first state, it receives the Flash information sent by the Flash module and sends the Flash information to the complex programmable logic device. When the controller receives the control signal of the second state, it receives the hardware status information sent by the hardware status module and sends the hardware status information to the complex programmable logic device.
[0076] Combined with scenario examples, such as Figure 8 As shown, the SPI pins include multiple signal transmission paths, including a first signal transmission path defined as MCLK or GPIO1, a second signal transmission path defined as CSPIN or GPIO2, a third signal transmission path defined as MISO or GPIO3, and a fourth signal transmission path defined as MOSI or GPIO4. After connecting the second control port, the first signal transmission path, and the second signal transmission path to a high level, the second control port, the first signal transmission path, and the second signal transmission path can operate normally. The CPLD sends control signals to the processor through the second control port to control the processor to switch the received information. Specifically, when the control signal sent by the CPLD to the controller is in the first state, the processor switches to receiving Flash information output by the Flash module. Specifically, it receives Flash information through the first, second, and third signal transmission paths, and transmits the received Flash information to the CPLD through the first, second, and third signal transmission paths. The CPLD returns first result data to the processor through the fourth signal transmission path, and the processor returns the first result data to the Flash module through the fourth signal transmission path.
[0077] Similarly, when the control signal sent by the CPLD to the controller is in the second state, the processor switches to receiving GPIO information output by the hardware status module. Specifically, the processor receives GPIO information through the first signal transmission path, the second signal transmission path, and the third signal transmission path, and transmits the received GPIO information to the CPLD through the first signal transmission path, the second signal transmission path, and the third signal transmission path. The CPLD returns the second result data to the processor through the fourth signal transmission path, and the processor returns the second result data to the hardware status module through the fourth signal transmission path.
[0078] Based on the circuit provided in this example, access to the Flash module and the hardware status module can be switched by controlling the status information of the control signal, so as to realize time-sharing access to the Flash module and the hardware status module.
[0079] Optional, Figure 9 Schematic diagram of the pin multiplexing circuit provided in this application Figure 8 ,like Figure 9 As shown, the circuit also includes: a third resistor R3, a fourth resistor R4, and a fifth resistor R5;
[0080] The first end of the third resistor R3 is connected to a high level, and the second end of the third resistor R3 is connected to the second control interface of the complex programmable logic device to reduce the current in the path.
[0081] The first end of the fourth resistor R4 is connected to the high level, and the second end of the fourth resistor R4 is connected to the first signal transmission path to reduce the current in the path.
[0082] The first end of the fifth resistor R5 is connected to the high level, and the second end of the fifth resistor R5 is connected to the second signal transmission path to reduce the current in the path.
[0083] Based on the scenario example, the resistance values of the third resistor R3, the fourth resistor R4, and the fifth resistor R5 can be determined according to the actual situation. Currently, the third resistor R3, the fourth resistor R4, and the fifth resistor R5 play a current-limiting role in the circuit to prevent the circuit board from burning out due to excessive current.
[0084] Figure 10 Schematic diagram of the pin multiplexing circuit provided in this application Figure 9 ,like Figure 10 As shown, the complex programmable logic device integrates a time-division multiplexing logic module, a pin function switching module, and a hardware status information logic control module. The time-division multiplexing logic module is used to control the state of the output control signals, the pin function switching module is used to switch the receiving state of the serial peripheral interface pins, and the hardware status information logic control module is used to analyze and process the received hardware status information.
[0085] Based on scenario examples, the pin function switching module can determine the module that needs to be accessed. When access to the Flash module is required, it outputs a first-state control signal through the CPLD; when access to the hardware status module is required, it outputs a second-state control signal through the CPLD. The time-division multiplexing logic module can define the function switching between control signals and SPI pins. For example, it can be specified that when the CPLD outputs a first-state control signal, the control processor switches the SPI pin to receive Flash information; and when the CPLD outputs a first-state control signal, the control processor switches the SPI pin to receive hardware status information.
[0086] Optionally, the pin multiplexing circuit obtained above can be verified. The verification process can be carried out by acquiring multiple preset test data, inputting the test data into the pin multiplexing circuit in sequence, and judging whether the pin multiplexing circuit can give a preset response.
[0087] The pin multiplexing circuit provided in this application allows for the multiplexing of target function pins, thereby meeting the pin requirements of logic devices. This solves the problems of resource waste and increased wiring pressure caused by packaging multiple logic devices or selecting larger logic devices regardless of cost in related technologies, thereby reducing the cost of logic devices and alleviating the pressure of wiring logic devices.
[0088] This application also provides a network device that includes the pin multiplexing circuits of the above embodiments.
[0089] The network device can be any type of network switching device, network interface card (NIC), or other electronic device. The network switching device can be a switch or a router. The electronic device includes at least one processor and a memory. Optionally, the electronic device also includes a communication component. The processor, memory, and communication component are connected via a bus. In the above embodiments, it should be understood that the processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the application can be directly implemented by a hardware processor, or implemented by a combination of hardware and software modules in the processor. The memory may include random access memory (RAM) and may also include non-volatile memory (NVM), such as at least one disk storage device. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.
[0090] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.
[0091] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0092] The pin multiplexing circuit provided in this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.
Claims
1. A pin multiplexing circuit, characterized in that, include: The system comprises a logic device, a processor, a first functional module, and a second functional module; wherein: the logic device includes a target functional pin, the first functional module includes a first functional pin corresponding to the target functional pin, and the second functional module includes a second functional pin corresponding to the target functional pin; The first functional pin of the first functional module is connected to the first terminal of the processor, and is used to transmit the first functional signal to the processor and receive the first result data returned by the processor; The second functional module's second functional pin is connected to the second terminal of the processor, and is used to transmit the second functional signal to the processor and receive the second result data returned by the processor; The third terminal of the processor is connected to the control signal; The fourth terminal of the processor is connected to the target function pin and is used to send the received first function signal to the logic device and receive the first result data returned by the logic device when the control signal is in the first state, so as to return the first result to the first function module; it is also used to send the received second function signal to the logic device and receive the second result data returned by the logic device when the control signal is in the second state, so as to return the second result to the second function module. The logic device is a complex programmable logic device; correspondingly, the target function pins include joint test group pins and serial peripheral interface pins; When the target function pin is a joint test working group pin; correspondingly, the first function module is an upper-layer system module, the first function signal is general information or online upgrade information, the second function module is an offline update module, and the second function signal is offline update information; When the target function pin is a serial peripheral interface pin; correspondingly, the first function module is a Flash module, the first function signal is Flash information, the second function module is a hardware status module, and the second function signal is hardware status information.
2. The circuit according to claim 1, characterized in that, When the target function pin is a joint test group pin, the complex programmable logic device further includes a first control interface; The control terminal of the upper-level system module is connected to the first control interface of the complex programmable logic device. When the first control interface is in a low-level state, the first functional signal sent to the controller is general information, and when the first control interface is in a high-level state, the first functional signal sent to the controller is online upgrade information.
3. The circuit according to claim 2, characterized in that, The circuit also includes: a first switch module and a second switch module; The first terminal of the first switch module is connected to a high level, and the second terminal of the first switch module is grounded. The first terminal of the second switch module is connected to a high level, and the second terminal of the second switch module is grounded; The first control interface of the complex programmable logic device is connected to the second terminal of the first switch module. It is in a low-level state when the path between the first terminal and the second terminal of the first switch module is disconnected, and in a high-level state when the path between the first terminal and the second terminal of the first switch module is connected. The third terminal of the controller is connected to the second terminal of the second switch module. When the path between the first and second terminals of the second switch module is disconnected, the received control signal is the control signal of the first state; when the path between the first and second terminals of the second switch module is connected, the received control signal is the control signal of the second state.
4. The circuit according to claim 3, characterized in that, The circuit further includes: a first resistor and a second resistor; The first end of the first resistor is connected to the second end of the first switch module, and the second end of the first resistor is grounded to reduce the current in the path. The first end of the second resistor is connected to the second end of the second switch module, and the second end of the second resistor is grounded to reduce the current in the path.
5. The circuit according to claim 1, characterized in that, When the target function pin is a serial peripheral interface pin, the complex programmable logic device also includes a second control interface; The second control interface is connected to a high-level signal; The third terminal of the controller is connected to the second control interface and is used to receive control signals sent by the complex programmable logic device. When receiving the control signal of the first state, it receives Flash information sent by the Flash module and sends the Flash information to the complex programmable logic device. When receiving the control signal of the second state, it receives hardware status information sent by the hardware status module and sends the hardware status information to the complex programmable logic device.
6. The circuit according to claim 5, characterized in that, The circuit also includes: a third resistor, a fourth resistor, and a fifth resistor; The first end of the third resistor is connected to a high level, and the second end of the third resistor is connected to the second control interface of the complex programmable logic device to reduce the current in the path. The first end of the fourth resistor is connected to a high level, and the second end of the fourth resistor is connected to the first signal transmission path to reduce the current in the path. The first end of the fifth resistor is connected to a high level, and the second end of the fifth resistor is connected to the second signal transmission path to reduce the current in the path.
7. A network device comprising a pin multiplexing circuit as described in any one of claims 1 to 6.