Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the steps of providing a substrate; forming a laminated structure on the substrate, wherein the laminated structure comprises a first dielectric layer and a conductive layer which are sequentially laminated from bottom to top; forming a continuously distributed second dielectric layer on the exposed surface of the laminated structure, and filling a gap region of the laminated structure with a sacrificial layer; forming a first groove penetrating through each layer of channel region in the laminated structure; sequentially depositing a channel material layer, an isolation dielectric material layer and a gate conductive layer on the inner wall of the first groove, wherein the gate conductive layer fills the first groove; forming a second groove penetrating through the sacrificial layer in a gap region on two opposite sides of the channel region along the first direction; and removing the sacrificial layer on the side wall of the second groove, and removing the channel material layer in contact with the sacrificial layer and the corresponding isolation medium material layer. By adopting the preparation method of the semiconductor structure, the problem of parasitic MOS (Metal Oxide Semiconductor) can be solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] With the development of semiconductor technology, the storage density of memory is getting higher and higher. However, as the feature size is getting closer and closer to the theoretical limit, 3D stacked memory based on oxide materials is expected to achieve high-density storage and is a possible development direction for the next generation of memory. However, 3D stacked memory still faces many difficult challenges, such as the parasitic transistor problem. The parasitic transistor problem refers to the interconnection between different capacitors through oxide materials, which makes it impossible to store information. Summary of the invention

[0003] Based on this, it is necessary to provide a semiconductor structure and a method for preparing the same in order to solve the problem of parasitic transistors in the related art.

[0004] In a first aspect, the present invention provides a method for preparing a semiconductor structure, comprising:

[0005] providing a substrate;

[0006] A stacked structure is formed on the substrate, the stacked structure comprising a first dielectric layer and a conductive layer stacked in sequence from bottom to top, each conductive layer comprising: a main body extending along a first direction and a plurality of extensions arranged at intervals along the first direction, each of the extensions being located on two opposite sides of the main body, the main body being integrally connected to each of the extensions, and a portion of the extension connected to the main body being used as a channel region; wherein a width of the extension along the first direction is greater than a width of the first dielectric layer located between the extensions along the first direction;

[0007] forming a continuously distributed second dielectric layer on the exposed surface of the stacked structure, and filling the gap area of ​​the stacked structure with a sacrificial layer;

[0008] A first groove penetrating through the channel region of each layer is formed in the stacked structure to remove the first dielectric layer and the conductive layer located in the channel region, and a portion of the second dielectric layer located on the two opposite sides of the first dielectric layer along the first direction, and a portion of the second dielectric layer located on the two opposite sides of the extension along the first direction is retained; wherein the sacrificial layer and the second dielectric layer alternately stacked in sequence are exposed on the two opposite side walls of the first groove along the first direction, and the position of each sacrificial layer corresponds to the position of each first dielectric layer, and the position of each second dielectric layer corresponds to the position of each conductive layer;

[0009] Depositing a channel material layer, an isolation dielectric material layer and a gate conductive layer on the inner wall of the first trench in sequence, wherein the gate conductive layer fills the first trench;

[0010] forming a second groove penetrating the sacrificial layer in the gap region on two opposite sides of the channel region along the first direction, wherein the sacrificial layer and the second dielectric layer alternately stacked in sequence are exposed on two opposite sidewalls of the second groove along the first direction;

[0011] The sacrificial layer located on the sidewall of the second trench is removed, and the channel material layer and the corresponding isolation dielectric material layer in contact with the sacrificial layer are removed to obtain an isolation dielectric layer and a channel layer surrounding the sidewall of the gate conductive layer and in contact with the second dielectric layer, wherein the isolation dielectric layer and the channel layer are both located between the gate conductive layer and the conductive layer.

[0012] The method for preparing the semiconductor structure is as follows: forming a stacked structure on the substrate, the stacked structure comprising a first dielectric layer and a conductive layer stacked in sequence from bottom to top, each conductive layer comprising: a main body extending along a first direction and a plurality of extensions arranged at intervals along the first direction, each extension being located on two opposite sides of the main body, the main body being integrally connected to each extension, and a portion of the extension connected to the main body being used as a channel region; wherein the width of the extension along the first direction is greater than the width of the first dielectric layer located between the extensions along the first direction; forming a continuously distributed second dielectric layer on the exposed surface of the stacked structure, and filling the gap region of the stacked structure with a sacrificial layer; forming a first groove penetrating through each channel region of each layer in the stacked structure, so as to remove the first dielectric layer and the conductive layer located in the channel region, and remove a portion of the second dielectric located on two opposite sides of the first dielectric layer along the first direction. A layer is formed in the first groove, and a part of the second dielectric layer is retained on the two side surfaces of the extension portion opposite to each other along the first direction; wherein the sacrificial layer and the second dielectric layer alternately stacked in sequence are exposed on the two side walls opposite to each other along the first direction of the first groove; a channel material layer, an isolation dielectric material layer and a gate conductive layer are sequentially deposited on the inner wall of the first groove, and the gate conductive layer fills the first groove; a second groove penetrating the sacrificial layer is formed in the gap region on the two sides opposite to each other along the first direction of the channel region, and the sacrificial layer and the second dielectric layer alternately stacked in sequence are exposed on the two side walls opposite to each other along the first direction of the second groove; the sacrificial layer located on the side wall of the second groove is removed, and the channel material layer and the corresponding isolation dielectric material layer contacting the sacrificial layer are removed to obtain an isolation dielectric layer and a channel layer surrounding the side wall of the gate conductive layer and contacting the second dielectric layer, and the isolation dielectric layer and the channel layer are both located between the gate conductive layer and the conductive layer. Since the position of each sacrificial layer corresponds to the position of each first dielectric layer, and the position of each second dielectric layer corresponds to the position of each conductive layer, the channel material layer covered by each sacrificial layer can be selectively removed by etching based on the second groove, and the channel material layer covered by each second dielectric layer can be retained to avoid the problem of parasitic MOS in the device. In this process, there is no need to etch and remove the extension part, so that the integrity of the extension part can be guaranteed. In the subsequent process, a part of the extension part can be used as the first electrode of the capacitor in the memory, so that the available area of ​​the capacitor can be increased.

[0013] In one embodiment, removing the sacrificial layer located on the sidewall of the second trench includes:

[0014] Using a steam etching process to remove the sacrificial layer located on the sidewall of the second trench;

[0015] The removing of the exposed portion of the channel material layer and the portion of the isolation dielectric material layer corresponding to the exposed portion of the channel material layer comprises:

[0016] A wet etching process is adopted to remove the exposed portion of the channel material layer and the portion of the isolation dielectric material layer corresponding to the exposed portion of the channel material layer.

[0017] In one embodiment, after removing the channel material layer and the isolation dielectric material layer in contact with the sacrificial layer, the method further comprises:

[0018] The second groove is filled with a filling layer.

[0019] In one embodiment, forming a stacked structure on the substrate includes:

[0020] forming an initial stacked structure on the substrate, the initial stacked structure comprising a first dielectric material layer and a conductive material layer stacked sequentially from bottom to top;

[0021] Etching and removing a portion of the initial stacked structure to form a third trench penetrating the initial stacked structure, wherein the sidewall of the third trench exposes the side surfaces of each layer of the first dielectric material; and the extensions of the same layer are separated by the third trench;

[0022] Each of the first dielectric material layers is laterally etched based on the third trench to form a fourth trench located between each of the conductive material layers, so that the width of the extension along the first direction is greater than the width of the first dielectric layer along the first direction.

[0023] In one embodiment, forming a continuously distributed second dielectric layer on the exposed surface of the stacked structure and filling the gap area of ​​the stacked structure with a sacrificial layer includes:

[0024] forming a continuously distributed second dielectric layer on the inner walls of the third trench and the fourth trench;

[0025] The sacrificial layer is filled in the third trench and the fourth trench.

[0026] In one embodiment, the portion of the extension away from the main body is used as a first electrode, and after the gap region of the stacked structure is filled with a sacrificial layer, before a first trench penetrating the channel region of each layer is formed in the stacked structure, the method further includes:

[0027] removing the second dielectric layer and the sacrificial layer located on the surface of the first electrode to expose the surface of the first electrode;

[0028] A capacitor dielectric layer and a second electrode are sequentially formed on the exposed surface of the first electrode.

[0029] In one embodiment, removing the second dielectric layer and the sacrificial layer located on the surface of the first electrode to expose the surface of the first electrode includes:

[0030] A fifth groove penetrating the sacrificial layer is formed in the gap region on two opposite sides of the first electrode along the first direction, wherein the sidewalls of the fifth groove expose the sacrificial layer and the second dielectric layer located on two opposite sides of each layer of the first electrode in sequence;

[0031] Lateral etching is performed based on the fifth trench to form a sixth trench located between the first electrodes of each layer.

[0032] In one embodiment, the capacitor dielectric layer and the second electrode are sequentially formed on the surface exposed by the first electrode, including:

[0033] forming a continuously distributed third dielectric layer on the inner wall of the fifth trench, the inner wall of the sixth trench and the upper surface of the stacked structure;

[0034] forming a conductive barrier layer on the surface of the third dielectric layer;

[0035] A conductive filling layer is deposited in the fifth trench, in the sixth trench and on the stacked structure; wherein the third dielectric layer serves as the capacitor dielectric layer, and the conductive barrier layer and the conductive filling layer together constitute the second electrode.

[0036] In the second aspect, the present application also provides a semiconductor structure, including:

[0037] substrate;

[0038] A stacked structure is located on the substrate, the stacked structure includes a first dielectric layer and a conductive layer stacked in sequence from bottom to top, each conductive layer includes: a main body extending along a first direction and a plurality of extensions arranged at intervals along the first direction, each of the extensions is located on two opposite sides of the main body, the main body is integrally connected to each of the extensions, and a portion of the extension connected to the main body serves as a channel region;

[0039] A second dielectric layer covering two opposite sides of the channel region of each layer along the first direction;

[0040] A device structure that runs through the channel regions of each layer, the device structure includes a gate conductive layer, multiple isolation dielectric layers surrounding the side walls of the gate conductive layer, and multiple channel layers corresponding to the surface of the isolation dielectric layer. Each layer of the isolation dielectric layer and each layer of the channel layer are located between the gate conductive layer and the conductive layer, and each layer of the channel layer is in contact with each layer of the second dielectric layer.

[0041] The semiconductor structure includes a substrate, a stacked structure, a second dielectric layer and a device structure. The stacked structure is located on the substrate, and the stacked structure includes a first dielectric layer and a conductive layer stacked in sequence from bottom to top. Each conductive layer includes: a main body extending along a first direction and a plurality of extensions arranged at intervals along the first direction. Each extension is located on two opposite sides of the main body. The main body is integrally connected to each extension, and the portion where the extension is connected to the main body is used as a channel region. The second dielectric layer covers two opposite sides of the channel region of each layer along the first direction. The device structure runs through each channel region. The device structure includes a gate conductive layer, a plurality of channel layers surrounding the sidewalls of the gate conductive layer, and a plurality of isolation dielectric layers corresponding to the surface of the channel layer. Each channel layer and each isolation dielectric layer are located between the gate conductive layer and the conductive layer, and each isolation dielectric layer is in contact with each second dielectric layer. Since the channel layer is formed by selectively removing the channel material layer, the extension is not etched away during this process, thereby ensuring the integrity of the extension. In a subsequent process, a portion of the extension portion can be used as a first electrode of a capacitor in the memory, thereby increasing the available area of ​​the capacitor.

[0042] In one embodiment, the semiconductor structure further includes a capacitor, which includes a first electrode, a capacitor dielectric layer and a second electrode sequentially covering the surface of the first electrode, and a portion of the extension away from the main body serves as the first electrode of the capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0044] Figure 1 is a flow chart of a method for preparing a semiconductor structure provided in an embodiment;

[0045] Figure 2 is a flowchart of step S20 in a method for preparing a semiconductor structure provided in an embodiment;

[0046] Figure 3A schematic diagram of a top view of a structure obtained in step S201 of a method for preparing a semiconductor structure provided in an embodiment;

[0047] Figure 4 is a schematic diagram of a cross-sectional structure of a structure obtained in step S201 provided in an embodiment, wherein (a) is ... Figure 3 Schematic diagram of AA' direction shown in (b), along Figure 3 Schematic diagram of BB' direction, (c) is along Figure 3 Schematic diagram of CC' direction shown in Figure 2, (d) is a schematic diagram of CC' direction along Figure 3 Schematic diagram of DD' direction shown;

[0048] Figure 5 A schematic diagram of a top view of a structure obtained in step S202 of a method for preparing a semiconductor structure provided in an embodiment;

[0049] Figure 6 is a schematic diagram of a cross-sectional structure of a structure obtained in step S202 provided in an embodiment, wherein (a) is ... Figure 5 Schematic diagram of AA' direction shown in (b), along Figure 5 Schematic diagram of BB' direction, (c) is along Figure 5 Schematic diagram of CC' direction shown in Figure 2, (d) is a schematic diagram of CC' direction along Figure 5 Schematic diagram of DD' direction shown;

[0050] Figure 7 A schematic diagram of a top view of a structure obtained in step S203 of a method for preparing a semiconductor structure provided in an embodiment;

[0051] Figure 8 Schematic diagram of the cross-sectional structure of the structure obtained in step S203 provided in an embodiment, wherein (a) is a ... Figure 7 Schematic diagram of AA' direction shown in (b), along Figure 7 Schematic diagram of BB' direction, (c) is along Figure 7 Schematic diagram of CC' direction shown in Figure 2, (d) is a schematic diagram of CC' direction along Figure 7 Schematic diagram of DD' direction shown;

[0052] Fig. 9 is a flowchart of step S30 in a method for preparing a semiconductor structure provided in an embodiment;

[0053] Fig.10 A schematic diagram of a top view of a structure obtained in step S302 of a method for preparing a semiconductor structure provided in an embodiment;

[0054] Fig.11 The schematic diagram of the cross-sectional structure of the structure obtained in step S302 provided in one embodiment, wherein (a) is a ... Fig.10 Schematic diagram of AA' direction shown in (b), along Fig.10 Schematic diagram of BB' direction, (c) is along Fig.10 Schematic diagram of CC' direction shown in Figure 2, (d) is a schematic diagram of CC' direction along Fig.10 Schematic diagram of DD' direction shown;

[0055] Fig.12 A schematic diagram of a top view of a structure obtained after a frame structure is formed in a method for preparing a semiconductor structure provided in an embodiment;

[0056] Fig.13 The schematic diagram of the cross-sectional structure of the structure obtained after the frame structure is formed in one embodiment, wherein (a) is a schematic diagram of the cross-sectional structure of the structure obtained after the frame structure is formed in one embodiment, Fig.12 Schematic diagram of AA' direction shown in (b), along Fig.12 Schematic diagram of BB' direction, (c) is along Fig.12 Schematic diagram of CC' direction shown in Figure 2, (d) is a schematic diagram of CC' direction along Fig.12 Schematic diagram of DD' direction shown;

[0057] Fig.14 A flowchart of steps after step S30 and before step S40 in a method for preparing a semiconductor structure provided in an embodiment;

[0058] Fig.15 is a flowchart of step S31 in a method for preparing a semiconductor structure provided in an embodiment;

[0059] Fig.16 A schematic diagram of a top view of a structure obtained in step S311 provided in an embodiment;

[0060] Fig.17 is a schematic diagram of a cross-sectional structure of a structure obtained in step S311 provided in an embodiment, wherein (a) is ... Fig.16 Schematic diagram of AA' direction shown in (b), along Fig.16 Schematic diagram of BB' direction, (c) is along Fig.16 Schematic diagram of CC' direction shown in Figure 2, (d) is a schematic diagram of CC' direction along Fig.16 Schematic diagram of DD' direction shown;

[0061] Fig.18 A schematic diagram of a top view of a structure obtained in step S312 provided in an embodiment;

[0062] Fig.19 Schematic diagram of the cross-sectional structure of the structure obtained in step S312 provided in an embodiment, wherein (a) is a ... Fig.18 Schematic diagram of AA' direction shown in (b), along Fig.18Schematic diagram of BB' direction, (c) is along Fig.18 Schematic diagram of CC' direction shown in Figure 2, (d) is a schematic diagram of CC' direction along Fig.18 Schematic diagram of DD' direction shown;

[0063] Fig. 20 is a flowchart of step S323 in a method for preparing a semiconductor structure provided in an embodiment;

[0064] Fig.21 A schematic diagram of a top view of a structure obtained in step S323 provided in an embodiment;

[0065] Fig. 22 Schematic diagram of the cross-sectional structure of the structure obtained in step S323 provided in one embodiment, wherein (a) is a ... Fig.21 Schematic diagram of AA' direction shown in (b), along Fig.21 Schematic diagram of BB' direction, (c) is along Fig.21 Schematic diagram of CC' direction shown in Figure 2, (d) is a schematic diagram of CC' direction along Fig.21 Schematic diagram of DD' direction shown;

[0066] Fig.23 A flowchart of steps after step S32 and before step S40 in a method for preparing a semiconductor structure provided in an embodiment;

[0067] Fig.24 A schematic diagram of a top view of a structure obtained in step S33 provided in an embodiment;

[0068] Fig.25 The schematic diagram of the cross-sectional structure of the structure obtained in step S33 provided in one embodiment, wherein (a) is a ... Fig.24 Schematic diagram of AA' direction shown in (b), along Fig.24 Schematic diagram of BB' direction, (c) is along Fig.24 Schematic diagram of CC' direction shown in Figure 2, (d) is a schematic diagram of CC' direction along Fig.24 Schematic diagram of DD' direction shown;

[0069] Fig.26 A schematic diagram of a top view of a structure obtained in step S34 provided in an embodiment;

[0070] Fig. 27 The schematic diagram of the cross-sectional structure of the structure obtained in step S34 provided in one embodiment, wherein (a) is a ... Fig.26 Schematic diagram of AA' direction shown in (b), along Fig.26 Schematic diagram of BB' direction, (c) is along Fig.26 Schematic diagram of CC' direction shown in Figure 2, (d) is a schematic diagram of CC' direction along Fig.26Schematic diagram of DD' direction shown;

[0071] Fig.28 A schematic diagram of a top view of a structure obtained in step S40 provided in an embodiment;

[0072] Fig.29 Schematic diagram of the cross-sectional structure of the structure obtained in step S40 provided in an embodiment, wherein (a) is a ... Fig.28 Schematic diagram of AA' direction shown in (b), along Fig.28 Schematic diagram of BB' direction, (c) is along Fig.28 Schematic diagram of CC' direction shown in Figure 2, (d) is a schematic diagram of CC' direction along Fig.28 Schematic diagram of DD' direction shown;

[0073] Fig.30 A schematic diagram of a top view of a structure obtained in step S50 provided in an embodiment;

[0074] Fig.31 The schematic diagram of the cross-sectional structure of the structure obtained in step S50 provided in one embodiment, wherein (a) is a ... Fig.30 Schematic diagram of AA' direction shown in (b), along Fig.30 Schematic diagram of BB' direction, (c) is along Fig.30 Schematic diagram of CC' direction shown in Figure 2, (d) is a schematic diagram of CC' direction along Fig.30 Schematic diagram of DD' direction shown;

[0075] Fig.32 A schematic diagram of a top view of a structure obtained in step S60 provided in an embodiment;

[0076] Fig.33 is a schematic diagram of a cross-sectional structure of a structure obtained in step S60 provided in an embodiment, wherein (a) is ... Fig.32 Schematic diagram of AA' direction shown in (b), along Fig.32 Schematic diagram of BB' direction, (c) is along Fig.32 Schematic diagram of CC' direction shown in Figure 2, (d) is a schematic diagram of CC' direction along Fig.32 Schematic diagram of DD' direction shown;

[0077] Fig.34 is a schematic diagram of a top view of a structure obtained after removing the sacrificial layer located on the sidewall of the second trench in step S70 provided in an embodiment;

[0078] Fig.35 FIG. 1 is a schematic diagram of a cross-sectional structure of a structure obtained after removing the sacrificial layer located on the sidewall of the second trench in step S70 provided in an embodiment, wherein FIG. (a) is a cross-sectional structure of a structure obtained after removing the sacrificial layer located on the sidewall of the second trench in step S70 provided in an embodiment, wherein FIG. Fig.34 Schematic diagram of AA' direction shown in (b), along Fig.34Schematic diagram of BB' direction, (c) is along Fig.34 Schematic diagram of CC' direction shown in Figure 2, (d) is a schematic diagram of CC' direction along Fig.34 Schematic diagram of DD' direction shown;

[0079] Fig.36 A schematic diagram of a top view of a structure obtained in step S70 provided in an embodiment;

[0080] Fig.37 The schematic diagram of the cross-sectional structure of the structure obtained in step S70 provided in one embodiment, wherein (a) is a ... Fig.36 Schematic diagram of AA' direction shown in (b), along Fig.36 Schematic diagram of BB' direction, (c) is along Fig.36 Schematic diagram of CC' direction shown in Figure 2, (d) is a schematic diagram of CC' direction along Fig.36 Schematic diagram of DD' direction shown;

[0081] Fig.38 A schematic diagram of a top view of a structure obtained after the second trench is filled with a filling layer in a method for preparing a semiconductor structure provided in an embodiment;

[0082] Fig.39 A schematic cross-sectional view of a structure obtained after the second trench is filled with a filling layer in a method for preparing a semiconductor structure provided in an embodiment, wherein (a) is a ... Fig.38 Schematic diagram of AA' direction shown in (b), along Fig.38 Schematic diagram of BB' direction, (c) is along Fig.38 Schematic diagram of CC' direction shown in Figure 2, (d) is a schematic diagram of CC' direction along Fig.38 Schematic diagram of DD' direction is shown.

[0083] Explanation of the reference numerals: 10-substrate, 101-first trench, 102-second trench, 103-third trench, 104-fourth trench, 105-fifth trench, 106-sixth trench, 20-first dielectric layer, 21-first dielectric material layer, 30-conductive layer, 301-main body, 302-extension portion, 303-channel region, 31-conductive material layer, 40-covering dielectric layer, 401-second dielectric layer, 402-sacrificial layer, 403-frame structure, 404-filling layer, 501-third dielectric layer, 502-conductive barrier layer, 503-conductive filling layer, 601-channel material layer, 611-channel layer, 602-isolation dielectric material layer, 612-isolation dielectric layer, 603-gate conductive layer. DETAILED DESCRIPTION

[0084] In order to facilitate understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0085] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0086] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0087] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0088] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0089] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of preferred embodiments of the invention (and intermediate structures), so that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0090] See also Figure 1 The present invention provides a method for preparing a semiconductor structure, comprising the following steps:

[0091] S10: providing a substrate;

[0092] S20: forming a stacked structure on a substrate, the stacked structure comprising a first dielectric layer and a conductive layer stacked in sequence from bottom to top, each conductive layer comprising: a main body extending along a first direction and a plurality of extensions arranged at intervals along the first direction, each extension being located on two opposite sides of the main body, the main body being integrally connected to each extension, and a portion where the extension is connected to the main body being used as a channel region; wherein a width of the extension along the first direction is greater than a width of the first dielectric layer between the extensions along the first direction;

[0093] S30: forming a continuously distributed second dielectric layer on the exposed surface of the stacked structure, and filling the gap area of ​​the stacked structure with a sacrificial layer;

[0094] S40: forming a first trench penetrating through the channel regions of each layer in the stacked structure, so as to remove the first dielectric layer and the conductive layer located in the channel region, and remove a portion of the second dielectric layer located on the two opposite sides of the first dielectric layer along the first direction, and retain a portion of the second dielectric layer located on the two opposite sides of the extension portion along the first direction; wherein, the sacrificial layers and the second dielectric layers alternately stacked in sequence are exposed on the two opposite side walls of the first trench along the first direction, and the position of each sacrificial layer corresponds to the position of each first dielectric layer, and the position of each second dielectric layer corresponds to the position of each conductive layer;

[0095] S50: depositing an isolation dielectric material layer, a channel material layer and a gate conductive layer in sequence on the inner wall of the first trench, wherein the gate conductive layer fills the first trench;

[0096] S60: forming a second trench penetrating the sacrificial layer in the gap region on two opposite sides of the channel region along the first direction, wherein the sacrificial layer and the second dielectric layer alternately stacked in sequence are exposed on two opposite sidewalls of the second trench along the first direction;

[0097] S70: removing the sacrificial layer located on the sidewall of the second trench, and removing the channel material layer and the corresponding isolation dielectric material layer in contact with the sacrificial layer to obtain a channel layer and an isolation dielectric layer surrounding the sidewall of the gate conductive layer and in contact with the second dielectric layer, wherein the channel layer and the isolation dielectric layer are both located between the gate conductive layer and the conductive layer.

[0098] The semiconductor structure obtained after steps S10-S60 can be referred to Fig.39 .certainly, Fig.39 What is given is an example of a semiconductor structure prepared by the method for preparing a semiconductor structure of the present invention. There may be other suitable examples of a semiconductor structure prepared by the method for preparing a semiconductor structure of the present invention, and the present invention is not limited thereto.

[0099] In addition, to facilitate understanding of the present solution, the first direction involved in the present invention may be the extension direction of the CC' interception line or the DD' interception line in the top view, and the second direction may be the extension direction of the AA' interception line or the BB' interception line in the top view. Of course, in other suitable application scenarios, the first direction and the second direction may have other definitions, which are not limited here.

[0100] The method for preparing the semiconductor structure is as follows: a stacked structure is formed on a substrate, wherein the stacked structure includes a first dielectric layer and a conductive layer stacked in sequence from bottom to top, wherein each conductive layer includes: a main body extending in a first direction and a plurality of extensions arranged at intervals in the first direction, wherein each extension is located on two opposite sides of the main body, the main body is integrally connected to each extension, and a portion where the extension is connected to the main body serves as a channel region; wherein the width of the extension along the first direction is greater than the width of the first dielectric layer located between the extensions along the first direction; a continuously distributed second dielectric layer is formed on an exposed surface of the stacked structure, and a sacrificial layer is used to fill the gap region of the stacked structure; a first groove is formed in the stacked structure that penetrates through each channel region, so as to remove the first dielectric layer and the conductive layer located in the channel region, and to remove a portion of the first dielectric layer located on two opposite sides of the first dielectric layer along the first direction; The invention relates to a method for forming a second dielectric layer, and retaining a part of the second dielectric layer located on the two side surfaces of the extension portion opposite to each other along the first direction; wherein, the sacrificial layer and the second dielectric layer alternately stacked in sequence are exposed on the two side walls of the first groove opposite to each other along the first direction; a channel material layer, an isolation dielectric material layer and a gate conductive layer are sequentially deposited on the inner wall of the first groove, and the gate conductive layer fills the first groove; a second groove penetrating the sacrificial layer is formed in the gap area on the two sides opposite to each other along the first direction of the channel area, and the sacrificial layer and the second dielectric layer alternately stacked in sequence are exposed on the two side walls of the second groove opposite to each other along the first direction; the sacrificial layer located on the side wall of the second groove is removed, and the channel material layer and the corresponding isolation dielectric material layer in contact with the sacrificial layer are removed to obtain the isolation dielectric layer and the channel layer surrounding the side wall of the gate conductive layer and in contact with the second dielectric layer, and the isolation dielectric layer and the channel layer are both located between the gate conductive layer and the conductive layer. Since the position of each sacrificial layer corresponds to the position of each first dielectric layer, and the position of each second dielectric layer corresponds to the position of each conductive layer, the channel material layer covered by each sacrificial layer can be selectively removed by etching based on the second groove, and the channel material layer covered by each second dielectric layer can be retained to avoid the problem of parasitic MOS in the device. In this process, there is no need to etch and remove the extension part, so that the integrity of the extension part can be guaranteed. In the subsequent process, a part of the extension part can be used as the first electrode of the capacitor in the memory, so that the available area of ​​the capacitor can be increased.

[0101] In step S10, refer to Figure 1 Step S10 in Figure 4 , providing a substrate 10.

[0102] The material of the substrate 10 may be any suitable substrate material known in the art, for example, at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or ceramic substrates such as alumina, quartz or glass substrates, etc., which are not limited in this embodiment.

[0103] In step S20, refer to Figure 1 Step S20 in Figure 7-Figure 8 , a stacked structure is formed on the substrate 10, and the stacked structure includes a first dielectric layer 20 and a conductive layer 30 stacked sequentially from bottom to top.

[0104] Each conductive layer 30 includes: a main body 301 extending along a first direction and a plurality of extensions 302 arranged at intervals along the first direction, each extension 302 is located on two opposite sides of the main body 301, the main body 301 is integrally connected with each extension 302, and the portion where the extension 302 is connected to the main body 301 serves as a channel region 303. The width of the extension 302 along the first direction is greater than the width of the first dielectric layer 20 located between the extensions 302 along the first direction.

[0105] In one embodiment, Figure 2 As shown, the above step S20 includes:

[0106] S201 : forming an initial stacked structure on a substrate 10 , wherein the initial stacked structure includes a first dielectric material layer 21 and a conductive material layer 31 stacked sequentially from bottom to top.

[0107] like Figure 3-Figure 4 As shown, a deposition process may be used to sequentially deposit multiple layers of first dielectric material layers 21 and multiple layers of conductive material layers 31 to form an initial stacked structure.

[0108] The material of the first dielectric material layer 21 may include any suitable dielectric material, such as an oxide material or a nitride material. Further, the oxide material may include at least one of silicon oxide, silicon oxynitride, silicon oxycarbide and silicon nitride-carbon oxynitride; the nitride material may include silicon nitride, etc.

[0109] The material of the conductive material layer 31 may include metal materials such as tungsten, copper, gold, titanium, silver, aluminum, etc., or may include a multilayer metal composed of the above metal materials, or may include a metal alloy, etc., which is not limited in this embodiment.

[0110] Optional, such as Figure 3-Figure 4 As shown, a covering dielectric layer 40 may be formed on the top of the initial stacked structure, and the material of the covering dielectric layer 40 may include any suitable dielectric material, such as an oxide material or a nitride material. Further, the oxide material may include at least one of silicon oxide, silicon oxynitride, silicon oxycarbide, and silicon oxynitride-carbon; the nitride material may include silicon nitride, etc.

[0111] Furthermore, the material of the cover dielectric layer 40 may be different from the material of the first dielectric material layer 21 . For example, the material of the first dielectric material layer 21 may be silicon oxide, and the material of the cover dielectric layer 40 may be silicon nitride.

[0112] Of course, it should be understood that the covering dielectric layer 40 is not necessary. In some suitable application scenarios, when the stacking of the laminated structure is appropriate, the first dielectric layer 20 or the conductive layer 30 can be directly used as the covering dielectric layer 40. The covering dielectric layer 40 is shown here only as a suitable embodiment, and the covering dielectric layer 40 can also be ignored in other preparation processes or application scenarios.

[0113] S202 : etching and removing a portion of the initial stacked structure to form a third trench 103 penetrating the initial stacked structure, the sidewall of the third trench 103 exposing the side surfaces of each first dielectric material layer 21 ; the extensions 302 of the same layer are separated by the third trench 103 .

[0114] like Figure 5-Figure 6 As shown, a photoresist layer can be first formed on the upper surface of the initial stacked structure, and then a patterned photoresist layer can be formed through steps such as exposure and development to define the morphology of each conductive material layer 31 and each first dielectric material layer 21, and then a portion of the initial stacked structure can be removed based on the patterned photoresist layer through an etching process to form a third groove 103.

[0115] S203 : etching each first dielectric material layer 21 laterally based on the third trench 103 to form a fourth trench 104 between each conductive material layer 31 , so that the width of the extension portion 302 along the first direction is greater than the width of the first dielectric layer 20 between the extension portions 302 along the first direction.

[0116] like Figure 7-Figure 8As shown, a suitable etching process may be used to complete the lateral etching process, for example, a wet process or a steam etching process. Specifically, a corresponding etching liquid or etching gas may be introduced into the third groove 103, wherein the difference in etching selectivity of each material layer is utilized to selectively etch and remove a portion of the first dielectric material layer 21 to form a lateral fourth groove 104, so that the initial stacked structure finally forms the morphology of the stacked structure of step S20.

[0117] Optional, such as Figure 8 As shown, in the process of lateral etching to form the fourth trench 104, the substrate 10 may also be over-etched and lose a small portion, forming a Figure 8 The shape shown.

[0118] In addition, in step 20, the top view morphology of the covering dielectric layer 40 is the same as the top view morphology of the conductive layer 30 of each layer, while the first dielectric layer 20 of each layer has a different morphology from that of the conductive layer 30 due to the loss of a portion of the first dielectric layer 20 due to the lateral etching. Figure 5 ), the main body 301, the extension portion 302 and the channel region 303 are drawn on the same layer as the covering dielectric layer 40. However, it should be understood that the main body 301, the extension portion 302 and the channel region 303 in the top view of the present invention can also represent the positions of the main body 301, the extension portion 302 and the channel region 303 included in each conductive layer 30 located below the covering dielectric layer 40.

[0119] In step S30, refer to Figure 1 Step S30 in Figure 10-11 A continuously distributed second dielectric layer 401 is formed on the exposed surface of the stacked structure, and a sacrificial layer 402 is used to fill the gap area of ​​the stacked structure.

[0120] Since the morphologies of the first dielectric layer 20 and the conductive layer 30 in the stacked structure are not consistent, specifically, due to the existence of the lateral fourth trench 104, this difference is caused, so that the second dielectric layer 401 presents an alternating covering feature. A typical figure that can describe this alternating covering feature can be referred to. Fig.11 As shown in Figure (c). Fig.11 As can be seen in Figure (c), the width of the first dielectric layer 20 is smaller, while the width of the conductive layer 30 is larger, which causes the second dielectric layer 401 corresponding to the surface of the conductive layer 30 to protrude outwards relatively more than the second dielectric layer 401 corresponding to the surface of the first dielectric layer 20. This will be helpful in indicating which material layers correspond to the position of the conductive layer 30 and which material layers correspond to the position of the first dielectric layer 20 in subsequent processes.

[0121] In one embodiment, Fig. 9 As shown, the above step S30 includes:

[0122] S301 : forming a continuously distributed second dielectric layer 401 on the inner walls of the third trench 103 and the fourth trench 104 .

[0123] like Figure 10-11 As shown, an atomic layer deposition process can be used to form a continuously distributed second dielectric layer 401. The material of the second dielectric layer 401 can include any suitable dielectric material, such as an oxide material or a silicide material. Optionally, the deposition temperature of the deposition process for forming the second dielectric layer 401 can be 630° C., and the thickness of the second dielectric layer 401 can be 3 nm. Of course, in other suitable preparation processes, the deposition temperature of the deposition process for forming the second dielectric layer 401 can also be other suitable deposition temperatures; the thickness of the second dielectric layer 401 can also be other suitable thicknesses, which are not limited in this embodiment.

[0124] S302 : filling the third trench 103 and the fourth trench 104 with a sacrificial layer 402 .

[0125] like Figure 10-11 As shown, the seed layer can be formed by atomic layer deposition process first, and then a thick sacrificial layer 402 can be formed by deposition process. At this time, the sacrificial layer 402 will also cover the upper surface of the stacked structure, and then the excess sacrificial layer 402 on the upper surface of the stacked structure can be removed by grinding process to finally form the following: Fig.11 The shape shown.

[0126] The material of the sacrificial layer 402 may include any suitable dielectric material, such as an oxide material or a silicide material. Optionally, the material of the sacrificial layer 402 is different from the material of the second dielectric layer 401, for example, the material of the sacrificial layer 402 may be silicon oxide, and the material of the second dielectric layer 401 may be silicon nitride.

[0127] Optionally, the thickness of the sacrificial layer 402 may be 600 nm.

[0128] In addition, since the second dielectric layer 401 is relatively thin, Fig.10 The second dielectric layer 401 is omitted in the figure. However, it should be noted that the second dielectric layer 401 will actually cover the inner walls of all the third trenches 103 and all the fourth trenches 104 (in Fig.11 shall prevail).

[0129] In one embodiment, after step S302, the method for preparing the semiconductor structure further includes: forming a frame structure 403 on both sides of the stacked structure, such as Figure 12-13 shown.

[0130] Parts on both sides of the stacked structure may be removed by combining photolithography and etching, and then filled by deposition to form the frame structure 403. The frame structure 403 may be made of nitride material or oxide material, such as silicon oxide.

[0131] In one embodiment, the portion of the extension portion 302 away from the main body portion 301 is used as the first electrode. After the sacrificial layer 402 is used to fill the gap region of the stacked structure in step S30 and before step S40, as shown in FIG. Fig.14 As shown, the method for preparing the semiconductor structure also includes:

[0132] S31: removing the second dielectric layer 401 and the sacrificial layer 402 located on the surface of the first electrode to expose the surface of the first electrode.

[0133] S32: forming a capacitor dielectric layer and a second electrode in sequence on the exposed surface of the first electrode.

[0134] In one embodiment, Fig.15 As shown, the above step S31 includes:

[0135] S311: removing part of the sacrificial layer 402 between the first electrodes of the same layer to form a fifth trench 105 penetrating the stacked structure, the sidewalls of the fifth trench 105 exposing the alternating sacrificial layers 402 and the second dielectric layers 401 on opposite sides of the first electrodes of each layer.

[0136] like Figure 16-Figure 17 As shown, a photoresist layer can be first formed on the upper surface of the stacked structure, and then a patterned photoresist layer can be formed again through steps such as exposure and development to expose the gap area on both sides of the first electrode, and then a portion of the sacrificial layer 402 can be removed based on the patterned photoresist layer through an etching process to form a fifth groove 105.

[0137] S312 : performing transverse etching on each first dielectric layer 20 based on the fifth trench 105 to form a sixth trench 106 located between each first electrode layer.

[0138] like Figure 18-19 As shown, a suitable etching process may be used to complete the lateral etching process, such as a wet process or a steam etching process. Specifically, a corresponding etching liquid or etching gas may be introduced into the fifth groove 105, and then a difference in etching selectivity of each material layer may be utilized to selectively etch and remove a portion of the sacrificial layer 402 to form a lateral sixth groove 106.

[0139] In addition, after S312, combined with Figure 18-19 It can be seen that the surface of the first electrode is completely exposed.

[0140] In one embodiment, Fig. 20 As shown, the above step S32 includes:

[0141] S321 : forming a continuously distributed third dielectric layer 501 on the inner wall of the fifth trench 105 , the inner wall of the sixth trench 106 and the upper surface of the stacked structure.

[0142] like Figure 21-22 As shown, the material of the third dielectric layer 501 may include a dielectric material, such as a high-K material, and the third dielectric layer 501 is used as an isolation layer in the capacitor to separate the first electrode from the second electrode.

[0143] S322 : forming a conductive barrier layer 502 on the surface of the third dielectric layer 501 .

[0144] like Figure 21-22 As shown, the conductive barrier layer 502 may include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or conductive nitrides such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and may be formed by CVD, PVD, ALD and / or other suitable processes.

[0145] S323: depositing a conductive filling layer 503 in the fifth trench 105, in the sixth trench 106 and on the stacked structure; wherein the third dielectric layer 501 serves as a capacitor dielectric layer, and the conductive barrier layer 502 and the conductive filling layer 503 together constitute a second electrode.

[0146] like Figure 21-22 As shown, the material of the conductive filling layer 503 may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta) or other metals, and may be formed by CVD, PVD, ALD, electroplating or other suitable processes.

[0147] In addition, since the capacitor dielectric layer and the conductive filling layer 503 are relatively thin and are wrapped by the conductive filling layer 503, Fig.21 Only the capacitor dielectric layer is shown in FIG. The specific positions of the capacitor dielectric layer and the conductive filling layer 503 can be combined with Fig. 22 to confirm.

[0148] In addition, in some top view drawings, although the first electrode is completely wrapped by the conductive filling layer 503 (for example Fig.21), but in order to more clearly distinguish the position of the first electrode, the position of the first electrode is still marked. In the actual preparation process, the specific structure of the semiconductor structure prepared by the preparation method of the semiconductor structure of the present invention can be based on the cross-sectional structure schematic diagram (for example Fig. 22 ), and the top view schematic diagram can help understand the specific location of each structure, so as to more clearly understand the 3D morphology of the semiconductor structure provided by the present invention.

[0149] Of course, in other suitable preparation processes, the second electrode may also be other single-layer conductive materials, which is not limited in this embodiment.

[0150] In one embodiment, after step S32, Fig.23 As shown, the method for preparing the semiconductor structure also includes:

[0151] S33 : sequentially removing the conductive filling layer 503 , the conductive barrier layer 502 and the third dielectric layer 501 that partially cover the upper surface of the stacked structure to expose a portion of the surface of the first dielectric layer 20 corresponding to the channel region 303 .

[0152] like Figure 24-25 As shown, an etching process can be used to sequentially remove the conductive filling layer 503, the conductive barrier layer 502 and the third dielectric layer 501 that partially cover the upper surface of the stacked structure. In the etching and removal process, the first dielectric layer 20 is used as the etching end point. When the partial surface of the first dielectric layer 20 corresponding to the channel region 303 is exposed, the etching can be stopped, which can facilitate the preparation steps of the channel region 303 in the subsequent process.

[0153] S34: depositing a filling layer 404 on the surface of the obtained structure.

[0154] like Figure 26-Figure 27 As shown, the material of the filling layer 404 can be the same as that of the sacrificial layer 402, and both can be dielectric materials, such as silicon oxide. In some embodiments, the function of the filling layer 404 is the same as that of the sacrificial layer 402, and both play the role of supporting other structures or filling some gap areas. Therefore, in some preparation processes, the filling layer 404 can be equivalent to the sacrificial layer 402, and in some drawings, the filling layer 404 can also be directly regarded as the sacrificial layer 402 (it can be seen that in some drawings, the filling shape of the filling layer 404 is the same as the filling shape of the sacrificial layer 402). Of course, in other suitable preparation processes, the material of the filling layer 404 and the material of the sacrificial layer 402 can also be different, and the functions of the two can also be different.

[0155] in addition, Fig.26The filling layer 404 in the embodiment should be able to cover all surfaces of the obtained structure. However, in order to more conveniently display the positions of the main structures, Fig.26 The positions of the first electrode, the conductive filling layer 503 and other structures are shown in FIG. 5 (this is also reflected in other top view structure diagrams). However, a more accurate structure can be shown as Fig. 27 The cross-sectional structure diagram shown in shall prevail.

[0156] In step S40, refer to Figure 1 Step S40 in Figure 28-Figure 29 , a first trench 101 penetrating through each layer of the channel region 303 is formed in the stacked structure to remove the first dielectric layer 20 and the conductive layer 30 located in the channel region 303, and to remove a portion of the second dielectric layer 401 located on the two side surfaces of the first dielectric layer 20 opposite to each other along the first direction, and to retain a portion of the second dielectric layer 401 located on the two side surfaces of the extension portion 302 opposite to each other along the first direction; wherein, the sacrificial layers 402 and the second dielectric layers 401 alternately stacked in sequence are exposed on the two side walls of the first trench 101 opposite to each other along the first direction, and the position of each layer of the sacrificial layer 402 corresponds to the position of each layer of the first dielectric layer 20, and the position of each layer of the second dielectric layer 401 corresponds to the position of each layer of the conductive layer 30.

[0157] like Figure 28-Figure 29 As shown, the first direction can be Fig.28 The extension direction of the CC' interception line or the DD' interception line in the figure can be that a photoresist layer is first formed on the upper surface of the stacked structure, and then a patterned photoresist layer is formed again through steps such as exposure and development, and then the part of the stacked structure located in the channel area 303 is removed based on the patterned photoresist layer through an etching process to form a first groove 101 that penetrates each layer of the channel area 303.

[0158] In step S50, refer to Figure 1 Step S50 in Figure 30-Figure 31 , a channel material layer 601 , an isolation dielectric material layer 602 and a gate conductive layer 603 are sequentially deposited on the inner wall of the first trench 101 , and the gate conductive layer 603 fills up the first trench 101 .

[0159] The material of the channel material layer 601 may include a metal oxide material, such as indium gallium zinc oxide (IGZO), ITO, IWO, IGO or IZO (indium-zinc-oxide) and the like.

[0160] The material of the isolation dielectric material layer 602 may include a suitable dielectric material, for example, a high-K dielectric material.

[0161] The material of the gate conductive layer 603 may include ITO, polysilicon, metal material or other suitable conductive materials.

[0162] In addition, it can be understood that although the steps of forming the capacitor (eg, steps S31 - S32 ) are performed before step S50 in the present figure, in other suitable preparation processes, the steps of forming the capacitor may also be performed after step S50 .

[0163] In step S60, refer to Figure 1 Step S60 in Figure 32-Figure 33 A second trench 102 penetrating the sacrificial layer 402 is formed in the gap region on opposite sides of the channel region 303 along the first direction, and the sacrificial layers 402 and the second dielectric layer 401 alternately stacked in sequence are exposed on opposite side walls of the second trench 102 along the first direction.

[0164] like Figure 32-Figure 33 As shown, a photoresist layer can be first formed on the upper surface of the stacked structure, and then a patterned photoresist layer can be formed again through steps such as exposure and development to expose the filling layer 404 covering the surface of the channel area 303, and then a portion of the filling layer 404 can be removed based on the patterned photoresist layer through an etching process to form a second groove 102 that penetrates each layer of the channel area 303.

[0165] At this time, in step S50, the channel material layer 601, the isolation dielectric material layer 602 and the gate conductive layer 603 have been sequentially deposited in the channel region 303, and the second trench 102 is located in the gap region on both sides of the channel region 303. Fig.11 and compare with Figure (c) in Fig.33As can be understood from Figure (c), it is precisely because the second dielectric layer 401 is used to cover the surface of the conductive layer 30 and the second dielectric layer 401 alternately, that when forming the vertical second trench 102, the sidewall of the second trench 102 will present the morphology of the sacrificial layer 402 alternately stacked in sequence and the second dielectric layer 401 located on the opposite sides of each layer of the channel region 303. Among them, the position of the second dielectric layer 401 located on the sidewall of the second trench 102 can correspond to the position of each layer of the conductive layer 30, and the position of the sacrificial layer 402 located on the sidewall of the second trench 102 can correspond to the position of each layer of the first dielectric layer 20. Or, in other words, after executing step S50, a continuously distributed channel material layer 601 is deposited on the inner wall of the first trench 101, and only the channel material layer 601 corresponding to each layer of the conductive layer 30 is the target structure and needs to be retained (that is, only the channel material layer 601 in each layer of the channel region 303 needs to be retained), and the channel material layer 601 corresponding to each layer of the first dielectric layer 20 needs to be removed. Otherwise, the channel material layer 601 will be completely connected, resulting in the formation of a parasitic transistor.

[0166] In one embodiment, the above step S60 includes: using a steam etching process to remove the sacrificial layer 402 located on the sidewall of the second trench 102. By directly passing the corresponding etching steam into the second trench 102, the sacrificial layer 402 can be easily removed, so that the corresponding channel material layer 601 of each layer of the first dielectric layer 20 is exposed. Since the channel material layer 601 corresponding to each layer of the conductive layer 30 is protected by the second dielectric layer 401, it will not be exposed.

[0167] In step S70, refer to Figure 1 Step S70 in Figure 34-Figure 37 , remove the sacrificial layer 402 located on the side wall of the second trench 102, and remove the channel material layer 601 and the corresponding isolation dielectric material layer 602 in contact with the sacrificial layer 402 to obtain an isolation dielectric layer 612 and a channel layer 611 surrounding the side wall of the gate conductive layer 603 and in contact with the second dielectric layer 401, and the isolation dielectric layer 612 and the channel layer 611 are both located between the gate conductive layer 603 and the conductive layer 30.

[0168] like Figure 34-Figure 35 , which is a schematic diagram of the structure obtained after the sacrificial layer 402 located on the sidewall of the second trench 102 is removed.

[0169] like Figure 36-Figure 37As shown, selective etching can continue to be used to remove only the exposed portion of the channel material layer 601 and the portion of the isolation dielectric material layer 602 corresponding to the exposed portion of the channel material layer 601. Since the channel material layer 601 corresponding to each conductive layer 30 is protected by the second dielectric layer 401, it will not be etched away.

[0170] In addition, combined Fig.37 Figure (a) and Fig.11 As can be seen from FIG. 6A , by selectively removing the channel material layer 601 , the first electrode of the capacitor is not etched away, thereby ensuring the integrity of the first electrode and increasing the available area of ​​the capacitor.

[0171] In one embodiment, the step S70 includes: removing the exposed portion of the channel material layer 601 and the portion of the isolation dielectric material layer 602 corresponding to the exposed portion of the channel material layer 601 by a wet etching process.

[0172] The use of wet etching can execute step S70 faster and more conveniently to selectively remove the channel material layer 601 and the isolation dielectric material layer 602 corresponding to each layer of the first dielectric layer 20, while retaining the channel material layer 601 and the isolation dielectric material layer 602 corresponding to each layer of the conductive layer 30, thereby obtaining the target structure. At the same time, the preparation process of the wet etching process is simple and can save process costs.

[0173] In one embodiment, after step S70 , the method for preparing the semiconductor structure further includes: filling the second trench 102 with a filling layer 404 .

[0174] The filling layer 404 can support and protect the target structure, so the material of the filling layer 404 can be the same as that of the sacrificial layer 402. Alternatively, in other suitable preparation processes, the material of the filling layer 404 can also be different from that of the sacrificial layer 402, which is not limited in this embodiment.

[0175] The present invention also provides a semiconductor structure, such as Figure 38-Figure 39 As shown, it includes: a substrate 10, a stacked structure, a second dielectric layer 401 and a device structure.

[0176] The material of the substrate 10 may be any suitable substrate material known in the art, for example, at least one of the following materials: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or ceramic substrates such as alumina, quartz or glass substrates, etc., which are not limited in this embodiment.

[0177] The stacked structure is located on the substrate 10, and the stacked structure includes a first dielectric layer 20 and a conductive layer 30 stacked in sequence from bottom to top. Each conductive layer 30 includes: a main body 301 extending along a first direction and a plurality of extensions 302 arranged at intervals along the first direction. Each extension 302 is located on two opposite sides of the main body 301. The main body 301 is integrally connected to each extension 302, and the portion where the extension 302 is connected to the main body 301 serves as a channel region 303.

[0178] The material of the first dielectric layer 20 may include any suitable dielectric material, such as an oxide material or a nitride material. Further, the oxide material may include at least one of silicon oxide, silicon oxynitride, silicon oxycarbide and silicon oxynitride and carbonitride; the nitride material may include silicon nitride, etc.

[0179] The material of the conductive layer 30 may include metal materials such as tungsten, copper, gold, titanium, silver, aluminum, etc., or may include a multilayer metal composed of the above metal materials, or may include a metal alloy, etc., which is not limited in this embodiment.

[0180] The second dielectric layer 401 covers two opposite sides of each channel region 303 along the first direction.

[0181] Optional, such as Figure 38-Figure 39 As shown, the top of the stacked structure may further include a covering dielectric layer 40, and the material of the covering dielectric layer 40 may include any suitable dielectric material, such as an oxide material or a nitride material. Further, the oxide material may include at least one of silicon oxide, silicon oxynitride, silicon oxycarbide, and silicon oxynitride-carbon; the nitride material may include silicon nitride, etc.

[0182] Furthermore, the material of the cover dielectric layer 40 may be different from the material of the first dielectric layer 20 . For example, the material of the first dielectric layer 20 may be silicon oxide, and the material of the cover dielectric layer 40 may be silicon nitride.

[0183] The device structure runs through each layer of the channel region 303, and the device structure includes a gate conductive layer 603, multiple layers of isolation dielectric layers 612 surrounding the side walls of the gate conductive layer 603, and multiple layers of channel layers 611 corresponding to the surface of the isolation dielectric layer 612. Each layer of the isolation dielectric layer 612 and each layer of the channel layer 611 are located between the gate conductive layer 603 and the conductive layer 30, and each layer of the channel layer 611 is in contact with each layer of the second dielectric layer 401.

[0184] The material of the channel layer 611 may include a metal oxide material, such as indium gallium zinc oxide (IGZO), ITO, IWO, IGO or IZO (indium-zinc-oxide) and the like.

[0185] The material of the isolation dielectric layer 612 may include a suitable dielectric material, for example, a high-K dielectric material.

[0186] The material of the gate conductive layer 603 may include ITO, polysilicon, metal material or other suitable conductive materials.

[0187] The semiconductor structure comprises a substrate 10, a stacked structure, a second dielectric layer 401 and a device structure. The stacked structure is located on the substrate 10, and the stacked structure comprises a first dielectric layer 20 and a conductive layer 30 stacked in sequence from bottom to top, and each conductive layer 30 comprises: a main body 301 extending along a first direction and a plurality of extensions 302 arranged at intervals along the first direction, each extension 302 is located on two opposite sides of the main body 301, the main body 301 is integrally connected with each extension 302, and the portion where the extension 302 is connected to the main body 301 serves as a channel region 303. The second dielectric layer 401 covers two opposite sides of each channel region 303 along the first direction. The device structure runs through each layer of the channel region 303, and the device structure includes a gate conductive layer 603, multiple layers of channel layers 611 surrounding the sidewalls of the gate conductive layer 603, and multiple layers of isolation dielectric layers 612 corresponding to the surface of the channel layer 611. Each layer of the channel layer 611 and each layer of the isolation dielectric layer 612 are located between the gate conductive layer 603 and the conductive layer 30, and each layer of the isolation dielectric layer 612 is in contact with each layer of the second dielectric layer 401. Since the channel layer 611 is formed by selectively removing the channel material layer 601, the extension portion 302 is not etched away during this process, thereby ensuring the integrity of the extension portion 302. In the subsequent process, a portion of the extension portion 302 can be used as the first electrode of the capacitor in the memory, thereby increasing the available area of ​​the capacitor.

[0188] In one embodiment, Figure 38-Figure 39 As shown, the semiconductor structure also includes a capacitor, which includes a first electrode, a capacitor dielectric layer and a second electrode sequentially covering the surface of the first electrode, and the portion of the extension portion 302 away from the main body portion 301 serves as the first electrode of the capacitor.

[0189] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0190] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, It is characterized in that include: providing a substrate; A stacked structure is formed on the substrate, the stacked structure comprising a first dielectric layer and a conductive layer stacked in sequence from bottom to top, each conductive layer comprising: a main body extending along a first direction and a plurality of extensions arranged at intervals along the first direction, each of the extensions being located on two opposite sides of the main body, the main body being integrally connected to each of the extensions, and a portion of the extension connected to the main body being used as a channel region; wherein a width of the extension along the first direction is greater than a width of the first dielectric layer located between the extensions along the first direction; forming a continuously distributed second dielectric layer on the exposed surface of the stacked structure, and filling the gap area of ​​the stacked structure with a sacrificial layer; A first groove penetrating through the channel region of each layer is formed in the stacked structure to remove the first dielectric layer and the conductive layer located in the channel region, and a portion of the second dielectric layer located on the two opposite sides of the first dielectric layer along the first direction, and a portion of the second dielectric layer located on the two opposite sides of the extension along the first direction is retained; wherein the sacrificial layer and the second dielectric layer alternately stacked in sequence are exposed on the two opposite side walls of the first groove along the first direction, and the position of each sacrificial layer corresponds to the position of each first dielectric layer, and the position of each second dielectric layer corresponds to the position of each conductive layer; Depositing a channel material layer, an isolation dielectric material layer and a gate conductive layer on the inner wall of the first trench in sequence, wherein the gate conductive layer fills the first trench; forming a second groove penetrating the sacrificial layer in the gap region on two opposite sides of the channel region along the first direction, wherein the sacrificial layer and the second dielectric layer alternately stacked in sequence are exposed on two opposite sidewalls of the second groove along the first direction; The sacrificial layer located on the sidewall of the second trench is removed, and the channel material layer and the corresponding isolation dielectric material layer in contact with the sacrificial layer are removed to obtain an isolation dielectric layer and a channel layer surrounding the sidewall of the gate conductive layer and in contact with the second dielectric layer, wherein the isolation dielectric layer and the channel layer are both located between the gate conductive layer and the conductive layer.

2. The method for preparing a semiconductor structure according to claim 1, It is characterized in that The removing the sacrificial layer located on the sidewall of the second trench comprises: Using a steam etching process to remove the sacrificial layer located on the sidewall of the second trench; The removing of the exposed portion of the channel material layer and the portion of the isolation dielectric material layer corresponding to the exposed portion of the channel material layer comprises: A wet etching process is adopted to remove the exposed portion of the channel material layer and the portion of the isolation dielectric material layer corresponding to the exposed portion of the channel material layer.

3. The method for preparing a semiconductor structure according to claim 1, It is characterized in that After removing the channel material layer and the isolation dielectric material layer in contact with the sacrificial layer, the method further includes: The second groove is filled with a filling layer.

4. The method for preparing a semiconductor structure according to claim 1, It is characterized in that The forming of a stacked structure on the substrate comprises: forming an initial stacked structure on the substrate, the initial stacked structure comprising a first dielectric material layer and a conductive material layer stacked sequentially from bottom to top; Etching and removing a portion of the initial stacked structure to form a third trench penetrating the initial stacked structure, wherein the sidewall of the third trench exposes the side surfaces of each layer of the first dielectric material; and the extensions of the same layer are separated by the third trench; Lateral etching is performed based on the third trench to form a fourth trench located between each layer of the conductive material, so that the width of the extension portion along the first direction is greater than the width of the first dielectric layer along the first direction.

5. The method for preparing a semiconductor structure according to claim 4, It is characterized in that The method of forming a continuously distributed second dielectric layer on the exposed surface of the stacked structure and filling the gap area of ​​the stacked structure with a sacrificial layer comprises: forming a continuously distributed second dielectric layer on the inner walls of the third trench and the fourth trench; The sacrificial layer is filled in the third trench and the fourth trench.

6. The method for preparing a semiconductor structure according to claim 1, It is characterized in that The portion of the extension away from the main body is used as a first electrode, and after the gap region of the stacked structure is filled with a sacrificial layer, before a first trench penetrating the channel region of each layer is formed in the stacked structure, the method further includes: removing the second dielectric layer and the sacrificial layer located on the surface of the first electrode to expose the surface of the first electrode; A capacitor dielectric layer and a second electrode are sequentially formed on the exposed surface of the first electrode.

7. The method for preparing a semiconductor structure according to claim 6, It is characterized in that The removing of the second dielectric layer and the sacrificial layer located on the surface of the first electrode to expose the surface of the first electrode includes: A fifth groove penetrating the sacrificial layer is formed in the gap region on two opposite sides of the first electrode along the first direction, wherein the sidewalls of the fifth groove expose the sacrificial layer and the second dielectric layer located on two opposite sides of each layer of the first electrode in sequence; Lateral etching is performed based on the fifth trench to form a sixth trench located between the first electrodes of each layer.

8. The method for preparing a semiconductor structure according to claim 7, It is characterized in that The capacitor dielectric layer and the second electrode are sequentially formed on the surface exposed by the first electrode, comprising: forming a continuously distributed third dielectric layer on the inner wall of the fifth trench, the inner wall of the sixth trench and the upper surface of the stacked structure; forming a conductive barrier layer on the surface of the third dielectric layer; A conductive filling layer is deposited in the fifth trench, in the sixth trench and on the stacked structure; wherein the third dielectric layer serves as the capacitor dielectric layer, and the conductive barrier layer and the conductive filling layer together constitute the second electrode.

9. A semiconductor structure, It is characterized in that include: substrate; A stacked structure is located on the substrate, the stacked structure includes a first dielectric layer and a conductive layer stacked in sequence from bottom to top, each conductive layer includes: a main body extending along a first direction and a plurality of extensions arranged at intervals along the first direction, each of the extensions is located on two opposite sides of the main body, the main body is integrally connected to each of the extensions, and a portion of the extension connected to the main body serves as a channel region; A second dielectric layer covering two opposite sides of the channel region of each layer along the first direction; A device structure that runs through the channel regions of each layer, the device structure includes a gate conductive layer, multiple isolation dielectric layers surrounding the side walls of the gate conductive layer, and multiple channel layers corresponding to the surface of the isolation dielectric layer. Each layer of the isolation dielectric layer and each layer of the channel layer are located between the gate conductive layer and the conductive layer, and each layer of the channel layer is in contact with each layer of the second dielectric layer.

10. The semiconductor structure according to claim 9, It is characterized in that The semiconductor structure further includes a capacitor, which includes a first electrode, a capacitor dielectric layer and a second electrode sequentially covering the surface of the first electrode, and a portion of the extension away from the main body serves as the first electrode of the capacitor.

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