Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof, and the method comprises the steps: providing a substrate, and forming a first stack structure on the substrate, the first stack structure comprising a plurality of alternately formed doped layers and sacrificial layers; etching the first stack structure to form a word line hole penetrating to the substrate; removing the sacrificial layer through the word line hole, and forming a metal material layer between the adjacent doped layers; carrying out heat treatment to enable the doping layer to react with the metal material layer so as to be converted into a metallide film layer; filling a first isolation layer between the adjacent metallization film layers; and forming a transistor structure based on the word line hole. The metallization film layer formed based on the preparation method of the semiconductor structure is good in compactness and conductivity and can bear relatively large driving current, so that the transistor structure and the process thereof are more optimized.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor device manufacturing, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0004] Based on this, it is necessary to provide a semiconductor structure and a method for preparing the same.

[0005] In order to achieve the above objectives, on the one hand, the present application provides a method for preparing a semiconductor structure, comprising:

[0006] Providing a substrate, and forming a first stacking structure on the substrate, wherein the first stacking structure includes a plurality of doped layers and sacrificial layers formed alternately;

[0007] Etching the first stack structure to form a word line hole penetrating into the substrate;

[0008] removing the sacrificial layer through the word line hole and forming a metal material layer between adjacent doping layers;

[0009] Through heat treatment, the doping layer reacts with the metal material layer to be transformed into a metallization film layer;

[0010] Filling a first isolation layer between adjacent metallization film layers;

[0011] Based on the word line hole, a transistor structure is formed.

[0012] The method for preparing the semiconductor structure described above converts the doped layer into a metallized film layer by heat treatment, and forms a first isolation layer between the metallized film layers, so that the transistor structure can be prepared based on the stacked structure formed by the metallized film layer and the first isolation layer. Since the metallized film layer formed by the method for preparing the semiconductor structure of the present application has good compactness and conductivity, it can carry a large driving current, thereby making the transistor structure and its process more optimized.

[0013] In one embodiment, the material of the doping layer has the same crystal lattice as the material of the sacrificial layer.

[0014] In this embodiment, the first stacked structure is formed by alternating doped layers and sacrificial layers. The material lattices of the doped layers and the sacrificial layers are the same, the two are relatively close, the interlayer stress is small, and a higher stacked semiconductor structure can be achieved. At the same time, the doped layers and sacrificial layers with similar materials have stronger etching feasibility, so that the side walls of the word line holes formed are not easy to bend and deform, and have better verticality.

[0015] In one embodiment, the doped layer includes doped polysilicon, and the metallization film layer includes metal silicide.

[0016] In one embodiment, removing the sacrificial layer through the word line hole and forming a metal material layer between adjacent doping layers includes:

[0017] removing the sacrificial layer through the word line hole;

[0018] Filling the metal material layer in the area between adjacent doping layers;

[0019] After the heat treatment is performed to make the doping layer react with the metal material layer to form a metallization film layer, the method comprises:

[0020] The remaining metal material layer is removed.

[0021] In one embodiment, filling a first isolation layer between adjacent metallization film layers comprises:

[0022] The first isolation layer having an air gap therein is formed between adjacent metallization film layers.

[0023] In one embodiment, the first isolation layer includes a first isolation sublayer, a second isolation sublayer and a third isolation sublayer which are stacked.

[0024] Filling a first isolation layer between adjacent metallization film layers comprises:

[0025] A first isolation sublayer, a second isolation sublayer and a third isolation sublayer are formed between adjacent metallization film layers, and the third isolation sublayer is located between the first isolation sublayer and the second isolation sublayer.

[0026] In one embodiment, after forming a transistor structure based on the word line hole, the method includes:

[0027] The third isolation sublayer is removed to form an air gap.

[0028] In one embodiment, a transistor structure is formed based on the word line hole, including:

[0029] Etching each metallization film layer through the word line hole to form a side hole surrounding the word line hole, wherein the side hole separates the metallization film layers of the same layer;

[0030] Sequentially forming a channel layer material and a gate dielectric material layer on the surface of the structure obtained after forming the side holes;

[0031] Removing the channel layer material and the gate dielectric material layer outside the side hole to form a channel layer and a gate dielectric layer, and exposing the first isolation layer;

[0032] removing the third isolation sublayer of the first isolation layer through the word line hole to form an air gap;

[0033] A word line is formed in the word line hole.

[0034] In one embodiment, before removing the channel layer material and the gate dielectric material layer outside the side hole, the method includes:

[0035] forming a conductive protective material layer covering the surface of the gate dielectric material layer;

[0036] The conductive protection material layer outside the side hole is removed to form a conductive protection layer in the side hole.

[0037] In one embodiment, a substrate is provided, and a first stacking structure is formed on the substrate, including:

[0038] providing a substrate;

[0039] By epitaxial process, doping material layers and sacrificial material layers are alternately stacked on the substrate;

[0040] Etching the doping material layer and the sacrificial material layer to form the first stacked structure, wherein the first stacked structure includes a first main body and a first branch, wherein the first main body extends along a first direction, the first branch extends along a second direction, the second direction intersects the first direction, and a plurality of the first branch are arranged at intervals along the first direction and are disposed on both sides of the first main body in the second direction;

[0041] Etching the first stack structure to form a word line hole penetrating the substrate includes:

[0042] An end of the first branch portion close to the first trunk portion is etched to form the word line hole.

[0043] The present application also provides a semiconductor structure, comprising:

[0044] substrate;

[0045] A second stacked structure, located on the substrate, comprises a plurality of alternately arranged metallized film layers and a first isolation layer, wherein the metallized film layers are film layers formed by reaction and conversion of a doping layer and a metal material layer;

[0046] At least one transistor structure includes a word line hole extending through the substrate.

[0047] In one embodiment, the metallization film layer includes metal silicide.

[0048] In one embodiment, the first isolation layer has an air gap inside.

[0049] In one embodiment, the first isolation layer includes a first isolation sublayer and a second isolation sublayer, the first isolation sublayer is located on the lower surface of the metallization film layer of the upper layer, the second isolation sublayer is located on the upper surface of the metallization film layer of the lower layer, and there is an air gap between the first isolation sublayer and the second isolation sublayer.

[0050] In one embodiment, the second stacking structure further includes:

[0051] A side hole, connected to and surrounding the word line hole, and arranged in the same layer as the metallization film layer;

[0052] The transistor structure comprises:

[0053] A channel layer, located in the side hole;

[0054] a gate dielectric layer, located in the side hole and located on a surface of the channel layer away from the side hole;

[0055] A conductive protection layer, located in the side hole and on a side of the gate dielectric layer away from the channel layer;

[0056] The word line is located in the word line hole.

[0057] In one embodiment, the second stacking structure includes a second main body and a second branch portion, the second main body extends along a first direction, the second branch portion extends along a second direction, the second direction intersects the first direction, a plurality of second branch portions are arranged at intervals along the first direction on both sides of the second main body along the second direction, and the word line is located at one end of the second branch portion close to the second main body. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0059] Figure 1 is a flow chart of a method for preparing a semiconductor structure provided in an embodiment;

[0060] Figure 2 is a schematic top view of a semiconductor structure provided in an embodiment;

[0061] Figures 3 to 18 A schematic diagram of the cross-sectional structure corresponding to the aa, bb, cc and dd directions of the structure obtained in different steps of the method for preparing a semiconductor structure provided in an embodiment;

[0062] Fig.19 A schematic diagram of a cross-sectional structure corresponding to the aa direction in a method for preparing a semiconductor structure provided in an embodiment;

[0063] Figures 20 to 30 It is a schematic diagram of the three-dimensional structure of the structure obtained in different steps of the method for preparing a semiconductor structure provided in an embodiment.

[0064] Description of reference numerals: 100 - doping layer, 200 - sacrificial layer, 310 - first mask layer, 320 - second mask layer, 330 - third mask layer, 340 - first patterned photoresist, 350 - second patterned photoresist, 400 - metal material layer, 500 - metallization film layer, 600 - first isolation layer, 610 - first isolation sublayer, 620 - second isolation sublayer, 630 - third isolation sublayer, 71 0-word line hole, 720-side hole, 810-channel layer, 811-channel layer material, 820-gate dielectric layer, 821-gate dielectric material layer, 830-conductive protection layer, 831-conductive protection material layer, 840-word line, 910-storage unit, 920-capacitor structure, 930-bit line, 940-first main stem, 950-first branch, 960-second main stem, 970-second branch. DETAILED DESCRIPTION

[0065] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0066] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0067] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0068] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0069] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0070] In one embodiment, see Figure 1, a method for preparing a semiconductor structure is provided, comprising the following steps:

[0071] Step S100, providing a substrate, and forming a first stacking structure on the substrate, the first stacking structure comprising a plurality of doped layers 100 and sacrificial layers 200 formed alternately;

[0072] Step S200, etching the first stack structure to form a word line hole 710 penetrating to the substrate;

[0073] Step S300 , removing the sacrificial layer 200 through the word line hole 710 , and forming a metal material layer 400 between adjacent doping layers 100 ;

[0074] Step S400, heat treatment is performed to allow the doping layer 100 to react with the metal material layer 400 to be transformed into a metallization film layer 500;

[0075] Step S500, filling a first isolation layer 600 between adjacent metallization film layers 500;

[0076] Step S600 , forming a transistor structure based on the word line hole 710 .

[0077] In step S100, the base may include only the substrate, or may include the substrate and the film layer formed on the substrate. The substrate may be, for example, a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. The substrate may support the entire semiconductor structure.

[0078] A first stacking structure is formed on the base. Specifically, the first stacking structure may be formed directly on the substrate, or may be formed on a film layer on the substrate.

[0079] The first stacked structure may include a plurality of alternately formed doped layers 100 and sacrificial layers 200. The number of sacrificial layers 200 and doped layers 100 is not limited here, and may be selected according to actual needs, for example, Figure 5 As shown, the first stacked structure can be formed by alternating three sacrificial layers 200 and three doping layers 100. At the same time, the thickness of the sacrificial layer 200 and the doping layer 100 is not limited here, and they can be deposited as needed. For example, a doping layer 100 can be deposited with a thickness of 50nm, and a sacrificial layer 200 can be deposited with a thickness of 50nm.

[0080] In step S200, refer to Figures 6 to 9 as well as Figure 22 to Figure 24, the first stacked structure is etched to form a word line hole 710 in the first stacked structure, and the word line hole 710 penetrates the first stacked structure and extends to the surface of the substrate. As an example, a first mask layer 310 and a first photoresist layer can be formed on the first stacked structure in sequence; then the first photoresist layer is patterned to form a first patterned photoresist 340. The first patterned photoresist 340 has an opening, and the opening defines the position and shape of the word line hole 710, and then the pattern of the first patterned photoresist 340 is transferred to the first mask layer 310 to form a first patterned mask layer. Finally, the first stacked structure is etched based on the first patterned mask layer to form the word line hole 710.

[0081] In step S300, refer to Fig.10 , Fig.11 , Fig.25 as well as Fig.26 , the sacrificial layer 200 in the first stacked structure is removed through the word line hole 710 , and a metal material layer 400 is formed between adjacent doping layers 100 .

[0082] As an example, the metal material layer 400 may be formed by an atomic layer deposition (ALD) process, and the metal material layer 400 may be made of cobalt (Co) metal material.

[0083] In addition, after the metal material layer 400 is formed, it can be etched to re-form the word line hole 710. Of course, it is also possible not to etch it, which is not limited here.

[0084] In step S400, refer to Fig.12 as well as Fig. 27 , through heat treatment, the doping layer 100 reacts with the metal material layer 400, thereby converting the doping layer 100 into a metallization film layer 500. As an example, the metallization film layer 500 includes metal silicide. Specifically, when the metal material layer 400 is made of cobalt (Co) metal material, the metal silicide is cobalt silicon (SiCo).

[0085] In step S500, refer to Fig.13 , Fig.29 as well as Fig.30 , a first isolation layer 600 is filled between adjacent metallization film layers 500 .

[0086] A first isolation material layer may be first formed between adjacent metallization film layers 500 and in the word line hole 710 . Then, the first isolation material layer in the word line hole 710 may be etched, and the remaining first isolation material layer forms the first isolation layer 600 .

[0087] In step S600 , a transistor structure is formed based on the word line hole 710 .

[0088] The transistor structure may include a source, a drain, and a gate. The source and the drain may be formed based on the metallization film layer 500 , and the gate may be formed in the word line hole 710 .

[0089] In this embodiment, the doped layer 100 is transformed into a metallization film layer 500 by heat treatment, and a first isolation layer 600 is formed between the metallization film layers 500, so that a transistor structure can be prepared based on the stacked structure formed by the metallization film layer 500 and the first isolation layer 600. Since the metallization film layer 500 formed by the method for preparing the semiconductor structure of the present application has good compactness and conductivity, it can carry a large driving current, thereby making the transistor structure and its process more optimized.

[0090] In one embodiment, the material of the doping layer 100 and the material of the sacrificial layer 200 may have the same lattice.

[0091] As an example, the material of the doping layer 100 includes but is not limited to silicon (Si). Specifically, heavily doped polysilicon can be used as the doping layer 100 to improve the conductivity of the subsequently formed device. The material of the sacrificial layer 200 can be, for example, silicon germanium (SiGe).

[0092] In this embodiment, the first stacked structure is formed by alternating doped layers 100 and sacrificial layers 200. The doped layers 100 and sacrificial layers 200 have the same material lattice, are relatively close to each other, and have low interlayer stress, so that a higher stacked semiconductor structure can be achieved. At the same time, the doped layers 100 and sacrificial layers 200 with similar materials have stronger etching feasibility, so that the sidewalls of the formed word line holes 710 are not easy to bend and deform, and have better verticality.

[0093] In one embodiment, step S300 includes:

[0094] Step S310, removing the sacrificial layer 200 through the word line hole 710;

[0095] Step S320 , filling the area between adjacent doping layers 100 with the metal material layer 400 ;

[0096] Step S400 includes:

[0097] Step S410 , removing the remaining metal material layer 400 .

[0098] In step S310, refer to Fig.10 as well as Fig.25As an example, the sacrificial layer 200 may be removed by wet etching, and an etching solution may be injected through the word line hole 710 to laterally etch the sacrificial layer 200. Specifically, the etching solution may be hydrofluoric acid (HF), hydrogen peroxide (H 2 O 2 ) and acetic acid (CH 3 COOH) mixed solution.

[0099] In step S320, refer to Fig.11 as well as Fig.26 , the area between the adjacent doping layers 100 is filled with the metal material layer 400 .

[0100] As an example, an atomic layer deposition (ALD) process may be used to form a metal material layer 400 between adjacent doped layers 100 and in the word line hole 710. Then, the metal material layer 400 in the word line hole 710 is etched and removed, and the metal material layer 400 between adjacent doped layers 100 is retained.

[0101] The area between adjacent doping layers 100 is filled with the metal material layer 400 to ensure that the doping layer 100 is completely formed.

[0102] The metal material layer 400 may be made of, but is not limited to, cobalt (Co) metal material.

[0103] In step S410, refer to Fig.12 as well as Fig.28 After the heat treatment, the remaining metal material layer 400 is removed. Since the metal material layer 400 fills the area between the adjacent doping layers 100, its thickness is relatively thick. Therefore, the doping layer 100 may not react with the doping layer 100 completely, that is, part of the metal material layer 400 may remain after the heat treatment. Therefore, it is necessary to remove the excess metal material layer 400. As an example, wet etching can be used to remove the excess metal material layer 400, and the etching solution can be selected from but not limited to monohydrated ammonia (NH 3 H 2 O).

[0104] In this embodiment, the area between adjacent doping layers 100 is filled with the metal material layer 400, and the thickness of the metal material layer 400 is relatively thick. When the thicker metal material layer 400 reacts with the doping layer 100 after heat treatment, the reaction between the two can be ensured to be more complete, thereby facilitating the doping layer 100 to completely form a metallization film layer 500 with better conductive properties.

[0105] In one embodiment, step S500 includes:

[0106] In step S510 , a first isolation layer 600 having an air gap therein is formed between adjacent metallization film layers 500 .

[0107] As an example, the first isolation layer 600 may be formed by an atomic layer deposition (ALD) process. Since the atomic layer deposition process is easy to deposit a film at a corner, an air gap is easily formed in the first isolation dielectric layer formed by the atomic layer deposition process. Since the dielectric constant of air is 1, the formation of the air gap helps to reduce the parasitic capacitance between adjacent metallization film layers 500.

[0108] Of course, other feasible processes may also be used to form the first isolation layer 600 having an air gap therein. The process for forming the first isolation layer 600 is not limited herein.

[0109] In one embodiment, see Fig.19 The first isolation layer 600 includes a first isolation sublayer 610, a second isolation sublayer 620 and a third isolation sublayer 630 which are stacked, and step S500 includes:

[0110] In step S520 , a first isolation sublayer 610 , a second isolation sublayer 620 and a third isolation sublayer 630 are formed between adjacent metallization film layers 500 . The third isolation sublayer 630 is located between the first isolation sublayer 610 and the second isolation sublayer 620 .

[0111] When forming the first isolation layer 600, a first isolation material layer may be first deposited on the surface of the structure obtained after forming the metallization film layer 500. Then, the first isolation material layer is etched to remove the first isolation material layer outside the region between adjacent metallization film layers 500, and the first isolation material layer remaining between adjacent metallization film layers 500 forms a first isolation sublayer 610 and a second isolation sublayer 620. As an example, the first isolation sublayer 610 may be located on the lower surface of the upper metallization film layer 500, and the second isolation sublayer 620 may be located on the upper surface of the lower metallization film layer 500.

[0112] Afterwards, a third isolation material sublayer is deposited to fill the area between the first isolation sublayer 610 and the second isolation sublayer 620, and then the third isolation material sublayer outside the area between the first isolation sublayer 610 and the second isolation sublayer 620 is removed, and the third isolation material sublayer retained between the first isolation sublayer 610 and the second isolation sublayer 620 forms a third isolation sublayer 630.

[0113] As an example, the first isolation sublayer 610 and the second isolation sublayer 620 may both be formed of oxide, and the third isolation sublayer 630 may be formed of nitride.

[0114] In one embodiment, after step S600, the following steps are included:

[0115] Step S700 , removing the third isolation sublayer 630 to form an air gap.

[0116] After forming the transistor structure based on the word line hole 710 , the third isolation sublayer 630 may be removed to form an air gap. The dielectric constant of air is 1. The air gap helps to reduce the parasitic capacitance between adjacent metallization film layers 500 .

[0117] In this embodiment, after the transistor structure is formed, the third isolation sublayer 630 is removed, which prevents the relevant film layers of the transistor structure (such as the channel layer 810, the gate dielectric layer 820, the conductive protection layer 830 and the word line 840, especially the word line 840) from entering the removal area of ​​the third isolation sublayer 630 during the formation of the transistor structure, thereby ensuring the reliability of the transistor structure.

[0118] In one embodiment, step S600 includes:

[0119] Step S610, etching each metallization film layer 500 through the word line hole 710 to form a side hole 720 surrounding the word line hole 710, and the side hole 720 separates the metallization film layers 500 of the same layer;

[0120] Step S620, forming a channel layer material 811 and a gate dielectric material layer 821 in sequence on the surface of the structure obtained after forming the side hole 720;

[0121] Step S650, removing the channel layer material 811 and the gate dielectric material layer 821 outside the side hole 720 to form the channel layer 810 and the gate dielectric layer 820, and exposing the first isolation layer 600;

[0122] Step S660, removing the third isolation sublayer 630 of the first isolation layer 600 through the word line hole 710 to form an air gap;

[0123] In step S670 , a word line 840 is formed in the word line hole 710 .

[0124] In step S610, refer to Fig.14 , each metallization film layer 500 is etched through the word line hole 710 to form a side hole 720 , and the side hole 720 surrounds the word line hole 710 and separates the metallization film layers 500 of the same layer.

[0125] As an example, the metallization film layer 500 may be laterally hollowed out by wet etching to form a side hole 720, and the radius of the side hole 720 is 20nm to 25nm larger than the radius of the word line hole 710. The side hole 720 separates the metallization film layer 500 of the same layer, so that a part of the metallization film layer 500 serves as the source of the transistor structure, and another part serves as the drain of the transistor structure.

[0126] In step S620, refer to Fig.15 After forming the side hole 720, a channel layer material 811 and a gate dielectric material layer 821 are sequentially formed on the surface of the resulting structure. The channel layer material 811 covers the surface of the side hole 720, the surface of the word line hole 710 and the upper surface of the second stacked layer, and the gate dielectric layer 820 is formed on the surface of the channel layer material 811.

[0127] As an example, the channel layer material 811 can be formed by deposition and can be deposited to a thickness of 6 nm, and can be made of indium gallium zinc oxide (IGZO). The gate dielectric layer 820 can also be formed by deposition, and can be formed of a material with a high dielectric constant (such as aluminum oxide), and the deposition thickness can be 10 nm.

[0128] In step S650, refer to Fig.16 as well as Fig.17 , remove the channel layer material 811 and the gate dielectric material layer 821 outside the side hole 720, form the channel layer 810 and the gate dielectric layer 820, and expose the first isolation layer 600. Remove the channel layer material 811 and the gate dielectric material layer 821 on the surface of the word line hole 710 and the upper surface of the second stacked layer, so that the channel layer 810 and the gate dielectric layer 820 are formed in the side hole 720. At this time, the first isolation layer 600 is exposed, effectively reducing the parasitic MOS tube effect. The channel layer 810 serves as a channel of the transistor structure, providing a conductive channel for the source and drain of the transistor structure.

[0129] In step S660 , since the first isolation layer 600 is exposed, the third isolation sublayer 630 of the first isolation layer 600 can be removed through the word line hole 710 , and an air gap is formed between the first isolation sublayer 610 and the second isolation sublayer 620 .

[0130] In step S670, refer to Fig.18, forming word line 840 in word line hole 710. As an example, atomic layer deposition (ALD) may be used to deposit a metal diffusion barrier layer of 2nm to 5nm first; then word line 840 material is deposited in word line hole 710 and side hole 720, and word line 840 material fills word line hole 710; then, chemical mechanical polishing (CMP) is performed on word line 840 material to remove word line 840 material outside word line hole 710 to form word line 840. The diameter of word line 840 may be 25nm, and it may be made of indium tin oxide thin film (ITO).

[0131] In this embodiment, before forming the transistor structure, the third isolation sublayer 630 is removed. Since the word line hole 710 is not filled at this time, the removal of the third isolation sublayer 630 is more convenient and feasible.

[0132] In one embodiment, before step S650, the following steps are included:

[0133] Step S630, forming a conductive protection material layer 831 covering the surface of the gate dielectric material layer 821;

[0134] In step S640 , the conductive protection material layer 831 outside the side hole is removed to form a conductive protection layer in the side hole 720 .

[0135] See also Fig.15 Before removing the trench material outside the side hole 720 and the gate dielectric material layer 821 , a conductive protection layer 830 may be covered on the surface of the gate dielectric material layer 821 .

[0136] Specifically, see Fig.16 , firstly, a conductive protection material layer 831 covering the gate dielectric material layer 821 is formed, then the conductive protection material layer 831 located on the gate dielectric material layer 821 on the side wall of the word line hole 710 and the upper surface of the second stacked layer is removed, and the conductive protection material layer 831 located on the gate dielectric material layer 821 in the side hole 720 is retained, thereby forming a conductive protection layer 830. For example, the conductive protection layer 830 can be made of an indium tin oxide film (ITO), and its thickness can be 15 nm. At this time, the word line hole 710 is not filled, and a space with a diameter of 25 nm is left.

[0137] In one embodiment, step S100 includes:

[0138] Step S110, providing a substrate;

[0139] Step S120, forming a semiconductor doping material layer and a sacrificial material layer by stacking on the substrate through an epitaxial process;

[0140] Step S130, etching the semiconductor doping material layer and the sacrificial material layer to form a first stacked structure, the first stacked structure comprising a first main body 940 and a first branch 950, the first main body 940 extending along a first direction, the first branch 950 extending along a second direction, the second direction intersecting the first direction, a plurality of first branch 950 arranged at intervals along the first direction and disposed on both sides of the first main body 940 along the second direction;

[0141] Step S200 includes:

[0142] In step S210 , the first branch portion 950 is etched to form a word line hole 710 .

[0143] In step S120, refer to Figure 3 as well as Fig. 20 , through an epitaxial growth process, doping material layers and sacrificial material layers are alternately stacked on the substrate. As an example, a sacrificial material layer may be first deposited on the substrate, then a doping material layer may be deposited on the sacrificial material layer, and then another sacrificial material layer may be deposited on the doping material layer, and so on, to form multiple alternating sacrificial material layers and doping material layers.

[0144] In step S130, refer to Figure 4 , Figure 5 as well as Fig.21 , etching the doping material layer and the sacrificial material layer so that the etched structure forms a first stacked structure.

[0145] As an example, see Figure 4 When forming the first stacked structure, the second mask layer 320, the third mask layer 330 and the second photoresist layer may be sequentially formed on the uppermost doping material layer; then, the second photoresist layer is patterned to form a second patterned photoresist 350. The second patterned photoresist 350 defines the structure of the first stacked structure; then, the pattern of the second patterned photoresist 350 is transferred to the third mask layer 330 to form a third patterned mask layer; then, the second mask layer 320 is etched based on the pattern of the third patterned mask layer to form a second patterned mask layer; finally, the second patterned mask layer is used as a mask to etch and form the first stacked structure.

[0146] The second mask layer 320 may include an oxide film layer and a nitride film layer, both of which may be formed by deposition. The oxide film layer may be deposited to a thickness of 50 nm, and the nitride film layer may be deposited to a thickness of 20 nm. Specifically, the material of the oxide film layer may be silicon dioxide (SiO 2) material, and the material of the nitride film layer can be silicon nitride (SiN) material. The third mask layer 330 can be a carbon mask. In addition, a silicon oxynitride (SiON) film layer can be formed between the third mask layer 330 and the second photoresist layer.

[0147] The first stacking structure includes a first main body 940 and a first branch portion 950. The first main body 940 extends along a first direction, and the first branch portion 950 extends along a second direction. The first direction intersects with the second direction. A plurality of first branch portions 950 are arranged at intervals along the first direction and are arranged on both sides of the first main body 940 along the second direction.

[0148] In step S210 , the word line hole 710 is located at the first branch portion 950 . Since the two first branch portions 950 are symmetrically arranged based on the first trunk portion 940 , the two word line holes 710 located on the two symmetrical first branch portions 950 are also symmetrical based on the first trunk portion 940 .

[0149] After the above steps S100 to S500, the first stacking structure can be transformed into a second stacking structure including metallization film layers 500 and first isolation layers 600 arranged alternately. At this time, the first trunk 940 becomes the second trunk 960, and the first branch 950 becomes the second branch 970. Figure 2 The metallization film layer 500 located in the second main body 960 can form a bit line 930. In addition, the second branch 970 can also form a capacitor structure 920 on a side away from the second main body 960. The capacitor structure 920 can use the metallization film layer 500 as a lower electrode. The capacitor structure 920 and the transistor structure can form a storage unit 910.

[0150] The bit line 930 and the capacitor structure 920 are respectively located on both sides of the transistor structure in the second direction, and are respectively connected to the source and drain of the transistor structure. The second trunk 960 is symmetrically provided with two second branches 970 on both sides along the second direction, so that the same bit line 930 simultaneously supplies power to the storage units 910 on both sides.

[0151] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0152] In one embodiment, please refer to Fig.18 , also provides a semiconductor structure, including: a substrate, a second stacking structure and at least one transistor structure.

[0153] The substrate may include only the substrate, or may include the substrate and the film layer formed on the substrate. The substrate may be, for example, a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate or other III / V semiconductor substrates or II / VI semiconductor substrates. The substrate may support the entire semiconductor structure.

[0154] The second stacked structure is located on the substrate and includes a plurality of alternately arranged metallization film layers 500 and first isolation layers 600, wherein the metallization film layers 500 are film layers formed by the reaction of the doping layer 100 and the metal material layer 400. The number of the metallization film layers 500 and the first isolation layer 600 is not limited here and can be selected according to actual needs, for example, Fig.30 As shown, the second stacked structure may be formed by alternating three metallization film layers 500 and three first isolation layers 600 .

[0155] As an example, the metallization film layer 500 includes metal silicide. Specifically, when the metal material layer 400 is made of cobalt (Co) metal material, the metal silicide is cobalt silicon (SiCo).

[0156] In addition, the first isolation layer 600 may have an air gap inside. Since the dielectric constant of air is 1, the formation of the air gap helps to reduce the parasitic capacitance between adjacent metallization film layers 500 .

[0157] At least one transistor structure includes a word line hole 710 penetrating to the substrate. Specifically, the word line hole 710 may penetrate the second stacked structure to the substrate.

[0158] In one embodiment, the first isolation layer 600 includes a first isolation sublayer 610 and a second isolation sublayer 620 .

[0159] The first isolation sublayer 610 is located on the lower surface of the upper metallization film layer 500 , and the second isolation sublayer 620 is located on the upper surface of the lower metallization film layer 500 . There is an air gap between the first isolation sublayer 610 and the second isolation sublayer 620 .

[0160] As an example, the first isolation sublayer 610 and the second isolation sublayer 620 may be formed of oxide.

[0161] In this embodiment, an air gap is formed between the first isolation sublayer 610 and the second isolation sublayer 620. Since the dielectric constant of air is 1, the formation of the air gap helps to reduce the parasitic capacitance between adjacent metallization film layers 500.

[0162] In one embodiment, the stacked structure further includes a side hole 720 , and the transistor structure includes a channel layer 810 , a gate dielectric layer 820 , a conductive protection layer 830 , and a word line 840 .

[0163] The side hole 720 is connected to and surrounds the word line hole 710 and is located between adjacent first isolation layers 600 together with the metallization film layer 500 .

[0164] The channel layer 810 is located in the side hole 720. The channel layer 810 serves as a channel of the transistor structure and provides a conduction channel for the source and drain of the transistor structure. As an example, the channel layer 810 may be made of indium gallium zinc oxide (IGZO) material.

[0165] The gate dielectric layer 820 is located in the side hole 720 and on the surface of the channel layer 810 away from the side hole 720. As an example, the gate dielectric layer 820 may be made of a material with a high dielectric constant (eg, aluminum oxide).

[0166] The conductive protection layer 830 is located in the side hole 720 and on the side of the gate dielectric layer 820 away from the channel layer 810. As an example, the material of the conductive protection layer 830 includes but is not limited to indium tin oxide film (ITO).

[0167] The word line 840 is located in the word line hole 710 . For example, the diameter of the word line 840 may be 25 nm, and the word line 840 may be made of an indium tin oxide (ITO) film material.

[0168] In one embodiment, see Fig.30 The second stacking structure includes a second main portion 960 and a second branch portion 970 .

[0169] The second main trunk 960 extends along the first direction, the second branch 970 extends along the second direction, the second direction intersects the first direction, and multiple second branch portions 970 are arranged at intervals along the first direction on both sides of the second main trunk 960 along the second direction. The word line 840 is located at one end of the second branch portion 970 close to the second main trunk 960.

[0170] It can be understood that the number of the word line holes 710 and the number of the second branches 970 can be consistent.

[0171] At this time, see Figure 2 The metallization film layer 500 located in the second main body 960 can form a bit line 930. In addition, the second branch 970 can also form a capacitor structure 920 on a side away from the second main body 960. The capacitor structure 920 can use the metallization film layer 500 as a lower electrode. The capacitor structure 920 and the transistor structure can form a storage unit 910.

[0172] The bit line 930 and the capacitor structure 920 are respectively located on both sides of the transistor structure in the second direction, and are respectively connected to the source and drain of the transistor structure. The second trunk 960 is symmetrically provided with two second branches 970 on both sides along the second direction, so that the same bit line 930 simultaneously supplies power to the storage units 910 on both sides.

[0173] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0174] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0175] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a semiconductor structure, It is characterized in that include: Providing a substrate, and forming a first stacking structure on the substrate, wherein the first stacking structure includes a plurality of doped layers and sacrificial layers formed alternately; Etching the first stack structure to form a word line hole penetrating into the substrate; removing the sacrificial layer through the word line hole and forming a metal material layer between adjacent doping layers; Through heat treatment, the doping layer reacts with the metal material layer to be transformed into a metallization film layer; Filling a first isolation layer between adjacent metallization film layers; Based on the word line hole, a transistor structure is formed.

2. The method for preparing a semiconductor structure according to claim 1, It is characterized in that The material of the doping layer has the same crystal lattice as that of the sacrificial layer.

3. The method for preparing a semiconductor structure according to claim 1, It is characterized in that The doping layer includes doped polysilicon, and the metallization film layer includes metal silicide.

4. The method for preparing a semiconductor structure according to claim 1, It is characterized in that The sacrificial layer is removed through the word line hole, and a metal material layer is formed between adjacent doping layers, including: removing the sacrificial layer through the word line hole; Filling the metal material layer in the area between adjacent doping layers; After the heat treatment is performed to make the doping layer react with the metal material layer to form a metallization film layer, the method comprises: The remaining metal material layer is removed.

5. The method for preparing a semiconductor structure according to claim 1, It is characterized in that Filling a first isolation layer between adjacent metallization film layers comprises: The first isolation layer having an air gap therein is formed between adjacent metallization film layers.

6. The method for preparing a semiconductor structure according to claim 1, It is characterized in that The first isolation layer includes a first isolation sublayer, a second isolation sublayer and a third isolation sublayer which are stacked. Filling a first isolation layer between adjacent metallization film layers comprises: A first isolation sublayer, a second isolation sublayer and a third isolation sublayer are formed between adjacent metallization film layers, and the third isolation sublayer is located between the first isolation sublayer and the second isolation sublayer.

7. The method for preparing a semiconductor structure according to claim 6, It is characterized in that After forming a transistor structure based on the word line hole, the method includes: The third isolation sublayer is removed to form an air gap.

8. The method for preparing a semiconductor structure according to claim 6, It is characterized in that Based on the word line hole, a transistor structure is formed, including: Etching each metallization film layer through the word line hole to form a side hole surrounding the word line hole, wherein the side hole separates the metallization film layers of the same layer; Sequentially forming a channel layer material and a gate dielectric material layer on the surface of the structure obtained after forming the side holes; Removing the channel layer material and the gate dielectric material layer outside the side hole to form a channel layer and a gate dielectric layer, and exposing the first isolation layer; removing the third isolation sublayer of the first isolation layer through the word line hole to form an air gap; A word line is formed in the word line hole.

9. The method for preparing a semiconductor structure according to claim 8, It is characterized in that Before removing the channel layer material and the gate dielectric material layer outside the side hole, the method includes: forming a conductive protective material layer covering the surface of the gate dielectric material layer; The conductive protection material layer outside the side hole is removed to form a conductive protection layer in the side hole.

10. The method for preparing a semiconductor structure according to claim 1, It is characterized in that A substrate is provided, and a first stacking structure is formed on the substrate, comprising: providing a substrate; By epitaxial process, doping material layers and sacrificial material layers are alternately stacked on the substrate; Etching the doping material layer and the sacrificial material layer to form the first stacked structure, wherein the first stacked structure includes a first main body and a first branch portion, wherein the first main body extends along a first direction, the first branch portion extends along a second direction, the second direction intersects the first direction, and a plurality of the first branch portions are arranged at intervals along the first direction and are disposed on both sides of the first main body along the second direction; Etching the first stack structure to form a word line hole penetrating the substrate includes: An end of the first branch portion close to the first trunk portion is etched to form the word line hole.

11. A semiconductor structure, It is characterized in that include: substrate; A second stacked structure, located on the substrate, comprises a plurality of alternately arranged metallized film layers and a first isolation layer, wherein the metallized film layers are film layers formed by reaction and conversion of a doping layer and a metal material layer; At least one transistor structure includes a word line hole extending through the substrate.

12. The semiconductor structure according to claim 11, It is characterized in that The metallization film layer includes metal silicide.

13. The semiconductor structure according to claim 11, It is characterized in that The first isolation layer has an air gap inside.

14. The semiconductor structure according to claim 11, It is characterized in that The first isolation layer includes a first isolation sublayer and a second isolation sublayer. The first isolation sublayer is located on the lower surface of the upper metallization film layer, and the second isolation sublayer is located on the upper surface of the lower metallization film layer. There is an air gap between the first isolation sublayer and the second isolation sublayer.

15. The semiconductor structure according to claim 11, It is characterized in that The second stacking structure further includes: A side hole, connected to and surrounding the word line hole, and arranged in the same layer as the metallization film layer; The transistor structure comprises: A channel layer, located in the side hole; a gate dielectric layer, located in the side hole and located on a surface of the channel layer away from the side hole; A conductive protection layer, located in the side hole and on a side of the gate dielectric layer away from the channel layer; The word line is located in the word line hole.

16. The semiconductor structure according to claim 15, It is characterized in that The second stacked structure includes a second main portion and second branch portions. The second main portion extends along a first direction, and the second branch portions extend along a second direction that intersects the first direction. A plurality of the second branch portions are arranged at intervals along the first direction on both sides of the second main portion along the second direction. The word line is located at one end of the second branch portion close to the second main portion.

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