Memory, manufacturing method thereof and electronic equipment

Abstract

The invention provides a memory, a manufacturing method thereof and electronic equipment. The memory comprises a substrate and a memory unit, wherein the memory unit comprises a read transistor and a write transistor which are sequentially arranged in the direction away from the substrate; the reading transistor comprises a first grid electrode, a first channel at least partially surrounding the first grid electrode, and a first source / drain electrode and a second source / drain electrode which are respectively connected with the first channel; the write transistor comprises an annular second channel, a third source / drain electrode located on one side, close to the substrate, of the second channel, a fourth source / drain electrode located on one side, away from the substrate, of the second channel and a second grid electrode at least partially surrounding the second channel; wherein the first grid electrode of the read transistor is electrically connected with the third source / drain electrode of the write transistor. According to the device architecture, electric leakage can be reduced, power consumption can be reduced, and the area can be reduced.

Description

Technical Field

[0001] The present application relates to but is not limited to semiconductor technology, and in particular to a memory and a manufacturing method thereof, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0005] In one aspect, an exemplary embodiment of the present application provides a memory including a substrate and a memory cell, the memory cell including a read transistor and a write transistor sequentially arranged in a direction away from the substrate;

[0006] The read transistor includes a first gate, a first channel at least partially surrounding the first gate, and a first source / drain and a second source / drain respectively connected to the first channel;

[0007] The write transistor comprises a second annular channel, a third source / drain located on a side of the second channel close to the substrate, a fourth source / drain located on a side of the second channel away from the substrate, and a second gate at least partially surrounding the second channel;

[0008] The first gate of the read transistor is electrically connected to the third source / drain of the write transistor.

[0009] In an exemplary embodiment, the first source / drain and the second source / drain respectively at least partially surround the first gate, and the first source / drain, the first channel and the second source / drain are sequentially arranged in a direction away from the substrate.

[0010] In an exemplary embodiment, at least one of the third source / drain and the fourth source / drain is ring-shaped.

[0011] In an exemplary embodiment, the first gate and the third source / drain are an integrated structure.

[0012] In an exemplary embodiment, the read transistor further includes a first annular gate insulating layer, the first gate insulating layer is located between the first channel and the first gate, and the first source / drain and the second source / drain are located on a side of the first gate insulating layer away from the first gate.

[0013] In an exemplary embodiment, the write transistor further includes a ring-shaped second gate insulating layer, the second gate insulating layer is located between the second channel and the second gate, and the third source / drain and the fourth source / drain are located on a side of the second gate insulating layer away from the second gate.

[0014] In an exemplary embodiment, the first channel includes P-type or N-type doped single crystal silicon or polycrystalline silicon.

[0015] In an exemplary embodiment, the first source / drain and the second source / drain each include N-type doped single crystalline silicon, and the first channel includes P-type doped single crystalline silicon.

[0016] In an exemplary embodiment, the second channel includes P-type or N-type doped single crystal silicon or polycrystalline silicon.

[0017] In an exemplary embodiment, the third source / drain and the fourth source / drain each include N-type doped single crystalline silicon, and the second channel includes P-type doped single crystalline silicon.

[0018] In an exemplary embodiment, a first through-hole structure is further included, and the first gate insulating layer and the first gate are located in the first through-hole structure.

[0019] In an exemplary embodiment, a second through-hole structure is further included, and the second gate insulating layer and the second channel are located in the second through-hole structure.

[0020] In an exemplary embodiment, the memory cell further includes a capacitor electrically connected to the read transistor.

[0021] In an exemplary embodiment, the first electrode of the capacitor is the first gate of the read transistor, the dielectric layer of the capacitor is a part of the first gate insulating layer, and the second electrode of the capacitor is disposed on a side of the first gate insulating layer away from the write transistor.

[0022] In an exemplary embodiment, the second electrode of the capacitor is a substrate, and a material of the substrate includes silicon.

[0023] In another aspect, an exemplary embodiment of the present application provides a method for manufacturing a memory, comprising the following steps:

[0024] Providing a substrate, and sequentially forming a first source / drain material layer, a first channel material layer, and a second source / drain material layer in a direction away from the substrate;

[0025] Forming a first through-hole structure penetrating the first source / drain material layer, the first channel material layer, and the second source / drain material layer to form a first source / drain, a first channel, and a second source / drain;

[0026] forming a first gate in the first through-hole structure;

[0027] forming a second gate material layer;

[0028] forming a second through-hole structure penetrating the second gate material layer to form a second gate;

[0029] forming a third source / drain material layer, a second channel material layer and a fourth source / drain material layer in sequence in the second through hole structure; and

[0030] Forming a third through-hole structure penetrating the third source / drain material layer, the second channel material layer and the fourth source / drain material layer to form a third source / drain, a second channel and a fourth source / drain;

[0031] The first gate is electrically connected to the third source / drain.

[0032] In an exemplary embodiment, forming the third source / drain, the second channel, and the fourth source / drain further includes:

[0033] forming a third source / drain material layer in the second through-hole structure, and performing N-type doping on the third source / drain material layer;

[0034] forming a second channel material layer, and performing P-type doping on the second channel material layer;

[0035] A fourth source / drain material layer is formed, and the fourth source / drain material layer is N-type doped.

[0036] In yet another aspect, an exemplary embodiment of the present application provides an electronic device, comprising any of the above-mentioned storage devices.

[0037] In an exemplary embodiment, the electronic device includes a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power source.

[0038] The memory of the present application can be a 2T0C memory structure, with read-write separation, no need to destroy data, no need to rewrite data. The upper write transistor has low leakage, large current, and fast speed, comparable to SRAM. The lower read transistor is made of silicon material, with high silicon mobility and fast reading speed.

[0039] The read transistor and write transistor of the present application are in a vertically stacked structure, which reduces the area and saves area compared to SRAM.

[0040] The read transistor and write transistor of the present application are made of silicon material, which can be easily integrated with a logic chip to form an embedded memory and can replace SRAM.

[0041] The write transistor of the present application adopts a ring-shaped hollow structure to ensure less leakage.

[0042] The memory of the present application may also be a 2T1C memory structure. The present application sets a capacitor in the substrate of the read transistor to prevent the problem of low gate capacitance and too high leakage through the write transistor and increase the data retention time, and can also suppress the current sharing problem in the 2T0C device.

[0043] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0045] Figure 1A A three-dimensional schematic diagram of a memory provided for an exemplary embodiment of the present application;

[0046] Figure 1B For along Figure 1A A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA';

[0047] Figure 1C A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA' of another memory provided for an exemplary embodiment of the present application;

[0048] Figure 1D A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA' of another memory provided in an exemplary embodiment of the present application;

[0049] Figure 1E A schematic cross-sectional view perpendicular to the substrate taken along the cross-sectional line AA' of another memory provided in an exemplary embodiment of the present application;

[0050] Figure 2A vertical cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a memory provided in an exemplary embodiment of the present application, taken along a plane perpendicular to a substrate;

[0051] Figure 3 A vertical cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a memory provided in an exemplary embodiment of the present application, taken along a plane perpendicular to a substrate;

[0052] Figure 4 A vertical cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a memory provided in an exemplary embodiment of the present application, taken along a plane perpendicular to a substrate;

[0053] Figure 5 A vertical cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a memory provided for an exemplary embodiment of the present application, taken along a plane perpendicular to a substrate; and

[0054] Figure 6 A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a memory provided in an exemplary embodiment of the present application, the intermediate product being cut along a plane perpendicular to a substrate. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solution and advantages of the present application more clear, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.

[0056] The embodiments herein can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the implementation and content can be transformed into various forms without departing from the purpose and scope of the present application. Therefore, the present application should not be interpreted as being limited to the contents recorded in the following embodiments. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

[0057] The proportions of the drawings in this application can be used as a reference in the actual process, but are not limited to this. For example, the aspect ratio of the semiconductor layer, the thickness and spacing of each film layer can be adjusted according to actual needs. The drawings described in this application are only schematic diagrams of the structure, and one embodiment of this application is not limited to the shapes or values ​​shown in the drawings.

[0058] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on this application. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification and can be appropriately replaced according to the situation.

[0059] In this specification, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0060] In the description of the present application, ordinal numbers such as "first" and "second" are provided to avoid confusion among constituent elements rather than to limit the quantity.

[0061] In this specification, "film" and "layer" may be interchanged. For example, "metal layer" may be replaced with "metal film" in some cases.

[0062] In the description of this application, a transistor refers to a component including at least three terminals: a gate, a drain, and a source. The transistor has a channel layer between the drain (drain terminal, drain region, or drain) and the source (source terminal, source region, or source), and current can flow through the drain, the channel layer, and the source. In this application, the channel layer refers to the area where the current mainly flows. In this application, the terms "metal oxide semiconductor channel", "channel", and "channel layer" are interchangeable.

[0063] Static random access memory (SRAM) is widely used because it can save the data stored in it without refreshing circuit and can work at a speed of 20ns or faster. However, SRAM has the problems of large area and leakage. Therefore, it is expected to provide a DRAM memory that can match the working response speed of SRAM and abandon the occupied area and leakage problems.

[0064] An exemplary embodiment of the present application provides a memory, comprising a substrate and a memory cell, wherein the memory cell comprises a read transistor and a write transistor arranged in sequence in a direction away from the substrate; the read transistor comprises a first gate, a first channel at least partially surrounding the first gate, and a first source / drain and a second source / drain respectively connected to the first channel; the write transistor comprises a ring-shaped second channel, a third source / drain located on a side of the second channel close to the substrate, a fourth source / drain located on a side of the second channel away from the substrate, and a second gate at least partially surrounding the second channel; wherein the first gate of the read transistor is electrically connected to the third source / drain of the write transistor.

[0065] As used in this application, the term "is an integrated structure" may refer to that there is no obvious boundary interface such as a fault or gap between A and B in the microstructure. Generally, a film layer patterned to form a connection is an integrated structure. For example, A and B are formed into a film layer using the same material and are simultaneously formed into a structure having a connection relationship through the same patterning process.

[0066] Figure 1A A three-dimensional schematic diagram of a memory provided for an exemplary embodiment of the present application; Figure 1B For along Figure 1A A schematic cross-sectional view perpendicular to the substrate taken along the section line AA' in FIG. Figure 1A and 1B As shown, the memory may include a substrate 1 and a memory cell, wherein the memory cell includes a read transistor 100 and a write transistor 200 arranged in sequence in a direction away from the substrate. The read transistor 100 may include a first gate 150, a first channel 120 at least partially surrounding the first gate 150, and a first source / drain 110 and a second source / drain 130 respectively connected to the first channel 120. The write transistor 200 may include a ring-shaped second channel 230, a third source / drain 210 located on a side of the second channel 220 close to the substrate, a fourth source / drain 230 located on a side of the second channel 220 away from the substrate, and a second gate 250 at least partially surrounding the second channel 220.

[0067] In an exemplary embodiment, the first source / drain 110 and the second source / drain 130 respectively at least partially surround the first gate 150, and the first source / drain 110, the first channel 120 and the second source / drain 130 are sequentially arranged in a direction away from the substrate. Such an arrangement can increase the contact area between the source and drain of the read transistor and the annular first channel, thereby reducing the contact resistance therebetween.

[0068] In an exemplary embodiment, at least one of the third source / drain 210 and the fourth source / drain 230 is in a ring shape. In an exemplary embodiment, both the third source / drain 210 and the fourth source / drain 230 are in a ring structure.

[0069] In the present application, surrounding can be understood as partially or completely surrounding the first gate 150 or the second channel 220. In some embodiments, surrounding can be completely surrounding as a whole, and the cross-section of the channel layer after surrounding can be a closed ring, and the ring shape is adapted to the outer contour shape of the cross-section of the first gate 150 or the second channel 220. Exemplarily, the cross-section of the first gate 150 or the second channel 220 is, for example, a circular, rectangular, elliptical or other structure. The interception direction of the cross section is intercepted along a direction parallel to the substrate 1. In an exemplary embodiment, surrounding can be partially surrounding, and the cross-section after surrounding is not closed, such as a ring with an opening.

[0070] Continue to refer Figure 1B The read transistor 100 may further include a first annular gate insulating layer 140, the first gate insulating layer 140 is located between the first channel 120 and the first gate 150, the first source / drain 110 and the second source / drain 130 are located on the side of the first gate insulating layer 140 away from the first gate 150. The write transistor 200 may further include a second annular gate insulating layer 240, the second gate insulating layer 240 is located between the second channel 220 and the second gate 250, the third source / drain 210 and the fourth source / drain 230 are located on the side of the second gate insulating layer 240 away from the second gate 250.

[0071] In an exemplary embodiment, the first gate 150 of the read transistor 100 may be directly connected to the third source / drain 210 of the write transistor 200, such as Figure 1E As shown; or the first gate 150 and the third source / drain 210 can be an integrated structure, such as Figure 1C As shown, such a structure can simplify the manufacturing process; or the first gate 150 can be connected to the third source / drain 210 through a conductive connecting member 50, such as Figure 1B and Figure 1D Therefore, the present application obtains a capacitor-free memory, such as a 2T0C DRAM memory, by interconnecting the gate of the read transistor with the third source / drain of the write transistor.

[0072] Continue to refer Figure 1B, it is also shown that the memory may also include a first through-hole structure K1 and a second through-hole structure K2, the first gate insulating layer 140 and the first gate 150 may be located in the first through-hole structure K1; the second gate insulating layer 240 and the second channel 220 may be located in the second through-hole structure K2. Such a structural arrangement allows the second channel 220 to be formed in the through-hole structure, facilitating the formation of a ring-shaped channel structure.

[0073] Figure 1E It is also shown that the annular hollow second channel 220 may also include an insulating layer 40. The metal layer above the insulating layer 40 can be used to connect to the write bit line 260, and the metal layer below the insulating layer 40 can be used to connect to the first gate 150. Therefore, the insulating layer 40 can be used to isolate different metal layers deposited in the second channel.

[0074] Although the first source / drain and the second source / drain and the third source / drain and the fourth source / drain references are used herein to indicate two separate and different source / drains, it is not intended that the source / drain referred to as the "first" source / drain, or the "second" source / drain and the "third" source / drain and the "fourth" source / drain have a unique meaning.

[0075] In an exemplary embodiment, the first source / drain and the second source / drain are independent of each other. In an exemplary embodiment, one of the first source / drain and the second source / drain is a source of a transistor, and the other is a drain of the transistor. Similarly, the third source / drain and the fourth source / drain are independent of each other, and one of the third source / drain and the fourth source / drain is a source of a transistor, and the other is a drain of the transistor.

[0076] like Figure 1A As shown, the first source / drain 110 of the read transistor can be connected to the read bit line 160, the second source / drain 130 can be connected to the read word line 170, or the first source / drain 110 of the read transistor can be connected to the read word line 170, the second source / drain 130 can be connected to the read bit line 160; the second gate 250 of the write transistor can be connected to the write word line 270, and the fourth source / drain 230 can be connected to the write bit line 260.

[0077] In an exemplary embodiment, the first channel 120 of the read transistor 100 may include P-type or N-type doped single crystal silicon or polycrystalline silicon. In an exemplary embodiment, the first source / drain 110 and the second source / drain 130 may include N-type doped single crystal silicon, and the first channel 120 may include P-type doped single crystal silicon.

[0078] In an exemplary embodiment, the second channel 220 of the write transistor 200 may include single crystal silicon or polycrystalline silicon doped with P type or N type. In an exemplary embodiment, the third source / drain 210 and the fourth source / drain 230 may include single crystal silicon doped with N type, and the second channel 220 may include single crystal silicon doped with P type. The write transistor made of silicon material can speed up the data writing.

[0079] In addition, the read transistor and write transistor of the present application are both made of silicon material and are compatible with peripheral processes. When making the silicon read transistor, the peripheral circuit can also be made at the same time, reducing the process steps.

[0080] The read transistor of the present application has a ring channel structure, which is simpler than the ring gate process, and the ring channel is made of silicon, has a fast response speed, can increase the turn-on current Ion, and improve the reading speed.

[0081] The write transistor of the present application also has a ring channel structure, and the middle of the ring channel is a hollow structure, thereby ensuring less leakage to the greatest extent possible.

[0082] The device architecture of the present application can reduce leakage, power consumption and area at a comparable operating response speed to SRAM. The device architecture of the present application can reduce the shutdown current I off 2 orders of magnitude lower, while the on current I on Not much difference.

[0083] The write transistor 200 can be mainly used to control leakage. The device structure of the present application can make the turn-off current I off Can be reduced to e -16 The turn-on current Ion can be reduced to e -4 Magnitude.

[0084] Further, if Figure 1D and 1E As shown, the memory of the present application may further include a capacitor 300 electrically connected to the read transistor. The capacitor 300 may include a first electrode 310, a dielectric layer 320, and a second electrode 330. The first electrode 310 may be electrically connected to the storage node SN, and the first gate insulating layer 140 of the read transistor may also serve as the dielectric layer 320.

[0085] The first electrode 310 of the capacitor may be the first gate 150 of the read transistor, the dielectric layer 320 of the capacitor may be a part of the first gate insulating layer 140 , and the second electrode 330 of the capacitor may be disposed on a side of the first gate insulating layer 140 away from the write transistor.

[0086] In an exemplary embodiment, the second electrode of the capacitor is a substrate, and the material of the substrate includes silicon. Since the substrate includes silicon material, it can be conductive and can serve as the second electrode of the capacitor, and the present application thus simplifies the manufacturing process of the capacitor.

[0087] The technical solution of the present application is further explained below through the manufacturing process of the memory of the exemplary embodiment of the present application. The "patterning process" mentioned in the exemplary embodiment includes deposition of film layers, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which are mature manufacturing processes in the relevant technology. The "photolithography process" mentioned in the exemplary embodiment includes coating of film layers, mask exposure and development, which are mature manufacturing processes in the relevant technology. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of the exemplary embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" also requires a patterning process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

[0088] In an exemplary embodiment, a method for manufacturing a memory may include the following steps:

[0089] S100: forming a source / drain material layer and a first channel material layer of a read transistor.

[0090] Exemplary steps may include: depositing a layer of silicon substrate on the substrate, and performing N-type doping to form an N+ type silicon substrate 1; depositing an insulating material film on the silicon substrate 1 to form a first insulating layer 10; forming a first source / drain material layer 110' of the read transistor 100 by depositing on the first insulating layer 10; then depositing an insulating material film on the first source / drain material layer 110' to form a second insulating layer 20; forming a through hole penetrating the second insulating layer 20 in the middle of the second insulating layer 20 by etching; filling Si into the through hole, performing P-type doping to form a first channel material layer 120'; depositing a layer of Si on the first channel material layer 120', doping it into N+ type, to form a second source / drain material layer 130' of the read transistor 100, as shown in FIG. Figure 2 shown. Figure 2 A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a memory provided in an exemplary embodiment of the present application, the intermediate product being cut along a plane perpendicular to a substrate.

[0091] In an exemplary embodiment, each insulating layer film may be deposited by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition (ALD), or the like.

[0092] In an exemplary embodiment, the first insulating layer 10 and the second insulating layer 20 may be made of any one or more non-conductive materials selected from silicon oxide, silicon oxynitride (SiON), silicon nitride (SiN), and silicon carbonitride (SiCN). In an exemplary embodiment, the first insulating layer 10 and the second insulating layer 20 may be made of an oxide insulating material, such as silicon dioxide (e.g., SiO 2 ), which is convenient for large-area deposition.

[0093] In an exemplary embodiment, the first insulating layer 10 and the second insulating layer 20 may be made of the same or different insulating materials.

[0094] In an exemplary embodiment, the doping concentration of the first source / drain material layer 110' and the second source / drain material layer 130' is different from the doping concentration of the first channel material layer 120'. In other exemplary embodiments, the first channel material layer 120' may also be N-type doped, that is, the doping type of the first source / drain material layer 110', the first channel material layer 120' and the second source / drain material layer 130' is the same.

[0095] In an exemplary embodiment, silicide may be formed on the first source / drain material layer 110 ′ and the second source / drain material layer 130 ′ to serve as connection wires.

[0096] S200: forming a first gate material layer of a read transistor.

[0097] An exemplary step may include: forming a first through-hole structure K1 in the structure formed in the aforementioned step by etching, the first through-hole structure K1 passing through the second source / drain material layer 130' and the first channel material layer 120' and terminating at a side of the first source / drain material layer 110' away from the first channel material layer 120'; depositing a dielectric layer film and a conductive film in the first through-hole structure K1 to form a first gate insulating material layer 140' and a first gate material layer 150' (i.e., a storage node SN of the read transistor); and then etching away excess film layers, i.e., forming a read transistor 100 having a ring channel structure, such as Figure 3 shown. Figure 3 A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a memory provided in an exemplary embodiment of the present application, the intermediate product being cut along a plane perpendicular to a substrate.

[0098] In an exemplary embodiment, the first gate insulating material layer 140' may be a dielectric layer with a high dielectric constant, that is, a dielectric layer with K≥3.9. The dielectric layer with a high dielectric constant may be used as a gate oxide. The first gate insulating material layer 140' may be made of silicon dioxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ) any one or more of ).

[0099] In an exemplary embodiment, the first gate material layer 150 ′ may be made of P-type amorphous silicon, metal tungsten W, tungsten nitride, titanium nitride, or a composite material of tungsten and titanium nitride.

[0100] In an exemplary embodiment, each thin film layer may be deposited using an atomic layer deposition method.

[0101] In an exemplary embodiment, the orthographic projection of the first through-hole structure K1 on a plane parallel to the substrate may be in a square, rectangle, circle, ellipse or the like.

[0102] S300: forming a second gate material layer of a write transistor.

[0103] Exemplary steps may include: depositing an insulating material film to form a third insulating layer 30, etching to form a groove, and filling the groove with metal; depositing a metal material film on the third insulating layer 30 to form a second gate material layer 250'; forming a second through-hole structure K2 in the second gate material layer 250' by etching; depositing a high dielectric constant material film around the inner sidewall of the second through-hole structure K2 by an ALD process and etching away the high dielectric constant material at the bottom of the through-hole, thereby forming a second gate insulating material layer 240', such as Figure 4 shown. Figure 4 A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a memory provided in an exemplary embodiment of the present application, the intermediate product being cut along a plane perpendicular to a substrate.

[0104] S400: forming a source-drain material layer and a second channel material layer of a write transistor.

[0105] The specific steps may include: depositing a third source / drain material layer 210' in the second through-hole structure K2, and then performing N-type doping on the third source / drain material layer 210'; depositing a second channel material layer 220', and then performing P-type doping on the second channel material layer 220'; depositing a fourth source / drain material layer 230', and then performing N-type doping on the fourth source / drain material layer 230'; that is, sequentially forming an N-type doped silicon layer, a P-type doped silicon layer and an N-type doped silicon layer in the second through-hole structure K2, and finally forming an npn three-layer; forming a third through-hole structure K3 penetrating the third source / drain material layer 210', the second channel material layer 220' and the fourth source / drain material layer 230' by etching, so as to form a third source / drain, a second channel and a fourth source / drain, and the orthographic projection of the third through-hole structure K3 on the substrate falls within the orthographic projection of the second through-hole structure K2 and the second channel material layer 220' on the substrate, such as Figure 5 shown. Figure 5 A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a memory provided in an exemplary embodiment of the present application, the intermediate product being cut along a plane perpendicular to a substrate.

[0106] S500: Through etching and interconnection processes, a metal film, an insulating layer film and a metal film are deposited in the hollow structure K3, the source / drain / input / output terminals are opened, and the Vout electrode is led out, such as Figure 6 shown. Figure 6 A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a memory provided in an exemplary embodiment of the present application, the intermediate product being cut along a plane perpendicular to a substrate.

[0107] The exemplary embodiment of the present application also provides a method for manufacturing a memory, comprising the following steps:

[0108] Providing a substrate, and sequentially forming a first source / drain material layer, a first channel material layer, and a second source / drain material layer in a direction away from the substrate;

[0109] Forming a first through-hole structure penetrating the first source / drain material layer, the first channel material layer, and the second source / drain material layer to form a first source / drain, a first channel, and a second source / drain;

[0110] forming a first gate in the first through-hole structure;

[0111] forming a second gate material layer;

[0112] forming a second through-hole structure penetrating the second gate material layer to form a second gate;

[0113] forming a third source / drain material layer, a second channel material layer and a fourth source / drain material layer in sequence in the second through hole structure; and

[0114] Forming a third through-hole structure penetrating the third source / drain material layer, the second channel material layer and the fourth source / drain material layer to form a third source / drain, a second channel and a fourth source / drain;

[0115] The first gate is electrically connected to the third source / drain.

[0116] An exemplary embodiment of the present application further provides an electronic device, comprising the memory provided by the exemplary embodiment of the present application as above.

[0117] In an exemplary embodiment, the electronic device may include a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power source.

[0118] Although the embodiments disclosed in this application are as above, the contents described are only embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any technician in the field to which this application belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be based on the scope defined in the attached claims.

Claims

1. A memory, It is characterized in that A method for manufacturing a semiconductor device comprising a substrate and a memory cell, wherein the memory cell comprises a read transistor and a write transistor arranged in sequence in a direction away from the substrate; The read transistor includes a first gate, a first channel at least partially surrounding the first gate, and a first source / drain and a second source / drain respectively connected to the first channel; The write transistor comprises a second annular channel, a third source / drain located on a side of the second channel close to the substrate, a fourth source / drain located on a side of the second channel away from the substrate, and a second gate at least partially surrounding the second channel; The first gate of the read transistor is electrically connected to the third source / drain of the write transistor.

2. The memory according to claim 1, It is characterized in that The first source / drain and the second source / drain respectively at least partially surround the first gate, and the first source / drain, the first channel and the second source / drain are sequentially arranged in a direction away from the substrate.

3. The memory according to claim 1, It is characterized in that At least one of the third source / drain and the fourth source / drain is in a ring shape.

4. The memory according to claim 1, It is characterized in that The first gate and the third source / drain are an integrated structure.

5. The memory according to claim 1, It is characterized in that The read transistor further includes a first annular gate insulating layer, the first gate insulating layer is located between the first channel and the first gate, and the first source / drain and the second source / drain are located on a side of the first gate insulating layer away from the first gate.

6. The memory according to claim 1, It is characterized in that The write transistor further includes a ring-shaped second gate insulating layer, the second gate insulating layer is located between the second channel and the second gate, and the third source / drain and the fourth source / drain are located on a side of the second gate insulating layer away from the second gate.

7. The memory according to claim 1, It is characterized in that The first channel includes P-type or N-type doped single crystal silicon or polycrystalline silicon.

8. The memory according to claim 7, It is characterized in that The first source / drain and the second source / drain both include N-type doped single crystal silicon, and the first channel includes P-type doped single crystal silicon.

9. The memory according to claim 1, It is characterized in that The second channel includes P-type or N-type doped single crystal silicon or polycrystalline silicon.

10. The memory according to claim 9, It is characterized in that The third source / drain and the fourth source / drain both include N-type doped single crystal silicon, and the second channel includes P-type doped single crystal silicon.

11. The memory according to claim 5, It is characterized in that It also includes a first through-hole structure, in which the first gate insulating layer and the first gate are located.

12. The memory according to claim 6, It is characterized in that A second through-hole structure is also included, and the second gate insulating layer and the second channel are located in the second through-hole structure.

13. The memory according to claim 5, It is characterized in that The memory cell also includes a capacitor electrically connected to the read transistor.

14. The memory according to claim 13, It is characterized in that The first electrode of the capacitor is the first gate of the read transistor, the dielectric layer of the capacitor is a part of the first gate insulating layer, and the second electrode of the capacitor is arranged on a side of the first gate insulating layer away from the write transistor.

15. The memory according to claim 14, It is characterized in that The second electrode of the capacitor is a substrate, and a material of the substrate includes silicon.

16. A method for manufacturing a memory, It is characterized in that The steps include: Providing a substrate, and sequentially forming a first source / drain material layer, a first channel material layer, and a second source / drain material layer in a direction away from the substrate; Forming a first through-hole structure penetrating the first source / drain material layer, the first channel material layer, and the second source / drain material layer to form a first source / drain, a first channel, and a second source / drain; forming a first gate in the first through-hole structure; forming a second gate material layer; forming a second through-hole structure penetrating the second gate material layer to form a second gate; sequentially forming a third source / drain material layer, a second channel material layer and a fourth source / drain material layer in the second through hole structure; as well as Forming a third through-hole structure penetrating the third source / drain material layer, the second channel material layer and the fourth source / drain material layer to form a third source / drain, a second channel and a fourth source / drain; The first gate is electrically connected to the third source / drain.

17. The manufacturing method according to claim 16, It is characterized in that Forming the third source / drain, the second channel, and the fourth source / drain further includes: forming a third source / drain material layer in the second through-hole structure, and performing N-type doping on the third source / drain material layer; forming a second channel material layer, and performing P-type doping on the second channel material layer; A fourth source / drain material layer is formed, and the fourth source / drain material layer is N-type doped.

18. An electronic device, It is characterized in that Comprising a memory according to any one of claims 1-15.

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