Semiconductor device and preparation method thereof, and storage system

Abstract

The embodiment of the invention provides a semiconductor device, a preparation method and a memory system. The semiconductor device comprises a first semiconductor structure and a power supply layer. The first semiconductor structure comprises a substrate and a peripheral circuit layer located on the first side of the substrate. The power supply layer is located on a second side, opposite to the first side, of the substrate in the first direction and connected with a peripheral circuit in the peripheral circuit layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor design and preparation, and more specifically, to a semiconductor device, a method for preparing a semiconductor device, and a storage system. Background Art

[0002] Memory is one of the important components in electronic systems. Taking memory as an example, a semiconductor device may include a memory cell composed of a capacitor and a transistor, wherein a plurality of memory cells may be arranged in the form of a two-dimensional array. In order to further reduce the size of the two-dimensional array, the transistor may include a vertical gate transistor (Vertical Gate Transistor, VGT). In this structure, the source and drain of the transistor are respectively located at both ends of the extension direction of the channel of the transistor, and the gate structure of the transistor is located at least on one side of the channel.

[0003] With the rapid development of semiconductor technology, how to improve the storage density of semiconductor devices such as memory, optimize their comprehensive performance and reduce their process costs is one of the important research directions in the industry. Summary of the invention

[0004] The present application provides a method for preparing a semiconductor device, a semiconductor device, and a memory system that can at least partially solve the above-mentioned problems or other problems in the art.

[0005] On the one hand, the present application provides a semiconductor device, which includes: a first semiconductor structure, including a substrate and a peripheral circuit layer located on a first side of the substrate; and a power supply layer, which is located on a second side of the substrate opposite to the first side in a first direction and connected to the peripheral circuit in the peripheral circuit layer.

[0006] In one embodiment of the present application, the semiconductor device also includes a second semiconductor structure and a connection layer, wherein the second semiconductor structure is located on a side of the first semiconductor structure away from the power supply layer along the first direction and includes a storage array connected to the peripheral circuit; and the connection layer is located between the second semiconductor structure and the first semiconductor structure.

[0007] In one embodiment of the present application, the first semiconductor structure also includes an interconnection layer, the interconnection layer includes a first interconnection layer and a second interconnection layer, wherein the first interconnection layer is located between the peripheral circuit and the power supply layer; the second interconnection layer is located between the peripheral circuit and the connection layer; and the interconnection layer includes an interconnection path extending along the first direction and an interconnection line extending along a second direction intersecting the first direction.

[0008] In one embodiment of the present application, the interconnection via of the first interconnection layer extends at least through the substrate and the peripheral circuit layer along the first direction to connect the peripheral circuit and the power layer.

[0009] In one embodiment of the present application, the memory array includes memory cells and word lines and bit lines connected to the memory cells; and the peripheral circuit includes a driving structure connected to the word lines and a sensing structure connected to the bit lines, wherein the second interconnect layer connects the word lines to the driving structure, and the bit lines to the sensing structure.

[0010] In one embodiment of the present application, the connection layer includes a bonding layer, wherein the semiconductor device also includes a first contact structure extending through the bonding layer along the first direction, and the first contact structure connects the word line with the second interconnect layer, and the bit line with the second interconnect layer.

[0011] In one embodiment of the present application, the power layer includes a pad lead-out structure and a power line, wherein the power line extends in a plane perpendicular to the first direction; and at least two of the power lines have different widths perpendicular to the extension direction.

[0012] In one embodiment of the present application, the memory array includes at least one of a non-volatile memory cell and a volatile memory cell.

[0013] In one embodiment of the present application, the volatile memory cell includes at least one of a dynamic random access memory cell, a phase change memory cell or a ferroelectric memory cell.

[0014] In one embodiment of the present application, the volatile memory cell includes a vertical transistor and a memory cell connected to the vertical transistor, wherein along the first direction, the vertical transistor is close to the first semiconductor structure relative to the memory cell.

[0015] In one embodiment of the present application, the vertical transistor includes at least one of a full-all-around gate transistor, a multi-gate transistor, and a single-gate transistor.

[0016] In one embodiment of the present application, the vertical transistor comprises a semiconductor body, wherein the substrate and the semiconductor body comprise a same semiconductor material layer.

[0017] On the other hand, the present application provides a method for manufacturing a semiconductor device, the method comprising: providing a substrate, and forming a peripheral circuit layer including a peripheral circuit on a first side of the substrate to form a first semiconductor structure; and forming a power supply layer connected to the peripheral circuit on a second side of the substrate opposite to the first side in a first direction.

[0018] In an embodiment of the present application, the method further comprises: combining a second semiconductor structure including a memory array with the first semiconductor structure, wherein the second semiconductor structure is located on a side of the first semiconductor structure away from the power supply layer along the first direction.

[0019] In an embodiment of the present application, before forming the power supply layer, the method further comprises: forming an interconnection path extending in the first semiconductor structure along the first direction, wherein the interconnection path extends at least through the substrate and the peripheral circuit layer to connect the peripheral circuit and the power supply layer.

[0020] In an embodiment of the present application, when combining a second semiconductor structure including a memory array with the first semiconductor structure, the combination includes bonding, and the method further comprises: forming a first contact structure extending through a bonding layer along the first direction to connect the second semiconductor structure and the first semiconductor structure.

[0021] In an embodiment of the present application, before forming a power supply layer connected to the peripheral circuit, the method further comprises: before combining a second semiconductor structure including a memory array with the first semiconductor structure, forming a second interconnection layer on a side of the peripheral circuit layer away from the substrate, the second interconnection layer connecting the peripheral circuit and the memory array; and after combining a second semiconductor structure including a memory array with the first semiconductor structure, forming a first interconnection layer on a side of the substrate away from the peripheral circuit layer, the first interconnection layer connecting the peripheral circuit and the power supply layer, wherein both the first interconnection layer and the second interconnection layer include an interconnection path extending along the first direction and an interconnection line extending along a second direction intersecting with the first direction.

[0022] In an embodiment of the present application, the power supply layer includes a pad lead-out structure and a power supply line, and forming a power supply layer connected to the peripheral circuit includes: forming the pad lead-out structure and a plurality of the power supply lines, wherein the plurality of power supply lines extend in a plane perpendicular to the first direction; and at least two of the power supply lines have different widths perpendicular to the extension direction.

[0023] Another aspect of the present application provides a storage system, which includes the semiconductor device provided in one aspect of the present application and a controller coupled to the semiconductor device, wherein the controller is used to store data in the semiconductor device.

[0024] According to the semiconductor device, preparation method and memory system provided by at least one embodiment of the present application, the semiconductor device includes a first semiconductor structure and a power layer, wherein the first semiconductor structure includes a peripheral circuit and a substrate, and the power layer is located on the side of the substrate away from the peripheral circuit. The lines included in the power layer are arranged on the side of the substrate away from the peripheral circuit, and the interconnection structure between the peripheral circuit and the power layer can be arranged on the side of the peripheral circuit close to the substrate without affecting the comprehensive performance of the semiconductor device, so that the interconnection structure between the peripheral circuit and other structures such as the memory array can be arranged on the side of the peripheral circuit away from the substrate. Therefore, the layout space of the interconnection structure related to the peripheral circuit is expanded, and the layout flexibility of these interconnection structures is improved. In addition, the crosstalk of the power layer to these interconnection structures can be reduced, the sensing margin of the interconnection structure can be improved, and the overall size of the chip where the semiconductor device is located can be reduced accordingly. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0026] Figure 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present application;

[0027] Figure 2A is a schematic top view of a power supply layer according to an embodiment of the present application;

[0028] Figure 2B is a partial top view schematic diagram of a power supply layer and an interconnection layer according to one embodiment of the present application;

[0029] Figure 2C is a partial perspective top view schematic diagram of a bit line and an interconnect layer according to one embodiment of the present application;

[0030] Figure 2D is a schematic top view of a power line and an interconnection layer according to one embodiment of the present application;

[0031] Figure 2E is a schematic top view of an interconnection layer according to one embodiment of the present application;

[0032] Figure 3 is a flow chart of a method for preparing a semiconductor device according to an exemplary embodiment of the present application;

[0033] Figure 4-Figure 8 are schematic process diagrams of a method for preparing a semiconductor device according to an embodiment of the present application; and

[0034] Fig. 9 It is a schematic diagram of the storage system structure according to one embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0036] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature area, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the second semiconductor structure discussed in this application may also be referred to as the first semiconductor structure, and vice versa.

[0037] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0038] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0039] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0040] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method recorded in this application are not necessarily limited to the recorded order, but can be performed in any order or in parallel.

[0041] In addition, in the present application, when “connected” or “coupled” is used, it may indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context.

[0042] The present application will be described in detail below with reference to the accompanying drawings and in combination with implementation modes.

[0043] Some embodiments of the present application provide a semiconductor device. Figure 1 is a cross-sectional view of a semiconductor device 1000 according to one embodiment of the present application.

[0044] like Figure 1 As shown, the semiconductor device 1000 includes a first semiconductor structure 200 and a power layer 500. The first semiconductor structure 200 includes a substrate 401 and a peripheral circuit layer 400 located on a first side 01 of the substrate 401. The power layer 500 is located on a second side 02 of the substrate 401 opposite to the first side 01 in a first direction (z direction) and is connected to a peripheral circuit 400-1 in the peripheral circuit layer 400.

[0045] In some embodiments, taking memory as an example, multiple memory cells (e.g., memory array) of a semiconductor device and peripheral circuits connected to the multiple memory cells can be formed on two different wafers (e.g., memory array wafer and peripheral circuit wafer), and then the peripheral circuit wafer and the memory array wafer are combined by processes such as wafer bonding, and the peripheral circuit and the memory array circuit are connected together by connecting wires, contact structures, interconnect structures, etc. However, as the structure of semiconductor devices continues to develop towards high density, the area of ​​the peripheral circuit wafer has become more and more a key factor in determining the size of the entire chip.

[0046] In addition, in some embodiments, the power supply layer that provides electrical signals to the peripheral circuit is usually arranged on the side of the peripheral circuit close to the memory array, so as to arrange the interconnection structure related to the peripheral circuit together, wherein the interconnection structure related to the peripheral circuit includes the interconnection structure between the peripheral circuit and the power supply layer and the interconnection structure between the peripheral circuit and the memory array. However, this layout limits the location of the above-mentioned interconnection structure and reduces the flexibility of the interconnection structure layout. In addition, it will also cause crosstalk between the power supply layer and the interconnection structure, thereby reducing the sensing tolerance of the interconnection structure.

[0047] According to a semiconductor device provided by at least one embodiment of the present application, the semiconductor device includes a first semiconductor structure and a power layer, wherein the first semiconductor structure includes a peripheral circuit and a substrate, and the power layer is located on a side of the substrate away from the peripheral circuit. The lines included in the power layer are arranged on a side of the substrate away from the peripheral circuit, and the interconnection structure between the peripheral circuit and the power layer (for example, the interconnection layer including interconnection paths and connection lines described below) can be arranged on a side of the peripheral circuit close to the substrate without affecting the comprehensive performance of the semiconductor device, so that the interconnection structure between the peripheral circuit and other structures such as a storage array can be arranged on a side of the peripheral circuit away from the substrate. Therefore, the layout space of the interconnection structure related to the peripheral circuit is expanded, and the layout flexibility of these interconnection structures is improved. In addition, the crosstalk of the power layer to these interconnection structures can be reduced, the sensing tolerance of the interconnection structure can be improved, and the chip size can be reduced accordingly.

[0048] It should be noted that in this article Figure 1 In the present invention, only the structure, quantity and position of the peripheral circuit, the memory cell and the interconnection structure (for example, the interconnection layer, the interconnection path and the interconnection line) in the memory array are shown by way of example, but it can be understood that the peripheral circuit, the memory cell and the interconnection structure shown in the figures and related contents of this document are only shown for the convenience of illustration, and the present application is not limited thereto. Those skilled in the art can adjust the memory cell, the interconnection structure and the peripheral circuit according to the idea of ​​the present invention to achieve the same technical effect.

[0049] Specifically, in some embodiments of the present application, the semiconductor device 1000 further includes a second semiconductor structure 100 and a connection layer 600. The second semiconductor structure 100 is located on a side of the first semiconductor structure 200 away from the power layer 500 along the z direction, and includes a memory array 300 connected to the peripheral circuit 400-1. The connection layer 600 is located between the second semiconductor structure 100 and the first semiconductor structure 200.

[0050] Therefore, according to the semiconductor device provided by at least one embodiment of the present application, the semiconductor device includes a first semiconductor structure, a second semiconductor structure, a connection layer and a power layer located therebetween, wherein the first semiconductor structure includes a peripheral circuit, and the power layer is located on a side of the peripheral circuit away from the second semiconductor structure. The peripheral circuit and the power layer can be connected together by, for example, an interconnection structure, and the peripheral circuit and the memory array can also be connected together by, for example, an interconnection structure, and the lines and the like included in the power layer are arranged on a side of the peripheral circuit away from the memory array. Without affecting the comprehensive performance of the semiconductor device, the interconnection structure between the peripheral circuit and the power layer can be arranged on a side of the peripheral circuit away from the memory array, thereby expanding the layout space of the interconnection structure between the peripheral circuit and the memory array circuit, and improving the flexibility of the layout of the interconnection structure. In addition, the crosstalk of the power layer to the interconnection structure can be reduced, the sensing tolerance of the interconnection structure can be improved, and the overall size of the chip can be reduced accordingly.

[0051] In addition, in at least one embodiment of the present application, the interconnection structure (also understood as the interconnection layer 700) may include a first interconnection layer 701 and a second interconnection layer 702, wherein the first interconnection layer 701 is located between the peripheral circuit 400-1 and the power layer 500; the second interconnection layer 702 is located between the peripheral circuit 400-1 and the connection layer 600, and both include an interconnection path extending along the z direction and an interconnection line extending along a second direction intersecting the z direction. Therefore, by setting the first interconnection layer and the second interconnection layer separately, the spatial position of the interconnection structure layout can be expanded, and the flexibility of the interconnection structure layout can be improved. In addition, the crosstalk of the power layer to the interconnection structure can be reduced, and the sensing tolerance of the interconnection structure can be improved.

[0052] In addition, in some embodiments of the present application, the material of the substrate 401 of the first semiconductor structure 200 may include any suitable semiconductor material, such as single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI) or III-V compounds such as gallium arsenide. As an option, the substrate 401 may include single crystal silicon.

[0053] In one embodiment of the present application, the substrate 401 may be, for example, a composite structure for supporting the peripheral circuit 400 thereon. As an option, a portion of the substrate 401 may also form a well region (not shown) doped with an N-type or P-type dopant via an ion implantation or diffusion process. The dopant may include any one or a combination of phosphorus (P), arsenic (As) and antimony (Sb); or any one or a combination of boron (B), gallium (Ga) or indium (In).

[0054] The substrate 401 includes a first side 01 and a second side 02 opposite to each other in the z direction, and the peripheral circuit layer 400 may be located on the first side 01 of the substrate 401. The peripheral circuit layer 400 may include a peripheral circuit 400-1. Optionally, the peripheral circuit 400-1 may include at least one of a driving structure (not shown) and a sensing structure (not shown).

[0055] Alternatively, the peripheral circuit 400-1 may be understood as a circuit for facilitating the operation of the memory array 300. The peripheral circuit 400-1 may include any suitable digital, analog, and / or mixed signal circuit for facilitating the operation of the memory array 300. For example, the peripheral circuit 400-1 may include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sensing structure (e.g., a bit line sensing amplification structure), a driving structure (e.g., a word line driving structure), an input / output circuit, a charge pump, a voltage source or generator, a current or voltage reference, any portion (e.g., a subcircuit) of the above functional circuits, or any active or passive component of the circuit (e.g., a transistor, a diode, a resistor, or a capacitor), and the present application is not limited thereto.

[0056] Optionally, part of the peripheral circuit 400-1 may extend along the z direction and extend from the first side 01 into the substrate 401. The part of the peripheral circuit 400-1 extending into the substrate 401 may be a subcircuit with independent functions or a part of a subcircuit with independent functions, which is not limited in the present application.

[0057] Figure 2A It is a schematic top view of a power line 501 according to one embodiment of the present application.

[0058] like Figure 1 and Figure 2A As shown, in some embodiments of the present application, the power layer 500 may be located on the second side 02 of the substrate 401. Optionally, the power layer 500 includes a pad lead-out structure 502 and a power line 501. The pad lead-out structure 502 may connect an external electrical signal to the power line 501; or connect an external electrical signal to the peripheral circuit 400-1. Optionally, the power line 501 extends in the xy plane, wherein at least two power lines 501 have different widths perpendicular to their own extension direction. For example, the first power line 511 and the second power line 512 extend along the y direction, and the third power line 513 and the fourth power line 514 extend along the x direction, wherein the first power line 511, the second power line 512, the third power line 513 and the fourth power line 514 all have widths perpendicular to their own extension direction, which are the first width W1, the second width W2, the third width W3 and the fourth width W4, respectively. Among them, the sizes of the first width W1, the second width W2, the third width W3 and the fourth width W4 may all be different.

[0059] Compared with an external electrical signal, there is a voltage drop in the power supply line in its extending direction. For example, the power supply line may have a voltage drop of 5% to 10% in its extending direction or the direction of current flow. By setting the power supply line as a wider conductor, the voltage drop caused by current fluctuations can be reduced, and the stability of power supply by the power supply line can be increased. In addition, the power supply line supplies power to the peripheral circuit, and it can be connected to a large number of parallel circuits, including high-frequency circuits, medium-frequency circuits, low-frequency circuits, etc. In this embodiment, the width of the power supply line connected to the circuit in its extending direction can be reasonably set according to the actual requirements of the above circuits in the peripheral circuit.

[0060] In addition, in some embodiments of the present application, the power supply layer 500 may further include a plurality of layer structures sequentially arranged in the z direction. For example, a plurality of power supply lines 501 extending in the x-y plane can be formed into one layer structure, and the power supply layer 500 may include a plurality of layer structures sequentially arranged in the z direction and including the power supply lines 501 to meet the actual needs.

[0061] In addition, referring again to Figure 1 , in some embodiments of the present application, the memory array 300 of the second semiconductor structure 100 may include a plurality of memory cells 300-1, and the memory array 300 formed by the plurality of memory cells 300-1 can be arranged in the form of a two-dimensional array.

[0062] Optionally, the memory cell 300-1 may include a transistor 301 and a memory cell 302 coupled to the transistor 301. For example, in some embodiments, the memory cell 302 may include a capacitor for storing charge as binary information stored by a corresponding DRAM (Dynamic Random Access Memory) cell. In addition, in some embodiments, the memory cell 302 may include a PCM element (for example, including a chalcogenide alloy) for storing binary information of a corresponding PCM cell based on different resistivity values of the PCM (Phase Change Memory) element in the amorphous phase and the crystalline phase. In addition, in some embodiments, the memory cell 302 may include a ferroelectric capacitor for storing binary information of a corresponding FRAM (Ferroelectric Random Access Memory) cell based on the switching between two polarization states of a ferroelectric material under an external electric field.

[0063] In addition, optionally, in addition to the above-mentioned volatile memory cells such as at least one of dynamic random access memory cells, phase change memory cells or ferroelectric memory cells, the memory array may further include non-volatile memory cells, and the present application does not limit this.

[0064] In some embodiments, in order to further reduce the size of the two-dimensional array, transistor 301 may include a vertical gate transistor (Vertical Gate Transistor, VGT, also referred to as a vertical transistor). In this structure, the source and drain of the transistor are respectively located at both ends of the extension direction of the channel of the transistor, and the gate structure of the transistor is located at least on one side of the channel. For example, transistor 301 may include a semiconductor body (not shown) extending along the z direction and a gate structure (not shown) located on at least one side wall of the semiconductor body. In other words, in some embodiments of the present application, transistor 301 may include at least one of a full-ring gate transistor, a multi-gate transistor, and a single-gate transistor.

[0065] In one embodiment of the present application, a vertical transistor such as a vertical metal oxide semiconductor field effect transistor (MOSFET) can replace a conventional planar transistor as a transfer transistor of a memory cell to reduce the area occupied by the transfer transistor, coupling capacitance, and interconnect wiring complexity. In some embodiments, the vertical transistor is formed on a substrate (not shown), and unlike a planar transistor in which an active region is formed in a substrate, the vertical transistor may include a semiconductor body extending vertically in a z-direction above the substrate. The semiconductor body may extend above the top surface of the substrate, exposing not only the top surface of the semiconductor body, but also one or more sidewalls of the semiconductor body.

[0066] Optionally, the semiconductor body may have a cubic shape to expose its four side walls. However, it should be understood by those skilled in the art that the semiconductor body may have any suitable 3D shape, such as a polyhedral shape or a cylindrical shape. In other words, the cross-section of the semiconductor body in the xy plane (wherein the x direction, the y direction, and the z direction intersect with each other) may have a square shape, a rectangular shape, a trapezoidal shape, a circular shape, an elliptical shape, or any other suitable shape. It should be understood that, consistent with the scope of the present application, for a semiconductor body having a circular or elliptical cross-section in the above plane, the semiconductor body may still be considered to have multiple side walls so that the gate structure contacts one of the side walls of the semiconductor body. Optionally, the semiconductor body may be formed by a substrate by, for example, etching or epitaxial processes, and therefore may have the same semiconductor material as the substrate.

[0067] Thus, as an option, the material of the semiconductor body or substrate may include, but is not limited to, silicon (e.g., single crystal silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable semiconductor material. For example, the semiconductor body or substrate may be a silicon substrate. In this case, the base 401 of the first semiconductor structure 200 and the semiconductor body may include the same semiconductor material layer.

[0068] Alternatively, the transistor 301 may include a thin film transistor. In other words, the memory array 300 including the thin film transistor may be formed by a thin film manufacturing process. Specifically, the semiconductor body included in the thin film transistor may be an oxide semiconductor layer including at least one of indium, gallium or zinc.

[0069] In some embodiments, transistor 301 may also include a source (not shown) and a drain (not shown) formed at two ends of the semiconductor body in the z direction, respectively, which may be understood as a doped region of the semiconductor body, and may also be referred to as a source electrode and a drain electrode. As an option, the source and the drain may be doped with any suitable P-type dopant, and the P-type dopant may include any one or a combination of boron (B) or gallium (Ga). As another option, the source and the drain may be doped with any suitable N-type dopant, and the N-type dopant may include any one or a combination of phosphorus (P), arsenic (As) and antimony (Sb). The source and the drain may be separated by a gate structure in the z direction. In other words, the gate structure is formed between the source and the drain along the z direction and has a gate control capability. When the gate voltage applied to the gate structure is higher than the threshold voltage of the vertical transistor, the channel of the vertical transistor may be formed in the semiconductor body along the z direction between the source and the drain.

[0070] Alternatively, if Figure 1 As shown, the transistor 301 is closer to the first semiconductor structure 200 along the z direction relative to the storage unit 302, so as to shorten the length of the interconnection structure (for example, the interconnection path or connection line described below) between the transistor 301 and the peripheral circuit 400-1, and reduce the parasitic capacitance of the interconnection structure. Optionally, the storage unit 302 may also be closer to the first semiconductor structure 200 along the z direction relative to the transistor 301, and this application is not limited to this.

[0071] Optionally, one of the source and the drain of the transistor 301 may be coupled to the memory cell 302. In addition, the second semiconductor structure 100 further includes a bit line 310 and a word line 330, wherein the bit line 310 may extend along the y direction and be connected to the other of the source and the drain of the transistor 301. The word line 330 may extend along the x direction and be connected to the gate structure of the transistor 301. It should be noted that the word line 330 extends along the x direction and thus cannot be shown in the yz plane, and the position of the word line 330 is only shown by a dotted arrow in the figure. In addition, it can be understood that the gate structure and the word line 330 may be continuous conductive structures.

[0072] Alternatively, the bit line 310 and the word line 330 may extend in two lateral directions perpendicular to each other, and the semiconductor body of the transistor 301 may extend in a vertical direction perpendicular to the two lateral directions along which the bit line 310 and the word line 330 extend. Therefore, due to the vertical arrangement of the transistor 301, the word line 330 and the bit line 310 may be arranged in different planes in the vertical direction, which simplifies the wiring of the word line 330 and the bit line 310.

[0073] In addition, as described above, the peripheral circuit 400 - 1 of the first semiconductor structure 200 may include a sensing structure and a driving structure, wherein the sensing structure may be connected to the bit line 310 , and the driving structure may be connected to the word line 330 .

[0074] According to some embodiments, both word line 330 and bit line 310 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), thallium nitride (TaN), polysilicon, silicide, or any combination thereof. In some embodiments, both word line 330 and bit line 310 may include multiple conductive material layers, such as a W layer on a TiN layer.

[0075] Figure 2B It is a partial top view schematic diagram of a power supply layer and an interconnection layer according to one embodiment of the present application. Figure 2C It is a partial perspective top view schematic diagram of a bit line and an interconnection layer according to one embodiment of the present application. Figure 2D It is a schematic top view of a power line and an interconnection layer according to one embodiment of the present application. Figure 2E is a schematic top view of an interconnection layer according to one embodiment of the present application.

[0076] Combination Figure 1-2EAs described above, in some embodiments, the interconnection layer 700 of the first semiconductor structure 200 may include a first interconnection layer 701 and a second interconnection layer 702, wherein the first interconnection layer 701 is located between the peripheral circuit 400-1 and the power layer 500; and the second interconnection layer 702 is located between the peripheral circuit 400-1 and the connection layer 600. The interconnection layer 700 includes an interconnection path extending along the z direction and an interconnection line extending along a second direction (e.g., the x direction or the y direction) intersecting the z direction. For example, the first interconnection layer 701 includes an interconnection path 701-1 extending along the z direction (hereinafter referred to as the first interconnection path 701-1) and an interconnection line 701-2 extending along at least one of the x direction and the y direction (hereinafter referred to as the first interconnection line 701-2).

[0077] Optionally, refer to Figure 1 and Figure 2B , the power layer 500 may include a plurality of power lines 501, wherein the power lines 501 may extend in the xy plane. For example, a plurality of bit lines parallel to the first power line 511 may extend in the y direction, and a plurality of bit lines parallel to the third power line 513 may extend in the x direction. Optionally, the first interconnection path 701-1 may be connected to any one of the plurality of power lines 501 to connect the power line with the peripheral circuit 400-1, wherein the first interconnection path 701-1 may extend at least through the substrate 401 and the peripheral circuit layer 400 in the z direction. The first interconnection path extends in the z direction to connect the peripheral circuit and the power layer, which is conducive to shortening the length of the interconnection structure between the peripheral circuit and the power layer, thereby reducing the parasitic capacitance of the interconnection structure, and improving the sensing tolerance and storage density of the semiconductor device. Optionally, the first interconnection path 701-1 may include a through silicon contact structure (Through Silicon Contact, TSC), which is not limited in the present application.

[0078] Optionally, the second interconnect layer 702 may connect the word line 330 with the driving structure, and the bit line 310 with the sensing structure. For example, the word line 330 may be connected to the second interconnect layer 702 through the first contact structure 610 described below, and connected to the driving structure in the peripheral circuit 400-1 through the second interconnect layer 702; the bit line 310 may also be connected to the second interconnect layer 702 through the first contact structure 610 described below, and connected to the sensing structure in the peripheral circuit 400-1 through the second interconnect layer 702.

[0079] refer to Figure 1 and Figure 2CTaking the sensing structure connected to the bit line 310 in the second interconnect layer 702 as an example, the plurality of bit lines 310 may include a first bit line 310-1, a second bit line 310-2, a third bit line 310-3, a fourth bit line 310-4, a fifth bit line 310-5, a sixth bit line 310-6, a seventh bit line 310-7 and an eighth bit line 310-8. The sensing structure connected to the bit line 310 in the second interconnect layer 702 may include a first sensing structure 702-1 and a second sensing structure 702-2, wherein the first sensing structure 702-1 is connected to the first bit line 310-1, the second bit line 310-2, the third bit line 310-3, and the fourth bit line 310-4 to sense the memory cells connected to the first bit line 310-1, the second bit line 310-2, the third bit line 310-3, and the fourth bit line 310-4; the second sensing structure 702-2 is connected to the fifth bit line 310-5, the sixth bit line 310-6, the seventh bit line 310-7, and the eighth bit line 310-8 to sense the memory cells connected to the fifth bit line 310-5, the sixth bit line 310-6, the seventh bit line 310-7, and the eighth bit line 310-8. Optionally, the first sensing structure 702-1 and the second sensing structure 702-2 may extend in the xy plane and extend in the z direction. For example, the second interconnect layer 702 includes a plurality of layer structures stacked in the z direction, and the first sensing structure 702 - 1 and the second sensing structure 702 - 2 may be located in different layer structures, respectively.

[0080] refer to Figure 1 and Figure 2D In some embodiments, the plurality of power lines 501 of the power layer 500 are disposed between the first semiconductor structure 200 and the second semiconductor structure 100. Therefore, the first connection layer 701 connecting the power layer 500 and the peripheral circuit 400-1, and the second connection layer 702 connecting the memory array 300 and the peripheral circuit 400-1 are both disposed between the first semiconductor structure 200 and the second semiconductor structure 100. Figure 2D As shown, the second connection layer 702 may include at least one first area 702-3 for setting the interconnection structure of the storage array 300 and at least one second area 702-4 for setting the interconnection structure of the peripheral circuit 400-1. The setting space of the plurality of power lines 501 overlaps with the setting space of the first area 702-3 and the second area 702-4 in space, so this layout limits the setting position of the above-mentioned interconnection structure and reduces the flexibility of the layout of the interconnection structure. In addition, it will also cause crosstalk between the power layer and the interconnection structure, thereby reducing the sensing tolerance of the interconnection structure.

[0081] refer to Figure 1 , Figure 2D and Figure 2EIn some embodiments of the present application, the first semiconductor structure 200 includes a peripheral circuit 400-1 and a substrate 401, and the power layer 500 is located on the second side 02 of the substrate 401 away from the peripheral circuit 400-1. Therefore, the first connection layer 701 connecting the power layer 500 and the peripheral circuit 400-1 is arranged on the second side 02 of the substrate 401, and the second connection layer 702 connecting the storage array 300 and the peripheral circuit 400-1 is arranged between the first semiconductor structure 200 and the second semiconductor structure 100. The setting space of the first area 702-3 and the second area 702-4 of the second connection layer 702 does not overlap with the setting space of the multiple power lines 501 in space. Therefore, the layout space of the interconnection structure related to the peripheral circuit can be expanded without affecting the comprehensive performance of the semiconductor device, and the layout flexibility of these interconnection structures can be improved. In addition, the crosstalk of the power layer to these interconnection structures can be reduced, the sensing tolerance of the interconnection structure can be improved, and the chip size can be reduced accordingly.

[0082] In addition, refer again Figure 1 In one embodiment of the present application, the connection layer 600 may include a bonding layer, and the semiconductor device 1000 may further include a first contact structure 610 extending through the bonding layer in the z direction, and the first contact structure 610 may connect the word line 330 and the second interconnect layer 702, and the bit line 310 and the second interconnect layer 702. Optionally, the first contact structure 610 may include a vertical interconnect channel. The use of a vertical interconnect channel can increase the input / output transmission speed between two bonded wafers, and is beneficial to the length of the interconnect structure between the two bonded wafers, thereby reducing the parasitic capacitance of the interconnect structure, and improving the sensing tolerance and storage density of the semiconductor device.

[0083] In addition, in one embodiment of the present application, the second semiconductor structure 100 further includes a second contact structure 320. The second contact structure 320 is used to connect the memory cell 302 and the peripheral circuit 400-1. Optionally, the memory cell 302 is connected to the peripheral circuit 400-1 through the second contact structure 320 and the first contact structure 610 connected to the second contact structure 320. The second contact structure 320 may include any suitable conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), thallium nitride (TaN), polysilicon, silicide or any combination thereof. In some embodiments, the second contact structure 320 may include multiple conductive material layers, such as a W layer on the TiN layer.

[0084] Therefore, according to the semiconductor device provided by at least one embodiment of the present application, the semiconductor device includes a first semiconductor structure and a power layer, wherein the first semiconductor structure includes a peripheral circuit and a substrate, and the power layer is located on the side of the substrate away from the peripheral circuit. The lines and the like included in the power layer are arranged on the side of the substrate away from the peripheral circuit, and the interconnection structure between the peripheral circuit and the power layer can be arranged on the side of the peripheral circuit close to the substrate without affecting the comprehensive performance of the semiconductor device, so that the interconnection structure between the peripheral circuit and other structures such as a storage array can be arranged on the side of the peripheral circuit away from the substrate. Therefore, the layout space of the interconnection structure related to the peripheral circuit is expanded, and the layout flexibility of these interconnection structures is improved. In addition, the crosstalk of the power layer to these interconnection structures can be reduced, the sensing tolerance of the interconnection structure can be improved, and the overall size of the chip where the semiconductor device is located can be reduced accordingly.

[0085] Some embodiments of the present application provide a method for preparing a semiconductor device. Figure 3 is a flow chart of a method 2000 for fabricating a semiconductor device according to an exemplary embodiment of the present application. Figure 4-Figure 8 They are respectively process schematic diagrams of a method 2000 for preparing a semiconductor device according to an embodiment of the present application.

[0086] like Fig. 9 As shown, the present application provides a method 2000 for preparing a semiconductor device, comprising:

[0087] S1, providing a substrate, and forming a peripheral circuit layer including a peripheral circuit on a first side of the substrate to form a first semiconductor structure.

[0088] S2, forming a power layer connected to a peripheral circuit on a second side of the substrate opposite to the first side in the first direction.

[0089] The following will be combined Figure 3-Figure 8 The specific process of each step of the above-mentioned preparation method 2000 in Example 1 is described in detail.

[0090] Step S1

[0091] Figure 4 It is a schematic cross-sectional view of a structure formed after forming an initial first semiconductor structure 200 ′ according to a manufacturing method in one embodiment of the present application.

[0092] like Figure 1 , Figure 3 and Figure 4As shown, in some embodiments of the present application, step S1 provides a substrate and forms a peripheral circuit layer including a peripheral circuit on a first side of the substrate to form a first semiconductor structure, which may, for example, include: forming a substrate 401; forming a peripheral circuit layer 400 including a peripheral circuit 400-1; and forming a second interconnect layer 702.

[0093] Specifically, Figure 4 As shown, in one embodiment of the present application, the material for preparing the substrate 401 can be any suitable semiconductor material, for example, single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI) or III-V compounds such as gallium arsenide. As an option, the substrate 401 can be selected from single crystal silicon.

[0094] In one embodiment of the present application, the substrate 401 may be, for example, a composite substrate for supporting a device structure thereon. The substrate 401 may be formed by sequentially arranging a plurality of layers made of different materials through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0095] In one embodiment of the present application, the substrate 401 may include a substrate sacrificial layer (not shown). Optionally, the substrate sacrificial layer may include a single layer, a multilayer or a suitable composite layer. For example, the substrate sacrificial layer may include any one or more of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer. As an option, the substrate sacrificial layer may be a high dielectric constant dielectric layer. As another option, the substrate sacrificial layer may include a dielectric layer, a sacrificial layer and a dielectric layer arranged in sequence, wherein the dielectric layer may be a silicon nitride layer and the sacrificial layer may be a silicon oxide layer. As another option, the substrate sacrificial layer may include any one or more of a dielectric material, a semiconductor material and a conductive material. For example, the sacrificial layer may be single crystal silicon or polycrystalline silicon. Specifically, in one embodiment of the present application, an exemplary material for forming the sacrificial layer may be polycrystalline silicon.

[0096] In addition, a part of the substrate 401 may also form a well region (not shown) doped with an N-type or P-type dopant via an ion implantation or diffusion process. The dopant may include any one or a combination of phosphorus (P), arsenic (As) and antimony (Sb); or any one or a combination of boron (B), gallium (Ga) or indium (In). In some embodiments of the present application, the well region may be prepared with the same dopant or with different dopants. Furthermore, the doping concentration of the well region may be the same or different, which is not limited in the present application.

[0097] Furthermore, the substrate 401 may include the same semiconductor material layer as the semiconductor body of the second semiconductor structure described below.

[0098] The substrate 401 includes two sides opposite to each other in a first direction (z direction), a first side 01 and a second side 02. After forming the substrate 401, a peripheral circuit layer 400 may be formed on the first side 01 of the substrate 401. The peripheral circuit layer 400 includes a peripheral circuit 400-1. Optionally, a portion of the peripheral circuit 400-1 may extend from the first side 01 into the substrate 401 along the z direction. In other words, the peripheral circuit 400-1 may be in or on the substrate 401. The peripheral circuit 400-1 may include at least one of a driving structure (not shown) and a sensing structure (not shown).

[0099] According to some embodiments, the peripheral circuit 400-1 may be implemented using complementary metal-oxide-semiconductor (CMOS) technology, for example. The manufacturing process and structural design of the peripheral circuit 400-1 may adopt existing conventional processes and be designed according to actual needs, which will not be described in detail here.

[0100] In some embodiments, a plurality of memory cells (e.g., a memory array) of a semiconductor device and peripheral circuits connected to the plurality of memory cells may be formed on two different wafers (e.g., a memory array wafer and a peripheral circuit wafer), and then the peripheral circuit wafer is bonded to the memory array wafer by processes such as wafer bonding, and the peripheral circuit and the memory array circuit are connected together by connecting wires, contact structures, interconnect structures, etc. However, as the structure of semiconductor devices continues to develop toward high density, the area of ​​the peripheral circuit wafer is increasingly becoming a key factor in determining the size of the entire chip.

[0101] In at least one embodiment of the present application, the lines and the like included in the power layer of the peripheral circuit wafer are arranged on the side of the substrate away from the peripheral circuit, and the interconnection structure between the peripheral circuit and the power layer can be arranged on the side of the peripheral circuit close to the substrate without affecting the comprehensive performance of the semiconductor device, so that the interconnection structure between the peripheral circuit and other structures such as the storage array can be arranged on the side of the peripheral circuit away from the substrate. Therefore, the layout space of the interconnection structure related to the peripheral circuit is expanded, and the layout flexibility of these interconnection structures is improved. In addition, the crosstalk of the power layer to these interconnection structures can be reduced, the sensing tolerance of the interconnection structure can be improved, and the overall size of the chip where the semiconductor device is located can be reduced accordingly.

[0102] Specifically, the interconnection structure may include an interconnection layer 700, and the interconnection layer 700 may include a second interconnection layer 702 and a first interconnection layer formed subsequently. The second interconnection layer 702 may include an interconnection path extending along the z direction and an interconnection line extending along a second direction (e.g., the x direction or the y direction) intersecting the z direction. The second interconnection layer 702 is used to connect the peripheral circuit 400-1 and the memory array 300 (e.g., Figure 1 The first interconnection layer may also include interconnection paths extending along the z direction and interconnection lines extending along a second direction intersecting the z direction. The first interconnection layer is used to connect the peripheral circuit 400-1 and a power supply layer formed subsequently.

[0103] After the peripheral circuit 400-1 is formed, a second interconnection layer 702 may be formed on the side of the peripheral circuit 400-1 away from the substrate 401. The structure and preparation process of the interconnection paths and interconnection lines of the second interconnection layer 702 may adopt existing conventional processes and be prepared according to actual needs, which will not be described in detail here.

[0104] In addition, after forming the second interconnect layer 702, a first dielectric spacer 220 covering at least the second interconnect layer 702 and the peripheral circuit 400-1 may be formed by one or more thin film deposition processes.

[0105] The first dielectric spacer layer 220 may include any suitable dielectric material, such as an oxide, a nitride, an oxynitride, or a high-k dielectric. For example, the first dielectric spacer layer 220 may include silicon oxide.

[0106] In addition, optionally, the surface of the first dielectric spacer layer 220 is processed by a planarization process of any suitable technology, such as grinding and / or chemical mechanical polishing process, so that the processed first dielectric spacer layer 220 has a relatively flat surface, so as to facilitate bonding on the flat surface. Optionally, the bonding process may be, for example, bonding.

[0107] Step S2

[0108] Figure 5 It is a schematic cross-sectional view of a structure formed after forming an initial second semiconductor structure 100 ′ according to a preparation method in one embodiment of the present application. Figure 6 It is a schematic cross-sectional view of a structure formed after forming a carrier 120 according to a preparation method in one embodiment of the present application. Figure 7 It is a schematic cross-sectional view of a structure formed after forming a partial interconnection structure according to a preparation method in one embodiment of the present application. Figure 8 It is a schematic diagram of a process of combining an initial first semiconductor structure 200 ′ and an initial second semiconductor structure 100 ′ according to a manufacturing method according to an embodiment of the present application.

[0109] like Figure 4-Figure 8 As shown, in some embodiments of the present application, before forming a power layer connected to a peripheral circuit on a second side of the substrate opposite to the first side in the first direction in step S2, the method 2000 for preparing a semiconductor device further includes forming an initial second semiconductor structure 100'.

[0110] Specifically, forming the initial second semiconductor structure 100' may include, for example: forming a substrate 110; forming a memory array 300 including a plurality of memory cells 300-1 on the substrate 110; attaching a temporary carrier 120 to the back side 04 of the substrate 110 away from the memory array 300; and forming a partial interconnect structure.

[0111] like Figure 5 As shown, in one embodiment of the present application, the material for preparing the substrate 110 can be any suitable semiconductor material, for example, single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI) or III-V compounds such as gallium arsenide. As an option, the substrate 110 can be selected from single crystal silicon.

[0112] In one embodiment of the present application, the substrate 110 may be, for example, a composite substrate for supporting a device structure thereon. The substrate 110 may be formed by sequentially arranging a plurality of layers made of different materials through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0113] In one embodiment of the present application, the substrate 110 may include a substrate sacrificial layer (not shown). Optionally, the substrate sacrificial layer may include a single layer, a multilayer or a suitable composite layer. For example, the substrate sacrificial layer may include any one or more of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer. As an option, the substrate sacrificial layer may be a high dielectric constant dielectric layer. As another option, the substrate sacrificial layer may include a dielectric layer, a sacrificial layer and a dielectric layer arranged in sequence, wherein the dielectric layer may be a silicon nitride layer and the sacrificial layer may be a silicon oxide layer. As another option, the substrate sacrificial layer may include any one or more of a dielectric material, a semiconductor material and a conductive material. For example, the sacrificial layer may be single crystal silicon or polycrystalline silicon. Specifically, in one embodiment of the present application, an exemplary material for forming the sacrificial layer may be polycrystalline silicon.

[0114] In addition, a part of the substrate 110 may also form a well region (not shown) formed by doping with an N-type or P-type dopant via an ion implantation or diffusion process. The dopant may include any one or a combination of phosphorus (P), arsenic (As) and antimony (Sb); or any one or a combination of boron (B), gallium (Ga) or indium (In). In some embodiments of the present application, the well region may be prepared with the same dopant or with different dopants. Further, the doping concentration of the well region may be the same or different, which is not limited in the present application.

[0115] After forming the substrate 110, a memory array 300 may be formed on the substrate 110. In some embodiments of the present application, forming the memory array 300 may include, for example: forming a first supporting layer 303 on the substrate 110; forming a memory cell 302 on the first supporting layer 303; and forming a semiconductor body 310 connected to the memory cell 302 on the memory cell 302, wherein the semiconductor body 310 extends along the z direction.

[0116] In addition, in some other embodiments of the present application, forming a memory array 300 may, for example, include: forming a bit line 310 on a substrate 100; forming a transistor 301 on the bit line 310, wherein the transistor 301 includes a semiconductor body and a gate structure; and forming a memory cell 302 connected to the transistor 301.

[0117] The present application does not limit the method for forming the memory array 300 and the structure of the memory cell 300 - 1 . The following will take the example of first forming the memory cell 302 and then forming the transistor 301 as an example, and describe the method for preparing the memory array 300 in detail with reference to the accompanying drawings.

[0118] Specifically, in one embodiment of the present application, the first support layer 303 may be formed by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. Thin film deposition process or any combination thereof. The first support layer 303 may include any suitable conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), thallium nitride (TaN), polysilicon, silicide or any combination thereof. In some embodiments, the first support layer 303 may include multiple conductive material layers, such as a W layer on a TiN layer. The first support layer 303 may extend in an xy plane, wherein the x direction, the y direction and the z direction intersect each other.

[0119] Optionally, the surface of the first support layer 303 is processed by a planarization process using any suitable technology, such as grinding and / or chemical mechanical polishing, so that the processed first support layer 303 has a relatively flat surface, so as to form a storage unit 302 on the flat surface. The structure and preparation process of the storage unit 302 can be prepared according to actual needs using existing conventional processes, and will not be described in detail in this application.

[0120] Alternatively, in some embodiments, taking DRAM as an example, the storage unit 302 may include a capacitor, and a plurality of storage units 302 may be arranged in a two-dimensional array. Alternatively, in some embodiments, taking a PCM element as an example, the storage unit 302 may include a unit having different resistivities in an amorphous phase and a crystalline phase to store a corresponding PCM. For example, a chalcogenide alloy is included. Alternatively, in some embodiments, taking FRAM as an example, the storage unit 302 may include a ferroelectric capacitor. This application is not limited thereto.

[0121] In addition, after forming the storage unit 302, a second dielectric spacer 111 covering at least the storage unit 302 may be formed by one or more thin film deposition processes. The thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0122] The second dielectric spacer 111 may include any suitable dielectric material, such as oxide, nitride, oxynitride or high-k dielectric. For example, the second dielectric spacer 111 may include silicon oxide. Optionally, the second dielectric spacer 111 and the subsequently formed third dielectric spacer 112 and fourth dielectric spacer 113 are made of the same material. When the same material is used, there is no obvious boundary between the three.

[0123] It should be noted that in this article Figure 4-Figure 8In the present invention, only the number and position of memory cells, interconnection structures and peripheral circuits are shown by way of example, but it can be understood that the memory cells, interconnection structures and peripheral circuits shown in the figures and related contents herein are only shown for the convenience of illustration, and the present application is not limited thereto. Those skilled in the art can adjust the memory cells, interconnection structures and peripheral circuits according to the concept of the present invention to achieve the same technical effect.

[0124] After forming the memory cell 302 , a semiconductor body 311 connected to the memory cell 302 may be formed on the memory cell 302 , wherein the semiconductor body 311 extends along the z-direction.

[0125] Alternatively, the semiconductor body 311 may be formed by a thin film process. For example, the semiconductor body 311 may be an oxide semiconductor layer including at least one of indium, gallium, or zinc.

[0126] As another option, the semiconductor body 311 may be formed by, for example, etching or epitaxial processes, and may have the same semiconductor material as the substrate 110. For example, the semiconductor body 311 may include, but is not limited to, silicon (e.g., single crystal silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable semiconductor material. In this case, the semiconductor body 311 may also be formed with the base 401 (e.g., Figure 4 ) include the same semiconductor material layers.

[0127] In addition, a source (not shown) and a drain (not shown) may be formed at opposite ends of the semiconductor body 311 in the z direction through a doping process, which may be understood as a doping region of the semiconductor body 311, and may also be referred to as a source electrode and a drain electrode. As an option, the source and the drain may be doped with any suitable P-type dopant, which may include any one or a combination of boron (B) or gallium (Ga). As another option, the source and the drain may be doped with any suitable N-type dopant, which may include any one or a combination of phosphorus (P), arsenic (As) and antimony (Sb).

[0128] After forming the semiconductor body 311, a gate structure (not shown) connected to the semiconductor body 311 may be formed. In one embodiment of the present application, forming the gate structure may, for example, include: using the third dielectric spacer 112 to at least cover the semiconductor body 311; forming an opening (not shown) by removing a portion of the third dielectric spacer 112, wherein the opening extends along the z direction and exposes a portion of the sidewall of the semiconductor body 311; and forming the gate structure in the opening.

[0129] Optionally, the opening is formed by, for example, a dry etching process or a combination of dry and wet etching processes; in addition, other manufacturing processes, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., may also be performed to form the opening.

[0130] After forming the opening, a gate structure may be formed on the inner wall of the opening by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0131] The gate structure may include a gate dielectric layer (not shown) and a gate conductive layer (not shown) on and in contact with the gate dielectric layer. In addition, the gate conductive layer may include: a gate adhesion layer (not shown) and a gate metal layer (not shown) on and in contact with the gate adhesion layer. In other words, the gate adhesion layer is located between the gate dielectric layer 312-1 and the gate metal layer.

[0132] The gate dielectric layer may include any suitable dielectric material, such as an oxide, a nitride, an oxynitride, or a high-k dielectric. For example, the gate dielectric layer may include silicon oxide. In addition, the gate adhesion layer may include, but is not limited to, titanium, titanium nitride, tantalum, tantalum nitride, etc. In addition, the gate metal layer may include any suitable conductive material, such as the gate metal layer may include, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), etc. The gate adhesion layer is used to block the diffusion of metal materials in the gate metal layer, and is also used to improve the adhesion between the gate metal layer and the gate dielectric layer.

[0133] In addition, the semiconductor body 311 includes an upper end and a lower end opposite to each other in the z direction, and the lower end is connected to the memory cell 302. As an option, a bit line 310 may be formed on the top of the semiconductor body 311.

[0134] For example, the bit line 310 is formed by one or more thin film deposition processes, which may include but are not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0135] Optionally, the gate structure may extend along an x-direction perpendicular to the z-direction and be located on at least one sidewall of the semiconductor body 311 .

[0136] The bit line 310 may extend in a y direction perpendicular to the z direction. Optionally, the bit line 310 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), thallium nitride (TaN), polysilicon, silicide, or any combination thereof. In some embodiments, the bit line 310 may include multiple conductive layers, such as a W layer on a TiN layer.

[0137] After forming the bit line 310, a fourth dielectric spacer 113 covering the bit line 310 may be formed by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0138] Alternatively, the fourth dielectric spacer 113 may include any suitable dielectric material, such as oxide, nitride, oxynitride, or high-k dielectric. For example, the fourth dielectric spacer 113 may include silicon oxide.

[0139] In addition, optionally, after the gate structure is formed, a word line (not shown) connecting the gate structure may be formed by one or more thin film deposition processes, and the thin film deposition process may include but is not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0140] The word line may extend in an x-direction perpendicular to the z-direction. Optionally, the word line may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), thallium nitride (TaN), polysilicon, silicide, or any combination thereof. In some embodiments, the word line may include multiple conductive layers, such as a W layer on top of a TiN layer.

[0141] like Figure 6 As shown, in some embodiments of the present application, the substrate 110 has two opposite sides along the z direction, namely, a front side 03 and a back side 04. After forming the memory array 300, a temporary carrier 120 may be attached to the back side 04 of the substrate 110 away from the memory array 300, so as to facilitate subsequent connection with the initial first semiconductor structure (such as Figure 4 shown) combination.

[0142] Optionally, the intermediate including the memory array 300 and the substrate 110 may be fixed on the temporary carrier 120 by, for example, a temporary attachment layer (not shown). The temporary attachment layer may be simply removed after being combined with the initial first semiconductor structure, and the present application does not limit the temporary attachment layer, the temporary carrier 120, and the attachment process.

[0143] like Figure 6 and Figure 7 As shown, in some embodiments of the present application, after the intermediate body is attached to the temporary carrier 120, a partial interconnection structure may be formed on a side of the intermediate body away from the temporary carrier 120, wherein the partial interconnection structure is Figure 1 A portion of the interconnect structure of the semiconductor device 1000 shown. Specifically, the partial interconnect structure may include a bit line interconnect line 16 connected to the bit line 310, a gate interconnect line 26 connected to the gate structure, and a storage unit connection line 36 connected to the first support layer 303. Optionally, the bit line interconnect line 16, the gate interconnect line 26, and the storage unit connection line 36 can be connected to the peripheral circuit of the first semiconductor structure through a first contact structure formed subsequently. The structure and preparation process of the above-mentioned interconnect line can be prepared according to actual needs using existing conventional processes, and this application will not be repeated here.

[0144] like Figure 8 As shown, in some embodiments of the present application, before forming a power layer connected to the peripheral circuit on the second side of the substrate opposite to the first side in the first direction in step S2, the method 2000 for preparing a semiconductor device also includes: after forming an initial first semiconductor 200' including the peripheral circuit 400-1 and an initial second semiconductor 100' including the storage array 300, the initial first semiconductor 200' and the initial second semiconductor 100' are combined, wherein the initial second semiconductor structure 100' is located on one side of the initial first semiconductor structure 100' along the z direction, and the subsequently formed power layer is located on the other side of the initial first semiconductor structure 100'.

[0145] Optionally, the bonding process may be a bonding process, for example, a hybrid bonding process is used to bond the initial first semiconductor 200 ′ and the initial second semiconductor 100 ′.

[0146] refer to Figure 8 In the case of using a bonding process, a first contact structure 610 extending through the bonding layer along the z direction may be formed. Optionally, the first contact structure 610 may include a vertical interconnection channel. Using a vertical interconnection channel may increase the input / output transmission speed between the two bonded wafers, and facilitate the interconnection between the two bonded wafers. The bit line interconnection line 16, the gate interconnection line 26, and the storage unit connection line 36 are connected at 610.

[0147] In addition, reference Figure 1 and Figure 8In some embodiments of the present application, after combining the initial second semiconductor structure 100' and the initial first semiconductor structure 200', step S2 forms a power layer connected to the peripheral circuit on a second side of the substrate opposite to the first side in the first direction, which may, for example, include: forming a power layer 500 on a side of the initial first semiconductor structure 200' away from the initial second semiconductor structure 100', thereby forming the second semiconductor structure 100 and the first semiconductor structure 200.

[0148] In addition, optionally, after combining the initial second semiconductor structure 100' and the initial first semiconductor structure 200', the first interconnection layer 701 may be formed first, and then the power layer 500 connected to the first interconnection layer 701 may be formed. Alternatively, after combining the initial second semiconductor structure 100' and the initial first semiconductor structure 200', the first interconnection layer 701 and the power layer 500 are formed in the same process. The preparation process of the first interconnection layer 701 and the power layer 500 can adopt the existing conventional process and be prepared according to actual needs, which will not be described in detail here.

[0149] In addition, combined Figure 1 , Figure 4 and Figure 8 As described above, in one embodiment of the present application, before combining the initial second semiconductor structure 100' and the initial first semiconductor structure 200', a second interconnect layer 702 is formed on a side of the peripheral circuit layer 400 away from the substrate 401, and the second interconnect layer 702 connects the peripheral circuit 400-1 and the storage array 300; after combining the initial second semiconductor structure 100' and the initial first semiconductor structure 200', a first interconnect layer 701 is formed on a side of the substrate 401 away from the peripheral circuit layer 400-1 (second side 02), and the first interconnect layer 701 connects the peripheral circuit 400-1 and a power supply layer formed subsequently.

[0150] Optionally, the first interconnection layer 701 and the second interconnection layer 702 each include an interconnection via extending along the z-direction and an interconnection line extending along a second direction (eg, the x-direction or the y-direction) intersecting the x-direction.

[0151] Optionally, in one embodiment of the present application, forming the first interconnection layer 701 may include: forming an interconnection path extending in the first semiconductor structure along the z direction, wherein the interconnection path 701-1 of the first interconnection layer 701 (hereinafter referred to as the first interconnection path 701-1) at least extends through the substrate 401 and the peripheral circuit layer 400. In other words, the first interconnection path 701-1 is set to extend along the z direction and pass through the substrate 401 and the peripheral circuit layer 400 to connect the peripheral circuit 400-1 and the subsequently formed power supply layer. The first interconnection path extends along the z direction to connect the peripheral circuit and the power supply layer, which is conducive to shortening the length of the interconnection structure between the peripheral circuit and the power supply layer, thereby reducing the parasitic capacitance of the interconnection structure and improving the sensing tolerance and storage density of the semiconductor device. Optionally, the first interconnection path 701-1 may include a through silicon contact structure (Through Silicon Contact, TSC), which is not limited in the present application.

[0152] Optionally, refer to Figure 1 , Figure 2A and Figure 8 , the power layer 500 includes a pad lead-out structure 502 and a power line 501. The pad lead-out structure 502 can connect an external electrical signal to the power line 501; or connect an external electrical signal to the peripheral circuit 400-1. Optionally, the power line 501 is set to extend in the xy plane, wherein at least two power lines 501 have different widths perpendicular to their own extension directions. For example, the first power line 511 and the second power line 512 are set to extend along the y direction, and the third power line 513 and the fourth power line 514 are set to extend along the x direction, wherein the first power line 511, the second power line 512, the third power line 513 and the fourth power line 514 all have widths perpendicular to their own extension directions, which are the first width W1, the second width W2, the third width W3 and the fourth width W4, respectively. Among them, the sizes of the first width W1, the second width W2, the third width W3 and the fourth width W4 can be set to be different.

[0153] Compared with the external electrical signal, the power line will have a voltage drop in the direction in which it extends. For example, the power line may have a voltage drop of 5% to 10% in the direction in which it extends or in the direction in which the current flows. By setting the power line as a wider conductor, the voltage drop caused by current fluctuations can be reduced and the stability of the power supply of the power line can be increased. In addition, the power line supplies power to the peripheral circuit, which can be connected to a large number of parallel circuits, including high-frequency circuits, medium-frequency circuits, low-frequency circuits, etc. In this embodiment, the width of the power line connected to the circuit in the direction in which it extends can be reasonably set according to the actual needs of the above-mentioned circuits in the peripheral circuit.

[0154] In addition, in one embodiment of the present application, the power layer 500 may also include a plurality of layer structures sequentially arranged in the z direction. For example, a plurality of power lines 501 extending in the xy plane may form a layer structure, and the power layer 500 may include a plurality of layer structures sequentially arranged in the z direction and including the power lines 501 to meet actual needs.

[0155] According to the method for preparing a semiconductor device provided by at least one embodiment of the present application, the semiconductor device includes a first semiconductor structure and a power layer, wherein the first semiconductor structure includes a peripheral circuit and a substrate, and the power layer is located on the side of the substrate away from the peripheral circuit. The lines included in the power layer are arranged on the side of the substrate away from the peripheral circuit, and the interconnection structure between the peripheral circuit and the power layer can be arranged on the side of the peripheral circuit close to the substrate without affecting the comprehensive performance of the semiconductor device, so that the interconnection structure between the peripheral circuit and other structures such as a storage array can be arranged on the side of the peripheral circuit away from the substrate. Therefore, the layout space of the interconnection structure related to the peripheral circuit is expanded, and the layout flexibility of these interconnection structures is improved. In addition, the crosstalk of the power layer to these interconnection structures can be reduced, the sensing tolerance of the interconnection structure can be improved, and the overall size of the chip where the semiconductor device is located can be reduced accordingly.

[0156] in addition, Fig. 9 It is a schematic diagram of the structure of a storage system 30000 according to one embodiment of the present application.

[0157] like Fig. 9 As shown, at least one embodiment of another aspect of the present application further provides a storage system 30000. The storage system 30000 may include a semiconductor device 20000 and a controller 32000. The semiconductor device 20000 may be the same as the semiconductor device described in any embodiment above, and the present application will not repeat it. The semiconductor device 20000 may be a two-dimensional semiconductor device or a three-dimensional semiconductor device, or even a part of a two-dimensional semiconductor device or a part of a three-dimensional semiconductor device. The following will be described by taking a three-dimensional semiconductor device as an example.

[0158] As an option, the three-dimensional semiconductor device may include at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0159] The storage system 30000 may include a semiconductor device 20000 and a controller 32000. The semiconductor device 20000 may be the same as the semiconductor device described in any of the above embodiments, and this application will not repeat them. The controller 32000 may control the semiconductor device 20000 through a channel CH, and the semiconductor device 20000 may perform operations based on the control of the controller 32000 in response to a request from a host 31000. The semiconductor device 20000 may receive a command CMD and an address ADDR from the controller 32000 through the channel CH and access an area selected from a memory cell array in response to the address. In other words, the semiconductor device 20000 may perform an internal operation corresponding to the command on the area selected by the address.

[0160] In some embodiments, the three-dimensional storage system can be implemented as a universal flash storage (UFS) device, a solid state drive (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and micro MMC, a secure digital card in the form of SD, mini SD and micro SD, a storage device of the Personal Computer Memory Card International Association (PCMCIA) card type, a storage device of the peripheral component interconnect (PCI) type, a storage device of the high-speed PCI (PCI-E) type, a compact flash (CF) card, a smart media card or a memory stick, etc. The storage system provided in the present application has the same beneficial effects as the semiconductor device provided in the present application because the semiconductor device provided in the present application is provided, and no further description is given here.

[0161] Although an exemplary method and structure of manufacturing a semiconductor device are described herein, it is understood that one or more features may be omitted, replaced or added from the structure of the semiconductor device. In addition, the materials of each layer exemplified are merely exemplary.

[0162] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by the selected combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other to form a technical solution.

Claims

1. A semiconductor device, characterized in that, it comprises: a first semiconductor structure including a substrate and a peripheral circuit layer located on a first side of the substrate; and a power supply layer located on a second side of the substrate opposite to the first side in a first direction and connected to a peripheral circuit in the peripheral circuit layer.

2. The semiconductor device according to claim 1, wherein, the semiconductor device further comprises a second semiconductor structure and a connection layer, wherein the second semiconductor structure is located on a side of the first semiconductor structure away from the power supply layer along the first direction and includes a storage array connected to the peripheral circuit; and the connection layer is located between the second semiconductor structure and the first semiconductor structure.

3. The semiconductor device according to claim 2, wherein, the first semiconductor structure further comprises an interconnect layer, and the interconnect layer includes a first interconnect layer and a second interconnect layer, wherein the first interconnect layer is located between the peripheral circuit and the power supply layer; the second interconnect layer is located between the peripheral circuit and the connection layer; and the interconnect layer includes interconnect paths extending along the first direction and interconnect lines extending along a second direction intersecting the first direction.

4. The semiconductor device according to claim 3, wherein, the interconnect paths of the first interconnect layer extend at least through the substrate and the peripheral circuit layer along the first direction to connect the peripheral circuit and the power supply layer.

5. The semiconductor device according to claim 3, wherein, the storage array includes memory cells and word lines and bit lines connected to the memory cells; and the peripheral circuit includes a driving structure connected to the word line and a sensing structure connected to the bit line, wherein the second interconnect layer connects the word line to the driving structure and the bit line to the sensing structure.

6. The semiconductor device according to claim 5, wherein, the connection layer includes a bonding layer, wherein the semiconductor device further includes a first contact structure extending through the bonding layer along the first direction, and the first contact structure connects the word line to the second interconnect layer and the bit line to the second interconnect layer.

7. The semiconductor device according to claim 1, wherein, the power supply layer includes a pad lead-out structure and a power line, wherein the power line extends in a plane perpendicular to the first direction; and at least two of the power lines have different widths perpendicular to the extending direction.

8. The semiconductor device according to claim 2, wherein, the storage array includes at least one of non-volatile memory cells and volatile memory cells.

9. The semiconductor device according to claim 8, wherein, the volatile memory cells include at least one of dynamic random access memory cells, phase change memory cells or ferroelectric memory cells.

10. The semiconductor device according to claim 8, wherein, the volatile memory cells include vertical transistors and storage cells connected to the vertical transistors, Wherein, along the first direction, the vertical transistor is close to the first semiconductor structure relative to the memory cell.

11. The semiconductor device according to claim 10, in, The vertical transistor includes at least one of a gate-all-around transistor, a multi-gate transistor, and a single-gate transistor.

12. The semiconductor device according to claim 10, in, The vertical transistor includes a semiconductor body, Wherein, the substrate and the semiconductor body include the same semiconductor material layer.

13. A method for preparing a semiconductor device, It is characterized in that include: Providing a substrate, and forming a peripheral circuit layer including a peripheral circuit on a first side of the substrate to form a first semiconductor structure; as well as A power supply layer connected to the peripheral circuit is formed on a second side of the substrate opposite to the first side in the first direction.

14. The method according to claim 13, in, The method further comprises: combining a second semiconductor structure including a memory array with the first semiconductor structure, The second semiconductor structure is located along the first direction on a side of the first semiconductor structure away from the power layer.

15. The method according to claim 13, in, Before forming the power layer, the method further includes: forming an interconnection via extending in the first semiconductor structure along the first direction, The interconnection path at least extends through the substrate and the peripheral circuit layer to connect the peripheral circuit and the power supply layer.

16. The method according to claim 14, in, Combining a second semiconductor structure including a memory array with the first semiconductor structure, wherein the combination includes bonding, and the method further includes: A first contact structure is formed along the first direction and penetrates the bonding layer to connect the second semiconductor structure and the first semiconductor structure.

17. The method according to claim 14, in, Before forming a power supply layer connected to the peripheral circuit, the method further includes: Before combining a second semiconductor structure including a memory array with the first semiconductor structure, forming a second interconnect layer on a side of the peripheral circuit layer away from the substrate, the second interconnect layer connecting the peripheral circuit and the memory array; and After combining the second semiconductor structure including the memory array with the first semiconductor structure, a first interconnection layer is formed on a side of the substrate away from the peripheral circuit layer, wherein the first interconnection layer connects the peripheral circuit and the power supply layer. The first interconnection layer and the second interconnection layer each include an interconnection path extending along the first direction and an interconnection line extending along a second direction intersecting the first direction.

18. The method according to claim 13, in, The power layer includes a pad lead-out structure and a power line, and the power layer connected to the peripheral circuit includes: forming the pad lead-out structure and a plurality of the power lines, wherein the plurality of power lines extend in a plane perpendicular to the first direction; and At least two of the power lines have different widths perpendicular to the extension direction.

19. A storage system, It is characterized in that The storage system comprises a controller and the semiconductor device according to any one of claims 1 to 12, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

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