Semiconductor element and manufacturing method thereof
By designing a multi-layer nitride and oxide layer structure in semiconductor components and depositing a protective lining layer on the inner side wall of the trench, the problem of increasing resistance after etching of the nitride layer is solved, and better electrical performance is achieved.
Patent Information
- Application Number
- CN202410304921.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-11-22
- Filing Date
- 2024-03-18
- Publication Date
- 2025-05-23
AI Technical Summary
In semiconductor processes, the etch resistance of the nitride layer causes shrinkage problems when the trench passes through the nitride layer, which in turn leads to high resistance between the electrode layer and the landing pad.
A semiconductor element is designed, which includes a multi-layer nitride and oxide layer structure. By forming a trench and depositing a protective lining layer on its inner side wall, the width of the expansion portion of the trench is controlled, thereby increasing the contact area between the electrode layer and the landing pad and reducing resistance.
Through this method, the electrical performance of the semiconductor element is improved, the resistance between the electrode layer and the landing pad is reduced, and the problem of increasing resistance after etching of the nitride layer is solved.
Smart Images
Figure CN120035131A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor device and a manufacturing method thereof. Background Art
[0002] As semiconductor processes continue to evolve, the process of forming trenches will face challenges. For example, the trenches in the semiconductor structure of dynamic random access memory (DRAM) are preferably manufactured to have a high aspect ratio. However, since the nitride layer has a large etching resistance, the portion of the trench that passes through the nitride layer may experience shrinkage problems, resulting in high resistance between the electrode layer and the landing pad formed in the subsequent process. Summary of the invention
[0003] In view of this, an object of the present disclosure is to provide a semiconductor device and a manufacturing method thereof that can solve the above problems.
[0004] In order to achieve the above-mentioned object, according to one embodiment of the present disclosure, a semiconductor element includes a landing pad, a first nitride layer, a first oxide layer, a second nitride layer, a second oxide layer, a third nitride layer, an electrode layer and a filling material. The first nitride layer is disposed above the landing pad. The first oxide layer is disposed on the first nitride layer. The second nitride layer is disposed on the first oxide layer. The second oxide layer is disposed on the second nitride layer. The third nitride layer is disposed on the second oxide layer. The groove passes through the third nitride layer, the second oxide layer, the second nitride layer, the first oxide layer and the first nitride layer. The groove further has an extension portion passing through the first nitride layer. The width of the top of the extension portion of the groove is greater than or equal to the width of the top of the groove. The electrode layer is disposed on the inner sidewall of the groove, on the top surface of the third nitride layer, and on the top surface and sidewall of the landing pad. The filling material is filled in the groove and contacts the landing pad through the electrode layer.
[0005] In one or more embodiments of the present disclosure, the filling material contacts the top surface and the sidewalls of the landing pad through the electrode layer.
[0006] In one or more embodiments of the present disclosure, the extended portion of the groove is located above the landing pad.
[0007] In one or more embodiments of the present disclosure, the width of the extended portion of the trench tapers downward from the top surface of the first nitride layer to the top surface of the landing pad.
[0008] In one or more embodiments of the present disclosure, a width of a top portion of the extended portion of the trench is greater than a width of a bottom portion of the extended portion of the trench.
[0009] In one or more embodiments of the present disclosure, the width of the top of the extended portion of the trench is greater than the width of the top of the trench.
[0010] In one or more embodiments of the present disclosure, a height from a top surface of the first nitride layer to a top surface of the landing pad is in a range from 20 nm to 25 nm.
[0011] In one or more embodiments of the present disclosure, the first oxide layer includes borophosphosilicate glass.
[0012] In one or more embodiments of the present disclosure, the second oxide layer includes tetraethylorthosilicate.
[0013] To achieve the above-mentioned purpose, according to one embodiment of the present disclosure, a method for manufacturing a semiconductor element includes: sequentially forming a landing pad, a first nitride layer, a first oxide layer, a second nitride layer, a second oxide layer and a third nitride layer; forming a groove penetrating the third nitride layer, the second oxide layer, the second nitride layer and the first oxide layer; depositing a protective liner layer on multiple surfaces of the first nitride layer, the second nitride layer and the third nitride layer; punching through the first nitride layer and exposing the landing pad; etching the first nitride layer and exposing the sidewall of the landing pad; removing the protective liner layer; depositing an electrode layer on the inner surface of the groove and on the top surface of the third nitride layer; and depositing a filling material to fill the groove.
[0014] In one or more embodiments of the present disclosure, the step of forming a trench is performed to expose the first nitride layer.
[0015] In one or more embodiments of the present disclosure, the step of depositing the protective liner layer is performed such that the protective liner layer contacts a top surface of the first nitride layer.
[0016] In one or more embodiments of the present disclosure, performing the step of punching through the first nitride layer and exposing the landing pad results in removal of a portion of the protective liner layer on a top surface of the first nitride layer and a portion of the protective liner layer on a top surface of the third nitride layer.
[0017] In one or more embodiments of the present disclosure, the step of etching the first nitride layer and exposing the sidewall of the landing pad is performed after the step of punching through the first nitride layer and exposing the landing pad.
[0018] In one or more embodiments of the present disclosure, the step of etching the first nitride layer and exposing the sidewall of the landing pad forms an extension portion of the trench, and the extension portion of the trench penetrates the first nitride layer.
[0019] In one or more embodiments of the present disclosure, etching the first nitride layer is performed to expose the sidewalls of the landing pad so that the extension of the trench is connected between the landing pad and the top surface of the first nitride layer.
[0020] In one or more embodiments of the present disclosure, the step of etching the first nitride layer and exposing the sidewall of the landing pad causes the width of the top of the extended portion of the trench to be greater than the width of the bottom of the extended portion of the trench.
[0021] In one or more embodiments of the present disclosure, the step of etching the first nitride layer and exposing the sidewall of the landing pad is performed so that the width of the top of the extension portion of the trench is greater than or equal to the width of the top of the trench.
[0022] In one or more embodiments of the present disclosure, the step of depositing the electrode layer is performed such that the electrode layer contacts the top surface and the sidewall of the landing pad.
[0023] In one or more embodiments of the present disclosure, the thickness of the protective liner layer is greater than or equal to 2 nanometers. The protective liner layer comprises silicon oxynitride.
[0024] In summary, in the semiconductor device and the manufacturing method thereof disclosed in the present invention, since the protective liner layer is lined on the inner sidewall of the trench, the critical dimension of the trench will not be enlarged after the step of punching through the first nitride layer is performed. In the semiconductor device and the manufacturing method thereof disclosed in the present invention, since only the portion of the protective liner layer located on the top surface of the first nitride layer is removed, only the width of the bottom of the trench increases when the step of isotropically etching the first nitride layer is performed. In the semiconductor device and the manufacturing method thereof disclosed in the present invention, since the trench has an extended portion when the step of etching the first nitride layer and exposing the sidewall of the landing pad is performed, the contact area between the electrode layer and the landing pad can be increased, thereby reducing the resistance between the electrode layer and the landing pad. Overall, the manufacturing method of the semiconductor device disclosed in the present invention improves the electrical performance of the entire semiconductor device.
[0025] The above description is only used to illustrate the problem to be solved by the present disclosure, the technical means to solve the problem, and the effects produced, etc. The specific details of the present disclosure will be described in detail in the following implementation methods and related drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] In order to make the above and other purposes, features, advantages and implementation methods of the present disclosure more obvious and understandable, the attached drawings are described as follows:
[0027] Figure 1 The flowchart is a method for manufacturing a semiconductor device according to one embodiment of the present disclosure.
[0028] Figure 2 FIG. 4 is a cross-sectional view illustrating an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.
[0029] Figure 3FIG. 4 is a cross-sectional view illustrating an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.
[0030] Figure 4 FIG. 4 is a cross-sectional view illustrating an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.
[0031] Figure 5 FIG. 4 is a cross-sectional view illustrating an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.
[0032] Figure 6 FIG. 4 is a cross-sectional view illustrating an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.
[0033] Figure 7 FIG. 4 is a cross-sectional view illustrating an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.
[0034] Figure 8 FIG. 4 is a cross-sectional view illustrating an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.
[0035] Fig. 9 FIG. 4 is a top view illustrating an intermediate stage of manufacturing a semiconductor device according to an embodiment of the present disclosure.
[0036] Fig.10 To illustrate an embodiment of the present disclosure based on Fig. 9 A cross-sectional view of an intermediate stage in the manufacture of a semiconductor device taken along the cut line AA'.
[0037] Fig.11 To illustrate an embodiment of the present disclosure based on Fig. 9 A cross-sectional view of an intermediate stage in the manufacture of a semiconductor device taken along the cut line BB'. DETAILED DESCRIPTION
[0038] The following disclosure provides many different embodiments or embodiments for realizing the different features of the provided patent subject matter. The specific embodiments of the components and configurations are described below to simplify the disclosure. Of course, these are only embodiments and are not intended to be limiting. For example, in the following specification, a first feature formed above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the disclosure may repeat reference numerals and / or letters in a variety of embodiments. Such repetition is for the purpose of simplicity and clarity, and does not itself dictate the relationship between the various embodiments and / or configurations discussed.
[0039] Additionally, for ease of description, spatially relative terms such as "below," "below," "lower," "above," "upper," etc. may be used herein to describe the relationship between one element or feature and another element or feature shown in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatially relative terms used herein may likewise be interpreted accordingly.
[0040] As used herein, "approximately," "about," "roughly," or "substantially" generally means within 20%, or within 10%, or within 5% of a given value or range. The numerical values given herein are approximate, meaning that if not explicitly stated, the term "approximately," "about," "roughly," or "substantially" can be inferred.
[0041] Please refer to Figure 1 . Figure 1 According to one embodiment of the present disclosure, Figure 8 A flow chart of method M of semiconductor device 100 is shown. Figure 1 The method M shown includes step S101, step S102, step S103, step S104, step S105, step S106, step S107 and step S108. For a better understanding of step S101 and step S102, please refer to Figure 1 as well as Figure 2 For a better understanding of step S103, please refer to Figure 1 as well as Figure 3 For a better understanding of step S104, please refer to Figure 1 as well as Figure 4 For a better understanding of step S105, please refer to Figure 1 as well as Figure 5 For a better understanding of step S106, please refer to Figure 1 as well as Figure 6 For a better understanding of step S107, please refer to Figure 1 as well as Figure 7 For a better understanding of step S108, please refer to Figure 1 , Figure 8 , Fig. 9 , Fig.10 as well as Fig.11 .
[0042] Step S101 , step S102 , step S103 , step S104 , step S105 , step S106 , step S107 , and step S108 are described in detail below.
[0043] In step S101 , a landing pad 110 , a first nitride layer 120 , a first oxide layer 130 , a second nitride layer 140 , a second oxide layer 150 , and a third nitride layer 160 are sequentially formed.
[0044] Please refer to Figure 1 as well as Figure 2 . Figure 2 FIG. 1 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. In the present embodiment, a landing pad 110, a first nitride layer 120, a first oxide layer 130, a second nitride layer 140, a second oxide layer 150, and a third nitride layer 160 are sequentially formed. In some embodiments, the landing pad 110, the first nitride layer 120, the first oxide layer 130, the second nitride layer 140, the second oxide layer 150, and the third nitride layer 160 are formed along Figure 2 The landing pad 110 is formed in the direction Z shown. More specifically, the first nitride layer 120 is disposed above the landing pad 110. In some embodiments, the first nitride layer 120 covers the landing pad 110. In some embodiments, the first nitride layer 120 covers at least the top surface and multiple side surfaces of the landing pad 110. The first oxide layer 130 is disposed on the first nitride layer 120. The second nitride layer 140 is disposed on the first oxide layer 130. The second oxide layer 150 is disposed on the second nitride layer 140. The third nitride layer 160 is disposed on the second oxide layer 150. Figure 2 As shown, the third nitride layer 160 has a top surface 160 a .
[0045] In some embodiments, the landing pad 110 may be a conductive material. In some embodiments, the landing pad 110 may be a metallic material. In some embodiments, the landing pad 110 may include materials such as tungsten (W) or other similar materials. However, any suitable material may be used.
[0046] In some embodiments, the landing pad 110 may be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating or other similar methods. The present disclosure is not intended to be limited to the method of forming the landing pad 110.
[0047] In some embodiments, the first nitride layer 120 may be a nitride material. In some embodiments, the first nitride layer 120 may include, for example, silicon nitride (Si x N y ) or other similar materials. However, any suitable material may be used.
[0048] In some embodiments, the first nitride layer 120 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating or other similar methods. The present disclosure is not intended to limit the method for forming the first nitride layer 120.
[0049] In some embodiments, the first oxide layer 130 may be an oxide material. In some embodiments, the first oxide layer 130 may include a material such as borophosphosilicate glass (BPSG) or other similar materials. However, any suitable material may be used.
[0050] In some embodiments, the first oxide layer 130 may be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating or other similar methods. The present disclosure is not intended to limit the method for forming the first oxide layer 130.
[0051] In some embodiments, the second nitride layer 140 may be a nitride material. In some embodiments, the second nitride layer 140 may include, for example, silicon nitride (Si x N y ) or other similar materials. However, any suitable material may be used.
[0052] In some embodiments, the second nitride layer 140 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating or other similar methods. The present disclosure is not intended to limit the method for forming the second nitride layer 140.
[0053] In some embodiments, the second oxide layer 150 may be an oxide material. In some embodiments, the second oxide layer 150 may include tetraethyl orthosilicate (TEOS) or other similar materials. However, any suitable material may be used.
[0054] In some embodiments, the second oxide layer 150 may be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating or other similar methods. The present disclosure is not intended to limit the method for forming the second oxide layer 150.
[0055] In some embodiments, the third nitride layer 160 may be a nitride material. In some embodiments, the third nitride layer 160 may include, for example, silicon nitride (Si x N y ) or other similar materials. However, any suitable material may be used.
[0056] In some embodiments, the third nitride layer 160 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating or other similar methods. The present disclosure is not intended to limit the method for forming the third nitride layer 160.
[0057] In step S102 , a trench T is formed.
[0058] Please continue to refer to Figure 1 as well as Figure 2 .like Figure 2 As shown, in this embodiment, the trench T is formed from the top surface 160a of the third nitride layer 160. In some embodiments, the trench T is formed so that the first nitride layer 120 is exposed. In some embodiments, the trench T penetrates the third nitride layer 160, the second oxide layer 150, the second nitride layer 140, and the first oxide layer 130. In some embodiments, step S102 is performed so that the trench T is located above the landing pad 110. Figure 2 As shown, the first nitride layer 120 has a top surface 120a. In some embodiments, the trench T is formed so that the top surface 120a of the first nitride layer 120 is exposed. In some embodiments, step S102 is performed so that the bottom of the trench T is flush with the top surface 120a of the first nitride layer 120. Figure 2 As shown, the trench T has an inner surface Ta, and the inner surface Ta includes a side surface 130 s of the first oxide layer 130 , a side surface 140 s of the second nitride layer 140 , a side surface 150 s of the second oxide layer 150 , and a side surface 160 s of the third nitride layer 160 .
[0059] In some embodiments, the trench T may be formed by any suitable method, such as dry etching or other similar methods. The present disclosure is not intended to be limited to the method for forming the trench T.
[0060] In step S103 , a protective liner layer 170 is formed.
[0061] Please refer to Figure 1 as well as Figure 3 . Figure 3 FIG. 1 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. Figure 3 As shown, the protective liner layer 170 is disposed on the third nitride layer 160. In some embodiments, the protective liner layer 170 lines the trench T. In some embodiments, the protective liner layer 170 is deposited on multiple surfaces of the first nitride layer 120, the second nitride layer 140, and the third nitride layer 160. More specifically, due to the difference in chemical properties between the oxide layer and the nitride layer, the protective liner layer 170 is deposited on the top surface 160a and the side surface 160s of the third nitride layer 160, on the side surface 140s of the second nitride layer 140, and on the top surface 120a of the first nitride layer 120. In some embodiments, the protective liner layer 170 is formed so that the protective liner layer 170 contacts the top surface 120a of the first nitride layer 120.
[0062] In some embodiments, the protective liner layer 170 has a thickness T 170 In some embodiments, the thickness T of the protective liner layer 170 is 170 is equal to or greater than about 2 nanometers (nm), but the present disclosure is not limited thereto. The thickness T of the protective liner layer 170 170 In some embodiments where the trench T is less than about 2 nanometers, the trench T may not be able to resist an etching process in a subsequent step, thereby causing the quality of the trench T to deteriorate.
[0063] In some embodiments, the protective liner layer 170 includes an oxide, a nitride, or an oxynitride. In some embodiments, the protective liner layer 170 may include a material such as silicon oxynitride (SiON) or other similar materials. However, any suitable material may be used.
[0064] In some embodiments, the protective liner layer 170 may be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating or other similar methods. The present disclosure is not intended to be limited to the method of forming the protective liner layer 170. In some embodiments, the protective liner layer 170 is preferably formed by an ALD process.
[0065] In some embodiments, the protective liner layer 170 is formed by a blanket deposition process. The present disclosure is not intended to be limited to the method of forming the protective liner layer 170 .
[0066] In step S104 , the first nitride layer 120 is punched through and the landing pad 110 is exposed.
[0067] Please refer to Figure 1 as well as Figure 4 . Figure 4 FIG. 1 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. Figure 4 As shown, in this embodiment, the first nitride layer 120 is penetrated to expose the landing pad 110. Figure 4 As shown, the landing pad 110 has a top surface 110a. In some embodiments, the first nitride layer 120 is etched through the trench T so that the top surface 110a of the landing pad 110 is exposed. In some embodiments, performing step S104 causes the portion of the protective liner layer 170 located on the top surface 120a of the first nitride layer 120 to be removed. Figure 4 As shown, in some embodiments, the first nitride layer 120 is punched through so that the trench T is connected to the landing pad 110 .
[0068] Please refer to Figure 4 In some embodiments, step S104 is performed to cause the width of the first nitride layer 120 to taper downward from the top surface 120 a of the first nitride layer 120 to the top surface 110 a of the landing pad 110 .
[0069] In some embodiments, the first nitride layer 120 may be punched through by any suitable method, such as dry etching or other similar methods. The present disclosure is not intended to be limited to the method of punching through the first nitride layer 120 .
[0070] In some embodiments, the first nitride layer 120 may be punched through by any suitable method, such as isotropic etching or other similar methods. The present disclosure is not intended to be limited to the method of punching through the first nitride layer 120 .
[0071] In some embodiments, the first nitride layer 120 may be etched through using any suitable etchant, such as ammonium (NH 4 ), Hydrogen fluoride (HF 4 ) or other similar etchants. The present disclosure is not intended to be limited to the method of punching through the first nitride layer 120.
[0072] In step S105 , the first nitride layer 120 is etched and the sidewalls of the landing pad 110 are exposed.
[0073] Please refer to Figure 1 as well as Figure 5 . Figure 5 FIG. 1 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. In this embodiment, after the first nitride layer 120 is punched through and the landing pad 110 is exposed, the first nitride layer 120 is etched and the sidewall of the landing pad 110 is exposed. More specifically, after performing step S104, the first nitride layer 120 is further consumed. Figure 5 As shown, in some embodiments, etching the first nitride layer 120 results in forming an extension portion T120 of the trench T. More specifically, the extension portion T120 extends from the trench T and penetrates the first nitride layer 120. In some embodiments, the extension portion T120 of the trench T is connected between the top surface 110a of the landing pad 110 and the top surface 120a of the first nitride layer 120. In some embodiments, the formation of the extension portion T120 results in the sidewall of the landing pad 110 being exposed. Figure 5 As shown, in step S105, the overall width of the extension portion T120 is relative to Figure 4 Increase.
[0074] In some embodiments, the first nitride layer 120 can be etched using any suitable method, such as isotropic etching or other similar methods. The present disclosure is not intended to be limited to the method of etching the first nitride layer 120 .
[0075] In some embodiments, the first nitride layer 120 may be etched by using any suitable etching gas, for example, phosphoric acid (H 3 PO 4 ) or other similar etching gases. The present disclosure is not intended to limit the method for etching the first nitride layer 120.
[0076] In some embodiments, the width of the top of the extension portion T120 of the trench T is greater than the width of the bottom of the extension portion T120 of the trench T. In some embodiments, the width of the extension portion T120 of the trench T tapers downward from the top surface 120 a of the first nitride layer 120 to the top surface 110 a of the landing pad 110 .
[0077] In some embodiments, the extension portion T120 has a height H 120 In some embodiments, the height H 120 is defined as the distance from the top surface 120a of the first nitride layer 120 to the top surface 110a of the landing pad 110. In some embodiments, the height H 120In the range between about 20 nanometers (nm) and about 25 nanometers (nm). In some embodiments where the distance from the top surface 120a to the top surface 110a is greater than about 25 nanometers, the top surface 110a may not be exposed. In some embodiments where the distance from the top surface 120a to the top surface 110a is less than about 20 nanometers, the first nitride layer 120 may be over-etched, causing a capacitor formed in a subsequent process to have a leakage problem due to a seam in a portion of the first nitride layer 120 surrounding the land pad 110.
[0078] In step S106 , the protective liner layer 170 is removed.
[0079] Please refer to Figure 1 as well as Figure 6 . Figure 6 FIG. 1 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. Figure 6 As shown, in the present embodiment, the protective liner layer 170 is removed from the inner surface Ta of the trench T. More specifically, the protective liner layer 170 is removed from the side surface 160s of the third nitride layer 160 and the side surface 140s of the second nitride layer 140. In some embodiments, the protective liner layer 170 is sacrificial, and the protective liner layer 170 is completely removed.
[0080] In some embodiments, the protective liner layer 170 can be removed by any suitable method, such as wet etching or other similar methods. In some embodiments, the protective liner layer 170 can be removed by using, for example, hydrofluoric acid (HF) or other similar materials. The present disclosure is not intended to be limited to the method of removing the protective liner layer 170.
[0081] In some embodiments, the protective liner layer 170 can be removed by any suitable method, such as isotropic etching or other similar methods. The present disclosure is not intended to be limited to the method of removing the protective liner layer 170 .
[0082] like Figure 6 As shown, in some embodiments, the extension portion T120 of the trench T has a width W of the top of the extension portion T120 of the trench T. T120U and the width W of the bottom of the extension portion T120 of the trench T T120L More specifically, the width W T120U is defined as the width of the extension portion T120 extending on the top surface 120a, and the width W T120L The width W of the top of the trench T is defined as the width of the extension portion T120 extending on the top surface 110a. T More specifically, the width W TThe width W of the top of the extended portion T120 of the trench T is defined as the width of the trench T extending on the top surface 160a. T120U Greater than the width W of the bottom of the extension portion T120 of the trench T T120L In some embodiments, the width W of the top of the extension portion T120 of the trench T is T120U Greater than the width W of the top of the trench T T .
[0083] In step S107 , the electrode layer 180 is formed.
[0084] Please refer to Figure 1 as well as Figure 7 . Figure 7 FIG. 1 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. Figure 7 As shown, in this embodiment, the electrode layer 180 is disposed on the third nitride layer 160. In some embodiments, the electrode layer 180 lines the trench T and the extension T120 of the trench T. In some embodiments, the electrode layer 180 is deposited on the inner surface Ta of the trench T, the top surface 160a of the third nitride layer 160, and the extension T120. In some embodiments, since the sidewall of the landing pad 110 is exposed in step S105, the electrode layer 180 is further deposited on the top surface 110a and the sidewall of the landing pad 110. In some embodiments, the electrode layer 180 is formed so that the electrode layer 180 contacts the top surface 110a and the sidewall of the landing pad 110.
[0085] In some embodiments, electrode layer 180 is configured as a lower electrode of a capacitor.
[0086] In some embodiments, the electrode layer 180 comprises a conductive material. In some embodiments, the electrode layer 180 comprises a nitride. In some embodiments, the electrode layer 180 may comprise a material such as titanium nitride (TiN) or other similar materials. However, any suitable material may be used.
[0087] In some embodiments, the electrode layer 180 can be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating or other similar methods. The present disclosure is not intended to limit the method for forming the electrode layer 180. In some embodiments, the electrode layer 180 is preferably formed by a CVD process.
[0088] In some embodiments, the electrode layer 180 is formed by a blanket deposition process. The present disclosure is not intended to be limited to the method of forming the electrode layer 180 .
[0089] In some embodiments, the method M also includes a step of modifying the trench T after step S106 and before step S107. More specifically, the trench T may be pulled back so that the profile of the trench T becomes straighter. Therefore, in some embodiments, the width W of the top of the extension portion T120 of the trench T is T120U Equal to the width W of the top of the trench T T .
[0090] In step S108 , a filling material FM is formed.
[0091] Please refer to Figure 1 as well as Figure 8 . Figure 8 FIG. 1 is a cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. Figure 8 As shown, in the present embodiment, a filling material FM is deposited to fill the trench T so as to form a semiconductor device 100. More specifically, the filling material FM fills the trench T and the extension T120 of the trench T. In some embodiments, the step of depositing the filling material FM to fill the trench T is performed so that the filling material FM contacts the landing pad 110. Specifically, the step of depositing the filling material FM to fill the trench T is performed so that the filling material FM contacts the top surface 110a and the sidewall of the landing pad 110 through the electrode layer 180.
[0092] In some embodiments, the filling material FM is configured as a memory of a capacitor.
[0093] In some embodiments, the fill material FM includes a conductive material. In some embodiments, the electrode layer 180 includes a nitride. In some embodiments, the fill material FM may include a material such as titanium nitride (TiN) or other similar materials. However, any suitable material may be used.
[0094] In some embodiments, the filling material FM may be formed by any suitable method, such as CVD (chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), PVD (physical vapor deposition), ALD (atomic layer deposition), PEALD (plasma enhanced atomic layer deposition), ECP (electrochemical plating), chemical plating or other similar methods. The present disclosure is not intended to be limited to the method of forming the filling material FM.
[0095] Please refer to Figure 1 and Fig. 9 . Fig. 9FIG. 1 is a top view of an intermediate stage of manufacturing a semiconductor device 100 according to an embodiment of the present disclosure. For simplicity of description, Fig. 9 Only the landing pad 110, the filling material FM, the cutting line AA' along the direction X, and the cutting line BB' along the direction Y are shown. Fig. 9 As shown, in this embodiment, the landing pad 110 has an oval or ellipse shape, and the filling material FM has a circle shape.
[0096] Please refer to Figure 1 as well as Fig.10 . Fig.10 According to an embodiment of the present disclosure, Fig. 9 FIG. 1 is a cross-sectional view of an intermediate stage of manufacturing the semiconductor device 100 along the cutting line AA′. Fig.10 As shown, in this embodiment, the filling material FM is located above the landing pad 110. Fig.10 As shown, the landing pad 110 has a side 110s. Fig.10 The electrode layer 180 is omitted. In some embodiments, along the Fig. 9 As shown along the cut line AA′, the filler material FM contacts the top surface 110 a of the landing pad 110 , but does not contact the side surfaces 110 s of the landing pad 110 .
[0097] Please refer to Figure 1 as well as Fig.11 . Fig.11 According to an embodiment of the present disclosure, Fig. 9 A cross-sectional view of an intermediate stage of manufacturing a semiconductor device 100 along the cutting line BB'. For simplicity of explanation, Fig.11 The electrode layer 180 is also omitted. Fig.11 As shown, in some embodiments, along the Fig. 9 As shown in the cut line BB', the filler material FM contacts the top surface 110a and the side surface 110s of the landing pad 110. More specifically, as shown in FIG. Fig.11 As shown, the shape of the structure of the filling material FM contacting the landing pad 110 is similar to a saddle. The “saddle contact” of the filling material FM results in an increase in the contact area between the filling material FM and the landing pad 110.
[0098] By executing this disclosure Figure 1 The method M shown can form a semiconductor device 100 with better electrical performance.
[0099] From the above detailed description of the specific embodiments of the present disclosure, it can be clearly seen that in the semiconductor device and the manufacturing method thereof disclosed in the present disclosure, since the protective liner layer is lined on the inner side wall of the groove, the critical dimension of the groove will not be enlarged after the step of punching through the first nitride layer is performed. In the semiconductor device and the manufacturing method thereof disclosed in the present disclosure, since only the portion of the protective liner layer located on the top surface of the first nitride layer is removed, only the width of the bottom of the groove increases when the step of isotropically etching the first nitride layer is performed. In the semiconductor device and the manufacturing method thereof disclosed in the present disclosure, since the groove has an extended portion when the step of etching the first nitride layer and exposing the side wall of the landing pad is performed, the contact area between the electrode layer and the landing pad can be increased, thereby reducing the resistance between the electrode layer and the landing pad. Overall, the manufacturing method of the semiconductor device disclosed in the present disclosure improves the electrical performance of the entire semiconductor device.
[0100] Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
[0101] The above content summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present invention. Those skilled in the art should understand that the above content can be easily used as a basis for designing or modifying other variations without departing from the spirit and scope of the present invention to implement the same purpose and / or achieve the same advantages of the embodiments described herein. The above content should be understood as an example of the present disclosure, and its scope of protection should be based on the claims.
[0102]
Explanation of symbols
[0103] 100:Semiconductor components
[0104] 110: Landing Pad
[0105] 110a, 120a, 160a: top surface
[0106] 110s,130s,140s,150s,160s: Side
[0107] 120: first nitride layer
[0108] 130: First oxide layer
[0109] 140: Second nitride layer
[0110] 150: Second oxide layer
[0111] 160: third nitride layer
[0112] 170: Protective lining
[0113] 180: Electrode layer
[0114] A-A', B-B': Cutting line
[0115] FM: Filling material
[0116] H 120 :high
[0117] M: Method
[0118] S101, S102, S103, S104, S105, S106, S107, S108: Steps
[0119] T: Groove
[0120] T120: Extension
[0121] T 170 :thickness
[0122] Ta: Inner surface
[0123] W T ,W T120L ,W T120U :width
[0124] X,Y,Z: direction.
Claims
1. A semiconductor element, characterized in that: Include: Landing pad; a first nitride layer disposed above the landing pad; A first oxide layer, disposed on the first nitride layer; A second nitride layer is disposed on the first oxide layer; A second oxide layer is disposed on the second nitride layer; a third nitride layer, disposed on the second oxide layer, and a trench penetrating the third nitride layer, the second oxide layer, the second nitride layer, the first oxide layer, and the first nitride layer, wherein the trench further has an extension portion penetrating the first nitride layer, and a width of a top of the extension portion of the trench is greater than or equal to a width of a top of the trench; an electrode layer, disposed on the inner sidewall of the groove, on the top surface of the third nitride layer, and on the top surface and sidewall of the landing pad; as well as A filling material is filled in the groove and contacts the landing pad through the electrode layer.
2. The semiconductor device according to claim 1, characterized in that The filling material contacts the top surface and the sidewall of the landing pad through the electrode layer.
3. The semiconductor device according to claim 1, wherein: The extended portion of the groove is located above the landing pad.
4. The semiconductor device according to claim 1, wherein: The width of the extended portion of the trench tapers downward from a top surface of the first nitride layer to a top surface of the landing pad.
5. The semiconductor device according to claim 1, wherein: The width of the top of the extended portion of the groove is greater than the width of the bottom of the extended portion of the groove.
6. The semiconductor device according to claim 1, characterized in that The width of the top of the extended portion of the groove is greater than the width of the top of the groove.
7. The semiconductor device according to claim 1, wherein: A height from a top surface of the first nitride layer to a top surface of the landing pad is in a range from 20 nanometers to 25 nanometers.
8. The semiconductor device according to claim 1, wherein: The first oxide layer includes borophosphosilicate glass.
9. The semiconductor device according to claim 1, wherein: The second oxide layer includes tetraethyl orthosilicate.
10. A method for manufacturing a semiconductor element, characterized in that: Include: sequentially forming a landing pad, a first nitride layer, a first oxide layer, a second nitride layer, a second oxide layer, and a third nitride layer; forming a groove penetrating the third nitride layer, the second oxide layer, the second nitride layer, and the first oxide layer; Depositing a protective liner layer on multiple surfaces of the first nitride layer, the second nitride layer, and the third nitride layer; punching through the first nitride layer and exposing the landing pad; etching the first nitride layer and exposing sidewalls of the landing pad; removing the protective liner; depositing an electrode layer on the inner surface of the trench and on the top surface of the third nitride layer; as well as A fill material is deposited to fill the trench.
11. The method according to claim 10, characterized in that The step of forming the trench is performed such that the first nitride layer is exposed.
12. The method according to claim 10, characterized in that The step of depositing the protective liner layer is performed such that the protective liner layer contacts a top surface of the first nitride layer.
13. The method according to claim 10, characterized in that Performing the step of punching through the first nitride layer and exposing the landing pad results in removal of a portion of the protective liner layer located on a top surface of the first nitride layer and a portion of the protective liner layer located on a top surface of the third nitride layer.
14. The method according to claim 10, characterized in that The step of etching the first nitride layer and exposing the sidewall of the landing pad is performed after the step of punching through the first nitride layer and exposing the landing pad.
15. The method according to claim 10, characterized in that Performing the step of etching the first nitride layer and exposing the sidewall of the landing pad results in forming an extension of the trench, and wherein the extension of the trench penetrates the first nitride layer.
16. The method according to claim 15, characterized in that The etching of the first nitride layer is performed to expose the sidewall of the landing pad so that the extension portion of the trench is connected between the landing pad and a top surface of the first nitride layer.
17. The method according to claim 15, characterized in that The step of etching the first nitride layer and exposing the sidewall of the landing pad is performed such that a width of a top portion of the extension portion of the trench is greater than a width of a bottom portion of the extension portion of the trench.
18. The method according to claim 17, characterized in that The step of etching the first nitride layer and exposing the sidewall of the landing pad is performed such that the width of the top of the extended portion of the trench is greater than or equal to the width of the top of the trench.
19. The method according to claim 10, characterized in that The step of depositing the electrode layer is performed such that the electrode layer contacts the top surface and the sidewalls of the landing pad.
20. The method according to claim 10, characterized in that The protective liner layer has a thickness greater than or equal to 2 nanometers, and wherein the protective liner layer comprises silicon oxynitride.