Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a manufacturing method of the semiconductor device. A semiconductor device may include: a peripheral circuit; a gate structure disposed on the peripheral circuit and including stacked gate lines; the first concave step structure is arranged in the gate structure; a second recessed stepped structure disposed within the gate structure and adjacent to the first recessed stepped structure in the first direction; a first gap filling insulating layer including a first line portion formed within the first recessed stepped structure, a second line portion formed within the second recessed stepped structure, and a bridge portion connecting the first line portion and the second line portion to each other; and a peripheral contact plug extending into the gate structure through the bridge portion of the first gap filling insulating layer and connected to a peripheral circuit.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to electronic devices, and more particularly, to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] The integration degree of a semiconductor device is mainly determined by the area occupied by a unit memory cell. Recently, as the improvement of the integration degree of a semiconductor device for forming a memory cell in a single layer on a substrate has reached a limit, a three-dimensional semiconductor device for stacking memory cells on a substrate has been proposed. In addition, in order to improve the operational reliability of such a semiconductor device, various structures and manufacturing methods have been developed. Summary of the invention

[0003] In an embodiment, a semiconductor device may include: a peripheral circuit; a gate structure, which is disposed on the peripheral circuit and includes a stacked gate line; a first recessed step structure, which is disposed within the gate structure; a second recessed step structure, which is disposed within the gate structure and is adjacent to the first recessed step structure in a first direction; a first gap-filling insulating layer, which includes a first line portion formed within the first recessed step structure, a second line portion formed within the second recessed step structure, and a bridging portion disposed between the first line portion and the second line portion and connecting the first line portion and the second line portion to each other; and a peripheral contact plug, which extends into the gate structure through the bridging portion of the first gap-filling insulating layer and is connected to the peripheral circuit.

[0004] In an embodiment, a semiconductor device may include: a peripheral circuit; a gate structure disposed on the peripheral circuit and including a stacked gate line; a first recessed step structure disposed within the gate structure; a second recessed step structure disposed within the gate structure; a first gap-filling insulating layer including a first line portion formed within the first recessed step structure, a second line portion formed within the second recessed step structure, and a bridging portion connecting the first line portion and the second line portion to each other; and a second gap-filling insulating layer located between the bridging portions and between the first line portion and the second line portion, wherein the second gap-filling insulating layer includes a gap extending along an edge of the first gap-filling insulating layer.

[0005] In an embodiment, a method for manufacturing a semiconductor device may include: forming a stack including a first material layer and a second material layer alternately stacked; forming a hard mask pattern on the stack, the hard mask pattern including a first opening having a ladder shape; forming a first recessed step structure by etching the stack exposed through the first opening; forming a second recessed step structure by etching the stack exposed through the first opening; forming a first gap-filling insulating layer, the first gap-filling insulating layer including a first line portion formed in the first recessed step structure, a second line portion formed in the second recessed step structure, and a bridge portion disposed between the first line portion and the second line portion and connecting the first line portion and the second line portion to each other; forming a second opening by removing the hard mask pattern; and forming a second gap-filling insulating layer in the second opening, the second gap-filling insulating layer including a void. The term "ladder shape" used herein means a structure having a series of horizontal elements and vertical elements with steps similar to a ladder. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figures 1A to 1E is a diagram showing a structure of a semiconductor device according to an embodiment.

[0007] Figure 2A and Figure 2B is a diagram for describing a structure of a semiconductor device according to an embodiment.

[0008] Figure 3A , Figure 4A , Figure 5A , Fig. 6A and Fig. 7A as well as Figure 3B , Figure 4B , Figure 5B , Figure 6B and Figure 7B 1 is a diagram for describing a method for manufacturing a semiconductor device according to an embodiment.

[0009] FIG. 8A to FIG. 8C 1 is a diagram for describing a method for manufacturing a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0010] Various embodiments relate to a semiconductor device having a stable structure and improved characteristics and a method of manufacturing the semiconductor device.

[0011] By three-dimensionally stacking memory cells, the integration degree of a semiconductor device can be improved. A semiconductor device having a stable structure and improved reliability can also be provided.

[0012] Hereinafter, embodiments according to the scope of the present disclosure will be described with reference to the accompanying drawings.

[0013] Figures 1A to 1Eis a diagram showing a structure of a semiconductor device according to an embodiment. Figure 1A is a plan view showing the structure of a semiconductor device according to an embodiment. Figure 1B It is along Figure 1A A cross-sectional view taken along line A-A', Figure 1C It is along Figure 1A A cross-sectional view taken along line BB' of Figure 1D It is along Figure 1A The cross-sectional view taken along the line C-C', Figure 1E yes Figure 1B Magnified view of area D in FIG.

[0014] Reference Figures 1A to 1D , the semiconductor device may include a gate structure GST, a first recessed step structure RS1, a second recessed step structure RS2, and a first gap-filling insulating layer GF1. The semiconductor device may also include a lower structure 10, a third recessed step structure RS31 to RS3n, a fourth recessed step structure RS41 to RS4n, a second gap-filling insulating layer GF2, a third gap-filling insulating layer GF31 to GF3n, a fourth gap-filling insulating layer GF41 to GF4n, a peripheral contact plug PCT, and cell contact plugs CCT1 to CCT4. Here, n may be an integer of 1 or more.

[0015] The lower structure 10 may include a substrate 1, an interlayer insulating layer 2, a peripheral circuit PC, a source structure, an interconnect structure, etc. An element isolation layer 6 may be located in the substrate 1, and an active region may be defined by the element isolation layer 6. The peripheral circuit PC may include a page buffer, a row decoder, a global data line (GDL) repeater, etc. In an embodiment, the peripheral circuit PC may include a transistor TR. The transistor TR may be located in the active region and may include a gate insulating layer 3, a gate electrode 4, and a junction 5. The transistor may constitute a repeater connected to the middle of the global data line.

[0016] The gate structure GST may be located on the lower structure 10. In an embodiment, the gate structure GST may be disposed on the peripheral circuit PC. The gate structure GST may include stacked gate lines 11. In an embodiment, the gate structure GST may include alternately stacked gate lines 11 and insulating layers 12. The gate line 11 may be a word line, a source selection line, or a drain selection line. The insulating layer 12 is used to insulate the stacked gate lines 11 from each other, and may each include oxide, nitride, air gap, etc.

[0017] The gate structure GST may include a first unit region CR1, a second unit region CR2, a first contact region CTR1, a second contact region CTR2, and a bridge region BR. The first unit region CR1 and the second unit region CR2 may be adjacent to each other in a first direction I. The bridge region BR may be located between the first unit region CR1 and the second unit region CR2. The first contact region CTR1 may be located between the first unit region CR1 and the bridge region BR, and the second contact region CTR2 may be located between the second unit region CR2 and the bridge region BR.

[0018] The first cell region CR1 and the second cell region CR2 may be regions where memory cells are stacked. The first contact region CTR1 and the second contact region CTR2 may be regions where an interconnect structure for transmitting a driving voltage to stacked memory cells is located. The first cell region CR1 and the first contact region CTR1 may belong to a first memory block MB1, and the second cell region CR2 and the second contact region CTR2 may belong to a second memory block MB2. Here, a memory block may be a unit of an erase operation.

[0019] The first channel structure CH1 may extend through the first cell region CR1 of the gate structure GST. The first channel structure CH1 may include at least one of a channel layer 13, a memory layer 14, and an insulating core 15. The memory layer 14 may include at least one of a barrier layer, a data storage layer, and a tunneling layer. The data storage layer may include a floating gate, polysilicon, a charge trapping material, a nitride, a variable resistance material, etc. The second channel structure CH2 may extend through the second cell region CR2 of the gate structure GST. The second channel structure CH2 may have a structure similar to the first channel structure CH1.

[0020] The recessed step structure may be located in the first contact region CTR1 and the second contact region CTR2 of the gate structure GST. The recessed step structure may be formed by patterning the gate structure GST in a stepped shape, and the pad PD of the gate line may be defined by the recessed step structure. The pad PD is a portion of the gate line that is not covered by the upper gate line. The gate structure GST may include a plurality of recessed step structures, and the recessed step structures may be located at different heights. The pads PD of the gate line 11 may be defined by the recessed step structures located at different heights, respectively.

[0021] The first recessed step structure RS1 and the second recessed step structure RS2 may be located within the gate structure GST. The first recessed step structure RS1 and the second recessed step structure RS2 may be located between the first channel structure CH1 and the second channel structure CH2. The first recessed step structure RS1 may be located in the first contact region CTR1, and the second recessed step structure RS2 may be located in the second contact region CTR2. The first recessed step structure RS1 and the second recessed step structure RS2 may be adjacent to each other in the first direction I with a bridge region BR interposed therebetween. The first recessed step structure RS1 may belong to the first storage block MB1, and the second recessed step structure RS2 may belong to the second storage block MB2.

[0022] The third recessed ladder structures RS31 to RS3n and the fourth recessed ladder structures RS41 to RS4n may be located within the gate structure GST. The third recessed ladder structures RS31 to RS3n may be located between the first channel structure CH1 and the first recessed ladder structure RS1. The pads of the gate lines 11 of the first storage block MB1 may be defined by the first recessed ladder structure RS1 and the third recessed ladder structures RS31 to RS3n, respectively. The fourth recessed ladder structures RS41 to RS4n may be located between the second channel structure CH2 and the second recessed ladder structure RS2. The pads of the gate lines 11 of the second storage block MB2 may be defined by the second recessed ladder structure RS2 and the fourth recessed ladder structures RS41 to RS4n, respectively.

[0023] The first gap-filling insulating layer GF1 may include a first line portion L1, a second line portion L2, and a bridge portion BP. For example, the first gap-filling insulating layer GF1 may include a plurality of bridge portions BP arranged in a second direction II intersecting the first direction I. The first line portion L1 may be located in the first recessed step structure RS1, and the second line portion L2 may be located in the second recessed step structure RS2. The bridge portion BP may be located in the bridge region BR, and may connect the first line portion L1 and the second line portion L2 to each other.

[0024] The first line portion L1 and the second line portion L2 may extend in the second direction II. The bridge portion BP may extend in the first direction I. In a plane defined by the first direction I and the second direction II (see Figure 1A ), the first gap-filling insulating layer GF1 may have a ladder shape. Figure 1B ), the first line portion L1 and the second line portion L2 may extend into the gate structure GST and may have a stepped bottom surface. The bottom surface of the first line portion L1 and the bottom surface of the second line portion L2 may be located at the same height or at different heights. The bridge portion BP may be located on the gate structure GST.

[0025] The second gap-filling insulating layer GF2 may be located on the gate structure GST, and may be located between the first line portion L1 and the second line portion L2 and the first gap-filling insulating layer GF1, the third gap-filling insulating layers GF31 to GF3n, and the fourth gap-filling insulating layers GF41 to GF4n. The second gap-filling insulating layer GF2 may extend in the second direction II between adjacent pairs of third gap-filling insulating layers among the third gap-filling insulating layers GF31 to GF3n and between adjacent pairs of fourth gap-filling insulating layers among the fourth gap-filling insulating layers GF41 to GF4n. The second gap-filling insulating layer GF2 may have an island shape surrounded by the first line portion L1, the second line portion L2, and the bridge portion BP, and the second gap-filling insulating layers GF2 having the island shape may be spaced apart from each other in the second direction II.

[0026] The third gap-filling insulating layers GF31 to GF3n may be located in the third recessed stepped structures RS31 to RS3n, respectively. The third gap-filling insulating layers GF31 to GF3n may have a stepped bottom surface. The fourth gap-filling insulating layers GF41 to GF4n may be located in the fourth recessed stepped structures RS41 to RS4n, respectively. The fourth gap-filling insulating layers GF41 to GF4n may have a stepped bottom surface.

[0027] The cell contact plugs CCT1 to CCT4 may extend through the gap-filling insulating layers GF1, GF31 to GF3n, and GF41 to GF4n, and may be respectively connected to the pads PD of the gate lines 11. The first cell contact plug CCT1 may extend through the first line portion L1 of the first gap-filling insulating layer GF1, and may be respectively connected to the pads PD defined by the first recessed step structure RS1. The second cell contact plug CCT2 may extend through the second line portion L2 of the first gap-filling insulating layer GF1, and may be respectively connected to the pads PD defined by the second recessed step structure RS2. The third cell contact plug CCT3 may extend through the third gap-filling insulating layers GF31 to GF3n, and may be respectively connected to the pads PD defined by the third recessed step structures RS31 to RS3n. The fourth cell contact plug CCT4 may extend through the fourth gap-filling insulating layers GF41 to GF4n, and may be respectively connected to the pads PD defined by the fourth recessed step structures RS41 to RS4n.

[0028] The peripheral contact plug PCT may extend through the gate structure GST and may be electrically connected to the peripheral circuit PC. Between the first recessed step structure RS1 and the second recessed step structure RS2, the gate structure GST may include a sacrificial layer 11S and an insulating layer 12 alternately stacked. Here, the sacrificial layer 11S may be a layer that is retained in the manufacturing process and is not replaced by the gate line 11. The peripheral contact plug PCT may extend through the alternately stacked sacrificial layer 11S and the insulating layer 12. Alternatively, the peripheral contact plug PCT may extend through the gate line 11 and the insulating layer 12, and an insulating spacer may surround the sidewall of the peripheral contact plug PCT.

[0029] The peripheral contact plug PCT may include a first peripheral contact plug PCT1 and a second peripheral contact plug PCT2. The first peripheral contact plug PCT1 may be connected to a gate electrode 4 of the transistor TR. The second peripheral contact plug PCT2 may be connected to a junction 5 of the transistor TR. In an embodiment, the transistor TR may belong to a global data line repeater. The first peripheral contact plug PCT1 and the second peripheral contact plug PCT2 may be directly connected to the transistor TR or connected to the transistor TR through an interconnection structure. In an embodiment, the first peripheral contact plug PCT1 and the second peripheral contact plug PCT2 may be connected to the transistor TR through a contact plug and / or a wiring.

[0030] According to the above structure, the first gap-filling insulating layer GF1 may have a ladder shape. The peripheral contact plug PCT may be spaced apart from the edge of the bridge portion BP and may extend into the gate structure GST through the bridge portion BP.

[0031] Figure 2A and Figure 2B is a diagram for describing a structure of a semiconductor device according to an embodiment. Figure 2B It is along Figure 2A Hereinafter, contents repeated with those previously described may be omitted.

[0032] Reference Figure 2A and Figure 2B The semiconductor device may include a gate structure GST, a first gap-filling insulating layer GF1, a second gap-filling insulating layer GF2, and a peripheral contact plug PCT. The gate structure GST may include alternately stacked gate lines 21 and insulating layers 22, or alternately stacked sacrificial layers 21S and insulating layers 22.

[0033] The first gap filling insulating layer GF1 may include a first line portion L1, a second line portion L2, and a bridge portion BP. The second gap filling insulating layer GF2 may be formed between the first line portion L1, the second line portion L2, and the bridge portion BP. The second gap filling insulating layer GF2 may include a void. The void V may be set adjacent to the edge EG of the first gap filling insulating layer GF1, but may be located at a position not in contact with the edge EG. The void V may extend along the edge EG of the first gap filling insulating layer GF1. The void V may be caused by the gradient of the sidewall of the first gap filling insulating layer GF1 in the manufacturing process. In an embodiment, the first gap filling insulating layer GF1 may have an inclined sidewall with an obtuse angle θ1, and the second gap filling insulating layer GF2 may have an inclined sidewall with an acute angle θ2. When the second gap filling insulating layer GF2 is formed by a deposition method, a void V may be formed in the second gap filling insulating layer GF2 by the inclined sidewall of the first gap filling insulating layer GF1. The void V may be spaced apart from the peripheral contact plug PCT.

[0034] When the first gap-filling insulating layer GF1 does not include the bridging portion BP, the void V and the peripheral contact plug PCT may overlap each other, and a bridge between the peripheral contact plugs PCT may be caused by the void V. According to an embodiment of the present disclosure, the first gap-filling insulating layer GF1 may have a ladder shape including the bridging portion BP, rather than a line shape extending in the second direction II. By locating the bridging portion BP at a position corresponding to the peripheral contact plug PCT, the peripheral contact plug PCT may be spaced apart from the void V, and a bridge caused by the void V may be prevented or reduced.

[0035] According to the above structure, even if the second gap-filling insulating layer GF2 includes the void V, the position of the void V may be adjusted by the bridge portion BP. The void V may not exist in the area covered by the bridge portion BP, and the peripheral contact plug PCT may be located in the bridge portion BP so that the peripheral contact plug PCT and the void V may be spaced apart from each other. Therefore, bridging caused between the peripheral contact plugs PCT by the void V may be prevented or reduced. In an embodiment, bridging caused between the peripheral contact plug PCT connected to the gate electrode of the transistor included in the global data line and the peripheral contact plug PCT connected to the junction of the transistor may be prevented or reduced.

[0036] Figure 3A , Figure 4A , Figure 5A , Fig. 6A and Fig. 7A as well as Figure 3B , Figure 4B , Figure 5B , Figure 6B and Figure 7B 1 is a diagram for describing a method for manufacturing a semiconductor device according to an embodiment. Figure 3A, Figure 4A , Figure 5A , Fig. 6A and Fig. 7A It is a floor plan. Figure 3B , Figure 4B , Figure 5B , Figure 6B and Figure 7B Along the Figure 3A , Figure 4A , Figure 5A , Fig. 6A and Fig. 7A Hereinafter, contents repeated with those previously described may be omitted.

[0037] Reference Figure 3A and Figure 3B , a stack ST including alternately stacked first material layers 31 and second material layers 32 may be formed. Here, the first material layers 31 may each include a material having a high etching selectivity relative to the second material layers 32. The first material layers 31 may be used to form gate lines. The second material layers 32 may be used to insulate the stacked gate lines from each other. In an embodiment, the first material layers 31 may each include a sacrificial material such as a nitride or a conductive material such as polysilicon or a metal. The second material layers 32 may each include an insulating material such as an oxide and a nitride or an air gap.

[0038] The stack ST may include a first contact region CTR1, a second contact region CTR2, and a bridge region BR. The bridge region BR may be located between the first contact region CTR1 and the second contact region CTR2. Here, the first contact region CTR1 may belong to the first memory block MB1, and the second contact region CTR2 may belong to the second memory block MB2.

[0039] Subsequently, a hard mask pattern HM may be formed on the stack ST. The hard mask pattern HM may include a first opening OP1 exposing an area where a recessed step structure is to be formed. The first opening OP1 may be located in the first contact region CTR1 and / or the second contact region CTR2. The first openings OP1 may have the same shape as each other or different shapes. For example, the first opening OP1A may have a ladder shape, and the first opening OP1B may have a line shape extending in the second direction II. The hard mask pattern HM may include nitride.

[0040] Reference Figure 4A and Figure 4B, a first mask pattern 41 may be formed on the hard mask pattern HM and the stack ST. The first mask pattern 41 may expose at least a portion of a region where a recessed step structure is to be formed. Subsequently, a recessed step structure RS may be formed by patterning the stack ST in a step shape using the first mask pattern 41 as an etching barrier. In an embodiment, a process of reducing the first mask pattern 41 and etching the stack ST may be repeatedly performed. Thus, the stack ST exposed by the first opening OP1 may be etched to form a recessed step structure RS. Subsequently, the first mask pattern 41 may be removed.

[0041] Reference Figure 5A and Figure 5B , a second mask pattern 42 may be formed on the stack ST and the hard mask pattern HM. The second mask pattern 42 may expose at least one recessed step structure RS. Subsequently, the exposed recessed step structure RS may be extended into the stack ST by using the second mask pattern 42 as an etching barrier. Subsequently, the second mask pattern 42 may be removed. The process of forming the second mask pattern 42 and etching the stack ST may be repeatedly performed for extending the recessed step structure RS into the stack ST, and forming first to fourth recessed step structures RS1, RS2, RS31 to RS3n, and RS41 to RS4n having different depths.

[0042] Reference Fig. 6A and Figure 6B , gap-filling insulating layers GF1, GF31 to GF3n, and GF41 to GF4n may be formed in the first to fourth recessed stepped structures RS1, RS2, RS31 to RS3n, and RS41 to RS4n. In an embodiment, an insulating layer may be formed to fill the first to fourth recessed stepped structures RS1, RS2, RS31 to RS3n, and RS41 to RS4n, and the gap-filling insulating layers GF1, GF31 to GF3n, and GF41 to GF4n may be formed by polishing the insulating layer to expose the hard mask pattern HM. Thus, the first gap-filling insulating layer GF1 may be formed in the first recessed stepped structure RS1 and the second recessed stepped structure RS2, the third gap-filling insulating layers GF31 to GF3n may be formed in the third recessed stepped structures RS31 to RS3n, respectively, and the fourth gap-filling insulating layers GF41 to GF4n may be formed in the fourth recessed stepped structures RS41 to RS4n, respectively. The first gap-filling insulating layer GF1 , the third gap-filling insulating layers GF31 to GF3n , and the fourth gap-filling insulating layers GF41 to GF4n may each include an oxide layer.

[0043] The first gap-filling insulating layer GF1 may include a first line portion L1 formed in the first recessed step structure RS1, a second line portion L2 formed in the second recessed step structure RS2, and a bridge portion BP disposed between the first line portion L1 and the second line portion L2 and connecting the first line portion L1 and the second line portion L2 to each other. In a plan view, the first gap-filling insulating layer GF1 may have a ladder shape. Since the hard mask pattern HM exists in an island shape between the bridge portions BP adjacent to each other in the second direction II, pits caused on the upper surface of the first gap-filling insulating layer GF1 in a process of polishing the insulating layer can be prevented or reduced.

[0044] Subsequently, the second opening OP2 may be formed by removing the hard mask pattern HM. Subsequently, the second gap-filling insulating layer GF2 may be formed in the second opening OP2, respectively. The second gap-filling insulating layer GF2 may include a void V therein, and the void V may have a shape extending along the edge of the first gap-filling insulating layer GF1. The second gap-filling insulating layer GF2 may include an oxide layer formed by a high-density plasma (HDP) method.

[0045] Reference Fig. 7A and Figure 7B , the first material layer 31 may be replaced with the third material layer 51. In an embodiment, after the first material layer 31 is removed, a conductive layer may be formed. Thus, a gate structure GST including the third material layer 51 and the second material layer 32 alternately stacked may be formed. During the replacement process, the first material layer 31 may remain in a partial region. In this case, a partial region of the gate structure GST may include the first material layer 31 and the second material layer 32 alternately stacked.

[0046] In addition, when the first material layers 31 each include a conductive material, a process of replacing the first material layers 31 with the third material layers 51 may be omitted. In this case, the first material layers 31 may be used as the third material layers 51, and the stack ST may be used as the gate structure GST.

[0047] Subsequently, a peripheral contact plug PCT may be formed. The peripheral contact plug PCT may be formed between the first line portion L1 and the second line portion L2. The peripheral contact plug PCT may extend into the gate structure GST through the bridge portion BP of the first gap-filling insulating layer GF1. The peripheral contact plug PCT may include a first peripheral contact plug PCT1 connected to a gate electrode of a transistor included in the peripheral circuit and a second peripheral contact plug PCT2 connected to a junction of the transistor. The peripheral contact plug PCT may be spaced apart from the gap V.

[0048] A first cell contact plug CCT1 extending through a first line portion L1 of the first gap-filling insulating layer GF1 and connected to the first recessed staircase structure may be formed. A second cell contact plug CCT2 extending through a second line portion L2 of the first gap-filling insulating layer GF1 and connected to the second recessed staircase structure may be formed. A third cell contact plug CCT3 extending through the third gap-filling insulating layers GF31 to GF3n and connected to the third recessed staircase structure may be formed. A fourth cell contact plug CCT4 extending through the fourth gap-filling insulating layers GF41 to GF4n and connected to the fourth recessed staircase structure may be formed. The first cell contact plug CCT1 and the third cell contact plug CCT3 may be electrically connected to the third material layer 51, respectively. The second cell contact plug CCT2 and the fourth cell contact plug CCT4 may be electrically connected to the third material layer 51, respectively.

[0049] According to the above-described manufacturing method, a first gap-filling insulating layer GF1 having a ladder shape may be formed. The first gap-filling insulating layer GF1 may be formed so that a bridge portion BP is located at a position where a peripheral contact plug PCT is to be formed, and the peripheral contact plug PCT may be formed to penetrate the bridge portion BP. Therefore, the peripheral contact plug PCT may be formed at a position spaced apart from the void V, and bridging between the peripheral contact plugs PCT due to the void V may be prevented or reduced.

[0050] FIG. 8A to FIG. 8C is a diagram for describing a method for manufacturing a semiconductor device according to an embodiment, and is a diagram along the Fig. 6A Hereinafter, contents repeated with those previously described may be omitted.

[0051] Reference Fig. 8A , the hard mask pattern HM may be located on the stack ST, and the hard mask pattern HM may include a first opening OP1 having a ladder shape in a plan view. In an embodiment, the hard mask pattern HM may be formed by forming a hard mask material and then etching the hard mask material. The hard mask pattern HM may be formed by etching the hard mask material to have an inclined sidewall. The inclined sidewall of the hard mask pattern HM may have an acute angle θ2 between the inclined sidewall of the hard mask pattern HM and the bottom surface. In an embodiment, the hard mask pattern HM may include an inclined sidewall having an angle θ2 of 70° to 90°.

[0052] The first gap-filling insulating layer GF1 may be located within the first opening OP1. In an embodiment, an insulating layer may be formed to fill the first recessed step structure and the second recessed step structure, and the first gap-filling insulating layer GF1 may be formed by polishing the insulating layer. The insulating layer may be deposited along the inclined sidewall of the hard mask pattern HM, and the first gap-filling insulating layer GF1 may include an inclined sidewall having an obtuse angle θ1 between the inclined sidewall and the bottom surface of the first gap-filling insulating layer GF1. In an embodiment, the first gap-filling insulating layer GF1 may include an inclined sidewall having an angle θ1 of 90° to 180°.

[0053] Reference Figure 8B , the second opening OP2 may be formed by removing the hard mask pattern HM. In an embodiment, the hard mask pattern HM may be selectively removed using a strip process. The second opening OP2 may expose the inclined sidewall of the first gap-filling insulating layer GF1 and may have a tapered cross-section in which the width of the lower portion is greater than the width of the upper portion.

[0054] Reference Figure 8C , a second gap-filling insulating layer GF2 may be formed in the second opening OP2. The inclined sidewall of the second gap-filling insulating layer GF2 may have an acute angle θ2 between the inclined sidewall and the bottom surface of the second gap-filling insulating layer GF2. In an embodiment, the second gap-filling insulating layer GF2 may be formed using a deposition process. An insulating material may be deposited along the contour of the inner surface of the second opening OP2, and a void V may be formed in the deposition process. The void V may be an empty space that is not filled with an insulating material. The void V may extend along the edge of the first gap-filling insulating layer GF1.

[0055] According to the above-described manufacturing method, the first gap-filling insulating layer GF1 and the second gap-filling insulating layer GF2 may have inclined sidewalls. Due to the inclined sidewalls of the first gap-filling insulating layer GF1, a void V may be formed in the second gap-filling insulating layer GF2. Since the void V is formed along the edge of the bridge portion BP, the peripheral contact plug PCT may be formed at a position spaced apart from the void V, and bridging between the peripheral contact plugs PCT may be prevented or reduced.

[0056] Although the embodiments of the technical concept according to the present disclosure are described above with reference to the accompanying drawings, this is only to illustrate the embodiments according to the concepts of the present disclosure, and the present disclosure is not limited to the above embodiments. Without departing from the scope of the present disclosure, technicians in the field to which the present disclosure belongs may make various types of substitutions, modifications, changes and combinations of the embodiments, and those skilled in the art should be aware that these substitutions, modifications, changes and combinations fall within the scope of the present disclosure.

[0057] CROSS-REFERENCE TO RELATED APPLICATIONS

[0058] This application claims priority to Korean Patent Application No. 10-2023-0163905, filed on November 23, 2023, which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: Peripheral circuits; A gate structure, the gate structure is arranged on the peripheral circuit, the gate structure includes stacked gate lines; a first recessed step structure, the first recessed step structure being disposed in the gate structure; a second recessed stepped structure, the second recessed stepped structure being disposed in the gate structure and adjacent to the first recessed stepped structure in a first direction; a first gap-filling insulating layer including a first line portion formed in the first recessed stepped structure, a second line portion formed in the second recessed stepped structure, and a bridge portion disposed between the first line portion and the second line portion to connect the first line portion and the second line portion to each other; as well as A peripheral contact plug extends into the gate structure through the bridge portion of the first gap-fill insulating layer and is connected to the peripheral circuit. 2 . The semiconductor device of claim 1 , further comprising a second gap-filling insulating layer formed on the gate structure and surrounded by the first line portion, the second line portion, and the bridge portion.

3. The semiconductor device according to claim 2, wherein: The second gap-filling insulating layer includes a void spaced apart from the peripheral contact plug.

4. The semiconductor device according to claim 3, wherein: The void extends along an edge of the first gap-filling insulating layer.

5. The semiconductor device according to claim 1, wherein The first gap-filling insulating layer has a ladder shape.

6. The semiconductor device according to claim 1, wherein The first line portion and the second line portion extend in a second direction crossing the first direction, and the bridge portion extends in the first direction.

7. The semiconductor device according to claim 1, wherein The first line portion and the second line portion have bottom surfaces in a step shape.

8. The semiconductor device according to claim 1, wherein The first line portion and the second line portion extend into the gate structure, and the bridge portion is located on the gate structure.

9. The semiconductor device according to claim 1, further comprising: a first channel structure extending through the gate structure; as well as A second channel structure extends through the gate structure.

10. The semiconductor device according to claim 9, wherein The first recessed stepped structure and the second recessed stepped structure are located between the first channel structure and the second channel structure.

11. The semiconductor device according to claim 9, further comprising: a third recessed step structure, the third recessed step structure being located between the first channel structure and the first recessed step structure; as well as A fourth recessed stepped structure is located between the second channel structure and the second recessed stepped structure.

12. The semiconductor device according to claim 11, further comprising: a third gap-filling insulating layer, the third gap-filling insulating layer being formed in the third recessed stepped structure; as well as A fourth gap-filling insulating layer is formed in the fourth recessed stepped structure.

13. The semiconductor device according to claim 1, further comprising: a first cell contact plug extending through the first line portion of the first gap-filling insulating layer and connected to the first recessed stepped structure; as well as A second cell contact plug extends through the second line portion of the first gap-filling insulating layer and is connected to the second recessed stepped structure.

14. The semiconductor device according to claim 1, wherein The peripheral contact plug comprises: a first peripheral contact plug connected to a gate electrode of a transistor included in the peripheral circuit; and A second peripheral contact plug is connected to the junction of the transistor.

15. The semiconductor device according to claim 1, wherein The peripheral contact plug is spaced apart from an edge of the bridge portion.

16. A semiconductor device, comprising: Peripheral circuits; a gate structure disposed on the peripheral circuit and comprising stacked gate lines; a first recessed step structure, the first recessed step structure being disposed in the gate structure; a second recessed step structure, the second recessed step structure being disposed in the gate structure; a first gap-filling insulating layer including a first line portion formed in the first recessed stepped structure, a second line portion formed in the second recessed stepped structure, and a bridge portion connecting the first line portion and the second line portion to each other; as well as A second gap-filling insulating layer is located between the bridge portions and between the first line portion and the second line portion, wherein the second gap-filling insulating layer includes a gap extending along an edge of the first gap-filling insulating layer. 17 . The semiconductor device according to claim 16 , further comprising a peripheral contact plug extending into the gate structure through the bridge portion and connected to the peripheral circuit.

18. The semiconductor device according to claim 17, wherein: The peripheral contact plug comprises: a first peripheral contact plug connected to a gate electrode of a transistor included in the peripheral circuit; and A second peripheral contact plug is connected to the junction of the transistor.

19. A method for manufacturing a semiconductor device, the method comprising the following steps: forming a laminate including alternately stacked first material layers and second material layers; forming a hard mask pattern on the stack, the hard mask pattern including a first opening having a ladder shape; forming a first recessed stepped structure by etching the stack exposed through the first opening; forming a second recessed stepped structure by etching the stack exposed through the first opening; forming a first gap-filling insulating layer including a first line portion formed in the first recessed stepped structure, a second line portion formed in the second recessed stepped structure, and a bridge portion connecting the first line portion and the second line portion to each other; forming a second opening by removing the hard mask pattern; as well as A second gap-filling insulating layer is formed in the second opening, the second gap-filling insulating layer including a void.

20. The manufacturing method according to claim 19, wherein: The hard mask pattern includes an inclined sidewall having an acute angle therebetween and a bottom surface of the hard mask pattern, and the first gap-filling insulating layer includes an inclined sidewall having an obtuse angle therebetween and a bottom surface of the first gap-filling insulating layer.

21. The manufacturing method according to claim 19, wherein: The first gap-filling insulating layer has an inclined sidewall with an obtuse angle between the inclined sidewall and a bottom surface thereof, and the second gap-filling insulating layer has an inclined sidewall with an acute angle between the inclined sidewall and a bottom surface thereof.

22. The manufacturing method according to claim 19, wherein: The first gap-filling insulating layer has a ladder shape in a plan view.

23. The manufacturing method according to claim 19, wherein: The void extends along an edge of the first gap-filling insulating layer.

24. The manufacturing method according to claim 19, further comprising the following steps: forming a gate structure by replacing the first material layer with a third material layer; as well as A peripheral contact plug is formed extending into the gate structure through the bridging portion of the first gap-fill insulating layer.

25. The manufacturing method according to claim 24, wherein: The void is spaced apart from the peripheral contact plug. 26 . The manufacturing method according to claim 19 , further comprising forming a first cell contact plug extending through the first line portion and connected to the first recessed step structure. 27 . The manufacturing method according to claim 19 , further comprising forming a second cell contact plug extending through the second line portion and connected to the second recessed step structure.

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