Semiconductor device and data storage system including same

Abstract

The invention provides a semiconductor device and a data storage system including the same. A semiconductor device includes: a first substrate structure including a substrate, first circuit devices on the substrate, second circuit devices extending into the substrate, a gate isolation layer penetrating the substrate and between the second circuit devices; and a second substrate structure electrically connected to the first substrate structure on the first substrate structure, and including a gate electrode electrically connected to the first circuit device and the second circuit device. Adjacent second circuit devices among the second circuit devices are symmetrically arranged relative to the gate isolation layer.

Description

Technical Field

[0001] Example embodiments of the present disclosure relate to a semiconductor device and a data storage system including the semiconductor device. Background Art

[0002] In a data storage system with data storage, there has been a need for a semiconductor device capable of storing a large amount of data. Therefore, methods for increasing the data storage capacity of a semiconductor device have been studied. For example, as a method for increasing the data storage capacity of a semiconductor device, a semiconductor device including a three-dimensionally arranged storage cell instead of a two-dimensionally arranged storage cell has been proposed. In order to increase the integration density of a semiconductor device, a method for reducing the area of ​​a circuit element driving a storage cell has been studied. Summary of the invention

[0003] Example embodiments of the present disclosure are to provide a semiconductor device having improved integration density.

[0004] Example embodiments of the present disclosure are to provide a data storage system including a semiconductor device having improved integration density.

[0005] According to an example embodiment of the present disclosure, a semiconductor device includes: a first substrate structure, the first substrate structure includes a substrate, a first circuit device located on the substrate, and a second circuit device extending into the substrate; and a second substrate structure, the second substrate structure is electrically connected to the first substrate structure on the first substrate structure and includes a plate layer, a gate electrode and a channel structure, the gate electrode is stacked below the plate layer along a first direction and spaced apart from each other, the first direction is perpendicular to the lower surface of the plate layer facing the first substrate structure, the channel structure extends into the gate electrode, extends along the first direction, and each includes a channel layer. Each of the second circuit devices includes a second gate dielectric layer, a second gate electrode layer, and a second source / drain region, the second gate dielectric layer extends into the substrate and extends along the first direction, the second gate electrode layer is located on the second gate dielectric layer, and the second source / drain region extends into the substrate from the opposite upper and lower surfaces of the substrate, respectively. The second substrate structure also includes a gate isolation layer, the gate isolation layer extends into the substrate between the second circuit devices adjacent to each other and contacts the second gate electrode layer.

[0006] According to an example embodiment of the present disclosure, a semiconductor device includes: a first substrate structure including a substrate, a first circuit device located on the substrate, a second circuit device extending into the substrate, and a gate isolation layer extending into the substrate and located between adjacent second circuit devices in the second circuit device; and a second substrate structure electrically connected to the first substrate structure on the first substrate structure and including a gate electrode electrically connected to the first circuit device and the second circuit device. Adjacent second circuit devices among the second circuit devices are symmetrically arranged with respect to the gate isolation layer.

[0007] According to an example embodiment of the present disclosure, a data storage system includes: a semiconductor memory device, the semiconductor memory device includes a first substrate structure, a second substrate structure and an input / output pad, the first substrate structure includes a substrate and a first circuit device and a second circuit device, the second substrate structure includes a gate electrode, the input / output pad is electrically connected to the first circuit device and the second circuit device; and a controller, the controller is electrically connected to the semiconductor memory device through the input / output pad and is configured to control the semiconductor memory device. The first circuit device is located on the substrate, and the second circuit device extends into the substrate. The first substrate structure also includes: a gate isolation layer, the gate isolation layer extends into the substrate and is located between adjacent second circuit devices in the second circuit device; a back insulating layer, the back insulating layer is located on the lower surface of the substrate; and a lower active contact plug, the lower active contact plug extends into the back insulating layer and is electrically connected to the second circuit device. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the present disclosure;

[0010] Figure 2 is a top view illustrating a semiconductor device according to an example embodiment of the present disclosure;

[0011] Figure 3A and Figure 3B is an enlarged view illustrating a portion of a semiconductor device according to an example embodiment of the present disclosure;

[0012] Figure 4 is an enlarged view illustrating a portion of a semiconductor device according to an example embodiment of the present disclosure;

[0013] Figure 5A and Figure 5B is an enlarged view illustrating a semiconductor device according to an example embodiment of the present disclosure;

[0014] Fig. 6A , Figure 6B and Figure 6C is an enlarged view illustrating a portion of a semiconductor device according to an example embodiment of the present disclosure;

[0015] Figure 7 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the present disclosure;

[0016] Figure 8 is a cross-sectional view illustrating a semiconductor device according to an example embodiment of the present disclosure;

[0017] Fig.9A , Fig. 9B , Fig. 9C , Fig.9D , Fig.9E , Fig.9F , Figure 9G , Figure 9H , Fig.9I , Figure 9J , Figure 9K , Figure 9L , Figure 9M , Figure 9N , Fig.9O and Figure 9P is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an example embodiment of the present disclosure;

[0018] Fig.10 is a diagram illustrating a data storage system including a semiconductor device according to an example embodiment of the present disclosure;

[0019] Fig.11 is a perspective view illustrating a data storage system including a semiconductor device according to an example embodiment of the present disclosure; and

[0020] Fig.12 is a cross-sectional view illustrating a semiconductor package according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings as follows.

[0022] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or cross-sections, these elements, components, regions, layers and / or cross-sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or cross-section from another element, component, region, layer or cross-section. Therefore, without departing from the scope of the present disclosure, the following first element, first component, first region, first layer or first cross-section may be referred to as a second element, second component, second region, second layer or second cross-section.

[0023] It should be understood that when an element such as a layer, film, region or substrate is referred to as "on another element", it can be directly on another element, or there may also be an intermediate element. In contrast, when an element is referred to as "directly on another element", there is no intermediate element. In addition, for ease of description, spatial relative terms such as "under ...", "under ...", "above ...", "on" and the like can be used herein to describe the relationship between an element or feature and another element or feature as illustrated in the various figures. It should be understood that in addition to the orientations depicted in the various figures, spatial relative terms are also intended to encompass different orientations of the device in use or operation. For example, if the device in each figure is turned over, the element described as "under other elements or features" or "under other elements or features" will be oriented "above other elements or features". Therefore, the term "under ..." can encompass two orientations above ..." and below ...". The device can be oriented in other ways (rotated 90 degrees or other orientations), and the spatial relative descriptors used herein can be interpreted accordingly. The term "and / or" includes any and all combinations of one or more related listed items.

[0024] Figure 1 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0025] Figure 2 is a top plan view illustrating a semiconductor device taken along line II′ according to example embodiments.

[0026] Figure 3A and Figure 3B is an enlarged view illustrating a portion of a semiconductor device according to example embodiments. Figure 3A yes Figure 1 is an enlarged view of area "A" in FIG. 1 , and Figure 3B yes Figure 1 Magnified view of area "B" in FIG.

[0027] Figure 4 is an enlarged view illustrating a portion of a semiconductor device according to an example embodiment, illustrating Figure 1 Area "C" in the.

[0028] refer to Figure 1 , Figure 2 , Figure 3A , Figure 3B and Figure 4 , the semiconductor device 100 may include a first substrate structure S1 and a second substrate structure S2 vertically bonded to each other. The first substrate structure S1 may include a peripheral circuit region, and the second substrate structure S2 may include a memory cell region.

[0029] The first substrate structure S1 may have a first device region LR and a second device region HR. The first substrate structure S1 may include: a substrate 201; a device isolation layer 210, which is located in the substrate 201; a first circuit device TR1, which is arranged on the substrate 201 in the first device region LR; a second circuit device TR2, which is arranged to penetrate the substrate 201 or extend into the substrate 201 in the second device region HR; a peripheral region insulating layer 290, which is located on the upper surface of the substrate 201; a back insulating layer 206, which is located on the lower surface of the substrate 201; a first circuit contact plug 272 and a second circuit contact plug 274, which are located on the substrate 201; a first circuit interconnection line 282, a second circuit interconnection line 284 and a third circuit interconnection line 286; a first bonding path 295; a first bonding pad 298; and a first bonding insulating layer 299.

[0030] The first substrate structure S1 may further include a first source / drain region 205A, a first upper active contact plug 250A, and a first gate contact plug 260A disposed in the first device region LR. The first substrate structure S1 may further include a substrate insulating layer 215, a gate isolation layer 240, second source / drain regions 205B and 205C, a second upper active contact plug 250B, a second gate contact plug 260B, a lower active contact plug 250C, a body contact plug 270, and a backside interconnection line 288 disposed in the second device region HR.

[0031] The substrate 201 may have an upper surface extending in the X direction and the Y direction. The device isolation layer 210 may be formed on the substrate 201 so that the active region may be defined. The first source / drain region 205A including impurities and the second source / drain regions 205B and 205C may be disposed in a portion of the active region. The substrate 201 may include a semiconductor material such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the substrate 201 may be provided as a single crystal bulk wafer.

[0032] The device isolation layer 210 may define an active region in the substrate 201. The device isolation layer 210 may be disposed in the first device region LR, and may be disposed in a region including at least an edge in the second device region HR. The device isolation layer 210 may be formed, for example, by a shallow trench isolation (STI) process. In example embodiments, the arrangement form and depth of the device isolation layer 210 may vary. The device isolation layer 210 may be formed of an insulating material. The device isolation layer 210 may include, for example, an oxide, a nitride, or a combination thereof.

[0033] The first circuit device TR1 may be disposed on the upper surface of the substrate 201 and may include a planar transistor. Each first circuit device TR1 may include a first gate structure 220 and a first source / drain region 205A. The first gate structure 220 may include a first gate dielectric layer 222, a first gate electrode layer 225, and a first gate spacer 224.

[0034] The first gate dielectric layer 222 may be disposed on the upper surface of the substrate 201 and may include oxide, nitride, or a high-κ material. The high-κ material may refer to a material having a dielectric constant higher than that of silicon oxide (SiO 2 ) dielectric material with a dielectric constant of .

[0035] The first gate electrode layer 225 may be disposed on the first gate dielectric layer 222 and may include a conductive material. The first gate electrode layer 225 may include, for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN); and / or a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo); or a semiconductor material such as doped polysilicon. In example embodiments, the first gate electrode layer 225 may include two or more conductive layers.

[0036] The first gate spacer 224 may be disposed on both side surfaces of the first gate electrode layer 225. The first gate spacer 224 may insulate the first source / drain region 205A and the first gate electrode layer 225. For example, the first gate spacer 224 may be formed of at least one of oxide, nitride, and / or oxynitride, and may be formed of a low dielectric constant film.

[0037] The first source / drain region 205A may be disposed in the substrate 201 at both sides of the first gate structure 220. The first source / drain region 205A may include a first impurity region 205_1 and a second impurity region 205_2 having different doping concentrations. However, in example embodiments, the shapes of the impurity regions forming the first source / drain region 205A and the number of these impurity regions may vary.

[0038] The second circuit device TR2 may penetrate the substrate 201 or extend into the substrate 201 and may be disposed in the substrate 201, and may include a vertical transistor. Each second circuit device TR2 may include a second gate structure 230 and second source / drain regions 205B and 205C. The second gate structure 230 may include a second gate dielectric layer 232 and a second gate electrode layer 235.

[0039] The second gate dielectric layer 232 may be disposed to penetrate the substrate 201 or extend into the substrate 201 and extend in the Z direction. Figure 1 As shown, the second gate dielectric layer 232 may extend only in the Z direction in the cross-sectional view without having a region extending in a direction parallel to the upper surface of the substrate 201 (such as the X direction). Figure 1 , the second gate dielectric layer 232 may be in the shape of a letter "I" or a number "1". The upper surface of the second gate dielectric layer 232 may be coplanar with the upper surface of the substrate 201, and the lower surface may be coplanar with the lower surface of the substrate 201. The thickness of the second gate dielectric layer 232 may be greater than the thickness of the first gate dielectric layer 222, but example embodiments thereof are not limited thereto. The second gate dielectric layer 232 may include a material that is the same as or different from that of the first gate dielectric layer 222, and may include an oxide, a nitride, or a high-κ material.

[0040] The second gate electrode layer 235 may be disposed on the second gate dielectric layer 232 and may extend through the substrate 201 in the Z direction. The second gate electrode layer 235 may not extend in a direction parallel to the upper surface of the substrate 201 (such as in the X direction) and may be disposed in the Z direction. Figure 1 In the cross-sectional view, it extends along the Z direction. Figure 1 In the cross-sectional view in FIG. 1 , the second gate electrode layer 235 may be in the shape of a letter “I” or a number “1”. Figure 2 In the top view of the substrate 201, the second gate electrode layer 235 may be in a quadrilateral shape. The upper surface of the second gate electrode layer 235 may be coplanar with the upper surface of the substrate 201, and the lower surface may be coplanar with the lower surface of the substrate 201. The thickness of the second gate electrode layer 235 may be greater than the thickness of the first gate electrode layer 225, but the example embodiment thereof is not limited thereto. The second gate electrode layer 235 may include a first conductive layer 235_1 and a second conductive layer 235_2 stacked in sequence from the second gate dielectric layer 232. The first conductive layer 235_1 and the second conductive layer 235_2 may include different materials. For example, the first conductive layer 235_1 may include a semiconductor material such as doped polysilicon, and the second conductive layer 235_2 may include a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo). However, in example embodiments, the number of conductive layers forming the second gate electrode layer 235 may vary.

[0041] The second source / drain regions 205B and 205C may include a second upper source / drain region 205B disposed at a predetermined depth from an upper surface of the substrate 201 and a second lower source / drain region 205C disposed at a predetermined depth from a lower surface of the substrate 201. An upper surface of the second upper source / drain region 205B may be coplanar with an upper surface of the substrate 201, and a lower surface of the second lower source / drain region 205C may be coplanar with a lower surface of the substrate 201. The second source / drain regions 205B and 205C may each include a first impurity region 205_1 and a second impurity region 205_2 having different doping concentrations. In example embodiments, the second source / drain regions 205B and 205C may have the same or different structure as the first source / drain region 205A, and the number of impurity regions included in the second source / drain regions 205B and 205C and their shapes may vary.

[0042] The channel direction of the first circuit device TR1 may be perpendicular to the channel direction of the second circuit device TR2. The channel direction of the first circuit device TR1 may be a direction parallel to the upper surface of the substrate 201, such as the X direction, and the channel direction of the second circuit device TR2 may be a direction perpendicular to the upper surface of the substrate 201, such as the Z direction.

[0043] In the second circuit device TR2, the channel length may correspond to a first length L1, which is a length of the second gate electrode layer 235 between the second source / drain regions 205B and 205C disposed side by side in the vertical direction. The first length L1 may be in a range of about 10 μm to about 50 μm, for example, from about 10 μm to about 20 μm. When manufacturing the semiconductor device 100, the thickness of the substrate 201 may be determined by considering the first length L1.

[0044] In the first circuit device TR1, the channel length may correspond to a second length L2, which is a length of the first gate electrode layer 225 between the first source / drain regions 205A disposed side by side in the horizontal direction. The second length L2 may be smaller than the first length L1. For example, the second circuit device TR2 may be a high voltage transistor to which a relatively high voltage is applied, compared to the first circuit device TR1.

[0045] In the semiconductor device 100, the second circuit device TR2 having a relatively long channel length may be provided in the form of a back contact vertical transistor (BCVT) penetrating the substrate 201, so that the integration density may be improved, unlike when the second circuit device TR2 is provided as a planar transistor. For example, the second circuit device TR2 may be selected as a device having the longest channel length among the transistors provided on the first substrate structure S1, or may be selected as a device having a relatively long channel length, which may be provided in plurality, or which may occupy a relatively large area.

[0046] The gate isolation layer 240 may be disposed between the second circuit devices TR2 adjacent to each other. The gate isolation layer 240 may be disposed to completely penetrate the substrate 201 or extend into the substrate 201. Figure 2 As shown, in a top view, the gate isolation layer 240 may include a quadrilateral-shaped region between at least the second circuit devices TR2. The gate isolation layer 240 may be disposed between the second gate electrode layers 235 of the second circuit devices TR2 adjacent to each other, and may contact the second gate electrode layer 235 through two side surfaces. The second circuit devices TR2 adjacent to each other may be symmetrically disposed with respect to the gate isolation layer 240. The gate isolation layer 240 may include an insulating material, such as at least one of an oxide, a nitride, and / or a nitride oxide.

[0047] The peripheral region insulating layer 290 may be disposed on the first circuit device TR1 and the second circuit device TR2 on the upper surface of the substrate 201. The back insulating layer 206 may be disposed on the lower surface of the substrate 201. The peripheral region insulating layer 290 and the back insulating layer 206 may each include a plurality of insulating layers formed in different processes. The peripheral region insulating layer 290 and the back insulating layer 206 may each be formed of an insulating material and may include, for example, at least one of an oxide, a nitride, and / or an oxynitride.

[0048] The first upper active contact plug 250A may be connected to the first source / drain region 205A through the peripheral region insulating layer 290. The second upper active contact plug 250B may be connected to the second upper source / drain region 205B through the peripheral region insulating layer 290. The first upper active contact plug 250A and the second upper active contact plug 250B may be connected to the first impurity region 205_1 including impurities with a relatively high concentration, but example embodiments thereof are not limited thereto.

[0049] The first gate contact plug 260A may penetrate the peripheral region insulating layer 290 or extend into the peripheral region insulating layer 290 and may be connected to the first gate electrode layer 225. The second gate contact plug 260B may penetrate the peripheral region insulating layer 290 or extend into the peripheral region insulating layer 290 and may be connected to the second gate electrode layer 235. The second gate contact plug 260B may be connected to the second conductive layer 235_2, but example embodiments thereof are not limited thereto.

[0050] Some of the first and second active contact plugs 250A and 250B and / or the first and second gate contact plugs 260A and 260B may have side surfaces inclined such that the width of the upper surface thereof may be greater than the width of the lower surface. The upper ends of the first and second active contact plugs 250A and 250B and the upper ends of the first and second gate contact plugs 260A and 260B may be disposed at substantially the same height, but example embodiments thereof are not limited thereto.

[0051] The lower active contact plug 250C may be connected to the second lower source / drain region 205C through the back insulating layer 206. Each lower active contact plug 250C may have a side surface inclined so that the width of its upper surface may be smaller than the width of the lower surface. The slope of the side surface of the lower active contact plug 250C relative to the substrate 201 may be opposite to the slope of the side surface of the first upper active contact plug 250A and the second upper active contact plug 250B relative to the substrate 201.

[0052] The body contact plug 270 may be connected to the substrate 201 through the back insulating layer 206 and the substrate insulating layer 215. The body contact plug 270 may be disposed between and / or around the second circuit device TR2. The body contact plug 270 may be configured to apply a body voltage to the substrate 201. The upper end of the body contact plug 270 may be disposed at a height higher than the height of the upper end of the lower active contact plug 250C, and may be disposed at a height lower than the lower ends of the first and second upper active contact plugs 250A and 250B and the lower ends of the first and second gate contact plugs 260A and 260B.

[0053] Each of the first upper active contact plug 250A and the second upper active contact plug 250B, the first gate contact plug 260A and the second gate contact plug 260B, the lower active contact plug 250C, and the body contact plug 270 forming a part of the first interconnection structure in the first substrate structure S1 may be in a cylindrical shape. The first upper active contact plug 250A and the second upper active contact plug 250B, the first gate contact plug 260A and the second gate contact plug 260B, the lower active contact plug 250C, and the body contact plug 270 may include a conductive material, for example, at least one of a semiconductor material, a metal semiconductor compound, or a metal material such as tungsten (W), cobalt (Co), molybdenum (Mo), copper (Cu), ruthenium (Ru), and / or aluminum (Al), and each may further include a diffusion barrier layer.

[0054] The substrate insulating layer 215 may extend from the lower surface of the substrate 201 into the substrate 201 to a predetermined depth, and may surround a portion of a side surface of the body contact plug 270. The substrate insulating layer 215 may be disposed on an upper portion of the body contact plug 270 to expose the side surface and an upper end of the body contact plug 270. The substrate insulating layer 215 may be formed of an insulating material, and may include, for example, at least one of oxide, nitride, and / or oxynitride.

[0055] The first and second circuit contact plugs 272 and 274 and the first, second and third circuit interconnects 282, 284, and 286 may form part of a first interconnect structure and may be disposed on the upper surface of the substrate 201 and may be connected to the first and second active contact plugs 250A and 250B and the first and second gate contact plugs 260A and 260B.

[0056] A backside interconnection line 288 forming a portion of the first interconnection structure may be disposed on the lower surface of the substrate 201 and may be connected to the lower active contact plug 250C and the body contact plug 270. At least a portion of the backside interconnection line 288 may form a backside power delivery network (BSPDN) and in this case may transmit power to the second circuit device TR2.

[0057] Each of the first circuit contact plug 272 and the second circuit contact plug 274 may be in a cylindrical shape. Each of the first circuit interconnection line 282, the second circuit interconnection line 284, the third circuit interconnection line 286, and the backside interconnection line 288 may have a line form. The first circuit contact plug 272 and the second circuit contact plug 274, the first circuit interconnection line 282, the second circuit interconnection line 284, the third circuit interconnection line 286, and the backside interconnection line 288 may include a conductive material such as tungsten (W), copper (Cu), aluminum (Al), and each may further include a diffusion barrier layer. However, in example embodiments, the number of layers of the first circuit contact plug 272 and the second circuit contact plug 274, the first circuit interconnection line 282, the second circuit interconnection line 284, the third circuit interconnection line 286, and the backside interconnection line 288 and their arrangement forms may vary.

[0058] The first joining path 295, the first joining pad 298 and the first joining insulating layer 299 may be included in the first joining structure and may be arranged on the top third circuit interconnection line 286. The first joining path 295 may be cylindrical in shape, and the first joining pad 298 may be linear in shape. The upper surface of the first joining pad 298 and the upper surface of the first joining insulating layer 299 may be exposed to the upper surface of the first substrate structure S1. The first joining path 295 and the first joining pad 298 may provide an electrical connection path between the first substrate structure S1 and the second substrate structure S2. Part of the first joining pad 298 may not be connected to the lower third circuit interconnection line 286 and may be arranged for joining. The first joining path 295 and the first joining pad 298 may include a conductive material, such as copper (Cu). The first joining insulating layer 299 may be arranged around the first joining pad 298. The first bonding insulation layer 299 may also serve as a diffusion barrier layer of the first bonding pad 298 , and may include, for example, at least one of SiN, SiON, SiCN, SiOC, SiOCN, and / or SiO.

[0059] The second substrate structure S2 may include a plate layer 101, a gate electrode 130 stacked on a lower surface of the plate layer 101, an interlayer insulating layer 120 alternately stacked with the gate electrode 130, a channel structure CH penetrating the gate electrode 130, an isolation region MS penetrating the gate electrode 130 and extending in one direction, a first cell contact plug 152 connected to the gate electrode 130, and a second cell contact plug 154 electrically connected to the plate layer 101. The second substrate structure S2 may also include a capping insulating layer 105, a passivation layer 106, a contact insulating layer 125, a cell upper contact 170, a cell interconnection line 180, and a cell region insulating layer 190. The second substrate structure S2 may also include a second bonding via 195, a second bonding pad 198, and a second bonding insulating layer 199 as a second bonding structure.

[0060] The plate layer 101 may have an upper surface extending in the X direction and the Y direction. The plate layer 101 may be used as a common source line of the semiconductor device 100. The plate layer 101 may include a conductive material. For example, the plate layer 101 may include a semiconductor material such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the Group IV semiconductor may include silicon, germanium, or silicon germanium. The plate layer 101 may also include impurities. The plate layer 101 may be provided as a polycrystalline semiconductor layer such as a polysilicon layer or an epitaxial layer. In some example embodiments, the plate layer 101 may include a plurality of conductive layers stacked vertically.

[0061] The gate electrodes 130 may be vertically stacked and spaced apart from each other on the lower surface of the plate layer 101, and may form a stack structure with the interlayer insulating layer 120. The stack structure may be vertically stacked and may include a lower stack structure and an upper stack structure surrounding the first channel structure CH1 and the second channel structure CH2, respectively. However, in example embodiments, the stack structure may include a single stack structure.

[0062] The gate electrode 130 may include at least one lower gate electrode 130L forming a gate of a ground selection transistor, a storage gate electrode 130M forming a plurality of memory cells, and an upper gate electrode 130U forming a gate of a string selection transistor. Here, the terms "lower" and "upper" of the lower stack structure and the upper stack structure, the lower gate electrode 130L, and the upper gate electrode 130U may be expressed relative to the direction during the manufacturing process. The number of storage gate electrodes 130M forming a memory cell may be determined according to the capacity of the semiconductor device 100. In example embodiments, the number of each of the upper gate electrode 130U and the lower gate electrode 130L may be 1 to 4 or more, and may have a structure that is the same as or different from that of the storage gate electrode 130M. In example embodiments, the gate electrode 130 may also include a gate electrode 130 disposed below the upper gate electrode 130U and / or disposed on the lower gate electrode 130L and forming an erase transistor used in an erase operation using a gate induced drain leakage (GIDL) phenomenon. A portion of the gate electrode 130 (eg, the memory gate electrode 130M adjacent to the upper gate electrode 130U or the lower gate electrode 130L) may be a dummy gate electrode.

[0063] The gate electrodes 130 may be stacked vertically and spaced apart from each other, may extend to different lengths in at least one direction (e.g., the Y direction), and may form a step structure having a staircase shape. The gate electrodes 130 may be arranged to have a step structure with each other in the X direction. Due to the step structure, the gate electrode 130 of the upper portion may extend longer than the gate electrode 130 of the lower portion, so that the gate electrode may have an area in which the lower surface may be exposed from below the interlayer insulating layer 120 and other gate electrodes 130, and these areas may be referred to as pad areas 130P. The gate electrode 130 may be connected to the first cell contact plug 152 in the pad area 130P. The gate electrode 130 may have an increased thickness in the pad area 130P.

[0064] The gate electrode 130 may include a metal material such as tungsten (W). In example embodiments, the gate electrode 130 may include polysilicon or a metal silicide material. In example embodiments, the gate electrode 130 may further include a diffusion barrier layer. For example, the diffusion barrier layer may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0065] Interlayer insulating layers 120 may be disposed between gate electrodes 130. Similar to gate electrodes 130, interlayer insulating layers 120 may be disposed to be spaced apart from each other in a direction perpendicular to the lower surface of plate layer 101 and extend in the Y direction. Interlayer insulating layers 120 may include an insulating material such as silicon oxide or silicon nitride.

[0066] Each channel structure CH may form a memory cell string and may be spaced apart from each other in rows and columns on the lower surface of the board layer 101. The channel structure CH may be arranged to form a grid pattern in a top view, or may be arranged in a zigzag pattern in one direction. The channel structure CH may be in a columnar shape and may have an inclined side surface so that its width may decrease toward the board layer 101 according to an aspect ratio.

[0067] Each channel structure CH may have a form in which a first channel structure CH1 and a second channel structure CH2 respectively penetrating a lower stack structure and an upper stack structure of the gate electrode 130 may be connected to each other, and may have a bent portion due to a width difference or width variation in a connection region. However, in example embodiments, the number of channel structures stacked in the Z direction may vary.

[0068] Each channel structure CH may include a channel layer 140 disposed in a channel hole, a gate dielectric layer 145, a channel filling insulating layer 147, and a channel pad 149. The channel layer 140 may be formed in a ring shape surrounding the channel filling insulating layer 147, but in example embodiments, the channel layer 140 may be in a column shape such as a cylindrical shape or a prism shape without the channel filling insulating layer 147. The channel layer 140 may include a semiconductor material such as polysilicon or single crystal silicon. The channel layer 140 may be exposed through an upper end and may be connected to the board layer 101.

[0069] like Figure 4 As shown, at the upper end of the channel structure CH, the upper end of the channel layer 140 may be exposed from the channel dielectric layer or the gate dielectric layer 145. The upper end of the channel layer 140 may include an upper surface and an upper region of a side surface connected to the upper surface. The upper end of the channel layer 140 may be in direct contact with the plate layer 101 and may be surrounded by the plate layer 101 in a top view. With this arrangement, the channel layer 140 may be physically and electrically connected to the plate layer 101.

[0070] The gate dielectric layer 145 may be disposed between the gate electrode 130 and the channel layer 140. Although not specifically illustrated, the gate dielectric layer 145 may include a tunneling layer, a charge storage layer, and a blocking layer stacked in sequence from the channel layer 140. The tunneling layer may tunnel charges into the charge storage layer, and may include, for example, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), or a combination thereof. The charge storage layer may be a charge trapping layer or a floating gate conductive layer. The blocking layer may include silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), a high-κ dielectric material, or a combination thereof. In example embodiments, at least a portion of the gate dielectric layer 145 may extend in a horizontal direction along the gate electrode 130 .

[0071] A channel pad 149 may be disposed on a lower end of the lower second channel structure CH2. The channel pad 149 may include, for example, doped polysilicon.

[0072] The channel layer 140, the gate dielectric layer 145, and the channel filling insulating layer 147 may be connected to each other between the first channel structure CH1 and the second channel structure CH2. An interlayer insulating layer 120 having a relatively large thickness may be further disposed between the first channel structure CH1 and the second channel structure CH2. However, the form of the interlayer insulating layer 120 may vary in example embodiments.

[0073] The isolation region MS may be disposed to extend through the gate electrode 130 in one direction (eg, the Y direction). Figure 1 Only one isolation region MS is illustrated in FIG. 1 , but a plurality of isolation regions MS may extend parallel to each other in the Y direction and may be spaced apart from each other in the X direction. The isolation region MS may penetrate or extend into all gate electrodes 130 stacked on the plate layer 101 and may be connected to the plate layer 101 .

[0074] The isolation region MS may have a shape in which a width decreases toward the board layer 101 due to a high aspect ratio, but example embodiments thereof are not limited thereto. The isolation region MS may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0075] The first cell contact plug 152 and the second cell contact plug 154 may extend in the Z direction and may have an inclined side surface such that the width may decrease toward the board layer 101. The upper end of the first cell contact plug 152 and the upper end of the second cell contact plug 154 may be disposed on the lower surface of the board layer 101, for example, at the lower surface of the board layer 101 or in the board layer 101. The first cell contact plug 152 and the second cell contact plug 154 may form a part of the second interconnect structure in the second substrate structure S2.

[0076] The first cell contact plug 152 may electrically connect the gate electrode 130 to the first interconnect structure in the first substrate structure S1. The first cell contact plug 152 may be physically and electrically connected to the gate electrode 130 in each pad region 130P, and an electrical signal may be applied to the gate electrode 130. The first cell contact plug 152 may penetrate the pad region 130P of the gate electrode 130 or extend therein. The first cell contact plug 152 may be disposed so that the gate electrode 130 may penetrate or extend thereinto the region where the step structure is formed, and may extend into the board layer 101. The first cell contact plug 152 may be electrically isolated from the board layer 101 by the capping insulating layer 105. However, in some example embodiments, the first cell contact plug 152 may have a shape that does not penetrate the gate electrode 130. In this case, the first cell contact plug 152 may extend to be connected to the lower surface or lower portion of each gate electrode 130.

[0077] The first cell contact plug 152 may be configured to extend horizontally in the pad region 130P. The first cell contact plug 152 may be spaced apart from the gate electrode 130 on the pad region 130P by the contact insulating layer 125. The contact insulating layer 125 may surround the side surface of the first cell contact plug 152 and may be spaced apart from each other in the Z direction. The contact insulating layers 125 may be respectively disposed at substantially the same height as that of the gate electrode 130. The contact insulating layer 125 may include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0078] The second cell contact plug 154 may be disposed in a region where the gate electrode 130 is not disposed, for example, outside the gate electrode 130. The second cell contact plug 154 may electrically connect the first circuit device TR1 and the second circuit device TR2 of the first substrate structure S1 to the board layer 101. The second cell contact plug 154 may penetrate a portion of the cell region insulating layer 190 or extend therein, and may extend into the board layer 101.

[0079] The first and second cell contact plugs 152 and 154 may include a metal material such as tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0080] The covering insulating layer 105 may be disposed between the first cell contact plug 152 and the plate layer 101. The covering insulating layer 105 may cover or overlap the upper end of the first cell contact plug 152. The covering insulating layer 105 may not extend to the channel structure CH and the second cell contact plug 154. The upper surface of the covering insulating layer 105 may have a curve along the upper end of the first cell contact plug 152, but the shape of the upper surface of the covering insulating layer 105 is not limited thereto. The covering insulating layer 105 may include an insulating material, for example, at least one of silicon oxide, silicon nitride and / or silicon carbide. In some example embodiments, the covering insulating layer 105 may be spaced apart from each other in a plurality of layers between the first cell contact plugs 152. In some example embodiments, the covering insulating layer 105 may be disposed to penetrate the plate layer 101 or extend into the plate layer 101.

[0081] The on-cell contacts 170 and the cell interconnection lines 180 may form a portion of the second interconnection structure, and may enable the second substrate structure S2 to be electrically connected to the first substrate structure S1 .

[0082] The cell upper contact 170 may include a first cell upper contact 172, a second cell upper contact 174, and a third cell upper contact 176, and the cell interconnection line 180 may include a first cell interconnection line 182 and a second cell interconnection line 184. The channel pad 149 and the lower ends of the first cell contact plug 152 and the second cell contact plug 154 may be connected to the first cell upper contact 172. The lower end of the first cell upper contact 172 may be connected to the second cell upper contact 174, and the lower end of the second cell upper contact 174 may be connected to the first cell interconnection line 182. The third cell upper contact 176 may connect the first cell interconnection line 182 and the second cell interconnection line 184 to each other upward and downward. The cell upper contact 170 may be in a cylindrical shape. In example embodiments, the cell upper contact 170 may have an inclined side surface whose width decreases toward the board layer 101 according to the aspect ratio and increases toward the first substrate structure S1.

[0083] The first cell interconnection line 182 may include a bit line connected to the channel structure CH and an interconnection line disposed at the same height as the bit line. The second cell interconnection line 184 may be an interconnection line disposed below the first cell interconnection line 182. The cell interconnection line 180 may be in the shape of a line extending in at least one direction. In example embodiments, the thickness of the second cell interconnection line 184 may be greater than the thickness of the first cell interconnection line 182. The cell interconnection line 180 may have a side surface inclined so that the width of the cell interconnection line 180 may decrease toward the board layer 101.

[0084] The cell upper contact 170 and the cell interconnection line 180 may include, for example, tungsten (W), aluminum (Al), copper (Cu), tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0085] The second bonding path 195 of the second bonding structure may be disposed below the second unit interconnect line 184 and may be connected to the second unit interconnect line 184, and the second bonding pad 198 of the second bonding structure may be connected to the second bonding path 195. The lower surface of the second bonding pad 198 may be exposed to the lower surface of the second substrate structure S2. The second bonding pad 198 may be connected to the first bonding pad 298 of the first substrate structure S1 by bonding, and the second bonding insulation layer 199 may be connected to the first bonding insulation layer 299 of the first substrate structure S1 by bonding. The second bonding path 195 and the second bonding pad 198 may include a conductive material, such as copper (Cu). The second bonding insulation layer 199 may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON and / or SiOCN.

[0086] The first substrate structure S1 and the second substrate structure S2 may be bonded to each other through bonding between the first bonding pad 298 and the second bonding pad 198 and bonding between the first bonding insulating layer 299 and the second bonding insulating layer 199. The bonding between the first bonding pad 298 and the second bonding pad 198 may be, for example, copper (Cu) to copper (Cu) bonding, and the bonding between the first bonding insulating layer 299 and the second bonding insulating layer 199 may be, for example, dielectric to dielectric bonding, such as SiCN to SiCN bonding. The first substrate structure S1 and the second substrate structure S2 may be bonded to each other through a hybrid bonding including copper (Cu) to copper (Cu) bonding and dielectric to dielectric bonding.

[0087] The cell region insulating layer 190 may be provided to cover or overlap the lower surface of the board layer 101 and the gate electrode 130 located on the lower surface of the board layer 101. The passivation layer 106 may be provided on the upper surface of the board layer 101 and may have an opening exposing the input / output pad region. The passivation layer 106 may serve as a layer for protecting the semiconductor device 100.

[0088] The cell region insulating layer 190 and the passivation layer 106 may include at least one insulating material, for example, silicon oxide, silicon nitride, and / or silicon carbide, and may include a plurality of insulating layers in example embodiments.

[0089] Figure 5A and Figure 5B is an enlarged view illustrating a semiconductor device according to an example embodiment, thereby illustrating Figure 3B The corresponding area.

[0090] refer to Figure 5A In the semiconductor device 100a, the structure of the second gate electrode layer 235 may be different from Figure 1 and Figure 3A In an example embodiment of the present invention, the second gate electrode layer 235 may include a single conductive layer. The second gate electrode layer 235 may include, for example, a metal material, but example embodiments thereof are not limited thereto. Similarly, in example embodiments, the number of conductive layers forming the second gate electrode layer 235 may vary.

[0091] refer to Figure 5B In the semiconductor device 100b, the height of the upper end of the body contact plug 270 may be different from Figure 1 and Figure 3AIn the example embodiment of FIG. 2 , the body contact plug 270 may be provided by being recessed into the substrate 201 to a depth that is the same as or similar to the depth of the lower active contact plug 250C. Therefore, the substrate insulating layer 215 (see FIG. 215 ) surrounding the body contact plug 270 may not be provided. Figure 3A ). Therefore, in example embodiments, the depth of the body contact plug 270 and the form of the substrate insulating layer 215 formed thereby may vary.

[0092] Fig. 6A , Figure 6B and Figure 6C is an enlarged view illustrating a portion of a semiconductor device according to an example embodiment, illustrating Figure 3B The corresponding area.

[0093] refer to Fig. 6A In the semiconductor device 100c, the body contact plug 270 may be disposed to extend from the upper surface of the substrate 201 into the substrate 201. Therefore, the substrate insulating layer 215 may also extend from the upper surface of the substrate 201 into the substrate 201. In example embodiments, the lower end of the body contact plug 270 may be disposed at a height lower than the height of the lower end of the second upper active contact plug 250B and the lower end of the second gate contact plug 260B. The lower end of the body contact plug 270 may be disposed at a height higher than the height of the upper end of the lower active contact plug 250C.

[0094] refer to Figure 6B In the semiconductor device 100d, part of the second gate contact plug 260B may be disposed on the lower surface of the substrate 201. For example, in two second circuit devices TR2 facing each other with the gate isolation layer 240 therebetween, the second gate contact plug 260B connected to the second gate electrode layer 235 of one of the two second circuit devices TR2 may be disposed on the upper surface of the substrate 201, while the second gate contact plug 260B connected to the second gate electrode layer 235 of the other second circuit device TR2 may be disposed on the lower surface of the substrate 201.

[0095] refer to Figure 6C In the semiconductor device 100e, all the second gate contact plugs 260B may be disposed on the lower surface of the substrate 201. Therefore, the second upper active contact plug 250B may be disposed on the upper surface of the substrate 201, and the second gate contact plug 260B, the lower active contact plug 250C, and the body contact plug 270 may be disposed on the lower surface of the substrate 201.

[0096] As in Fig. 6A , Figure 6B and Figure 6CAs in the example embodiments, the disposition positions of the second gate contact plug 260B and the body contact plug 270 may vary. Figure 5A , Figure 5B , Fig. 6A , Figure 6B and Figure 6C The exemplary embodiments of the present invention may be combined with each other in various ways.

[0097] Figure 7 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0098] refer to Figure 7 , the semiconductor device 100f may include a peripheral circuit region PERI and a memory cell region CELL, the peripheral circuit region PERI includes a substrate 201, and the memory cell region CELL includes a board layer 101. The memory cell region CELL may be disposed on the peripheral circuit region PERI. In an example embodiment, unlike the above example, the memory cell region CELL may be disposed below the peripheral circuit region PERI.

[0099] As for the peripheral circuit area PERI, refer to Figures 1 to 4 The description of the first semiconductor structure S1 described above may be applicable. However, unlike the first semiconductor structure S1, the peripheral circuit region PERI may not include the first bonding via 295, the first bonding pad 298, and the first bonding insulating layer 299 which may be bonding structures.

[0100] As for the memory cell region CELL, unless otherwise indicated, refer to Figures 1 to 4 The description of the second semiconductor structure S2 described above may be applicable. However, unlike the second semiconductor structure S2, the memory cell region CELL may not include the second bonding via 195, the second bonding pad 198, and the second bonding insulating layer 199, which may serve as a bonding structure, and may not include the passivation layer 106. The memory cell region CELL may also include a first horizontal conductive layer 102 and a second horizontal conductive layer 104, a horizontal insulating structure 110, and a substrate penetration insulating layer 121 located on the plate layer 101.

[0101] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may be sequentially stacked and disposed on the upper surface of the plate layer 101. For example, the first horizontal conductive layer 102 may be used as a portion of a common source line of the semiconductor device 100f and may be used as a common source line together with the plate layer 101. The first horizontal conductive layer 102 may be directly connected to the channel layer 140 around the channel layer 140 of each channel structure CH (see Figure 4 ). The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may include a semiconductor material, such as polysilicon.

[0102] The horizontal insulating structure 110 may be disposed on the plate layer 101 in parallel with the first horizontal conductive layer 102. The horizontal insulating structure 110 may include three horizontal insulating layers sequentially stacked on the plate layer 101. The horizontal insulating structure 110 may be a layer remaining after a portion is replaced with the first horizontal conductive layer 102 in a process of manufacturing the semiconductor device 100f. The horizontal insulating structure 110 may include silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

[0103] The through-substrate insulating layer 121 may be disposed to penetrate the board layer 101, the horizontal insulating structure 110, and the second horizontal conductive layer 104 or extend therein. An upper surface of the through-substrate insulating layer 121 may be coplanar with an upper surface of the second horizontal conductive layer 104, but example embodiments thereof are not limited thereto. The through-substrate insulating layer 121 may include an insulating material such as silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

[0104] In example embodiments, the first and second cell contact plugs 152 and 154 may penetrate the gate electrode 130 or extend therein, may penetrate the substrate insulating layer 121 or extend therein, and may be connected to the third circuit interconnection line 286 of the peripheral circuit region PERI.

[0105] Figure 8 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0106] refer to Figure 8 , the semiconductor device 300 may include a substrate 301, a gate structure 330, a source / drain region 305, a gate isolation layer 340, an upper active contact plug 350, a lower active contact plug 355, a gate contact plug 360, and a body contact plug 370. The semiconductor device 300 may also include an upper insulating layer 390, a lower insulating layer 306, a substrate insulating layer 315, an upper interconnection line 382, ​​and a lower interconnection line 388. The gate structure 330 and two source / drain regions 305 adjacent to the gate structure 330 may form a vertical transistor, and the semiconductor device 300 may include at least two vertical transistors facing the gate isolation layer 340.

[0107] The substrate 301 may include a semiconductor material. The gate structure 330 may include a gate dielectric layer 332 and a gate electrode layer 335 sequentially stacked from the inner sidewall of the substrate 301. The gate electrode layer 335 may include a first conductive layer 335_1 and a second conductive layer 335_2 that may be stacked. However, the number of conductive layers forming the gate electrode layer 335 in the example embodiment may vary. The source / drain region 305 may be disposed adjacent to the upper and lower portions of the gate structure 330 in the substrate 301, respectively. The source / drain region 305 may include a first impurity region 305_1 and a second impurity region 305_2 having different impurity concentrations, but the example embodiment thereof is not limited thereto.

[0108] The upper active contact plug 350 may be connected to the source / drain region 305 adjacent to the upper surface of the substrate 301, and the lower active contact plug 355 may be connected to the source / drain region 305 adjacent to the lower surface of the substrate 301. The gate contact plug 360 may be connected to the gate electrode layer 335 and may be disposed on the upper surface of the substrate 301 or may be disposed on the lower surface of the substrate 301. The body contact plug 370 may be connected to the substrate 301 and may be disposed on the upper surface of the substrate 301 or may be disposed on the lower surface of the substrate 301. The substrate insulating layer 315 may be disposed in the substrate 301 to surround the side surface except for the end of the body contact plug 370. The gate isolation layer 340 may be disposed between the vertical transistors disposed adjacent to each other and may contact the gate electrode layer 335. In example embodiments, the width of the gate isolation layer 340 may vary.

[0109] Also, as for each component of the semiconductor device 300, refer to Figures 1 to 3B The description of the corresponding components of the described second device region HR may apply.

[0110] Fig.9A , Fig. 9B , Fig. 9C , Fig.9D , Fig.9E , Fig.9F , Figure 9G , Figure 9H , Fig.9I , Figure 9J , Figure 9K , Figure 9L , Figure 9M , Figure 9N , Fig.9O and Figure 9P is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an example embodiment, illustrating Figure 1 The corresponding area.

[0111] refer to Fig.9A , a preliminary substrate 201p can be prepared.

[0112] The preliminary substrate 201p may be configured as a semiconductor substrate, such as a semiconductor wafer. The preliminary substrate 201p may have a first thickness T1. For example, the first thickness T1 may range from tens of micrometers to hundreds of micrometers.

[0113] refer to Fig. 9B , the substrate 201 may be formed by partially removing the preliminary substrate 201p.

[0114] The preliminary substrate 201p may be removed and thinned by, for example, grinding, lapping, polishing, or etching processes. The substrate 201 may have a second thickness T2 that is less than the first thickness T1, and the second thickness T2 may be in the range of about 10 μm to about 50 μm. In this process, the substrate 201 may be prepared such that Figure 1 The substrate 201 in the embodiment may be inverted, that is, Figure 1 The lower surface of the substrate 201 in the embodiment may be disposed at the upper portion.

[0115] refer to Fig. 9C , a through region TH penetrating the substrate 201 can be formed.

[0116] The through region TH may be formed at Figure 3B The through region TH may be formed to penetrate the entire region from the upper surface to the lower surface of the substrate 201 or extend therein using, for example, an etching process. The through region TH may be in a shape that penetrates the substrate 201 and extends in one direction (for example, the Y direction).

[0117] refer to Fig.9D , a second gate dielectric layer 232 and a first preliminary conductive layer 235p_1 may be formed in each through region TH, and a second lower source / drain region 205C may be formed.

[0118] The second gate dielectric layer 232 may be formed on the inner sidewall of the substrate 201 exposed by the through region TH using a radical oxidation process or a deposition process. The first preliminary conductive layer 235p_1 may be formed by a subsequent process to form the first conductive layer 235_1 (see Figure 3B The first preliminary conductive layer 235p_1 may be, for example, polysilicon, and may be formed through a deposition process to partially or completely fill the through region TH.

[0119] The second lower source / drain region 205C may be formed by implanting impurities into the substrate 201 through an ion implantation process. In the second lower source / drain region 205C, the impurity concentration of the first impurity region 205_1 may be higher than the impurity concentration of the second impurity region 205_2.

[0120] refer to Fig.9E , the first conductive layer 235_1 may be formed by partially removing the first preliminary conductive layer 235p_1, so that the through region TH′ may be formed again, and the contact opening CR may be formed.

[0121] In each first preliminary conductive layer 235p_1, a portion including a central region may be removed by an etching process. Thus, a first conductive layer 235_1 on the second gate dielectric layer 232 may be formed, and a through region TH′ may be formed again between the first conductive layers 235_1 facing each other.

[0122] The contact opening CR may be formed by partially removing the substrate 201. The contact opening CR may be formed together with the partial through region TH′, or may be formed in a process different from the process of forming the through region TH′. In some example embodiments, the contact opening CR may be formed in a subsequent process (such as the reference numeral 204). Figure 9G The contact opening CR is formed in the process described above.

[0123] refer to Fig.9F , the second preliminary conductive layer 235p_2 may be formed to partially or completely fill each through region TH′.

[0124] The second preliminary conductive layer 235p_2 can be formed into a second conductive layer 235_2 by subsequent processes (see Figure 3B The second preliminary conductive layer 235p_2 may be, for example, a metal material such as tungsten (W), and may be formed to fill the through region TH′ through a deposition process.

[0125] refer to Figure 9G , a second conductive layer 235_2 may be formed by partially removing the second preliminary conductive layer 235p_2, and a gate isolation layer 240 and a substrate insulating layer 215 may be formed.

[0126] In each second preliminary conductive layer 235p_2, a portion including the central region may be removed by an etching process. Thus, a second conductive layer 235_2 may be formed on the first conductive layer 235_1. Thus, a second gate electrode layer 235 including the first conductive layer 235_1 and the second conductive layer 235_2 may be completed, and a second gate structure 230 including a second gate dielectric layer 232 and a second gate electrode layer 235 may be completed. By filling an insulating material in the region from which the second preliminary conductive layer 235p_2 is partially removed and in the contact opening CR, a gate isolation layer 240 and a substrate insulating layer 215 may be formed, respectively.

[0127] refer to Figure 9H , a second upper source / drain region 205B may be formed.

[0128] First, as mentioned above Figure 9G The structure including the substrate 201 formed as described above may be disposed inverted so that the substrate insulating layer 215 may face downward. Therefore, for the inverted structure, by performing an ion implantation process, the second upper source / drain region 205B may be formed at a predetermined depth from the upper surface of the substrate 201. Through the above process, the second circuit device TR2 disposed in the second device region HR may be formed.

[0129] refer to Fig.9I , the peripheral region insulating layer 290 may be partially formed, and the second upper active contact plug 250B and the second gate contact plug 260B may be formed, the second upper active contact plug 250B and the second gate contact plug 260B forming a part of the first interconnection structure.

[0130] In this process, contact plugs such as the second upper active contact plug 250B and the second gate contact plug 260B extending from the upper surface of the substrate 201 into the substrate 201 may be formed. The second upper active contact plug 250B and the second gate contact plug 260B may be formed by partially removing the peripheral region insulating layer 290 and filling a conductive material therein.

[0131] refer to Figure 9J , a first circuit device TR1 disposed in the first device region LR may be formed, and a portion of a first interconnect structure and a first bonding structure may be further formed, thereby forming a first substrate structure S1.

[0132] First, a device isolation layer 210 may be formed in the substrate 201, and a first gate dielectric layer 222 and a first gate electrode layer 225 may be sequentially formed on the substrate 201 in the first device region LR. The device isolation layer 210 may be formed, for example, by a shallow trench isolation (STI) process. In some example embodiments, the device isolation layer 210 may be formed in a previous process (e.g., Fig. 9B The device isolation layer 210 is preferentially formed in the process of FIG.

[0133] The first gate dielectric layer 222 may be formed of silicon oxide, and the first gate electrode layer 225 may be formed of at least one of polysilicon, metal silicide, and / or a metal material, but example embodiments thereof are not limited thereto. Thereafter, the first gate structure 220 may be formed by forming a first gate spacer 224 on both sidewalls of the first gate dielectric layer 222 and both sidewalls of the first gate electrode layer 225. Thereafter, by performing an ion implantation process, a first source / drain region 205A may be formed in the substrate 201 at both sides of the first gate structure 220. Thus, the first circuit device TR1 may be completed.

[0134] Thereafter, a first upper active contact plug 250A and a first gate contact plug 260A may be formed in the first device region LR. In some example embodiments, a planar transistor such as the first circuit device TR1 may also be formed in the second device region HR.

[0135] In some example embodiments, at least a portion of the components of the first circuit device TR1 (e.g., at least one of the first source / drain region 205A, the first upper active contact plug 250A, and the first gate contact plug 260A) may be formed together with corresponding components of the second device region HR during a process of forming the second circuit device TR2. Likewise, in some example embodiments, the first circuit device TR1 may be formed earlier than the second circuit device TR2.

[0136] Thereafter, in the first device region LR and the second device region HR, first circuit contact plugs 272 and second circuit contact plugs 274 and first circuit interconnection lines 282, second circuit interconnection lines 284, and third circuit interconnection lines 286 may be formed. The first circuit contact plugs 272 and second circuit contact plugs 274 may be formed by, after forming a portion of the peripheral region insulating layer 290, etching and removing a portion thereof and filling a conductive material therein. The first circuit interconnection lines 282, second circuit interconnection lines 284, and third circuit interconnection lines 286 may be formed, for example, by depositing a conductive material and patterning the material.

[0137] Thereafter, a first bonding insulation layer 299 may be formed on the third circuit interconnection line 286. A first bonding via 295 and a first bonding pad 298 of a first bonding structure may be formed after partially removing the first bonding insulation layer 299 and the peripheral region insulation layer 290.

[0138] Through this process, a first substrate structure S1 can be prepared.

[0139] refer to Figure 9K , a process of manufacturing the second substrate structure S2 may start. First, sacrificial insulating layers 118 and interlayer insulating layers 120 may be alternately stacked on the base substrate SUB, and a vertical sacrificial layer 129 may be formed.

[0140] The base substrate SUB may be removed through a subsequent process, and may be configured as a semiconductor substrate such as undoped silicon (Si).

[0141] Thereafter, in order to form a lower stack structure, a first channel structure CH1 may be provided therein (see Figure 1 ) in the region of the gate electrode 110, the sacrificial insulating layer 118 and the interlayer insulating layer 120 are alternately stacked. The sacrificial insulating layer 118 may be replaced with a gate electrode 130 (see Figure 1 ). The sacrificial insulating layer 118 may be formed of a material that is etched with etching selectivity with respect to the interlayer insulating layer 120. For example, the interlayer insulating layer 120 may be formed of at least one of silicon oxide and / or silicon nitride, and the sacrificial insulating layer 118 may be formed of a material different from that of the interlayer insulating layer 120 selected from silicon, silicon oxide, silicon carbide, and / or silicon nitride. In example embodiments, the thickness of the interlayer insulating layer 120 and the number of films included therein may be different from the illustrated example.

[0142] Thereafter, in the region including the end of the sacrificial insulating layer 118, the photolithography process and the etching process for the sacrificial insulating layer 118 and the interlayer insulating layer 120 may be repeatedly performed so that the sacrificial insulating layer 118 of the upper portion may extend to a length shorter than the sacrificial insulating layer 118 of the lower portion. Therefore, the sacrificial insulating layer 118 may form a stepped shape. The sacrificial insulating layer 118 may be formed to have a relatively greater thickness at the end, and a process for forming the thickness may be further performed. Thereafter, a portion of the lower stacked structure of the cell region insulating layer 190 covering the sacrificial insulating layer 118 and the interlayer insulating layer 120 or overlapping therewith may be formed.

[0143] The vertical sacrificial layer 129 may be formed by forming a lower channel hole to penetrate or extend into the lower stack structure in a region corresponding to the first channel structure CH1 and depositing a material of the vertical sacrificial layer 129 in the lower channel hole. The vertical sacrificial layer 129 may include, for example, polysilicon.

[0144] The upper stack structure may be formed on the lower stack structure in the same or similar manner as the lower stack structure. Figure 1 ), an upper channel hole may be formed to penetrate the upper stack structure or extend therein, and a vertical sacrificial layer may be further formed. In some example embodiments, in this process, a vertical sacrificial layer may also be formed in the region corresponding to the upper stack structure. Figure 1 In the region corresponding to the first cell contact plug 152 and the second cell contact plug 154 .

[0145] refer to Figure 9L , a channel structure CH penetrating the stack structure of the sacrificial insulating layer 118 and the interlayer insulating layer 120 may be formed.

[0146] First, a channel hole may be formed by removing the vertical sacrificial layer 129. Thereafter, a gate dielectric layer 145, a channel layer 140, a channel filling insulating layer 147, and a channel pad 149 may be sequentially formed in each channel hole to form a channel structure CH including a first channel structure CH1 and a second channel structure CH2. The channel layer 140 may be formed on the gate dielectric layer 145 in the channel structure CH. The channel filling insulating layer 147 may be formed to fill the channel structure CH and may include an insulating material. However, in example embodiments, the space between the channel layers 140 may be filled with a conductive material instead of the channel filling insulating layer 147. The channel pad 149 may be formed of a conductive material (e.g., polysilicon).

[0147] refer to Figure 9M , the sacrificial insulating layer 118 may be removed, the gate electrode 130 may be formed, the isolation region MS may be formed, and the first and second cell contact plugs 152 and 154 may be formed.

[0148] First, using a mask layer, a contact hole may be formed in a region where the first contact unit plug 152 is to be formed. Thereafter, a portion of the sacrificial insulating layer 118 exposed by the contact hole may be removed. A tunneling portion may be formed by removing the sacrificial insulating layer 118 to a predetermined length around the contact hole. The tunneling portion may be formed to have a relatively short length in the uppermost sacrificial insulating layer 118, and may be formed to have a relatively long length in the sacrificial insulating layer 118 below it. An insulating material may be deposited in the contact hole and the tunneling portion. An insulating material may be formed on the sidewalls of the contact hole and may fill the tunneling portion. In the uppermost sacrificial insulating layer 118, the insulating material may not completely fill the tunneling portion. Thereafter, a contact sacrificial layer filling the contact hole and the uppermost tunneling portion may be formed.

[0149] Thereafter, in a region corresponding to the isolation region MS, an opening penetrating the sacrificial insulating layer 118 and the interlayer insulating layer 120 and extending to the board layer 101 may be formed, and an etchant may be supplied through the opening to remove the sacrificial insulating layer 118. For example, wet etching may be used to selectively remove the sacrificial insulating layer 118 relative to the interlayer insulating layer 120.

[0150] The gate electrode 130 may be formed by depositing a conductive material in the region from which the sacrificial insulating layer 118 is removed. The conductive material may include a metal, polysilicon, or a metal silicide material. After forming the gate electrode 130, an isolation region MS may be formed by depositing an insulating material in the opening.

[0151] Thereafter, the first cell contact plug 152 may be formed by removing the contact sacrificial layer from the contact hole and depositing a conductive material. After the contact sacrificial layer is removed, a portion of the exposed insulating material may also be removed. In this case, all insulating materials may be removed from the pad region 130P, and the insulating material may remain thereunder and a contact insulating layer 125 may be formed. The first cell contact plug 152 may be formed to have an area extending horizontally from the pad region 130P, and therefore, the first cell contact plug 152 may be physically and electrically connected to the gate electrode 130. The second cell contact plug 154 may be formed by forming other contact holes penetrating the cell region insulating layer 190 and extending into the base substrate SUB on the outside of the gate electrode 130 and depositing a conductive material in the contact hole. A deposition process for the conductive material may be performed simultaneously with a deposition process for the first cell contact plug 152, but example embodiments thereof are not limited thereto.

[0152] refer to Figure 9N , a second interconnection structure and a second bonding structure may be formed on the gate electrode 130 , and the first substrate structure S1 and the second substrate structure S2 may be bonded to each other.

[0153] In the second interconnect structure, the cell upper contact 170 may be formed by etching the cell region insulating layer 190 and depositing a conductive material on the channel pad 149 and the first and second cell contact plugs 152 and 154. The cell interconnect line 180 may be formed by a process of depositing and patterning a conductive material, or by partially forming the cell region insulating layer 190, patterning the layer, and depositing a conductive material.

[0154] In the second bonding structure, a second bonding insulating layer 199 may be formed on the cell region insulating layer 190. Thereafter, a second bonding via 195 may be formed by partially removing the second bonding insulating layer 199 and the cell region insulating layer 190 and depositing a conductive material, and a second bonding pad 198 may be formed on the second bonding via 195. In some example embodiments, the second bonding via 195 disposed upward and the second bonding pad 198 disposed downward may be formed to be integrated with each other. The upper surface of the second bonding pad 198 may be exposed from the cell region insulating layer 190.

[0155] Thereafter, the first substrate structure S1 and the second substrate structure S2 may be connected to each other by bonding the first bonding pad 298 to the second bonding pad 198 by annealing and / or pressurizing. At the same time, the first bonding insulating layer 299 and the second bonding insulating layer 199 may also be bonded to each other. The second substrate structure S2 may be invertedly disposed on the first substrate structure S1 so that the second bonding pad 198 may face downward, and bonding may be performed. The first substrate structure S1 and the second substrate structure S2 may be directly bonded to each other without using an adhesive such as a separate adhesive layer between them.

[0156] refer to Fig.9O , the base substrate SUB may be removed from the joined structure of the first substrate structure S1 and the second substrate structure S2 , and the board layer 101 may be formed.

[0157] For example, a portion of the base substrate SUB may be removed from the upper surface by a polishing process such as a fine grinding process, and the remaining portion may be removed by an etching process such as a wet etching process. By removing the base substrate SUB of the second substrate structure S2, the overall thickness of the semiconductor device may be reduced. By removing the base substrate SUB, the upper end of the channel structure CH and the upper ends of the first cell contact plug 152 and the second cell contact plug 154 may be exposed. The channel dielectric layer or the gate dielectric layer 145 (see FIG. 1 ) may be removed from the upper end of the exposed channel structure CH. Figure 4 An insulating material may be deposited on the exposed upper end of the first cell contact plug 152 to form a capping insulating layer 105.

[0158] The plate layer 101 may be formed by depositing a semiconductor material. The plate layer 101 may be formed, for example, by depositing amorphous silicon (Si) and crystallizing the material. A passivation layer 106 may be formed on the plate layer 101 .

[0159] refer to Figure 9P , the bonding structure of the first substrate structure S1 and the second substrate structure S2 may be reversed, and a back insulating layer 206 may be formed on the back side of the substrate 201, and a lower active contact plug 250C, a body contact plug 270, and a back interconnection line 288 may be formed.

[0160] First, the bonding structure may be reversed so that the back side of the substrate 201 may be disposed at the upper portion. Thereafter, a portion of the back side insulating layer 206 may be formed and a portion thereof may be removed, thereby forming the lower active contact plug 250C and the body contact plug 270, and the back side interconnection line 288 connected to the lower active contact plug 250C and the body contact plug 270 may be formed. In example embodiments, additional contact plugs and interconnection lines may also be formed on the back side interconnection line 288. In some example embodiments, reference may be performed in this process. Fig. 9B , Fig. 9C , Fig.9D , Fig.9E , Fig.9F and Figure 9G At least one of the processes described.

[0161] Therefore, it is possible to produce Figure 1 A semiconductor device 100 is provided in FIG.

[0162] Fig.10 is a view illustrating a data storage system including a semiconductor device according to example embodiments.

[0163] refer to Fig.10 , the data storage system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be implemented as a storage device including one or more semiconductor devices 1100 or an electronic device including a storage device. For example, the data storage system 1000 may be implemented as a solid state drive device (SSD), a universal serial bus (USB), a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0164] The semiconductor device 1100 may be implemented as a nonvolatile memory device, such as, for example, the nonvolatile memory device described in the aforementioned example embodiments. Figures 1 to 7 The NAND flash memory device described herein. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S located on the first structure 1100F. In an example embodiment, the first structure 1100F may be disposed on one side of the second structure 1100S. The first structure 1100F may be implemented as a peripheral circuit structure including a decoder circuit (DECODER) 1110, a page buffer 1120, and a logic circuit 1130. The second structure 1100S may be implemented as a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a memory cell string CSTR disposed between the bit line BL and the common source line CSL.

[0165] In the second structure 1100S, each memory cell string CSTR may include lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. In example embodiments, the number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may vary.

[0166] In example embodiments, the upper transistors UT1 and UT2 may include string selection transistors, and the lower transistors LT1 and LT2 may include ground selection transistors. The first gate lower line LL1 and the second gate lower line LL2 may be configured as gate electrodes of the lower transistors LT1 and LT2, respectively. The word line WL may be configured as a gate electrode of the memory cell transistor MCT, and the first gate upper line UL1 and the second gate upper line UL2 may be configured as gate electrodes of the upper transistors UT1 and UT2, respectively.

[0167] In example embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground selection transistor LT2 connected in series to each other. The upper transistors UT1 and UT2 may include a string selection transistor UT1 and an upper erase control transistor UT2 connected in series to each other. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used in an erase operation for erasing data stored in the memory cell transistor MCT using the GIDL phenomenon.

[0168] The common source line CSL, the first and second gate lower lines LL1 and LL2, the word lines WL, and the first and second gate upper lines UL1 and UL2 may be electrically connected to the decoder circuit 1110 through a first connection interconnect 1115 extending from the first structure 1100F to the second structure 1100S. The bit line BL may be electrically connected to the page buffer 1120 through a second connection interconnect 1125 extending from the first structure 110F to the second structure 1100S.

[0169] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one selected memory cell transistor among the plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by a logic circuit 1130. The semiconductor device 1100 may communicate with the controller 1200 through an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130 through an input / output connection line 1135 extending from the first structure 1100F to the second structure 1100S.

[0170] The controller 1200 may include a processor 1210 , a NAND controller 1220 , and a host interface 1230 . In example embodiments, the data storage system 1000 may include a plurality of semiconductor devices 1100 , and in this case, the controller 1200 may control the plurality of semiconductor devices 1100 .

[0171] The processor 1210 may control the overall operation of the data storage system 1000 including the controller 1200. The processor 1210 may operate according to a predetermined firmware, and may access the semiconductor device 1100 by controlling the NAND controller 1220. The NAND controller 1220 may include a controller interface 1221 that processes communication with the semiconductor device 1100. Through the controller interface 1221, a control command for controlling the semiconductor device 1100, data to be written to the memory cell transistor MCT of the semiconductor device 1100, and data to be read from the memory cell transistor MCT of the semiconductor device 1100 may be sent. The host interface 1230 may provide a communication function between the data storage system 1000 and an external host. When a control command from an external host is received through the host interface 1230, the processor 1210 may control the semiconductor device 1100 in response to the control command.

[0172] Fig.11 is a perspective view illustrating a data storage system including a semiconductor device according to example embodiments.

[0173] refer to Fig.11 , the data storage system 2000 in the example embodiment may include a main board 2001, a controller 2002 mounted on the main board 2001, one or more semiconductor packages 2003, and a DRAM 2004. The semiconductor package 2003 and the DRAM 2004 may be connected to the controller 2002 through an interconnection pattern 2005 formed on the main board 2001.

[0174] The mainboard 2001 may include a connector 2006 having a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. In an example embodiment, the data storage system 2000 may communicate with the external host using one of the interfaces among M-Phy according to a universal serial bus (USB), a peripheral component interconnect fast (PCI-Express), a serial advanced technology attachment (SATA), and / or a universal flash memory (UFS). In an example embodiment, the data storage system 2000 may operate by power supplied from an external host via the connector 2006. The data storage system 2000 may also include a power management integrated circuit (PMIC) for distributing power supplied from an external host to the controller 2002 and the semiconductor package 2003.

[0175] The controller 2002 may write data to the semiconductor package 2003 or may read data from the semiconductor package 2003 , and may increase the operating speed of the data storage system 2000 .

[0176] The DRAM 2004 may be configured as a buffer memory for alleviating the speed difference between the semiconductor package 2003 as a data storage space and an external host. The DRAM 2004 included in the data storage system 2000 may work as a cache memory and may provide a space for temporarily storing data in a control operation for the semiconductor package 2003. When the data storage system 2000 may include the DRAM 2004, the controller 2002 may further include a DRAM controller for controlling the DRAM 2004 in addition to the NAND controller for controlling the semiconductor package 2003.

[0177] The semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. The first semiconductor package 2003a and the second semiconductor package 2003b may each be configured as a semiconductor package including a plurality of semiconductor chips 2200. The first semiconductor package 2003a and the second semiconductor package 2003b may each include a package substrate 2100, a semiconductor chip 2200 located on the package substrate 2100, an adhesive layer 2300 respectively disposed on the lower surface of the semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 to the package substrate 2100, and a mold layer 2500 covering or overlapping the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0178] The package substrate 2100 may be configured as a printed circuit board including the upper package pads 2130. Each semiconductor chip 2200 may include an input / output pad 2210. The input / output pad 2210 may correspond to Fig.10 Each semiconductor chip 2200 may include a gate stack structure 3210 and a channel structure 3220. Each semiconductor chip 2200 may include the gate stack structure 3210 and the channel structure 3220. Figures 1 to 7 A semiconductor device is described.

[0179] In example embodiments, the connection structure 2400 may be configured as a bonding wire that electrically connects the input / output pad 2210 to the upper package pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other by a bonding wire method, and may be electrically connected to the upper package pad 2130 of the package substrate 2100. In example embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other by a connection structure including a through electrode (TSV) instead of the connection structure 2400 of the bonding wire method.

[0180] In an example embodiment, the controller 2002 and the semiconductor chip 2200 may be included in a single package. In an example embodiment, the controller 2002 and the semiconductor chip 2200 may be mounted on a built-in layer substrate different from the main board 2001, and the controller 2002 and the semiconductor chip 2200 may be connected to each other through an interconnect formed on the built-in layer substrate.

[0181] Fig.12 is a cross-sectional view illustrating a semiconductor package according to an example embodiment, illustrating a cross-sectional view taken along line II-II′. Fig.11 An example embodiment of a semiconductor package 2003 in FIG.

[0182] refer to Fig.12 In the semiconductor package 2003A, the package substrate 2100 may be implemented as a printed circuit substrate. The package substrate 2100 may include a package substrate body portion 2120, an upper package pad 2130 (see FIG. 213 ) disposed on an upper surface of the package substrate body portion 2120, and a printed circuit substrate. Fig.11 ), a lower pad 2125 disposed on or exposed through the lower surface of the package substrate main body portion 2120, and an internal interconnect 2135 electrically connecting the upper package pad 2130 to the lower pad 2125 in the package substrate main body portion 2120. The lower pad 2125 may be as shown in FIG. Fig.11 As shown, the interconnect pattern 2005 is connected to the substrate or main board 2001 of the data storage system 2000 through the conductive connection portion 2800.

[0183] Each semiconductor chip 2200 may include a semiconductor substrate 4010 , and a first structure 4100 and a second structure 4200 sequentially stacked on the semiconductor substrate 4010 .

[0184] The first structure 4100 may include a peripheral circuit region including a peripheral interconnect 4110 and a first bonding structure 4150. The second structure 4200 may include a common source line 4205, a gate stack structure 4210 between the common source line 4205 and the first structure 4100, a memory channel structure 4220 penetrating the gate stack structure 4210, and a word line ( Fig.10The first bonding structure 4150 of the first structure 4100 and the second bonding structure 4250 of the second structure 4200 may be bonded to each other and may contact each other. For example, the bonding portions of the first bonding structure 4150 and the second bonding structure 4250 may be formed of copper (Cu).

[0185] In each semiconductor chip 2200, as illustrated in the enlarged view, the first structure 4100 may include a first circuit device TR1 having a planar transistor and a second circuit device TR2 having a vertical transistor. Each semiconductor chip 2200 may also include an input / output pad ( Fig.11 2210).

[0186] The semiconductor chip 2200 may be connected via a connection structure 2400 in the form of a bonding wire (see Fig.11 However, in example embodiments, semiconductor chips in a semiconductor package (such as the semiconductor chip 2200) may be electrically connected to each other through a connection structure including a through-hole electrode (TSV).

[0187] According to the aforementioned example embodiments, by including a circuit device having a back contact vertical transistor (BCVT) structure, a semiconductor device having improved integration density and a data storage system including the semiconductor device may be provided.

[0188] While example embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: a first substrate structure, the first substrate structure comprising a substrate, a first circuit device located on the substrate, and a second circuit device extending into the substrate; as well as a second substrate structure, the second substrate structure being electrically connected to the first substrate structure on the first substrate structure and comprising a plate layer, a gate electrode and a channel structure, the gate electrodes being stacked and spaced apart from each other along a first direction below the plate layer, the first direction being perpendicular to a lower surface of the plate layer facing the first substrate structure, the channel structures extending into the gate electrode, extending in the first direction, and each comprising a channel layer, wherein each of the second circuit devices comprises a second gate dielectric layer, a second gate electrode layer, and a second source / drain region, the second gate dielectric layer extending into the substrate and extending in the first direction, the second gate electrode layer being located on the second gate dielectric layer, and the second source / drain region extending into the substrate from opposite upper and lower surfaces of the substrate, respectively, and The second substrate structure further includes a gate isolation layer, which extends into the substrate between the second circuit devices adjacent to each other in the second circuit devices and contacts the second gate electrode layer.

2. The semiconductor device according to claim 1, wherein An upper surface of the second gate electrode layer is coplanar with the upper surface of the substrate.

3. The semiconductor device according to claim 2, wherein: An upper surface of the second gate dielectric layer is coplanar with the upper surface of the substrate.

4. The semiconductor device according to claim 1, in, An upper surface of one of the second source / drain regions extending from the upper surface of the substrate is coplanar with the upper surface of the substrate, and Wherein, a lower surface of one of the second source / drain regions extending from the lower surface of the substrate is coplanar with the lower surface of the substrate.

5. The semiconductor device according to claim 1, wherein Pairs of second circuit devices among the second circuit devices are disposed symmetrically with respect to the gate isolation layer.

6. The semiconductor device according to claim 1, wherein In a plan view, the gate isolation layer includes a region in a quadrilateral shape between adjacent ones of the second circuit devices.

7. The semiconductor device according to claim 1, wherein Each of the first circuit devices includes a first gate dielectric layer on the substrate, a first gate electrode layer on the first gate dielectric layer, and a first source / drain region extending from an upper surface of the substrate into the substrate.

8. The semiconductor device according to claim 7, in, A second length of a portion of the second gate electrode layer located between the second source / drain regions is greater than a first length of the first gate electrode layer between the first source / drain regions.

9. The semiconductor device according to claim 1, wherein: A length of a portion of the second gate electrode layer located between the second source / drain regions is in a range of 10 μm to 50 μm.

10. The semiconductor device according to claim 1, wherein The first substrate structure further includes: a back insulating layer, the back insulating layer being located on the lower surface of the substrate; and A lower active contact plug extends into the back side insulating layer and is electrically connected to at least one of the second source / drain regions.

11. The semiconductor device according to claim 10, wherein: The first substrate structure further includes: a body contact plug extending into the back insulating layer and into the substrate between the second source / drain regions; and A substrate insulating layer is located on a portion of a side surface of the body contact plug.

12. The semiconductor device according to claim 11, wherein An upper end of the body contact plug extends in the substrate beyond an upper end of the lower active contact plug.

13. The semiconductor device according to claim 1, wherein The first substrate structure further includes: a peripheral region insulating layer, the peripheral region insulating layer being located on the substrate; and A gate contact plug extends into the peripheral region insulating layer and is electrically connected to the second gate electrode layer.

14. A semiconductor device, comprising: a first substrate structure, the first substrate structure comprising a substrate, a first circuit device located on the substrate, a second circuit device extending into the substrate, and a gate isolation layer extending into the substrate and located between adjacent second circuit devices in the second circuit device; as well as a second substrate structure electrically connected to the first substrate structure on the first substrate structure and comprising a gate electrode electrically connected to the first circuit device and the second circuit device, Wherein, adjacent second circuit devices among the second circuit devices are arranged symmetrically with respect to the gate isolation layer.

15. The semiconductor device according to claim 14, wherein: Each of the second circuit devices includes a second gate dielectric layer, a second gate electrode layer, and a second source / drain region, wherein the second gate dielectric layer extends into the substrate and extends in a first direction perpendicular to the upper surface of the substrate, the second gate electrode layer is located on the second gate dielectric layer, and the second source / drain region extends into the substrate from the upper surface and the lower surface of the substrate, respectively.

16. The semiconductor device according to claim 15, wherein: In a cross-sectional view, the second gate electrode layer extends in the first direction and has no region extending in a second direction parallel to the upper surface of the substrate.

17. The semiconductor device according to claim 15, wherein: In a top view, the second gate electrode layer is in a quadrilateral shape.

18. The semiconductor device according to claim 14, wherein: The first substrate structure further includes: an upper active contact plug located on an upper surface of the substrate and electrically connected to the substrate; and A lower active contact plug is located on a lower surface of the substrate and is electrically connected to the substrate.

19. A data storage system, the data storage system comprising: A semiconductor memory device, the semiconductor memory device comprising a first substrate structure, a second substrate structure and an input / output pad, the first substrate structure comprising a substrate and a first circuit device and a second circuit device, the second substrate structure comprising a gate electrode, the input / output pad being electrically connected to the first circuit device and the second circuit device; as well as a controller electrically connected to the semiconductor memory device through the input / output pad and configured to control the semiconductor memory device, wherein the first circuit device is located on the substrate, and the second circuit device extends into the substrate, Wherein, the first substrate structure further includes: a gate isolation layer extending into the substrate and located between adjacent ones of the second circuit devices; a back insulating layer, the back insulating layer being located on the lower surface of the substrate; and A lower active contact plug extends into the back side insulating layer and is electrically connected to the second circuit device.

20. The data storage system according to claim 19, wherein: A channel of a corresponding one of the first circuit devices extends in a direction perpendicular to a channel of a corresponding one of the second circuit devices.

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