BCD integrated circuit manufacturing method for realizing low-cost embedded nonvolatile memory

Abstract

The invention relates to a manufacturing method of a BCD integrated circuit for realizing a low-cost embedded nonvolatile memory. An exemplary integrated circuit fabrication method, the integrated circuit fabrication method comprising: a process operation sequence for disposing a bipolar device, a complementary metal oxide semiconductor (CMOS) device, and a double diffused metal oxide semiconductor (DMOS) device on a monolithic integrated circuit substrate; and further operations for disposing non-volatile memory cells on the monolithic integrated circuit substrate, with respect to the sequence of process operations, without additional thermal budget, without additional implant operations, and using only a single additional mask.

Description

Technical Field

[0001] The present disclosure relates generally to integrated circuit electronics, and more particularly to a BCD (bipolar, CMOS, DMOS) integrated circuit manufacturing process capable of embedding low-cost, high-density silicon-oxide-nitride-oxide-semiconductor (SONOS) nonvolatile memory cells. Background Art

[0002] The manufacturing process for integrated circuits involves applying repeated patterning, deposition, and etching steps to a semiconductor wafer or other substrate to form interconnect structures that operate as analog and / or digital components of electronic circuits. Different sequences of process steps produce different semiconductor device technologies, each of which can offer a variety of different advantages.

[0003] For example, bipolar junction devices generally offer relatively high speed and low output impedance at the expense of relatively high power consumption per device. For broadband analog circuits with relatively low complexity, such as low noise radio frequency amplifiers, bipolar junction devices may be desirable.

[0004] Complementary metal oxide semiconductor (CMOS) devices generally provide relatively high input impedance and low power consumption at the expense of a relatively nonlinear response curve.CMOS devices may be desirable for digital circuits with relatively high complexity, such as digital processors and control logic.

[0005] Double diffused metal oxide semiconductor (DMOS) devices generally provide relatively high voltage tolerance at the expense of relatively large area requirements.DMOS devices may be desirable for monitoring and controlling power signals.

[0006] The development of the BCD integrated circuit manufacturing process employs a series of process steps that enable bipolar junction devices, CMOS devices, and DMOS devices to be formed in isolated areas of a shared semiconductor wafer or substrate and interconnected as needed to form an integrated circuit with all three types of semiconductor devices.

[0007] Non-volatile memory elements are commonly used in many integrated circuit products, allowing information to be quickly accessed and retained in a compact format even in the absence of power. U.S. Patent Application Publication 2017 / 0345833, "Method of manufacturing and operating an on-volatile memory cell," provides an example of a BCD process including a non-volatile memory element, which is incorporated herein by reference in its entirety. Unfortunately, this example requires an increased number of mask, implant, and anneal operations, making it undesirably costly and undesirably limiting the achievable device density. Summary of the invention

[0008] Therefore, an exemplary integrated circuit manufacturing method that can embed low-cost, high-density non-volatile memory cells in BCD integrated circuits is disclosed herein. An exemplary integrated circuit manufacturing method, the integrated circuit manufacturing method comprising: a sequence of process operations for providing bipolar devices, complementary metal oxide semiconductor (CMOS) devices, and double diffused metal oxide semiconductor (DMOS) devices on a monolithic integrated circuit substrate; and further operations for providing non-volatile memory cells on the monolithic integrated circuit substrate, with no additional thermal budget, no additional implantation operations, and only a single additional mask relative to the sequence of process operations. The sequence of process operations includes: one or more ion implantation operations for forming wells and / or buried layers for bipolar devices, CMOS devices, and DMOS devices on the monolithic integrated circuit substrate; an annealing operation for repairing damage caused by one or more ion implantation operations; and a gate formation operation for forming gates for CMOS devices and DMOS devices.

[0009] Another exemplary integrated circuit manufacturing method includes: forming one or more isolation structures to isolate between multiple regions of a semiconductor substrate, the multiple regions including at least one bipolar device region, at least one MOS device region, and at least one non-volatile storage region; forming a pad oxide layer above the multiple regions; performing ion implantation of impurities through the pad oxide layer to form at least one well or buried layer in each of the multiple regions; depositing a silicon nitride layer above the pad oxide layer; depositing an interlayer oxide layer above the silicon nitride layer to form an oxide-nitride-oxide stack; heating to anneal away damage caused by the ion implantation while densifying the oxide-nitride-oxide stack; and using a mask to define one or more portions of the oxide-nitride-oxide stack so that each portion serves as a state element in at least one non-volatile storage region.

[0010] Another exemplary integrated circuit manufacturing method includes: forming one or more isolation structures, which are configured to isolate between multiple regions of a semiconductor substrate, the multiple regions including at least one bipolar device region, at least one MOS device region, and at least one non-volatile storage region; performing ion implantation to form one or more wells in each of the at least one bipolar device region and the at least one MOS device region; forming an oxide-nitride-oxide stack in the at least one non-volatile storage region before annealing away damage caused by the ion implantation, the annealing being used to densify the oxide-nitride-oxide stack; using a mask to protect one or more portions of the oxide-nitride-oxide stack while removing remaining portions of the oxide-nitride-stack; forming a gate dielectric layer to replace the remaining portions; and patterning a gate electrode over each of the one or more portions, while also patterning a gate electrode at each of the one or more MOS device gate locations in each of the at least one MOS device region and the at least one non-volatile storage region.

[0011] Each of the above methods may be used alone or in combination, and may include one or more of the following optional features in any appropriate combination: 1. The non-volatile memory cells each include a state transistor having a SONOS (silicon-oxide-nitride-oxide-semiconductor) or MONOS (metal-oxide-nitride-oxide-semiconductor) state element. 2. The non-volatile memory cells each include an access transistor capable of accessing the state element. 3. Further operations include, before an annealing operation, forming an oxide-nitride-oxide stack including a pad oxide layer used during one or more ion implantation operations. 4. Further operations include, after the annealing operation, using a single additional mask to retain a portion of the oxide-nitride-oxide stack of the state element and to remove the remaining portion of the oxide-nitride-oxide stack. 5. As part of using a single additional mask to remove the remaining portion of the oxide-nitride-oxide stack, further operations include: performing a reactive ion etch to remove an oxide layer above the nitride layer of the oxide-nitride-oxide stack; and performing a second reactive ion etch to remove the nitride layer. 6. As part of removing the remaining portion of the oxide-nitride-oxide stack using a single additional mask, the additional operation further comprises: performing a wet etch to remove the pad oxide layer. 7. Further operations include, after the annealing operation, removing the single additional mask. 8. Further operations include forming a new pad oxide layer after removing the single additional mask. 9. Removing the oxide-nitride-oxide stack outside of the one or more state elements. 10. Providing a gate dielectric layer; and at each location of the one or more MOS devices, forming a gate over each of the one or more state elements, and forming a gate over the gate dielectric layer. 11. Using the gate to form self-aligned sources and drains for the one or more state elements and the one or more MOS devices. 12. Forming a gate contact to the gate and surface contacts to the source and drain and the well in at least one bipolar device region, the gate contact and the surface contacts serving as terminals for 2T SONOS memory cells in at least one non-volatile memory region, terminals for MOS devices in at least one MOS device region, and terminals for bipolar devices in at least one bipolar device region. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1A is a block diagram of an exemplary BCD integrated circuit.

[0013] Figure 1B is a block diagram of an exemplary nonvolatile memory.

[0014] Figure 2A is a circuit schematic of an exemplary 2T SONOS memory cell.

[0015] Figure 2B yes Figure 2A An exemplary storage unit operation table is shown in FIG.

[0016] Figure 3 is a flow chart of an exemplary integrated circuit manufacturing method.

[0017] Figure 4A yes Figure 3 An exemplary cross-sectional view after step 302 of FIG.

[0018] Figure 4B yes Figure 3 An exemplary cross-sectional view after step 304 of FIG.

[0019] Figure 4C yes Figure 3 An exemplary cross-sectional view after step 306 of FIG.

[0020] Figure 4D yes Figure 3 An exemplary cross-sectional view after step 308 of FIG.

[0021] Figure 4E yes Figure 3 An exemplary cross-sectional view after step 310 of FIG.

[0022] Figure 4F yes Figure 3 An exemplary cross-sectional view after step 318 of FIG.

[0023] Figure 4G yes Figure 3 An exemplary cross-sectional view after step 328 of FIG.

[0024] Figure 4H yes Figure 3 An exemplary cross-sectional view after step 330 of FIG.

[0025] FIG4I is Figure 3 An exemplary cross-sectional view after step 332 of FIG.

[0026] Figure 4J yes Figure 3 An exemplary cross-sectional view after step 336 of FIG.

[0027] Figure 4K yes Figure 3 An exemplary cross-sectional view during step 338 of . DETAILED DESCRIPTION

[0028] The following description and drawings are provided for the purpose of explanation, not limitation of the present disclosure. Rather, they provide a basis for one of ordinary skill in the art to understand all modifications, equivalents, and alternatives that fall within the scope of the claims.

[0029] For the sake of simplicity and clarity of illustration, the elements in the figures are not necessarily in proportion, and the same reference numerals in different figures indicate the same elements. In addition, for the sake of simplicity of description, the description and details of well-known steps and elements are omitted. Although the device is described herein as certain n-channel or p-channel devices or certain n-type or p-type doped regions, it will be understood by those skilled in the art that complementary devices according to embodiments of the present invention are also possible. It will be understood by those skilled in the art that the words "during", "at the same time" and "when" used herein are not intended to be exact words for actions to occur immediately after the initiation of the action, but rather to mean that there may be some short but reasonable delays, such as propagation delays, between the reactions initiated by the initial action. The use of the words "approximately", "about" or "substantially" means that the value of the element has a parameter that is expected to be very close to the stated value or position. However, as is well known in the art, there are always minor differences that prevent the value or position from being exactly the stated value or position. It is recognized in the art that deviations of up to about ten percent (10%) (and for semiconductor doping concentrations, up to twenty percent (20%)) are considered to be reasonable deviations from the ideal target exactly as described.

[0030] Herein, the term "oxide" is used as an abbreviation for silicon oxide, or more precisely, silicon dioxide. "Nitride" may be used as an abbreviation for silicon nitride, or more precisely, silicon nitride.

[0031] Figure 1A 1 is a schematic diagram of an exemplary BCD (bipolar, CMOS, DMOS) integrated circuit 100 having a monolithic semiconductor substrate 101 carrying multiple semiconductor device technologies. The integrated circuit 100 may include analog circuits 102 implemented using bipolar junction transistors and other bipolar junction devices (e.g., PN diodes, NPN transistors, PNP transistors, silicon-controlled rectifiers, JFETs), power management circuits 104 implemented using double diffused metal oxide semiconductor (DMOS) devices, digital circuits 106 implemented using metal oxide semiconductor (MOS) devices (e.g., NMOS, PMOS, CMOS), and non-volatile memory 108 that may be implemented using a combination of MOS devices and silicon-oxide-nitride-oxide-semiconductor (SONOS) or metal-oxide-nitride-oxide-semiconductor (MONOS) devices. In this document, SONOS and MONOS devices are essentially interchangeable and are distinguished only by the composition of the top layer. Although the various device types can be isolated from each other by isolation trenches, buried layers, tubes, or other functionally similar isolation structures, they can also be interconnected via appropriately patterned metal layers or other conductive layers deposited on the surface of the substrate, as described below.

[0032] Figure 1B1 is a block diagram of an exemplary non-volatile memory 108 having an interface logic circuit 110 that can control various signal lines of a memory cell array 112, enabling the interface logic 110 to write to and read from selected cells in the array 112. The array 112 has bit cells organized in rows and columns. Each row in the array 112 can have an associated access gate line, an erase gate line, and a control gate line. Each column in the array 112 can have an associated bit line and an associated source line.

[0033] Array 112 may be used as Figure 2A 2 is implemented as shown in the bit cell 202. The illustrated bit cell 202 is a two-transistor (2T) SONOS memory cell having an n-channel MOSFET access transistor 204 and an n-channel SONOS state transistor 206. An access gate (AG) line is connected to the gate of the access transistor 204 and establishes a conductive path between the bit line (BL) and the state transistor 206 when asserted.

[0034] State transistor 206 comprises a SONOS or MONOS state element having a floating gate that provides either a high conductivity path or a low conductivity path between a source line (SL) and access transistor 204, depending on the charge stored thereon. By monitoring the bit line current at a given bit line voltage, interface logic 110 can determine whether the charge on the floating gate represents a binary 1 or 0.

[0035] The control gate (CG) line is connected to the gate of state transistor 206, and the erase gate (EG) line is connected to the bulk terminals of access transistor 204 and state transistor 206. By appropriate control of the control gate and erase gate, interface logic 110 stores or removes charge from the floating gate.

[0036] Figure 2B is a table of operations that can be implemented by the interface logic 110. The operations include clear, set, read, inhibit row, and inhibit column. For the clear operation, the interface logic 110 lowers the control gate voltage to V SS (usually zero volts), while raising the erase gate voltage of the selected row to the programming voltage V PP . Programming voltage V PP It can be a relatively large voltage, such as 15 volts, sufficient to tunnel charge to and from the floating gate of the state transistor. To protect the access transistor, the same programming voltage V is applied to the access gate. PP, thereby minimizing the gate-to-source voltage drop of the access transistor. The bit line and the source line can be kept disconnected (in the figure, Z represents high impedance). In these cases, electrons are drawn away from the floating gate, leaving a net positive charge that is associated with a more conductive channel during a read operation. Note that the asterisk shown for the erase operation indicates that this can be a block operation, i.e., applied simultaneously to multiple cells in a given row of the array 112 having a shared erase gate, rather than to individually selectable bit cells.

[0037] For the set operation, the interface logic 110 raises the control gate voltage for the selected row to the programming voltage V pp , while lowering the erase gate voltage to V SS . The access gate voltage can also be set to V SS to minimize the gate-to-source voltage drop of the access transistor. The bit line of the selected column can be kept disconnected, while the source line of the selected column can be lowered to V SS . (In the unselected columns, both the bit line and the source line are disconnected). For the selected cells in these cases, electrons are drawn to the floating gate of the state transistor of the selected bit cell, leaving a net negative charge that is associated with a less conductive channel during a read operation.

[0038] For the read operation, the interface logic 110 connects the control gate line of the selected row to the intermediate gate voltage V GR , and lowers the erase gate voltage to V SS . The interface logic enables the access transistor by supplying a positive supply voltage V DD (e.g., 3.3V) to the access gate line. The source line is connected to V SS , while the bit line is connected to the intermediate sense voltage V DR . The intermediate gate voltage and the sense voltage can be selected to optimize the read operation, e.g., to maximize the ratio between the sense currents associated with the erased and set states of the state transistor 206. In one example, V GR is about 1.2V, while V DR is 2.5V.

[0039] The interface logic 110 can inhibit the operation of unselected rows by disconnecting their control gates and erase gates, and keeping their access gate lines at V SS . The interface logic 110 can inhibit the operation of unselected columns by disconnecting the associated bit lines and source lines.

[0040] Figure 3 is a flowchart showing a sequence of process operations that can be used in an exemplary integrated circuit manufacturing method. When discussing each block, reference will be made to Figures 4A to 4K .

[0041] Figure 3 A sequence of process operations 302, 304, 308, and 320-338 are shown for providing bipolar devices, CMOS devices, and DMOS devices on a monolithic integrated circuit substrate. Further operations 306, 310-318 (boxes with thick outlines) are also shown in the figure for providing non-volatile memory cells on a monolithic integrated circuit substrate, without requiring additional thermal budgets and additional implant operations in addition to the existing BCD process represented by boxes 302, 304, 308, and 320-338. Only a single additional mask is used, and this can be seen in box 310. The annealing operations and implant operations in the existing operations are sufficient for the new process; therefore, the integration of non-volatile memory elements can be achieved without the need for additional thermal budgets and additional implant operations.

[0042] The fabrication method begins in block 302 where one or more isolation structures, such as isolation trenches, are formed between different regions of a semiconductor substrate to provide isolation between the multiple regions. Figure 4A is an exemplary cross-sectional view after step 302, showing a p-type substrate 402 having a trench 404 separating a storage region 406 from a bipolar region 408. These two regions are representative, and in practice there may be multiple such regions and other region types, including, for example, at least one MOS device region for digital circuits and a DMOS region for power circuits. The substrate material may be a single crystal semiconductor material, a semiconductor substrate on an insulator, a silicon layer above a glass plate, an epitaxial layer grown on a semiconductor substrate, a semiconductor material containing a Group 14 element (e.g., carbon, silicon, germanium, or a combination thereof), or another semiconductor material commonly used in the manufacture of semiconductor components. According to an embodiment, the semiconductor material is lightly doped with an impurity material of p-type conductivity, i.e., a p-type dopant. Alternatively, the semiconductor material may be doped with an impurity material of n-type conductivity.

[0043] A trench may be formed between any adjacent regions to maintain electrical isolation between these regions. The isolation trench 404 may be formed using shallow trench isolation (STI), deep trench isolation, or local oxidation of silicon (LOCOS) techniques.

[0044] During or after trench formation, a thin pad layer 410 is formed on the surface of the semiconductor substrate using, for example, a wet oxidation technique such as an in-situ steam generation (ISSG) operation. Although it is preferred that the pad layer 410 is silicon oxide, in practice the pad layer can be any suitable dielectric material, such as silicon nitride. In some cases, the pad layer can be supplemented with a stop layer, such as, for example, a polish stop layer or an etch stop layer sequentially formed on or from a semiconductor substrate material using, for example, thermal growth techniques, deposition techniques, combinations of thermal growth techniques and deposition techniques, etc. The pad layer can be the same material as the stop layer, or the pad layer can be a different material than the stop layer.

[0045] In block 304, deep ion implantation operations may be performed to create buried layers, wells, and field plates in those areas of the substrate where such features are needed, for example, at least one well or buried layer in each of at least one MOS device area and non-volatile storage area. The ability to form wells and buried layers in each of multiple areas is an advantage of the BCD process. Each feature type may be created using a corresponding photoresist layer coupled to a corresponding photolithography operation to pattern the layer, thereby creating a mask with exposed areas that causes the implanted ions to reach only the areas where these features are needed. Thus, Figure 4B The buried layer 412 shown in the figure can be created using a buried n-layer mask that exposes the storage area 406 and any other area where a buried n-layer is required. The n-well mask can be used to create an n-well 414 in the bipolar region 408, the power region, and other places where it is needed. The p-well mask can be used to create a p-well 416 in the bipolar region and other places where it is needed. The buried layer, n-well, and p-well are doped with impurities ("dopants") that provide the desired conductivity type, which can be implanted ions. The associated masks are removed after use.

[0046] Following these deep implant operations, an annealing cycle may be performed to allow the dopants to integrate into the crystal structure of the substrate while also repairing dislocations and other crystal damage caused during the implantation process. However, prior to such annealing, the exemplary integrated circuit fabrication method of block 306 includes depositing a silicon nitride layer 418 over the pad oxide layer 410 used during one or more implantation operations of block 304. Over the silicon nitride layer 418, a second overlying oxide layer 420 (sometimes referred to herein as a "sandwich" oxide layer) is deposited to form an oxide-nitride-oxide (ONO) stack that includes the pad oxide layer used during one or more ion implantation operations. The ONO stack as shown in FIG. Figure 4C These layers can be deposited over the entire surface of the substrate.

[0047] In block 308, an annealing cycle may be performed for the reasons described above, but also to densify the amorphous material of the oxide-nitride-oxide stack. That is, heating is performed to anneal away the damage caused by the ion implantation while densifying the ONO stack. A side effect of the annealing cycle, which is also a motivation for adhering to the thermal budget, is the migration of dopants, resulting in an expansion of the doped regions, such as Figure 4D Indicated.

[0048] In block 310, a photoresist layer is added and patterned to create Figure 4E The protective mask 422 shown is used to protect and thereby define one or more portions of the state element of the ONO stack that is retained as a state transistor. Each state transistor has a corresponding portion of the ONO stack as a state element. Mask 422 is a single additional mask mentioned elsewhere. It is not part of the existing BCD process and is the only additional mask used by the disclosed process to integrate non-volatile memory into a completed circuit. Although only a single state transistor is shown in the figure, it should be understood that a plurality of such state transistors can be formed in the non-volatile storage area 406 and any other non-volatile storage area 406. Each row of the memory cell array 112 can have a separate, trench-isolated non-volatile storage area.

[0049] In block 312, a reactive ion etching process may be performed using a first set of parameters or "recipes" to remove exposed portions of the top oxide layer 420, and a second recipe may be used in block 314 to remove exposed portions of the nitride layer 418. In block 316, the pad layer 410 may be removed using, for example, a wet etch. Again, a protective mask 422 is used to retain the portion of the ONO stack used for the state transistor while removing the remainder of the ONO stack in blocks 312-316. Each of these etching operations may be viewed as using a single additional mask to remove a portion of the remainder of the ONO stack.

[0050] In block 318, the mask is removed or "stripped", leaving an isolated ONO stack ( 424 ) that can be used as a SONOS or MONOS state element. Figure 4F ). After that, a BCD process can be performed to complete the integrated circuit, and a standard MOS gate is used to complete the state transistor. When the standard MOS gate is, for example, polysilicon, a SONOS configuration can be achieved. If metal is used, the state element adopts a MONOS configuration.

[0051] Figure 3Two optional boxes 320 and 322 are included, which represent operations that can be performed when multiple gate thicknesses need to be provided (for example, for use with different supply voltages). In box 320, a new pad oxide or other suitable gate dielectric layer is deposited over the exposed silicon surface of the substrate. In box 322, a photolithography operation is performed, that is, a patterned mask layer with openings is created to remove the new pad oxide or other suitable dielectric layer where a thicker gate is not required. Before depositing a new oxide layer or other suitable dielectric layer 426 in box 324, the exposed dielectric layer area is removed and the patterned mask layer is stripped. Therefore, after removing a single additional mask in box 318, a new pad oxide layer 426 can be formed in box 320 and / or box 324. The new pad oxide layer 426 may also be referred to as a gate dielectric layer 426.

[0052] In block 326, a layer of doped polysilicon (polysilicon) (short for polycrystalline silicon) or another suitable conductive gate material is deposited. In block 328, another photolithography operation is performed to pattern a layer of photoresist material to create openings where gates are not needed to remove the gate material layer. Removal can be performed using a reactive ion etchant. In general, blocks 320-328 are gate formation operations, which are used to form a gate 428 above the gate dielectric layer at each location of the MOS device and the DMOS device, in addition to forming an access gate for an access transistor above the gate dielectric layer for each memory cell and a control gate for a state transistor above the state element. The photolithography operation patterns the photoresist material layer to serve as a mask for patterning a gate electrode above each of one or more portions of the ONO stack, while also patterning a gate electrode at each of one or more MOS device gate locations in each of at least one MOS device region and at least one non-volatile storage region. Figure 4G A gate electrode 428 for the state transistor and a gate electrode 430 for the access transistor are shown prior to removal of an overlying photoresist 432 .

[0053] After stripping the photoresist 432, another photolithography operation is performed to create a source-drain mask 433 in block 330, which has openings to expose areas where transistor sources and drains 434 or other lightly doped regions 436 are needed to be provided. Ion implantation may be used to create these lightly doped regions. Figure 4HAs shown, the existing gate structure provides shielding of the channel region, thereby enabling self-alignment of the source and drain regions 434. Thereafter, the mask is stripped, and optionally followed by deposition of a conformal oxide or a suitable dielectric layer, for example on the order of 20 nm to 500 nm, to insulate the sides of the gate electrode. If so, an etching or polishing operation may be performed to expose at least a portion of the upper surface of the gate electrode.

[0054] In block 332, another photolithography operation is performed to create an n+ region mask, i.e., patterned layer 438, to expose areas where heavy n-type doping is required for ohmic contact between the n-type region and the conductive capping layer. Figure 4i As shown, an ion implantation operation may be performed to create these n+ ohmic regions 440 .

[0055] After stripping the patterned layer 438, in block 334, similar operations may be performed to form a p+ region mask and provide a heavily p-type doped region 442 for ohmic contact between the p-type region and the conductive capping layer. Figure 4J As shown, the conductive surface contact 444 and the gate contact 445 can be formed after surface exposure etching using similar photolithography operations using refractory metals (e.g., nickel, titanium, platinum, cobalt, tungsten, iridium) or other suitable conductive contact materials. Figure 4J As shown, these surface contacts 444 are connected to the source, drain and well in at least one bipolar device region, while the gate contact 445 is connected to the gate of the state transistor, the gate of the access transistor and the gate of the MOS device in other regions. The gate contacts and surface contacts provide connection terminals for the 2T SONOS memory cell in at least one non-volatile storage region, the MOS device in at least one MOS device region and the bipolar device in at least one bipolar device region.

[0056] Afterwards, if Figure 4K As shown, a thicker oxide or other suitable dielectric layer 448, for example on the order of 20 nm to about 500 nm, may be deposited and planarized prior to forming and filling vias 450 that provide electrical connections to surface contacts 444. Via filling may be performed simultaneously with the deposition of a first metal layer or other conductive material layer that may be patterned using standard photolithography operations to form connections between the transistor and other devices formed in the substrate.

[0057] Additional layers and "metal" layers may be provided in block 338 before forming a final passivation layer with apertures for external connections to the integrated circuit. Standard packaging techniques may be employed, such as wire bonding to a lead frame during the packaging process, or multi-chip fabrication to bond a chip to another chip or an intermediate interposer to provide additional pin routing.

[0058] Now, it should be understood that a non-volatile memory cell consisting of two active devices has been provided, wherein the two active devices include an access transistor and a state transistor. Multiple cells can be combined in a row to share a block erase gate terminal. According to an embodiment, the access transistor and the state transistor can be n-channel devices formed by n-type source regions and drain regions in a p-type bulk semiconductor substrate. A floating nitride layer is provided between the channel and the gate of the state transistor for capturing positive or negative charges representing the stored information bits. As described above, such a state element can be provided using only a single additional mask relative to existing BCD integrated circuit manufacturing processes, and without increasing the thermal budget.

Claims

1. A method for manufacturing an integrated circuit, the method comprising: A process operation sequence, wherein the process operation sequence is used to set a bipolar device, a complementary metal oxide semiconductor (CMOS) device, and a double diffused metal oxide semiconductor (DMOS) device on a monolithic integrated circuit substrate, and the process operation sequence comprises: one or more ion implantation operations for forming wells and / or buried layers for the bipolar device, the CMOS device, and the DMOS device on the monolithic integrated circuit substrate; an annealing operation for repairing damage caused by the one or more ion implantation operations; and a gate forming operation for forming gates for the CMOS device and the DMOS device; and Further operations are provided for providing non-volatile memory cells on the monolithic integrated circuit substrate with no additional thermal budget, no additional implant operations, and using only a single additional mask relative to the sequence of process operations. 2 . The integrated circuit manufacturing method according to claim 1 , wherein the non-volatile memory cells each comprise a silicon-oxide-nitride-oxide semiconductor (SONOS) or a metal-oxide-nitride-oxide semiconductor (MONOS) state transistor. 3 . 3 . The method of manufacturing an integrated circuit according to claim 2 , wherein each of the nonvolatile memory cells comprises an access transistor capable of accessing the state transistor.

4. The integrated circuit manufacturing method according to claim 2, wherein the further operation comprises, before the annealing operation: An oxide-nitride-oxide stack is formed including a pad oxide layer used during the one or more ion implantation operations.

5. The integrated circuit manufacturing method according to claim 4, wherein the further operation comprises, after the annealing operation: The single additional mask is used to retain portions of the oxide-nitride-oxide stack of the state transistor and to remove remaining portions of the oxide-nitride-oxide stack.

6. The integrated circuit manufacturing method of claim 5, wherein as part of using the single additional mask to remove the remaining portion of the oxide-nitride-oxide stack, the further operation comprises: performing reactive ion etching to remove an oxide layer above a nitride layer of the oxide-nitride-oxide stack; as well as A second reactive ion etching is performed to remove the nitride layer.

7. The integrated circuit manufacturing method of claim 6, wherein as part of using the single additional mask to remove the remaining portion of the oxide-nitride-oxide stack, the further operation comprises: A wet etch is performed to remove the pad oxide layer.

8. The integrated circuit manufacturing method according to claim 5, wherein the further operation comprises, after the annealing operation: The single additional mask is removed. 9 . The integrated circuit manufacturing method according to claim 8 , wherein the further operation further comprises forming a new pad oxide layer after removing the single additional mask.

10. A method for manufacturing an integrated circuit, the method comprising: forming one or more isolation structures to isolate between a plurality of regions of a semiconductor substrate, the plurality of regions including at least one bipolar device region, at least one MOS device region, and at least one nonvolatile storage region; forming a pad oxide layer over the plurality of regions; performing ion implantation of impurities through the pad oxide layer to form at least one well or buried layer in each of the plurality of regions; depositing a silicon nitride layer over the pad oxide layer; depositing an interlayer oxide layer over the silicon nitride layer to form an oxide-nitride-oxide stack; heating to anneal away damage caused by the ion implantation while densifying the oxide-nitride-oxide stack; as well as A mask is used to define one or more portions of the oxide-nitride-oxide stack such that each portion functions as a state element in the at least one nonvolatile storage region.

11. The integrated circuit manufacturing method according to claim 10, further comprising: The oxide-nitride-oxide stack except for the one or more state elements is removed. 12 . The integrated circuit manufacturing method according to claim 11 , wherein the removing comprises performing reactive ion etching to remove the interlayer oxide layer. 13 . The method of manufacturing an integrated circuit according to claim 12 , wherein the removing further comprises performing a second reactive ion etching to remove the silicon nitride layer. 14 . The method of manufacturing an integrated circuit according to claim 13 , wherein the removing further comprises performing a wet etch to remove the pad oxide layer.

15. The integrated circuit manufacturing method according to claim 11, further comprising: removing the mask; providing a gate dielectric layer; as well as At each location of one or more MOS devices, a gate is formed over each of the one or more state elements, and a gate is formed over the gate dielectric layer.

16. The integrated circuit manufacturing method according to claim 15, further comprising: The gate is used to form self-aligned sources and drains of the one or more state elements and the one or more MOS devices.

17. The integrated circuit manufacturing method according to claim 16, further comprising: A gate contact to the gate and surface contacts to the source and the drain and the well are formed in the at least one bipolar device region, at least some of the gate contacts and the surface contacts forming terminals for 2T SONOS memory cells in the at least one non-volatile storage region, terminals for MOS devices in the at least one MOS device region, and terminals for bipolar devices in the at least one bipolar device region.

18. A method for manufacturing an integrated circuit, the method comprising: forming one or more isolation structures configured to isolate between a plurality of regions of a semiconductor substrate, the plurality of regions including at least one bipolar device region, at least one MOS device region, and at least one non-volatile storage region; performing ion implantation to form one or more wells in each of the at least one bipolar device region and the at least one MOS device region; forming an oxide-nitride-oxide stack in the at least one nonvolatile storage region before annealing away damage caused by the ion implantation, the annealing being used to densify the oxide-nitride-oxide stack; using a mask to protect one or more portions of the oxide-nitride-oxide stack while removing remaining portions of the oxide-nitride-oxide stack; forming a gate dielectric layer to replace the remaining portion; as well as A gate electrode is patterned over each of the one or more portions while also patterning a gate electrode at each of one or more MOS device gate locations in each of the at least one MOS device region and the at least one nonvolatile storage region.

19. The integrated circuit manufacturing method according to claim 18, further comprising: The gate electrode is used to form a self-aligned source and drain.

20. The integrated circuit manufacturing method according to claim 19, further comprising: A gate contact to the gate electrode and surface contacts to the source and the drain and the one or more wells are formed, the gate contact and the surface contacts providing terminals for a 2T SONOS cell in the at least one nonvolatile storage region, terminals for a MOS device in the at least one MOS device region, and terminals for a bipolar device in the at least one bipolar device region.

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