Semiconductor device

Abstract

A semiconductor device includes: a substrate; a bit line disposed on the substrate; a first insulating pattern disposed on the bit line; a first word line disposed on the first insulating pattern; a channel pattern disposed on the bit line and spaced apart from the first word line in the first direction; a second insulating pattern disposed on the first word line and extending in a second direction; a third insulating pattern disposed on the channel pattern, the channel pattern including a horizontal portion interposed between the bit line and the third insulating pattern and a vertical portion interposed between the third insulating pattern and the first word line; and a landing pad connected to the channel pattern and covering an upper surface of a vertical portion of the channel pattern and opposite side surfaces of the vertical portion.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices. Background Art

[0002] It is desirable to increase the integration of semiconductor memory devices in order to meet consumer demand for superior performance and low prices. In the case of semiconductor memory devices, it is particularly desirable to increase the degree of integration because the degree of integration is an important factor in determining product prices.

[0003] In the case of a two-dimensional or planar semiconductor memory device, the integration level is mainly determined by the area occupied by the unit memory cell and is therefore greatly affected by the level of fine pattern formation technology. However, because ultra-high-priced equipment is required to refine the pattern, the integration level of two-dimensional semiconductor memory devices is increasing, but is still limited. Therefore, a semiconductor memory device including a vertical channel transistor whose channel extends in the vertical direction has been proposed. Summary of the invention

[0004] The present disclosure provides semiconductor devices having improved reliability and operating characteristics.

[0005] According to one aspect of the present disclosure, a semiconductor device includes: a substrate; a bit line disposed on the substrate and extending in a first direction; a first insulating pattern disposed on an upper surface of the bit line and extending in a second direction intersecting the first direction, wherein the first direction and the second direction are parallel to the upper surface of the substrate; a first word line disposed on an upper surface of the first insulating pattern and extending in the second direction; a channel pattern disposed on an upper surface of the bit line and spaced apart from the first word line in the first direction; a gate insulating pattern disposed between a first side surface of the first word line and the channel pattern; a second insulating pattern disposed on an upper surface of the first word line and extending in the second direction; a third insulating pattern disposed on the channel pattern, wherein the channel pattern includes a horizontal portion and a vertical portion, wherein the horizontal portion extends in the first direction and is interposed between an upper surface of the bit line and a lower surface of the third insulating pattern, wherein the vertical portion extends from the horizontal portion in a third direction and is interposed between a side surface of the third insulating pattern and the first word line, and wherein the third direction is perpendicular to the upper surface of the substrate; and a landing pad connected to the channel pattern and covering an upper surface of the vertical portion of the channel pattern and opposite side surfaces of the vertical portion extending from the upper surface of the vertical portion.

[0006] According to one aspect of the present disclosure, a semiconductor device includes: a substrate; a bit line disposed on the substrate and extending in a first direction; a first insulating pattern disposed on the bit line and extending in a second direction intersecting the first direction; a first word line disposed on the first insulating pattern and extending in the second direction; a channel pattern spaced apart from the first word line in the first direction; a gate insulating pattern disposed between the first word line and the channel pattern; a second insulating pattern disposed on the first word line and extending in the second direction; a third insulating pattern disposed on the channel pattern; and a landing pad connected to the channel pattern. The landing pad contacts at least three surfaces of the channel pattern.

[0007] According to one aspect of the present disclosure, a semiconductor device includes: a substrate; a bit line, which is arranged on the substrate and extends in a first direction; and a word line structure, which is arranged on the bit line and extends in a second direction intersecting the first direction. The word line structure includes a first insulating pattern covering the upper surface of the bit line, a pair of word lines arranged on the first insulating pattern and spaced apart from each other in the first direction, a first gate insulating pattern covering the side surface of each of the pair of word lines, and a second insulating pattern covering the upper surface of the pair of word lines. The semiconductor device further includes a channel pattern arranged between adjacent word line structures in the first direction, a second gate insulating pattern arranged between the channel pattern and the word line structure, a third insulating pattern arranged on the channel pattern, and a landing pad connected to the channel pattern. The channel pattern includes a horizontal portion extending in the first direction along the upper surface of the bit line, and a vertical portion extending from the horizontal portion along the side surface of the adjacent word line structure. The landing pad includes a first portion protruding between the channel pattern and the third insulating pattern, and a second portion protruding between the channel pattern and the second insulating pattern.

[0008] According to an aspect of the present disclosure, a contact area between a channel pattern and a landing pad is increased, thereby reducing contact resistance and improving operating characteristics of a semiconductor device.

[0009] According to an aspect of the present disclosure, interface reliability between a channel pattern and a gate insulating pattern may be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A layout diagram of a semiconductor device according to some embodiments is shown.

[0011] Figure 2 Shows Figure 1 A cross-sectional view of the semiconductor device taken along line AA'.

[0012] Figure 3 Shows Figure 2 Magnified view of “P1” in .

[0013] Figure 4 Shows Figure 3 Magnified view of “P2” in .

[0014] Figures 5 to 10 A cross-sectional view of a semiconductor device according to some embodiments is shown.

[0015] Figures 11 to 25 A cross-sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments is shown. DETAILED DESCRIPTION

[0016] The present disclosure will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the present disclosure are shown. As those skilled in the art will appreciate, the described embodiments may be modified in various ways, all without departing from the spirit or scope of the present disclosure.

[0017] In order to clearly describe the present disclosure, parts or portions irrelevant to the description are omitted, and the same or similar constituent elements are denoted by the same reference numerals throughout the specification.

[0018] In addition, in the drawings, for ease of description, the size and thickness of each element are arbitrarily shown, and the present disclosure is not necessarily limited to the size and thickness shown in the drawings. In the drawings, for clarity, the thickness of layers, films, panels, regions, areas, etc. are exaggerated. In the drawings, for ease of description, the thickness of some layers and areas is exaggerated.

[0019] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it may be directly on the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements. In addition, in the specification, the words "on..." or "above..." mean disposed on or below a target portion, and do not necessarily mean disposed on the upper side of the target portion based on the direction of gravity.

[0020] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0021] Furthermore, throughout the specification, the phrase "in a plan view" or "on a plane" means viewing the target portion from the top, and the phrase "in a sectional view" or "on a cross section" means a cross section formed by vertically cutting the target portion from the side.

[0022] In the following, reference will be made to Figures 1 to 4 Semiconductor devices according to some embodiments are described.

[0023] Figure 1 A layout diagram of a semiconductor device according to some embodiments is shown. Figure 2 Shows Figure 1 A cross-sectional view of the semiconductor device taken along line AA'. Figure 3 Shows Figure 2 Magnified view of “P1” in . Figure 4 Shows Figure 3 Magnified view of “P2” in .

[0024] Reference Figures 1 to 4 , a semiconductor device according to some embodiments may include a peripheral circuit structure PS and a cell array structure CS disposed on the peripheral circuit structure PS.

[0025] The peripheral circuit structure PS may include a substrate 100 and a core and peripheral circuit SA integrated on an upper surface of the substrate 100. The substrate 100 may have a structure in which a base substrate and an epitaxial layer are stacked, but is not limited thereto. For example, the substrate 100 may be a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, or a semiconductor on insulator (SOI) substrate. Hereinafter, the substrate 100 will be described as a silicon substrate.

[0026] The core and peripheral circuit SA may include an NMOS transistor and a PMOS transistor integrated on the substrate 100. The core and peripheral circuit SA may be electrically connected to the bit line BL through the peripheral circuit wiring and the peripheral circuit contact plug. The sense amplifiers in the core and peripheral circuit SA may be electrically connected to the bit line BL, and each sense amplifier may amplify and output a difference in voltage levels sensed by a pair of bit lines BL.

[0027] The cell array structure CS may include a memory cell including a vertical channel transistor (VCT). The vertical channel transistor may refer to a structure in which a channel length extends in a direction perpendicular to the upper surface of the substrate 100.

[0028] In some embodiments, the cell array structure CS may include a lower insulating layer 110, a bit line BL, a first insulating pattern 120, a channel pattern CP, a word line WL, a gate insulating pattern Gox, a low dielectric constant material pattern 130 (i.e., a low-k material pattern), a second insulating pattern 140, a third insulating pattern 150, a landing pad LP, an interlayer insulating layer 160 and a data storage pattern DSP.

[0029] The lower insulating layer 110 may cover the core and peripheral circuit SA, the peripheral circuit wiring, and the peripheral circuit contact plug on the substrate 100. The lower insulating layer 110 may include a multilayer insulating film. For example, the lower insulating layer 110 may include or may be a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and / or a low dielectric film.

[0030] The bit lines BL may be disposed on the substrate 100. For example, the lower insulating layer 110 may be disposed on the substrate 100, and the bit lines BL may be disposed on the lower insulating layer 110. The bit lines BL may extend along a first direction DR1. The bit lines BL may be disposed to be spaced apart from each other in a second direction DR2 intersecting the first direction DR1. For example, the second direction DR2 may be a direction perpendicular to the first direction DR1. In some embodiments, the first direction DR1 and the second direction DR2 may be parallel to the upper surface of the substrate 100. The lower insulating layer 110 may be disposed to fill the space between the bit lines BL. For example, the upper surface of the lower insulating layer 110 and the upper surface of the bit lines BL may be disposed at substantially the same level. Terms such as "same", "equal", "plane" or "coplanar" used herein cover approximate identity, including variations that may occur, for example, due to a manufacturing process. The term "substantially" may be used here to emphasize the meaning unless the context or other statements indicate otherwise.

[0031] The bit line BL may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof, or may be formed of doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. For example, the bit line BL may include Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, or may be formed of Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but is not limited thereto. The bit line BL may include a single layer or multiple layers made of the above materials.

[0032] In some embodiments, the bit line BL may include a two-dimensional semiconductor material, which may include, for example, graphene, carbon nanotubes, or a combination thereof.

[0033] The first insulating patterns 120 may be disposed on the bit lines BL and may extend in the second direction DR2. The first insulating patterns 120 may be disposed to cross the bit lines BL. The first insulating patterns 120 may be disposed to be spaced apart from each other in the first direction DR1.

[0034] The first insulating pattern 120 may include, for example, at least one of low dielectric constant (low-k) materials, or may be formed of, for example, at least one of low dielectric constant (low-k) materials, but is not limited thereto, wherein the low dielectric constant (low-k) material has a dielectric constant smaller than that of silicon oxide, silicon oxynitride, silicon nitride and silicon oxide.

[0035] The low-k material may include, for example, at least one of flowable oxide (FOX), ton-sulphid (TOSZ), undoped silicate glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PETEOS), fluoride silicate glass (FSG), carbon-doped silicon oxide (CDO), xerogel, aerogel, amorphous fluorinated carbon, organosilicate glass (OSG), polyparaxylene, bisbenzocyclobutene (BCB), SiLK, polyimide, porous polymer materials, and combinations thereof, but is not limited thereto.

[0036] The word line WL is disposed on the first insulating pattern 120 and may extend in the second direction DR2. The word line WL may be disposed to cross the bit line BL. The word line WL may be disposed to be spaced apart in the first direction DR1. The word line WL may be spaced apart from the bit line BL in the third direction DR3. The third direction DR3 may be a direction perpendicular to the upper surface of the substrate 100, and may be a direction perpendicular to the first direction DR1 and the second direction DR2. The word line WL may be spaced apart from the bit line BL in the third direction DR3 by the first insulating pattern 120.

[0037] A pair of word lines WL1 and WL2 may be disposed on the first insulating pattern 120. The pair of word lines WL1 and WL2 may be disposed on an upper surface of the first insulating pattern 120. The pair of word lines WL1 and WL2 may include a first word line WL1 and a second word line WL2 spaced apart from each other in the first direction DR1. For example, the first word line WL1 may be disposed near one edge of the upper surface of the first insulating pattern 120, and the second word line WL2 may be disposed near the other edge of the upper surface of the first insulating pattern 120. One side surface of the first word line WL and one side surface of the second word line WL2 may face each other in the first direction DR1.

[0038] The word line WL may include, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof, or may be formed of, for example, doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof. The word line WL may include, for example, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, or may be formed of, for example, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but is not limited thereto.

[0039] The gate insulation pattern Gox may be disposed between the word line WL and a channel pattern CP to be described later. The gate insulation pattern Gox may be disposed on a side surface of the word line WL. In some embodiments, the gate insulation pattern Gox may include a first gate insulation pattern Gox1 disposed directly on the word line WL (i.e., contacting the word line WL) and a second gate insulation pattern Gox2 disposed on the first gate insulation pattern Gox1. The first gate insulation pattern Gox1 may be disposed directly on a side surface of the word line WL (i.e., contacting the side surface). The second gate insulation pattern Gox2 may be disposed between the first gate insulation pattern Gox1 and a channel pattern CP to be described later.

[0040] The gate insulating pattern Gox may include silicon oxide, silicon oxynitride, a high-k material having a higher dielectric constant than silicon oxide, or a combination thereof, or may be formed of silicon oxide, silicon oxynitride, a high-k material having a higher dielectric constant than silicon oxide, or a combination thereof. The high-k material may include metal oxide or metal oxynitride. The high-k material may include, for example, HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO 2 、Al 2 O 3 However, not limited thereto, the material included in the gate insulating pattern Gox may be variously changed.

[0041] For example, the first gate insulating pattern Gox1 may be Al 2 O 3 The second gate insulating pattern Gox2 may be SiO 2 , but they are not limited to this.

[0042] The first gate insulating pattern Gox1 may be disposed on the first insulating pattern 120. The first gate insulating pattern Gox1 may be disposed on an upper surface of the first insulating pattern 120. In some embodiments, the first gate insulating pattern Gox1 may include a first portion Gox1_P1 covering side surfaces of the first and second word lines WL1 and WL2 facing a channel pattern CP to be described later, and a second portion Gox1_P2 covering side surfaces of the first and second word lines WL1 and WL2 facing each other.

[0043] The second portion Gox1_P2 of the first gate insulating pattern Gox1 may cover the upper surface of the first insulating pattern 120 exposed between the first and second word lines WL1 and WL2. The second portion Gox1_P2 of the first gate insulating pattern Gox1 conformally covers the side surfaces of the first and second word lines WL1 and WL2 facing each other and the upper surface of the first insulating pattern 120.

[0044] The second gate insulating pattern Gox2 will be described in detail later.

[0045] The second insulating pattern 140 is disposed on the word line WL and may extend in the second direction DR2. The second insulating pattern 140 may be disposed to cross the bit line BL. The second insulating pattern 140 may be disposed to be spaced apart from each other along the first direction DR1. The second insulating pattern 140 may overlap the first insulating pattern 120 in the third direction DR3.

[0046] The second insulating pattern 140 may include or be formed of the same material as the first insulating pattern 120, but is not limited thereto. For example, the second insulating pattern 140 may include or be formed of at least one of low-k materials having a dielectric constant smaller than that of silicon oxide, silicon oxynitride, silicon nitride, or silicon oxide.

[0047] The second insulating pattern 140 may be disposed on the pair of word lines WL1 and WL2 and the first gate insulating pattern Gox1 covering side surfaces of the pair of word lines WL1 and WL2. The second insulating pattern 140 may be disposed on upper surfaces of the first and second word lines WL1 and WL2 and the first gate insulating pattern Gox1.

[0048] The first word line WL1 and the second word line WL2 may be disposed between the first insulating pattern 120 and the second insulating pattern 140. The first word line WL1 and the second word line WL2 may be disposed between the upper surface of the first insulating pattern 120 and the lower surface of the second insulating pattern 140. The first word line WL1 may connect one portion of the upper surface of the first insulating pattern 120 and one portion of the lower surface of the second insulating pattern 140. The second word line WL2 may connect another portion of the upper surface of the first insulating pattern 120 and another portion of the lower surface of the second insulating pattern 140. In some embodiments, the first word line WL1 may contact a first portion of the upper surface of the first insulating pattern 120 and a first portion of the lower surface of the second insulating pattern 140. The second word line WL2 may contact a second portion of the upper surface of the first insulating pattern 120 and a second portion of the lower surface of the second insulating pattern 140. For example, the first word line WL1 and the second word line WL2 spaced apart from each other in the first direction DR1 may be disposed between the upper surface of the first insulating pattern 120 and the lower surface of the second insulating pattern 140.

[0049] The low-k material pattern 130 may be disposed in a space surrounded by an upper surface of the first insulating pattern 120, a lower surface of the second insulating pattern 140, and side surfaces of the first word line WL1 and the second word line WL2 facing each other. In some embodiments, a first gate insulating pattern Gox1 may be disposed between the low-k material pattern 130 and the first word line WL1, between the low-k material pattern 130 and the second word line WL2, and between the low-k material pattern 130 and the first insulating pattern 120.

[0050] The first gate insulating pattern Gox1 may include a first portion Gox1_P1 covering side surfaces of the first and second word lines WL1 and WL2 facing a channel pattern CP to be described later, and a second portion Gox1_P2 covering side surfaces of the first and second word lines WL1 and WL2 facing each other.

[0051] In some embodiments, a space between the second portion Gox1_P2 of the first gate insulation pattern Gox1 and the second insulation pattern 140 may be filled with a low-k material. The low-k material filled in the space between the second portion Gox1_P2 of the first gate insulation pattern Gox1 and the second insulation pattern 140 may be referred to as a low-k material pattern 130. The low-k material pattern 130 may be disposed on the second portion Gox1_P2 of the first gate insulation pattern Gox1, and the second insulation pattern 140 may be disposed on the low-k material pattern 130.

[0052] In some embodiments, the second insulating pattern 140 may cover upper surfaces of the first word line WL1, the second word line WL2, the first gate insulating pattern Gox1, and the low-k material pattern 130. A lower surface of the second insulating pattern 140 may be disposed at substantially the same level as upper surfaces of the first word line WL1, the second word line WL2, the first gate insulating pattern Gox1, and the low-k material pattern 130.

[0053] A structure including the above-mentioned first insulating pattern 120, a pair of word lines WL1 and WL2 set on the first insulating pattern 120, a first gate insulating pattern Gox1 covering side surfaces of the pair of word lines WL1 and WL2, and a second insulating pattern 140 covering upper surfaces of the pair of word lines WL1 and WL2 may be hereinafter referred to as a word line structure WLS.

[0054] The channel patterns CP may be disposed between the word line structures WLS adjacent to each other in the first direction DR1. A plurality of channel patterns CP may be alternately arranged with the plurality of word line structures WLS in the first direction DR1.

[0055] The channel pattern CP may cover the upper surface of the bit line BL exposed between the side surfaces facing each other and the adjacent word line structure WLS. The channel pattern CP may have a conformal shape. The channel pattern CP may cover the upper surface of the bit line BL and the side surfaces facing each other of the adjacent word line structure WLS with a predetermined thickness.

[0056] In a cross-sectional view taken along the first and third directions DR1 and DR3, the channel pattern CP may have an approximately "U" shape. Figure 3 The channel pattern CP may include a horizontal portion CP_H extending along an upper surface of the bit line BL in the first direction DR1 and a vertical portion CP_V extending along a side surface of the word line structure WLS adjacent to the horizontal portion CP_H.

[0057] The channel pattern CP may overlap the word line WL in the first direction DR1 but may not overlap the word line WL in the third direction DR3. The channel pattern CP may not be disposed between a lower surface of the word line WL and an upper surface of the bit line BL.

[0058] The second gate insulating pattern Gox2 may be disposed between the channel pattern CP and the side surface of the word line structure WLS. The second gate insulating pattern Gox2 may be disposed on the bit line BL exposed between adjacent word line structures WLS. The second gate insulating pattern Gox2 may extend from the upper surface of the bit line BL in the third direction DR3. The second gate insulating pattern Gox2 may extend in the third direction DR3 to cover the side surface of the word line structure WLS from the upper surface of the bit line BL.

[0059] The side surface of the word line structure WLS may include the side surface of the first insulating pattern 120, the side surface of the first gate insulating pattern Gox1, and the side surface of the second insulating pattern 140. The second gate insulating pattern Gox2 may extend in the third direction DR3 to cover the side surfaces of the first insulating pattern 120, the side surfaces of the first gate insulating pattern Gox1, and the side surfaces of the second insulating pattern 140.

[0060] In some embodiments, the upper surface of the second gate insulation pattern Gox2 may be disposed at substantially the same level as or higher than the upper surface of the first gate insulation pattern Gox1. The upper surface of the second gate insulation pattern Gox2 may be disposed at a lower level than the upper surface of the second insulation pattern 140.

[0061] The channel pattern CP may extend in a direction parallel to the substrate 100 to cover the upper surface of the bit line BL. The channel pattern CP may extend in a direction perpendicular to the substrate 100 to cover the side surface of the first insulating pattern 120, the side surface of the gate insulating pattern Gox, and the side surface of the second insulating pattern 140. In some embodiments, a vertical portion CP_V of the channel pattern CP may extend from the upper surface of the bit line BL to the side surface of the second gate insulating pattern Gox2. The channel pattern CP may extend in a third direction DR3 to cover the side surface of the first insulating pattern 120, the side surface of the first gate insulating pattern Gox1, and the side surface of the second insulating pattern 140, with the second gate insulating pattern Gox2 interposed therebetween. The upper surface of the vertical portion CP_V of the channel pattern CP may be disposed at a level higher than the upper surface of the second gate insulating pattern Gox2.

[0062] The channel pattern CP may be in contact with the upper surface of the bit line BL. The horizontal portion CP_H of the channel pattern CP may be in contact with the upper surface of the bit line BL. The channel pattern CP may be in contact with a landing pad LP to be described later. The vertical portion CP_V of the channel pattern CP may be in contact with the landing pad LP. The term "contact" or "in contact with..." used herein refers to direct connection (i.e., physical contact) unless the context indicates otherwise.

[0063] The channel pattern CP may include a first source / drain region and a second source / drain region. For example, a horizontal portion CP_H of the channel pattern CP may be connected to the bit line BL to serve as the first source / drain region, a vertical portion CP_V of the channel pattern CP may be connected to the landing pad LP to serve as the second source / drain region, and a portion of the channel pattern CP between the first source / drain region and the second source / drain region may serve as a channel region.

[0064] The channel pattern CP may include an oxide semiconductor material, or may be formed of an oxide semiconductor material. The oxide semiconductor material may be a combination of at least two or more of In, Ga, Zn, Al, Sn, and Hf, but is not limited thereto. The oxide semiconductor material may further include materials such as Si, Mg, Ta, La, Nd, Ce, Sc, Cr, Co, Nb, Mo, Ba, Gd, Ti, W, Pd, Ru, Ni, and Mn added to the above composition.

[0065] For example, the channel pattern CP may include indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc tin oxide (ZTO), zinc oxynitride (ZnON), zirconium zinc tin oxide (ZZTO), tin oxide (SnO), hafnium indium zinc oxide (HIZO), gallium zinc tin oxide (GZTO), aluminum zinc tin oxide (AZTO), ytterbium gallium zinc oxide (YGZO), indium gallium oxide (IGO), or a combination thereof, or may be formed of indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc tin oxide (ZTO), zinc oxynitride (ZnON), zirconium zinc tin oxide (ZZTO), tin oxide (SnO), hafnium indium zinc oxide (HIZO), gallium zinc tin oxide (GZTO), aluminum zinc tin oxide (AZTO), ytterbium gallium zinc oxide (YGZO), indium gallium oxide (IGO), or a combination thereof. However, the present disclosure is not limited thereto, and the oxide semiconductor material included in the channel pattern CP may be variously changed.

[0066] The third insulating pattern 150 may be disposed on the channel pattern CP. The third insulating pattern 150 may fill the inside of the space surrounded by the U-shaped channel pattern CP. The horizontal portion CP_H of the channel pattern CP may extend along the first direction DR1 between the bit line BL and the third insulating pattern 150. The vertical portion CP_V of the channel pattern CP may extend from the horizontal portion CP_H along the third direction DR3 between the third insulating pattern 150 and the word line WL.

[0067] The third insulating pattern 150 may extend in the second direction DR2. The third insulating pattern 150 may be arranged to be spaced apart from each other in the first direction DR1. Ordinal numbers such as "first", "second", "third", etc. may simply be used as labels for certain elements, steps, etc. to distinguish these elements, steps, etc. from each other. In the specification, terms that are not described using "first", "second", etc. may still be referred to as "first" or "second" in the claims. In addition, terms referenced with a specific ordinal number (e.g., "first" in a specific claim) may be described elsewhere with a different ordinal number (e.g., "second" in the specification or another claim).

[0068] The third insulating pattern 150 may include a material having an etching selectivity that is the same as or similar to that of the second gate insulating pattern Gox2, or may be formed of the material. For example, the third insulating pattern 150 may include at least one of a low-k material having a dielectric constant smaller than that of silicon oxide, silicon oxynitride, silicon nitride, or silicon oxide, or may be formed of at least one of the materials.

[0069] The upper surface of the third insulating pattern 150 adjacent to the vertical portion CP_V of the channel pattern CP may be disposed at a lower level than the upper surface of the vertical portion CP_V of the channel pattern CP. In some embodiments, the upper surface of the third insulating pattern 150 may be disposed at a level substantially equal to or higher than the upper surface of the second insulating pattern 140.

[0070] The landing pad LP may be connected to the channel pattern CP. The channel pattern CP may include at least three surfaces in contact with the landing pad LP. The landing pad LP may cover the upper surface of the channel pattern CP and the opposite side surfaces extending from the upper surface. Specifically, the landing pad LP may cover the upper surface of the vertical portion CP_V of the channel pattern CP and the opposite side surfaces extending from the upper surface. Figure 4 The described channel pattern CP may be a vertical portion CP_V of the channel pattern CP.

[0071] Reference Figure 4 The landing pad LP may include a first portion LP_P1 disposed between the third insulating pattern 150 and the channel pattern CP, a second portion LP_P2 disposed between the channel pattern CP and the second insulating pattern 140, and a connecting portion LP_C connecting the first portion LP_P1 to the second portion LP_P2 and covering an upper surface of the channel pattern CP.

[0072] The first portion LP_P1 and the second portion LP_P2 of the landing pad LP may respectively contact side surfaces of the channel pattern CP facing each other in the first direction DR1. The first portion LP_P1 of the landing pad LP may contact one side surface of the channel pattern CP, and the second portion LP_P2 of the landing pad LP may contact the other side surface of the channel pattern CP. The connection portion LP_C of the landing pad LP may connect the first portion LP_P1 to the second portion LP_P2. The connection portion LP_C of the landing pad LP may contact the upper surface of the channel pattern CP.

[0073] The first portion LP_P1 of the landing pad LP may protrude from the lower surface of the connection portion LP_C of the landing pad LP between the channel pattern CP and the third insulating pattern 150. The second portion LP_P2 of the landing pad LP may protrude from the lower surface of the connection portion LP_C of the landing pad LP between the channel pattern CP and the second insulating pattern 140. The lower surface of the connection portion LP_C of the landing pad LP may be disposed at substantially the same level as the upper surface of the channel pattern CP.

[0074] A lower surface of the first portion LP_P1 of the landing pad LP may contact the third insulating pattern 150. A lower surface of the second portion LP_P2 of the landing pad LP may contact the gate insulating pattern Gox. The second portion LP_P2 of the landing pad LP may contact the second gate insulating pattern Gox2. The second portion LP_P2 of the landing pad LP may cover an upper surface of the second gate insulating pattern Gox2.

[0075] although Figure 4 It is shown that the first portion LP_P1 of the landing pad LP and the second portion LP_P2 of the landing pad LP have substantially the same length in the third direction DR3, but the present disclosure is not limited thereto. For example, the length of the first portion LP_P1 in the third direction DR3 may be longer than the length of the second portion LP_P2 in the third direction DR3. The height of the upper surface of the third insulating pattern 150 adjacent to the channel pattern CP may be lower than the height of the upper surface of the second gate insulating pattern Gox2.

[0076] The landing pad LP may extend higher than the upper surface of the third insulating pattern 150. The width of the upper surface of the landing pad LP (the length in the first direction DR1) may be greater than the width of the landing pad LP between the second insulating pattern 140 and the third insulating pattern 150. However, the present disclosure is not limited thereto, and for example, the width of the upper surface of the landing pad LP (the length in the first direction DR1) may be substantially the same as the width of the landing pad LP between the second insulating pattern 140 and the third insulating pattern 150.

[0077] Figures 1 to 3 It is illustrated that the connection portion LP_C of the landing pad LP does not extend higher than the upper surface of the second insulating pattern 140 , but the present disclosure is not limited thereto.

[0078] The landing pad LP may include doped polysilicon, metal, conductive metal nitride, conductive metal oxide, or a combination thereof, or may be formed of doped polysilicon, metal, conductive metal nitride, conductive metal oxide, or a combination thereof. For example, the landing pad LP may include Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, or may be formed of Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but is not limited thereto.

[0079] The interlayer insulating layer 160 may fill the space between the landing pads LP spaced apart from each other in the first direction DR1 on the second and third insulating patterns 140 and 150. For example, the lower surface of the interlayer insulating layer 160 may be disposed at substantially the same level as the lower surface of a portion of the landing pad LP extending higher than the upper surface of the third insulating pattern 150, but is not limited thereto.

[0080] The data storage patterns DSP may be disposed on the landing pads LP, respectively. The data storage patterns DSP may be electrically connected to the channel patterns CP through the landing pads LP, respectively. Figure 1 As shown, the data storage patterns DSP may be arranged in a matrix form along the first direction DR1 and the second direction DR2.

[0081] In some embodiments, the data storage pattern DSP may be a capacitor and may include a lower electrode and an upper electrode and a capacitor dielectric film interposed therebetween. When the data storage pattern DSP is a capacitor, the lower electrode may contact the landing pad LP, and the lower electrode may have various shapes in a plan view, such as a circular, oval, rectangular, square, diamond, and hexagonal shape.

[0082] Alternatively, the data storage pattern DSP may be a variable resistance pattern that can be switched into two resistance states by an electric pulse applied to the memory element. For example, the data storage pattern DSP may include a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material whose crystal state changes depending on the amount of current.

[0083] A semiconductor device according to some embodiments may include a second gate insulating pattern Gox2 disposed between the first gate insulating pattern Gox1 and the channel pattern CP. Since the first gate insulating pattern Gox1 and the channel pattern CP do not directly contact each other through the second gate insulating pattern Gox2, reliability of an interface between the channel pattern CP and the gate insulating pattern Gox may be improved.

[0084] According to some embodiments, a semiconductor device includes an Al 2 O 3 Or by Al 2 O 3 The first gate insulating pattern Gox1 formed includes SiO 2 Or by SiO 2 The second gate insulating pattern Gox2 is formed, thereby reducing the interface trap density and leakage current of the channel pattern CP to improve reliability.

[0085] A semiconductor device according to some embodiments may include a channel pattern CP and a landing pad LP, at least three surfaces of which are in contact with each other. According to a comparative example, the landing pad LP may contact only the upper surface of the channel pattern CP. According to some embodiments, the landing pad LP may cover the upper surface of the channel pattern CP and the opposite side surfaces extending from the upper surface. Therefore, the contact area between the channel pattern CP and the landing pad LP is increased, so that the contact resistance can be reduced and the operating characteristics of the semiconductor device can be improved.

[0086] In the following, reference will be made to Figures 5 to 10 Semiconductor devices according to some embodiments are described. In the following embodiments, the same components as those in the above-described embodiments are denoted by the same reference numerals, repeated descriptions are omitted or simplified, and differences are mainly explained.

[0087] Figures 5 to 10 A cross-sectional view of a semiconductor device according to some embodiments is shown. Figure 5 , Figure 6 , Figure 7 , Figure 8 and Fig.10 Shown with Figure 2 An enlarged view of the area corresponding to "P1". Fig. 9 Shows Figure 8 Magnified view of “P3” in .

[0088] Reference Figure 5 ,and Figures 1 to 4According to some embodiments, the air gap 130A may be disposed in a space surrounded by an upper surface of the first insulating pattern 120, a lower surface of the second insulating pattern 140, and side surfaces of the first word line WL1 and the second word line WL2 facing each other. According to some embodiments, the air gap 130A may be disposed in a space between the second portion Gox1_P2 of the first gate insulating pattern Gox1 and the second insulating pattern 140. The air gap 130A may be disposed on the second portion Gox1_P2 of the first gate insulating pattern Gox1, and the second insulating pattern 140 may be disposed on the air gap 130A.

[0089] The first gate insulating pattern Gox1 may be disposed between the air gap 130A and the first word line WL1 , between the air gap 130A and the second word line WL2 , and between the air gap 130A and the first insulating pattern 120 .

[0090] exist Figure 5 In, only Figures 1 to 4 The low-k material pattern 130 is changed into an air gap 130A, and the remaining components may be the same.

[0091] exist Figure 6 In, with Figures 1 to 4 Unlike the embodiment of the present invention, the first gate insulating pattern Gox1 may cover only the side surface facing the channel pattern CP among the opposite side surfaces of the first word line WL1 and the second word line WL2. Figure 6 In the embodiment, the first gate insulating pattern Gox1 may include only Figures 1 to 4 The first gate insulating pattern Gox1 may not include a first portion Gox1_P1. Figures 1 to 4 The second part of Gox1_P2.

[0092] According to some embodiments, a space defined by an upper surface of the first insulating pattern 120, a lower surface of the second insulating pattern 140, and side surfaces of the first and second word lines WL1 and WL2 facing each other may be filled with a low-k material. Figure 6 In an embodiment of the present invention, the low-k material filled in a space surrounded by the upper surface of the first insulating pattern 120, the lower surface of the second insulating pattern 140, and the side surfaces of the first word line WL1 and the second word line WL2 facing each other may be referred to as a low-k material pattern 130. The low-k material pattern 130 may be in contact with the side surfaces of the first word line WL1 and the second word line WL2 facing each other. The low-k material pattern 130 may be in contact with the upper surface of the first insulating pattern 120.

[0093] exist Figure 6 In the implementation mode, only Figures 1 to 4 The structure of the first gate insulating pattern Gox1 of the embodiment is partially changed, and the remaining components may be the same.

[0094] exist Figure 7 In, with Figures 1 to 4 Unlike the embodiment of the present invention, the first gate insulating pattern Gox1 may cover only the side surface facing the channel pattern CP among the opposite side surfaces of the first word line WL1 and the second word line WL2. Figure 7 In an embodiment, the first gate insulating pattern Gox1 may include only Figures 1 to 4 The first part of Gox1_P1. Figure 7 In the embodiment, the first gate insulating pattern Gox1 may not include Figures 1 to 4 The second part of Gox1_P2.

[0095] According to some embodiments, the air gap 130A may be disposed in a space defined by an upper surface of the first insulating pattern 120, a lower surface of the second insulating pattern 140, and side surfaces of the first word line WL1 and the second word line WL2 facing each other. The air gap 130A may be disposed in a space surrounded by an upper surface of the first insulating pattern 120, a lower surface of the second insulating pattern 140, and side surfaces of the first word line WL1 and the second word line WL2 facing each other.

[0096] exist Figure 7 In the implementation mode, only Figure 6 The low-k material pattern 130 of the embodiment of FIG. 1 is changed to an air gap 130A, and the remaining components may be the same.

[0097] Reference Figure 8 and Fig. 9 , the first insulating pattern 120 may be disposed on the bit line BL extending in the first direction DR1. The first insulating pattern 120 may extend in a second direction DR2 crossing the first direction DR1. A pair of word lines WL1 and WL2 extending in the second direction DR2 may be disposed on the first insulating pattern 120. The first word line WL1 and the second word line WL2 may be disposed to be spaced apart from each other in the first direction DR1 on the first insulating pattern 120. One side surface of the first word line WL and one side surface of the second word line WL2 may face each other in the first direction DR1.

[0098] The gate insulating pattern Gox may be disposed on the side surface of the first word line WL1 and the side surface of the second word line WL2. The gate insulating pattern Gox may include a first portion Gox_P1 disposed on the side surface of the first word line WL1 and the second word line WL2 facing the channel pattern CP, and a second portion Gox_P2 disposed on the side surfaces of the first word line WL1 and the second word line WL2 facing each other. The first portion Gox_P1 may be disposed between the first word line WL1 and the channel pattern CP and between the second word line WL2 and the channel pattern CP. The second portion Gox_P2 may be disposed between the first word line WL1 and the second word line WL2.

[0099] The first portion Gox_P1 may cover the side surfaces of the first word line WL1 and the second word line WL2 facing the channel pattern CP. The second portion Gox_P2 may cover the side surfaces of the first word line WL1 and the second word line WL2 facing each other and the upper surface of the first insulating pattern 120 exposed between the first word line WL1 and the second word line WL2. The second portion Gox_P2 may conformally cover the side surfaces of the first word line WL1 and the second word line WL2 facing each other and the upper surface of the first insulating pattern 120 exposed between the side surfaces.

[0100] For example, the gate insulating pattern Gox may be Al 2 O 3 , but not limited to this.

[0101] The upper surface of the gate insulating pattern Gox may be disposed at the same level as the upper surfaces of the first word line WL1 and the second word line WL2. The low-k material pattern 130 may be disposed on the second portion Gox_P2 of the gate insulating pattern Gox. The low-k material pattern 130 may be disposed on the second portion Gox_P2 of the gate insulating pattern Gox, and the second insulating pattern 140 may be disposed on the low-k material pattern 130. The low-k material pattern 130 may be a low-k material filled in the space between the second portion Gox_P2 of the gate insulating pattern Gox and the second insulating pattern 140. The upper surface of the low-k material pattern 130 may be disposed at the same level as the upper surfaces of the first word line WL1 and the second word line WL2.

[0102] The second insulating pattern 140 may be disposed on upper surfaces of the first and second word lines WL1 and WL2, an upper surface of the gate insulating pattern Gox, and an upper surface of the low-k material pattern 130. The second insulating pattern 140 may cover upper surfaces of the first and second word lines WL1 and WL2, an upper surface of the gate insulating pattern Gox, and an upper surface of the low-k material pattern 130, and may extend in the second direction DR2.

[0103] The first word line WL1 and the second word line WL2 may be disposed between the upper surface of the first insulating pattern 120 and the lower surface of the second insulating pattern 140. The first word line WL1 may connect one portion of the upper surface of the first insulating pattern 120 and one portion of the lower surface of the second insulating pattern 140. The second word line WL2 may connect another portion of the upper surface of the first insulating pattern 120 and another portion of the lower surface of the second insulating pattern 140.

[0104] The low-k material pattern 130 may be disposed in a space surrounded by an upper surface of the first insulating pattern 120, a lower surface of the second insulating pattern 140, and side surfaces of the first word line WL1 and the second word line WL2 facing each other. The second portion Gox_P2 of the gate insulating pattern Gox may be disposed between the low-k material pattern 130 and the first word line WL1, between the low-k material pattern 130 and the second word line WL2, and between the low-k material pattern 130 and the first insulating pattern 120.

[0105] A structure including the above-mentioned first insulating pattern 120, a pair of word lines WL1 and WL2 set on the first insulating pattern 120, a gate insulating pattern Gox covering side surfaces of the pair of word lines WL1 and WL2, and a second insulating pattern 140 covering upper surfaces of the pair of word lines WL1 and WL2 may be referred to as a word line structure WLS hereinafter.

[0106] The channel pattern CP may be disposed on the side surface and the upper surface of the word line structure WLS. Figure 8 and Fig. 9 In the embodiment shown, Figures 1 to 4 Unlike the illustrated embodiment, the channel pattern CP may be directly disposed on (ie, contacting) a side surface of the word line structure WLS.

[0107] Each word line structure WLS may extend in the second direction DR2. The word line structures WLS may be disposed to be spaced apart from each other in the first direction DR1. A channel pattern CP may be disposed between adjacent word line structures WLS.

[0108] The horizontal portion CP_H of the channel pattern CP may cover the upper surface of the bit line BL between the adjacent word line structures WLS. The horizontal portion CP_H of the channel pattern CP may contact the bit line BL and may be electrically connected to the bit line BL. The vertical portion CP_V of the channel pattern CP may extend from the upper surface of the bit line BL in the third direction DR3 along the side surface of the word line structure WLS. The vertical portion CP_V of the channel pattern CP may extend from the upper surface of the bit line BL in the third direction DR3 to cover the side surface of the first insulating pattern 120, the side surface of the first portion Gox_P1 of the gate insulating pattern Gox, and the side surface of the second insulating pattern 140. The vertical portion CP_V of the channel pattern CP may be spaced apart from the first word line WL1 and the second word line WL2 by the first portion Gox_P1 of the gate insulating pattern Gox.

[0109] exist Figure 8 and Fig. 9 In the embodiment shown, Figures 1 to 4Unlike the embodiment shown, the vertical portion CP_V of the channel pattern CP may be disposed directly above the side surfaces of the first insulating pattern 120 and the second insulating pattern 140. The gate insulating pattern Gox disposed between the vertical portion CP_V of the channel pattern CP and the word line WL may include one type of material. Figure 8 and Fig. 9 In the embodiment shown, only Al 2 O 3 The gate insulation pattern ( Figures 1 to 4 A first gate insulating pattern Gox1) may exist between the vertical portion CP_V of the channel pattern CP and the word line WL, including SiO 2 The gate insulation pattern ( Figures 1 to 4 The second gate insulation pattern Gox2) may not exist. Figure 8 and Fig. 9 In the embodiment shown in the figure, the vertical portion CP_V of the channel pattern CP may be directly disposed on the Al 2 O 3 The gate insulation pattern ( Figures 1 to 4 The first gate insulation pattern Gox1) is on (ie, contacts the gate insulation pattern).

[0110] exist Figure 8 and Fig. 9 In the embodiment shown, Figures 1 to 4 Unlike the embodiment shown, the channel pattern CP may be further extended to cover the upper surface of the word line structure WLS. The channel pattern CP may be further extended to cover the upper surface of the second insulating pattern 140. The channel pattern CP may cover a portion of the upper surface of the second insulating pattern 140 adjacent to the side surface of the second insulating pattern 140. The upper surface of the channel pattern CP may be disposed at a higher level than the upper surface of the second insulating pattern 140.

[0111] The channel pattern CP may have a conformal shape and may conformally cover an upper surface of the bit line BL, a side surface of the first insulating pattern 120 , a side surface of the first portion Gox_P1 of the gate insulating pattern Gox, and a side surface and an upper surface of the second insulating pattern 140 .

[0112] In some embodiments, the channel pattern CP may include or may be formed of an oxide semiconductor such as IGZO, but is not limited thereto.

[0113] The third insulating pattern 150 may be disposed on the channel pattern CP. The third insulating pattern 150 may be disposed between adjacent word line structures WLS. A lower surface and opposite side surfaces of the third insulating pattern 150 between adjacent word line structures WLS may be surrounded by the channel pattern CP.

[0114] exist Figure 8 and Fig. 9 In some of the embodiments shown, Figures 1 to 4 Unlike the illustrated embodiment, a third insulating pattern 150 may be further disposed on the word line structure WLS. The third insulating pattern 150 may be further disposed on the second insulating pattern 140. The third insulating pattern 150 may be disposed on an upper surface of the second insulating pattern 140.

[0115] In some embodiments, the third insulating pattern 150 may include or may be formed of an insulating material having an etch selectivity with respect to the second insulating pattern 140 .

[0116] The landing pad LP may be connected to the channel pattern CP. Figure 8 and Fig. 9 In the embodiment shown, as in Figures 1 to 4 As in the illustrated embodiment, the landing pad LP may contact at least three surfaces of the channel pattern CP. The landing pad LP includes a first portion LP_P1 and a second portion LP_P2 respectively contacting side surfaces of the channel pattern CP facing each other in the first direction DR1, and a connection portion LP_C contacting an upper surface of the channel pattern CP. The connection portion LP_C may connect the first portion LP_P1 to the second portion LP_P2.

[0117] according to Figure 8 and Fig. 9 In some embodiments shown, the first portion LP_P1 and the second portion LP_P2 of the landing pad LP may be disposed between the third insulating pattern 150 and the channel pattern CP. The connection portion LP_C of the landing pad LP may connect the first portion LP_P1 and the second portion LP_P2 to cover the upper surface of the channel pattern CP. The lower surface of the connection portion LP_C of the landing pad LP may be disposed at substantially the same level as the upper surface of the channel pattern CP.

[0118] The first portion LP_P1 of the landing pad LP may protrude from a lower surface of the connection portion LP_C of the landing pad LP between a portion of the third insulating pattern 150 disposed between adjacent word line structures WLS and the channel pattern CP.

[0119] exist Figure 8 and Fig. 9 In the embodiment shown, Figures 1 to 4Unlike the illustrated embodiment, the second portion LP_P2 of the landing pad LP may protrude between the third insulating pattern 150 disposed on the word line structure WLS and the channel pattern CP. The lower surface of the second portion LP_P2 of the landing pad LP may contact the second insulating pattern 140. The lower surface of the second portion LP_P2 of the landing pad LP may contact the upper surface of the second insulating pattern 140.

[0120] Figure 8 and Fig. 9 It is shown that the length of the first portion LP_P1 of the landing pad LP in the third direction DR3 is longer than the length of the second portion LP_P2 of the landing pad LP in the third direction DR3, but the present disclosure is not limited thereto. For example, the length of the first portion LP_P1 in the third direction DR3 may be substantially the same as or shorter than the length of the second portion LP_P2 in the third direction DR3.

[0121] Figure 8 and Fig. 9 The width (e.g., length in the first direction DR1) of the connection portion LP_C of the landing pad LP is shown to be constant, but the present disclosure is not limited thereto. For example, the landing pad LP may extend higher than the uppermost surface of the third insulating pattern 150, so that the width of the upper surface of the connection portion LP_C of the landing pad LP may be greater than the width of the connection portion LP_C of the landing pad LP between the third insulating patterns 150.

[0122] The landing pads LP may be disposed to be spaced apart from each other in the first direction DR1. Although not shown, the landing pads LP may be disposed to be spaced apart from each other in the second direction DR2. The interlayer insulating layer 160 may fill the space between the landing pads LP on the third insulating pattern 150.

[0123] exist Fig.10 In the implementation mode, only Figure 8 and Fig. 9 The low-k material pattern 130 of the embodiment of FIG. 1 is changed to an air gap 130A, and the remaining components may be the same.

[0124] Reference Fig.10 ,and Figure 8 and Fig. 9According to some embodiments, the air gap 130A may be disposed in a space surrounded by an upper surface of the first insulating pattern 120, a lower surface of the second insulating pattern 140, and side surfaces of the first word line WL1 and the second word line WL2 facing each other. According to some embodiments, the air gap 130A may be disposed in a space between the second portion Gox_P2 of the gate insulating pattern Gox and the second insulating pattern 140. The air gap 130A may be disposed on the second portion Gox_P2 of the gate insulating pattern Gox, and the second insulating pattern 140 may be disposed on the air gap 130A.

[0125] The gate insulating pattern Gox may be disposed between the air gap 130A and the first word line WL1 , between the air gap 130A and the second word line WL2 , and between the air gap 130A and the first insulating pattern 120 .

[0126] and Figures 1 to 4 The same as the embodiment shown, according to Figures 8 to 10 The semiconductor device of the embodiment includes a channel pattern CP and a landing pad LP in contact with at least three surfaces, and the landing pad LP can cover the upper surface of the channel pattern CP and the opposite side surfaces extending from the upper surface. Therefore, the contact area between the channel pattern CP and the landing pad LP is increased, so that the contact resistance can be reduced, and the operating characteristics of the semiconductor device can be improved.

[0127] In the following, reference will be made to Figures 11 to 25 Description of manufacturing basis Figures 1 to 4 A method for a semiconductor device according to an embodiment of the present invention is provided. Figures 11 to 25 For convenience, the Figures 1 to 4 The core and peripheral circuits SA may be provided between the substrate 100 and the lower insulating layer 110 .

[0128] Figures 11 to 25 A cross-sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments is shown.

[0129] Reference Fig.11 , a bit line BL may be formed on the lower insulating layer 110 .

[0130] The lower insulating layer 110 may include a multilayer insulating film. For example, the lower insulating layer 110 may include or be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and / or a low dielectric film.

[0131] The bit lines BL may extend in a first direction DR1 and may be disposed to be spaced apart from each other in a second direction DR2 crossing the first direction DR1. For example, the second direction DR2 may be a direction perpendicular to the first direction DR1. The bit lines BL may be formed by depositing a conductive layer on the lower insulating layer 110 and then patterning the conductive layer.

[0132] Although not shown, an insulating material may fill the space between the bit lines BL, and may include or may be the same insulating material as the lower insulating layer 110, but is not limited thereto. When the insulating material filling the space between the bit lines BL includes or is the same insulating material as the lower insulating layer 110, the insulating material may be integrated with the lower insulating layer 110. For example, the upper surface of the lower insulating layer 110 and the upper surface of the bit lines BL may be disposed at substantially the same level.

[0133] Reference Fig.12 , a first insulating pattern material layer 120_L may be formed on the bit line BL and the lower insulating layer 110. The first insulating pattern material layer 120_L may be formed using at least one of physical vapor deposition (PVD), thermal chemical vapor deposition (thermal CVD), low pressure chemical vapor deposition (LP-CVD), plasma enhanced chemical vapor deposition (PE-CVD), and atomic layer deposition (ALD) techniques. However, the method of depositing the first insulating pattern material layer 120_L is not limited thereto and may be variously changed.

[0134] The first insulating pattern material layer 120_L may include at least one of silicon oxide, silicon oxynitride, silicon nitride, and a low-k material having a dielectric constant lower than that of silicon oxide, or may be formed of at least one of silicon oxide, silicon oxynitride, silicon nitride, and a low-k material having a dielectric constant lower than that of silicon oxide, but is not limited thereto.

[0135] Reference Fig.13 , a word line material layer WL_L may be formed. The word line material layer WL_L may be deposited by CVD, PVD or ALD process, but is not limited thereto.

[0136] The word line material layer WL_L may include or be formed of doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or a combination thereof.

[0137] Reference Fig.14, the first word line WL1 and the second word line WL2 may be formed by patterning the word line material layer WL_L. The first word line WL1 and the second word line WL2 may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The first word line WL1 and the second word line WL2 may be alternately disposed.

[0138] Next, a first gate insulating pattern material layer Gox1_L may be formed to conformally cover the first and second word lines WL1 and WL2 . The first gate insulating pattern material layer Gox1_L may be deposited by a CVD, PVD, or ALD process, but is not limited thereto.

[0139] The first gate insulating pattern material layer Gox1_L may include or be formed of silicon oxide, silicon oxynitride, a high-k material having a higher dielectric constant than silicon oxide, or a combination thereof. The high-k material may include metal oxide or metal oxynitride.

[0140] In some embodiments, the first gate insulating pattern material layer Gox1_L may include Al 2 O 3 Or it can be done by Al 2 O 3 form.

[0141] In some embodiments, Fig.14 After forming the first gate insulating pattern material layer Gox1_L in the process of forming the first gate insulating pattern material layer Gox1_L, patterning may be further performed to remove a portion of the first gate insulating pattern material layer Gox1_L disposed between the side surfaces of the pair of first word lines WL1 and second word lines WL2 facing each other. Subsequently, by performing subsequent processes, a Figure 6 A semiconductor device according to the embodiment shown.

[0142] Reference Fig.15 , a preliminary first gate insulation pattern Gox1_P and a preliminary low-k material pattern 130_P may be formed.

[0143] First, a low-k material layer may be deposited to a thickness covering the upper surface of the first gate insulating pattern material layer Gox1_L. The low-k material layer may be deposited by CVD, PVD or ALD processes, but is not limited thereto. The low-k material layer may include a low-k material. The low-k material may include, for example, a flowable oxide (FOX), a toner silazane (TOSZ), an undoped silicate glass (USG), a borosilicate glass (BSG), a phosphosilicate glass (PSG), a borophosphosilicate glass (BPSG), a plasma enhanced tetraethyl orthosilicate (PETEOS), a fluoride silicate glass (FSG), a carbon-doped silicon oxide (CDO), a dry gel, an aerogel, amorphous fluorinated carbon, an organic silicate glass (OSG), polyparaxylene, bibenzocyclobutene (BCB), SiLK, a polyimide, a porous polymer material and at least one of a polymer material of a combination thereof, but is not limited thereto.

[0144] Next, upper surfaces of the first gate insulation pattern material layer Gox1_L and the low-k material layer may be polished by a chemical mechanical polishing (CMP) process to form a preliminary first gate insulation pattern Gox1_P and a preliminary low-k material pattern 130_P.

[0145] The preliminary low-k material pattern 130_P may be disposed between side surfaces of the first and second word lines WL1 and WL2 and may be spaced apart from side surfaces of the first and second word lines WL1 and WL2 by the preliminary first gate insulating pattern Gox1_P.

[0146] The preliminary low-k material pattern 130_P may be disposed on the first insulating pattern material layer 120_L. The preliminary low-k material pattern 130_P may be spaced apart from an upper surface of the first insulating pattern material layer 120_L by the preliminary first gate insulating pattern Gox1_P.

[0147] The preliminary low-k material pattern 130_P may be disposed on the preliminary first gate insulating pattern Gox1_P.

[0148] Reference Fig.16 , a second insulating pattern material layer 140_L may be formed on the first word line WL1 and the second word line WL2. The second insulating pattern material layer 140_L may be deposited by a CVD, PVD, or ALD process, but is not limited thereto.

[0149] The second insulating pattern material layer 140_L may include at least one of silicon oxide, silicon oxynitride, silicon nitride, and a low-k material having a dielectric constant lower than that of silicon oxide, or may be formed of at least one of silicon oxide, silicon oxynitride, silicon nitride, and a low-k material having a dielectric constant lower than that of silicon oxide, but is not limited thereto.

[0150] The second insulating pattern material layer 140_L may cover the upper surfaces of the first word line WL1 and the second word line WL2. The second insulating pattern material layer 140_L may cover the upper surface of the preliminary first gate insulating pattern Gox1_P (which covers the side surfaces of the first word line WL1 and the second word line WL2). The second insulating pattern material layer 140_L may cover the upper surface of the preliminary low-k material pattern 130_P.

[0151] Reference Fig.17 , a word line structure WLS including a first insulating pattern 120 , a first word line WL1 , a second word line WL2 , a first gate insulating pattern Gox1 , a low-k material pattern 130 , and a second insulating pattern 140 may be formed.

[0152] The word line structure WLS may be formed by patterning the first insulating pattern material layer 120_L, the preliminary first gate insulating pattern Gox1_P, the preliminary low-k material pattern 130_P, and the second insulating pattern material layer 140_L. The word line structures WLS may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1.

[0153] The first word line WL1 and the second word line WL2 may be disposed between the upper surface of the first insulating pattern 120 and the lower surface of the second insulating pattern 140. The first word line WL1 may connect a portion of the upper surface of the first insulating pattern 120 and a portion of the lower surface of the second insulating pattern 140. The second word line WL2 may connect another portion of the upper surface of the first insulating pattern 120 and another portion of the lower surface of the second insulating pattern 140. The first word line WL1 and the second word line WL2 may be disposed to be spaced apart from each other in the first direction DR1 between the upper surface of the first insulating pattern 120 and the lower surface of the second insulating pattern 140.

[0154] The first gate insulating pattern Gox1 may cover side surfaces of the first word line WL1 and the second word line WL2. The first gate insulating pattern Gox1 may include a first portion Gox1_P1 covering side surfaces of the first word line WL1 and the second word line WL2 facing the outside of the word line structure WLS, and a second portion Gox1_P2 covering side surfaces of the first word line WL1 and the second word line WL2 facing the inside of the word line structure WLS.

[0155] The first portion Gox1_P1 of the first gate insulating pattern Gox1 may form opposite side surfaces of the word line structure WLS. The second portion Gox1_P2 of the first gate insulating pattern Gox1 may cover side surfaces of the first word line WL1 and the second word line WL2 facing each other. The second portion Gox1_P2 of the first gate insulating pattern Gox1 may cover an upper surface of the first insulating pattern 120 exposed between side surfaces of the first word line WL1 and the second word line WL2 facing each other.

[0156] The low-k material pattern 130 may be disposed in a space surrounded by an upper surface of the first insulating pattern 120, a lower surface of the second insulating pattern 140, and side surfaces of the first word line WL1 and the second word line WL2 facing each other. The second portion Gox1_P2 of the first gate insulating pattern Gox1 may be disposed between the side surfaces of the first word line WL1 and the second word line WL2 facing each other and the low-k material pattern 130 and between an upper surface of the first insulating pattern 120 and the low-k material pattern 130. In other words, the low-k material pattern 130 may fill a space between the second portion Gox1_P2 of the first gate insulating pattern Gox1 and the second insulating pattern 140.

[0157] In some embodiments, a spin-on hard mask (SOH) layer may be deposited instead of Figures 15 to 17 The process of low-k material layer and can be performed in Figures 15 to 17 After the process of removing the spin-on hard mask layer by an ashing process, an air gap is formed instead of the low-k material pattern 130. Then, by performing subsequent processes, a Figure 5 A semiconductor device according to the embodiment shown.

[0158] Reference Fig.18 , a second gate insulating pattern material layer Gox2_L conformally covering the word line structure WLS may be formed. The second gate insulating pattern material layer Gox2_L may be deposited by a CVD, PVD or ALD process, but is not limited thereto.

[0159] The second gate insulating pattern material layer Gox2_L may include or be formed of silicon oxide, silicon oxynitride, a high-k material having a higher dielectric constant than silicon oxide, or a combination thereof. The high-k material may include metal oxide or metal oxynitride.

[0160] According to some embodiments, the second gate insulating pattern material layer Gox2_L may include a material of a different type from that of the first gate insulating pattern Gox1. For example, the second gate insulating pattern material layer Gox2_L may include SiO 2 Or it can be made of SiO 2form.

[0161] The second gate insulating pattern material layer Gox2_L may cover the upper surface and side surfaces of the word line structure WLS. The second gate insulating pattern material layer Gox2_L may cover the upper surface of the bit line BL exposed between the upper surface of the lower insulating layer 110 and the word line structure WLS.

[0162] Reference Fig.19 , a preliminary second gate insulation pattern Gox2_P may be formed by partially etching the second gate insulation pattern material layer Gox2_L. For example, a portion of the second gate insulation pattern material layer Gox2_L disposed on the upper surface of the word line structure WLS and a portion of the second gate insulation pattern material layer Gox2_L disposed on the upper surface of the bit line BL and the upper surface of the lower insulation layer 110 may be removed by an anisotropic etching process. The preliminary second gate insulation pattern Gox2_P may remain only on the side surface of the word line structure WLS. The preliminary second gate insulation pattern Gox2_P may extend along the second direction DR2 on the side surface of the word line structure WLS.

[0163] The preliminary second gate insulation pattern Gox2_P may extend from the upper surface of the bit line BL in the third direction DR3. The preliminary second gate insulation pattern Gox2_P may extend in the third direction DR3 to cover the side surface of the word line structure WLS. The side surface of the word line structure WLS may include the side surface of the first insulation pattern 120, the side surface of the first portion Gox1_P1 of the first gate insulation pattern Gox1, and the side surface of the second insulation pattern 140. The preliminary second gate insulation pattern Gox2_P may cover the side surface of the first insulation pattern 120, the side surface of the first portion Gox1_P1 of the first gate insulation pattern Gox1, and the side surface of the second insulation pattern 140.

[0164] An upper surface of the preliminary second gate insulation pattern Gox2_P may be disposed at the same level as or at a lower level than an upper surface of the second insulation pattern 140 .

[0165] like Fig.19 As shown, the upper surface of the preliminary second gate insulation pattern Gox2_P may be disposed at a higher level than the upper surface of the first gate insulation pattern Gox1, but is not limited thereto. In some embodiments, the upper surface of the preliminary second gate insulation pattern Gox2_P may be disposed at the same level as the upper surface of the first gate insulation pattern Gox1.

[0166] Reference Fig. 20A channel pattern material layer CP_L conformally covering the word line structure WLS in which the preliminary second gate insulating pattern Gox2_P is formed may be formed on opposite side surfaces of each word line structure WLS. The channel pattern material layer CP_L may be deposited by CVD, PVD or ALD processes, but is not limited thereto.

[0167] In some embodiments, the channel pattern material layer CP_L may include an oxide semiconductor material or may be formed of an oxide semiconductor material. The oxide semiconductor material may include at least two or more of In, Ga, Zn, Al, Sn, and Hf, and the component may further include materials such as Si, Mg, Ta, La, Nd, Ce, Sc, Cr, Co, Nb, Mo, Ba, Gd, Ti, W, Pd, Ru, Ni, Mn, etc. For example, the oxide semiconductor material may include or may be IGZO.

[0168] For example, the channel pattern material layer CP_L may include IGZO or may be formed of IGZO.

[0169] The channel pattern material layer CP_L may cover the upper surface of the word line structure WLS. The channel pattern material layer CP_L may cover the side surface of the word line structure WLS. The channel pattern material layer CP_L may cover the upper surface and side surface of the preliminary second gate insulation pattern Gox2_P. The channel pattern material layer CP_L may cover the upper surface of the bit line BL exposed between the upper surface of the lower insulation layer 110 and the adjacent word line structure WLS.

[0170] Reference Fig.21 , the channel pattern material layer CP_L and the preliminary second gate insulation pattern Gox2_P may be patterned to form the channel pattern CP and the second gate insulation pattern Gox2.

[0171] First, the upper portion of the channel pattern material layer CP_L may be removed by an etch-back process. For example, a portion of the channel pattern material layer CP_L covering the upper surface of the word line structure WLS and the upper surface of the preliminary second gate insulation pattern Gox2_P may be removed. For example, the upper surface of the channel pattern material layer CP_L may be etched until it is disposed at the same level as the upper surface of the preliminary second gate insulation pattern Gox2_P.

[0172] Subsequently, although not shown in the cross-sectional views taken along the first direction DR1 and the third direction DR3, the remaining channel pattern material layer CP_L and the preliminary second gate insulation pattern Gox2_P may be cut at regular intervals along the second direction DR2. Therefore, a plurality of channel patterns CP and a plurality of second gate insulation patterns Gox2_P may be disposed to be spaced apart from each other in the first direction DR1, and may also be disposed to be spaced apart from each other in the second direction DR2.

[0173] The second gate insulating pattern Gox2 may extend from the upper surface of the bit line BL in the third direction DR3 to cover side surfaces of the first insulating pattern 120 , the first portion Gox1_P1 of the first gate insulating pattern Gox1 , and the second insulating pattern 140 .

[0174] The channel pattern CP may be spaced apart from a side surface of the word line structure WLS by the second gate insulating pattern Gox2 . The channel pattern CP may be spaced apart from the word line WL by the second gate insulating pattern Gox2 and the first portion Gox1_P1 of the first gate insulating pattern Gox1 .

[0175] The channel pattern CP may conformally cover side surfaces of the second gate insulating pattern Gox2 disposed on side surfaces of adjacent word line structures WLS facing each other and upper surfaces of the bit lines BL exposed between the adjacent word line structures WLS. Portions of the channel pattern CP covering the side surfaces of the word line structures WLS (e.g., Figure 3 The vertical portion CP_V of the channel pattern CP may extend in the third direction DR3. The portion of the channel pattern CP covering the upper surface of the bit line BL (eg, Figure 3 The horizontal portion CP_H) of the channel pattern CP may extend in the first direction DR1. In a cross-sectional view taken along the first direction DR1 and the third direction DR3, the channel pattern CP may have an approximately “U” shape.

[0176] Subsequently, a third insulating pattern 150 may be formed on the channel pattern CP. For example, after the third insulating pattern material layer is deposited to a thickness covering the upper surface of the second insulating pattern 140, the third insulating pattern material layer may be polished by a CMP process to form the third insulating pattern 150. Fig.21 As shown, the upper surface of the third insulating pattern 150 may be disposed at substantially the same level as the upper surface of the second insulating pattern 140, but is not limited thereto. When the upper surface of the third insulating pattern 150 is disposed at the same level as or at a lower level than the upper surface of the second insulating pattern 140, the third insulating patterns 150 may be spaced apart from each other in the first direction DR1. For example, the third insulating pattern 150 may be disposed in a space between word line structures WLS adjacent to each other along the first direction DR1, and may be disposed to be spaced apart from each other in the first direction DR1.

[0177] The third insulating pattern 150 may fill the inside of the space surrounded by the U-shaped channel pattern CP. The third insulating pattern 150 may extend in the second direction DR2. The third insulating pattern 150 may fill the space between the channel patterns CP spaced apart from each other along the second direction DR2. The third insulating pattern 150 may fill the space between the second gate insulating patterns Gox2 spaced apart from each other in the second direction DR2.

[0178] The third insulating pattern 150 may cover an upper surface of the channel pattern CP and an upper surface of the second gate insulating pattern Gox2 .

[0179] The third insulating pattern 150 may include or may be formed of a material having an etch selectivity that is the same as or similar to that of the second gate insulating pattern Gox2 .

[0180] Subsequently, a photoresist pattern PR may be formed on the second and third insulating patterns 140 and 150. After the photoresist layer is formed on the upper surfaces of the second and third insulating patterns 140 and 150, the photoresist layer may be patterned into a pattern corresponding to a landing pad LP to be described later through an exposure process and a development process.

[0181] Reference Fig. 22 , the third insulating pattern 150 and the second gate insulating pattern Gox2 may be partially etched using the photoresist pattern PR as an etching mask.

[0182] Since upper portions of the third insulation pattern 150 and the second gate insulation pattern Gox2 are partially etched, an upper surface of the channel pattern CP and opposite side surfaces extending from the upper surface may be exposed.

[0183] Through the etching process, an upper surface of the third insulation pattern 150 adjacent to the channel pattern CP and an upper surface of the second gate insulation pattern Gox2 may be lower than an upper surface of the channel pattern CP.

[0184] An upper surface of the second gate insulation pattern Gox2 may be disposed at a higher level than an upper surface of the first gate insulation pattern Gox1 .

[0185] Through the etching process, the first recess R1 and the second recess R2 may be formed. The lower surface of the first recess R1 may be defined as the upper surface of the second gate insulation pattern Gox2. The sidewall of the first recess R1 may be defined as the side surface of the second insulation pattern 140 and one side surface of the channel pattern CP. The bottom surface of the second recess R2 may be defined as the upper surface of the third insulation pattern 150 adjacent to the channel pattern CP. The sidewall of the second recess R2 may be defined as the side surface of the third insulation pattern 150 and the other side surface of the channel pattern CP.

[0186] Reference Fig.23 , the photoresist pattern PR may be removed. For example, the photoresist pattern PR may be removed by an ashing process and / or a stripping process.

[0187] The channel pattern CP may be Fig. 22 Therefore, the reliability can be improved by performing a PN process on the channel pattern CP. The PN process can be performed before or after removing the photoresist pattern PR.

[0188] Reference Fig.24 , a landing pad material layer LP_L may be formed. The landing pad material layer LP_L may be deposited by CVD, PVD or ALD process, but is not limited thereto.

[0189] The landing pad material layer LP_L may include doped polysilicon, metal, conductive metal nitride, conductive metal oxide, or a combination thereof, or may be formed of doped polysilicon, metal, conductive metal nitride, conductive metal oxide, or a combination thereof. For example, the landing pad material layer LP_L may include Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, or may be formed of Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof, but is not limited thereto.

[0190] The landing pad material layer LP_L may be formed to fill the first and second recesses R1 and R2 and cover upper surfaces of the second insulating pattern 140 , the second gate insulating pattern Gox2 , the channel pattern CP, and the third insulating pattern 150 .

[0191] The landing pad material layer LP_L may fill the first recess R1 and the second recess R2 and may contact opposite side surfaces of the channel pattern CP. The landing pad material layer LP_L may fill a space between side surfaces of the second insulating pattern 140 and the third insulating pattern 150 at a level higher than the upper surface of the channel pattern CP and may contact the upper surface of the channel pattern CP.

[0192] Reference Fig.25, after patterning the landing pad material layer LP_L to form a hole exposing the upper surfaces of the second insulating pattern 140 and the third insulating pattern 150, the interlayer insulating layer 160 may be embedded in the hole, and then a planarization process may be performed. Thus, the landing pad LP may be formed. However, the order of forming the landing pad LP and the interlayer insulating layer 160 is not limited thereto.

[0193] In some embodiments, an interlayer insulating layer 160 may be formed and patterned on upper surfaces of the second insulating pattern 140 , the third insulating pattern 150 , the second gate insulating pattern Gox2 , and the channel pattern CP, and then a landing pad LP penetrating the interlayer insulating layer 160 may be formed.

[0194] The landing pad LP may be in contact with three surfaces of the channel pattern CP. The landing pad LP may be in contact with an upper surface of the channel pattern CP and opposite side surfaces extending from the upper surface.

[0195] For example, the landing pad LP may include a first portion (eg, Figure 4 The first portion LP_P1 of the landing pad LP in the channel pattern CP and the second portion (eg, Figure 4 The second portion LP_P2 of the landing pad LP) and the connecting portion connecting the first portion and the second portion (eg, Figure 4 The connecting portion LP_C of the landing pad LP in the channel pattern CP may be in contact with the upper surface of the channel pattern CP. The first portion of the landing pad LP may be in contact with one side surface of the channel pattern CP extending from the upper surface of the channel pattern CP. The second portion of the landing pad LP may be in contact with the other side surface of the channel pattern CP extending from the upper surface of the channel pattern CP.

[0196] For example, the width of the upper surface of the landing pad LP (the length in the first direction DR1 ) may be greater than the width of the landing pad LP between the second and third insulation patterns 140 and 150 (the length in the first direction DR1 ), but is not limited thereto.

[0197] Subsequently, data storage patterns DSP may be formed on upper surfaces of the landing pads LP, respectively. In some embodiments, the data storage patterns DSP may be capacitors including a lower electrode, a capacitor dielectric film, and an upper electrode, in which case the lower electrode may contact the landing pad LP.

[0198] In some embodiments, the Fig.18 and Fig.19 process, and can be Fig.17 After the process is performed Figure 20 to Figure 25In this case, the second gate insulating pattern Gox2 is not formed, and the channel pattern CP may be directly formed on the opposite side surface of the word line structure WLS. The channel pattern CP may be formed to further cover a portion of the upper surface of the second insulating pattern 140. The third insulating pattern 150 may be formed not only on the channel pattern CP but also on the second insulating pattern 140.

[0199] The landing pad LP may include a first portion disposed between a portion of the third insulating pattern 150 formed on the channel pattern CP and the channel pattern CP, a second portion disposed between a portion of the third insulating pattern 150 formed on the second insulating pattern 140 and the channel pattern CP, and a connecting portion connecting the first portion and the second portion. A lower surface of the first portion may contact the third insulating pattern 150, and a lower surface of the second portion may contact the second insulating pattern 140.

[0200] The landing pad LP may be in contact with the upper surface of the channel pattern CP and the opposite side surface extending from the upper surface. The connecting portion may be in contact with the upper surface of the channel pattern CP. The first portion may be in contact with one side surface of the channel pattern CP, the one side surface facing the portion of the third insulating pattern 150 formed on the channel pattern CP. The second portion may be in contact with the other side surface of the channel pattern CP, the other side surface facing the portion of the third insulating pattern 150 formed on the second insulating pattern 140.

[0201] Therefore, it can be formed Figure 8 A semiconductor device according to the embodiment shown.

[0202] While embodiments of the present disclosure have been described in connection with what are presently considered to be practical embodiments, it is to be understood that the disclosure is not limited to the disclosed embodiments, but on the contrary is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

[0203] CROSS-REFERENCE TO RELATED APPLICATIONS

[0204] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0163645 filed in the Korean Intellectual Property Office on November 22, 2023, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor device, comprising: substrate; A bit line disposed on the substrate and extending in a first direction; a first insulating pattern disposed on an upper surface of the bit line and extending in a second direction crossing the first direction, wherein the first direction and the second direction are parallel to an upper surface of the substrate; a first word line disposed on an upper surface of the first insulating pattern and extending in the second direction; a channel pattern disposed on the upper surface of the bit line and spaced apart from the first word line in the first direction; a gate insulating pattern disposed between a first side surface of the first word line and the channel pattern; a second insulating pattern disposed on an upper surface of the first word line and extending in the second direction; a third insulating pattern disposed on the channel pattern, wherein the channel pattern includes a horizontal portion and a vertical portion, wherein the horizontal portion extends along the first direction and is interposed between the upper surface of the bit line and the lower surface of the third insulating pattern, wherein the vertical portion extends from the horizontal portion along a third direction and is interposed between a side surface of the third insulating pattern and the first word line, and Wherein, the third direction is perpendicular to the upper surface of the substrate; and A landing pad is connected to the channel pattern and covers an upper surface of the vertical portion of the channel pattern and opposite side surfaces of the vertical portion extending from the upper surface of the vertical portion.

2. The semiconductor device according to claim 1, in, The landing pad comprises: a first portion, disposed between the third insulating pattern and the channel pattern, a second portion disposed between the channel pattern and the second insulating pattern, and A connecting portion connects the first portion to the second portion and covers an upper surface of the channel pattern.

3. The semiconductor device according to claim 2, in, The gate insulating pattern comprises: a first gate insulating pattern contacting the first side surface of the first word line, and a second gate insulating pattern disposed between the first gate insulating pattern and the vertical portion of the channel pattern, and Wherein, the second portion of the landing pad covers an upper surface of the second gate insulation pattern.

4. The semiconductor device according to claim 3, in, The upper surface of the second gate insulating pattern is disposed at the same level as or at a higher level than an upper surface of the first gate insulating pattern.

5. The semiconductor device according to claim 3, further comprising: a second word line disposed on the upper surface of the first insulating pattern and extending in the second direction, wherein the second word line is spaced apart from the first word line in the first direction, wherein the first word line and the second word line are disposed between the upper surface of the first insulating pattern and a lower surface of the second insulating pattern, Wherein, the first gate insulating pattern comprises: a first portion contacting the first side surface of the first word line facing the channel pattern and a first side surface of the second word line facing the channel pattern, and a second portion contacting a second side surface of the first word line opposite to the first side surface and a second side surface of the second word line opposite to the first side surface, and The second side surface of the first word line and the second side surface of the second word line are adjacent to each other and are disposed between the first side surface of the first word line and the first side surface of the second word line.

6. The semiconductor device according to claim 5, further comprising: A low dielectric constant (low-k) material fills a space between the second portion of the first gate insulating pattern and the lower surface of the second insulating pattern.

7. The semiconductor device according to claim 5, in, An air gap is disposed in a space between the second portion of the first gate insulating pattern and the lower surface of the second insulating pattern.

8. The semiconductor device according to claim 1, further comprising: a second word line disposed on the upper surface of the first insulating pattern and extending in the second direction, wherein the second word line is spaced apart from the first word line in the first direction, wherein the first word line contacts the upper surface of the first insulating pattern and the lower surface of the second insulating pattern, wherein the second word line contacts the upper surface of the first insulating pattern and the lower surface of the second insulating pattern, and A space defined by the upper surface of the first insulating pattern, the lower surface of the second insulating pattern, and side surfaces of the first word line and the second word line facing each other is filled with a low-k material.

9. The semiconductor device according to claim 1, further comprising: a second word line disposed on the upper surface of the first insulating pattern and extending in the second direction, wherein the second word line is spaced apart from the first word line in the first direction, wherein the first word line connects a portion of the upper surface of the first insulating pattern to a portion of the lower surface of the second insulating pattern, wherein the second word line connects another portion of the upper surface of the first insulating pattern to another portion of the lower surface of the second insulating pattern, and The air gap is disposed in a space defined by the upper surface of the first insulating pattern, the lower surface of the second insulating pattern, and side surfaces of the first word line and the second word line facing each other.

10. The semiconductor device according to claim 1, in, The channel pattern further extends to cover an upper surface of the second insulating pattern, and Wherein, the third insulating pattern is further arranged on the second insulating pattern.

11. The semiconductor device according to claim 10, in, The landing pad comprises: a first portion and a second portion disposed between the third insulating pattern and the channel pattern, and a connecting portion connecting the first portion and the second portion and covering an upper surface of the channel pattern, wherein a lower surface of the first portion contacts the third insulating pattern, and Wherein a lower surface of the second portion contacts the second insulating pattern.

12. A semiconductor device comprising: substrate; A bit line disposed on the substrate and extending in a first direction; a first insulating pattern disposed on the bit line and extending in a second direction intersecting the first direction; a first word line disposed on the first insulating pattern and extending in the second direction; a channel pattern spaced apart from the first word line in the first direction; a gate insulating pattern, disposed between the first word line and the channel pattern; a second insulating pattern disposed on the first word line and extending in the second direction; a third insulating pattern, disposed on the channel pattern; as well as Landing pad, connected to the channel pattern, Wherein, the landing pad contacts at least three surfaces of the channel pattern.

13. The semiconductor device according to claim 12, in, The landing pad comprises: a first portion contacting a first side surface of the channel pattern, a second portion contacting a second side surface of the channel pattern opposite to the first side surface, and A connecting portion connecting the first portion and the second portion and contacting an upper surface of the channel pattern.

14. The semiconductor device according to claim 13, in, A lower surface of the first portion of the landing pad contacts the third insulating pattern, and Wherein, a lower surface of the second portion of the landing pad contacts the gate insulation pattern.

15. The semiconductor device according to claim 14, in, The gate insulating pattern comprises: a first gate insulating pattern having a first side surface contacting a side surface of the first word line, and a second gate insulating pattern contacting a second side surface of the first gate insulating pattern opposite to the first side surface, and Wherein, the lower surface of the second portion of the landing pad contacts the second gate insulation pattern.

16. The semiconductor device according to claim 13, in, The lower surface of the first portion of the landing pad contacts the third insulating pattern, and Wherein, the lower surface of the second portion of the landing pad contacts the second insulating pattern.

17. The semiconductor device according to claim 13, further comprising: a second word line disposed on the first insulating pattern and extending in the second direction, wherein the second word line is spaced apart from the first word line in the first direction, wherein the first word line and the second word line are disposed between an upper surface of the first insulating pattern and a lower surface of the second insulating pattern, and The first space is surrounded by the upper surface of the first insulating pattern, the lower surface of the second insulating pattern, and side surfaces of the first word line and the second word line facing each other.

18. The semiconductor device according to claim 17, further comprising: a low-k material pattern disposed in the first space, The gate insulating pattern is further disposed between the low-k material pattern and the first word line, between the low-k material pattern and the second word line, and between the low-k material pattern and the first insulating pattern.

19. The semiconductor device according to claim 17, further comprising: an air gap provided in the first space, The gate insulating pattern is further disposed between the air gap and the first word line, between the air gap and the second word line, and between the air gap and the first insulating pattern.

20. A semiconductor device comprising: substrate; A bit line disposed on the substrate and extending in a first direction; a word line structure disposed on the bit line and extending in a second direction intersecting the first direction, Wherein, the word line structure comprises: a first insulating pattern covering an upper surface of the bit line, a pair of word lines disposed on the first insulating pattern and spaced apart from each other in the first direction, a first gate insulating pattern covering a side surface of each of the pair of word lines, and a second insulating pattern covering upper surfaces of the pair of word lines; a channel pattern disposed between adjacent word line structures in the first direction; a second gate insulating pattern disposed between the channel pattern and the word line structure; a third insulating pattern disposed on the channel pattern; and Landing pad, connected to the channel pattern, Wherein, the channel pattern includes: a horizontal portion extending in the first direction along an upper surface of the bit line, and a vertical portion extending from the horizontal portion along the side surface of the adjacent word line structure, and Wherein, the landing pad comprises: a first portion protruding between the channel pattern and the third insulating pattern, and A second portion protrudes between the channel pattern and the second insulating pattern.

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