Semiconductor memory device and manufacturing method thereof

Abstract

The invention relates to a semiconductor memory device and a manufacturing method thereof. A semiconductor memory device includes a gate stack including interlayer insulating layers and conductive pattern layers alternately stacked with each other in a first direction. A channel structure is formed through the gate stack and has an end protruding over the gate stack. The memory layer surrounds a channel structure having a core insulating layer. The channel layer surrounds the core insulating layer. A void is formed in the channel layer.

Description

Technical Field

[0001] The present disclosure relates to electronic devices, and more particularly, to a semiconductor memory device including a vertical channel structure. The present disclosure also relates to a method for manufacturing the memory device. Background Art

[0002] Recently, the paradigm of computer environments has shifted to ubiquitous computing, which enables computer systems to be used almost anywhere. The use of portable electronic devices such as mobile phones, digital cameras, and notebook computers is increasing rapidly. These and other portable electronic devices typically use semiconductor memory systems that use one or more semiconductor memory devices, i.e., data storage devices. The data storage devices are used as primary storage devices or auxiliary storage devices of the portable electronic devices.

[0003] Data storage devices using semiconductor memory devices have advantages including excellent data stability and excellent device durability because, unlike magnetic hard disk drives or optical memory devices, semiconductor memory devices do not have or use any mechanical components. The data access time of semiconductor memory devices is also much shorter than the access time of even the fastest hard disk drives and optical drives. Equally important, the power consumption of semiconductor memory devices is also much lower than the power consumption of even the most energy-efficient hard disk drives and optical drives.

[0004] The semiconductor memory system includes a data storage device Universal Serial Bus (USB) memory device, a memory card populated with a semiconductor memory device having various interfaces, a solid state disk drive (SSD), and the like.

[0005] Semiconductor memory devices are generally classified as either volatile memory devices or nonvolatile memory devices.

[0006] The writing speed and reading speed of nonvolatile memory devices are generally longer than those of volatile memory devices, however, nonvolatile memory devices advantageously maintain data even after the power of the nonvolatile memory devices is turned off. Therefore, nonvolatile memory devices are used to store data that needs to be retained or maintained without power.

[0007] The nonvolatile memory device includes a read-only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase change random access memory (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), etc. The flash memory is divided into a NOR type and a NAND type. Summary of the invention

[0008] Embodiments of the present disclosure provide a semiconductor memory device and a method of manufacturing the same by more uniformly forming a junction region of a vertical channel structure.

[0009] According to an embodiment of the present disclosure, a semiconductor memory device includes: a gate stack including an interlayer insulating layer and a conductive pattern layer alternately stacked in a vertical direction on a substrate; a channel structure that passes through the gate stack and protrudes at one end above the top surface or top height of the gate stack; a memory layer that surrounds the sidewall of the channel structure; and a source layer that is formed on the gate stack. The channel structure includes a core insulating layer extending in the vertical direction and formed in a central area, and a channel layer that surrounds the sidewall of the core insulating layer and is formed in the vertical direction to be higher than the memory layer. A gap extending from a position lower than the lowest height of at least one conductive pattern layer corresponding to a source selection line among a plurality of conductive pattern layers to a position at least higher than the highest height of the gate stack is included in the core insulating layer.

[0010] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor memory device includes the following steps: forming a memory cell array on a first substrate so that the memory cell array includes a gate stack including an interlayer insulating layer and a conductive pattern layer alternately stacked in a vertical direction, a core insulating layer passing through the gate stack and extending its end into the first substrate, a channel layer surrounding the sidewall and end of the core insulating layer, and a memory layer extending from between the channel layer and the gate stack to between the end of the channel layer and the first substrate; removing the first substrate so that the memory layer is exposed; forming a junction at the upper end of the channel layer by performing an ion implantation process; and exposing the end of the channel layer by etching the exposed memory layer.

[0011] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor memory device includes the following steps: forming a memory cell array on a first substrate so that the memory cell array includes a gate stack including an interlayer insulating layer and a conductive pattern layer alternately stacked in a vertical direction, a core insulating layer passing through the gate stack and extending its end into the first substrate, a channel layer surrounding the sidewall and end of the core insulating layer, and a memory layer extending from between the channel layer and the gate stack to between the end of the channel layer and the first substrate; removing the first substrate so that the memory layer is exposed; exposing the end of the channel layer by removing the exposed memory layer; forming a spacer on the end sidewall of the channel layer; and forming a junction at the upper end of the channel layer by performing an ion implantation process.

[0012] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor memory device includes the following steps: forming a memory cell array on a first substrate so that the memory cell array includes a gate stack including interlayer insulating layers and conductive pattern layers alternately stacked in a vertical direction, a core insulating layer passing through the gate stack and extending its end into the first substrate, a channel layer surrounding the sidewall and end of the core insulating layer, and a memory layer extending from between the channel layer and the gate stack to between the end of the channel layer and the first substrate; removing the first substrate so that the memory layer is exposed; exposing the end of the channel layer by removing the exposed memory layer; forming a first source layer along the surface of the entire structure including the exposed end of the channel layer; forming a spacer on the sidewall of the first source layer extending in the vertical direction along the sidewall of the end of the channel layer; and forming a junction at the upper end of the channel layer by performing an ion implantation process.

[0013] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor memory device includes the following steps: forming a memory cell array on a first substrate so that the memory cell array includes a gate stack including an interlayer insulating layer and a conductive pattern layer alternately stacked in a vertical direction, a core insulating layer passing through the gate stack and extending its end into the first substrate, a channel layer surrounding the sidewall and end of the core insulating layer, a memory layer configured by a blocking insulating layer extending from between the channel layer and the gate stack to between the end of the channel layer and the first substrate, a data storage layer, and a tunnel insulating layer; removing the first substrate so that the memory layer is exposed; exposing the data storage layer by removing the blocking insulating layer of the exposed memory layer; forming a spacer on the surface of the data storage layer; and forming a junction at the upper end of the channel layer by performing an ion implantation process.

[0014] According to the present technology, after forming a vertical channel structure so that the vertical channel structure protrudes by passing through a gate stack, a junction region can be formed at a uniform depth in a channel layer by performing an ion implantation process after forming a spacer on a side of the protruding vertical channel structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0016] Figure 2 It is shown Figure 1 Circuit diagram of a memory cell array.

[0017] Figure 3 is a perspective view schematically showing a semiconductor memory device according to an embodiment of the present disclosure.

[0018] Figure 4 It is shown Figure 1 A vertical cross-sectional view of a memory cell array.

[0019] FIG. 5A to FIG. 5F , Figure 6 , Figure 7 as well as FIG. 8A to FIG. 8D is a vertical cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0020] 9A to 9D is a vertical cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present disclosure.

[0021] FIG. 10A to FIG. 10D is a vertical cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present disclosure.

[0022] FIG. 11A to FIG. 11D is a vertical cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present disclosure.

[0023] Fig.12 is a block diagram showing a configuration of a memory system according to an embodiment of the present disclosure.

[0024] Fig.13 is a block diagram showing a configuration of a computing system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] The specific structural or functional description of the embodiments of the concepts disclosed in this specification or application is only shown for describing the embodiments of the concepts disclosed in this specification. The embodiments of the concepts disclosed in this specification can be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or application.

[0026] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings so as to be described in sufficient detail to allow those having ordinary skill in the art to easily implement the technical concept of the present disclosure.

[0027] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0028] Reference Figure 1 , a semiconductor memory device 10 includes a peripheral circuit PC and a memory cell array 20 .

[0029] The peripheral circuit PC can be configured to control at least three different operations of the memory cell array 20: 1) a programming operation for storing data in the memory cell array 20; 2) a read operation for outputting data stored in the memory cell array 20; and 3) an erase operation for erasing data stored in the memory cell array 20.

[0030] In a preferred embodiment, the peripheral circuit PC may include a voltage generator 31 , a row decoder 33 , a control circuit 35 , and a page buffer group 37 .

[0031] The memory cell array 20 may include a plurality of memory blocks ( Figure 1 1. The memory cell array 20 may be connected to the row decoder 33 through word lines WL. The memory cell array 20 may be connected to the page buffer group 37 through bit lines BL.

[0032] The control circuit 35 of the peripheral circuit PC may control the voltage generator 31 , the row decoder 33 , and the page buffer group 37 in response to the command CMD and the address ADD.

[0033] The voltage generator 31 may generate various operation voltages for program operations, read operations, and erase operations, such as an erase voltage, a ground voltage, a program voltage, a verification voltage, a pass voltage, and a read voltage in response to control of the control circuit 35 .

[0034] The row decoder 33 may select a memory block in response to a signal it receives from the control circuit 35. The row decoder 33 may be configured to apply an operating voltage to a word line WL connected to the selected memory block.

[0035] The page buffer group 37 may be connected to the memory cell array 20 through the bit lines BL. The page buffer group 37 may temporarily store data received from an input / output circuit (not shown) during a program operation in response to the control of the control circuit 35. The page buffer group 37 may sense a voltage on one or more bit lines BL or a current flowing through one or more bit lines BL during a read operation or a verification operation in response to the control of the control circuit 35. The page buffer group 37 may select a bit line BL in response to a signal received by the page buffer group 37 from the control circuit 35.

[0036] Structurally, the memory cell array 20 may overlap a portion of the peripheral circuit PC.

[0037] Figure 2 It is shown Figure 1 A three-dimensional diagram of a circuit of a memory cell array.

[0038] Reference Figure 2 , the memory cell array 20 may include a plurality of transistors connected in series (referred to herein as cell strings CS1 and CS2 ). Figure 2 Four (4) separate cell strings are depicted.

[0039] Each cell string CS1 and CS2 is connected to Figure 2 Depicted as relatively close Figure 2 The bottom edge of the source line SL is connected to Figure 2 Depicted as relatively close Figure 2The gate terminals of the respective "cell" transistors of the respective strings of the plurality of cell strings CS1 and CS2 are commonly connected to the plurality of word lines WL1 to WLn.

[0040] Each of the plurality of cell strings CS1 and CS2 may include a source select transistor SST located at the "bottom" of each cell string CS1, CS2, with its gate terminal connected to the source line SL. The gate of the drain select transistor DST located at the "top" of each cell string CS1, CS2 is connected to the bit line BL. A plurality of individual memory cells MC1 to MCn are connected in series to each other, thus forming a string. The opposite ends of each string are connected between the corresponding source select transistor SST and the corresponding drain select transistor DST.

[0041] like Figure 2 As shown, the gates of the transistors of the memory cells MC among the plurality of memory cells MC1 to MCn may be connected to specific word lines WL among the plurality of word lines named WL1 to WLn. Figure 2 1 and 12 are shown as being “vertically” stacked on top of each other, such that the word lines WL are considered to be vertically stacked on top of each other and vertically spaced apart a separation distance.

[0042] Of course, one of ordinary skill will recognize that vertical is often referred to or defined as "perpendicular to the horizon plane". For the purpose of claim construction of this disclosure, the wordline stacking direction is designated as "vertical" for illustration only. As an example, if Figure 2 If the structure depicted in is redrawn or simply rotated ninety degrees, the word lines of this memory cell MC configuration will be stacked horizontally.

[0043] For claim construction purposes, "vertical" should not be interpreted as perpendicular to the horizon plane. "Vertical" should be interpreted as the direction in which various structures can be oriented (i.e., the same direction). Figure 1 As shown, the word lines WL1 to WLn may be connected to and located between the source selection line SSL and two or more drain selection lines DSL1 and DSL2. The two or more drain selection lines DSL1 and DSL2 may be spaced apart from each other at the same height.

[0044] A gate of the source select transistor SST may be connected to a source select line SSL. A gate of the drain select transistor DST may be connected to a drain select line corresponding to the gate of the drain select transistor DST.

[0045] The source line SL may be connected to the source of the source selection transistor SST. The drain of the drain selection transistor DST may be connected to a bit line corresponding to the drain of the drain selection transistor DST.

[0046] A plurality of cell strings CS1 and CS2 may be divided into string groups connected to two or more drain selection lines DSL1 and DSL2, respectively. Cell strings connected to the same word line and the same bit line may be independently controlled by different drain selection lines. In addition, cell strings connected to the same drain selection line may be independently controlled by different bit lines.

[0047] As an embodiment, the two or more drain selection lines DSL1 and DSL2 may include a first drain selection line DSL1 and a second drain selection line DSL2. The plurality of cell strings CS1 and CS2 may include a first cell string CS1 of a first string group connected to the first drain selection line DSL1 and a second cell string CS2 of a second string group connected to the second drain selection line DSL2.

[0048] Figure 3 is a perspective view schematically showing a semiconductor memory device 10 according to an embodiment of the present disclosure.

[0049] Reference Figure 3 , the semiconductor memory device 10 may include a peripheral circuit PC located on a substrate SUB. A source line SL is formed on top of the substrate SUB. Two gate stacks GST are formed on top of the source line SL and within the "coverage area" of the source line SL. Therefore, the X size and Y size of the two gate stacks GST are smaller than the X size and Y size of the source line SL. The X size and Y size of the source line are smaller than the X size and Y size of the peripheral circuit PC. The X size and Y size of the peripheral circuit PC and the substrate SUB are the same or at least substantially the same. Each gate stack GST may include a source selection line SSL, a plurality of word lines WL1 to WLn, and two or more drain selection lines DSL1 and DSL2, which are "horizontally" separated from each other (i.e., separated from each other in the X direction) at the same "vertical" height (i.e., separated from the substrate SUB by substantially the same distance in the Z direction). The separation space between the gate stacks GST is named "DSM".

[0050] like Figure 3 As shown, the source selection line SSL (in Figure 3 The bottom "layer" of the gate stack (depicted in FIG. 1 ) and the plurality of word lines WL1 to WLn (stacked atop the source select line SSL) both extend in a first X-axis direction and in a second Y-axis direction orthogonal to the X-axis direction.

[0051] The source select line SSL and the word lines WL1-WLn have substantially the same shape, which is substantially a rectangular parallelepiped shape. A parallelepiped is a well-known 6-sided polyhedron, all of which are parallelograms, flat and located in pairs of parallel planes. Each of the six surfaces including the source select line SSL and the word lines WL1-WLn is flat or substantially flat, and the surfaces extend on two of the three mutually orthogonal axes of the XYZ coordinate system.

[0052] The plurality of word lines WL1 to WLn may be considered as separate layers, which are vertically stacked with each other in a third Z-axis direction and spaced apart from each other in the third Z-axis direction. The third Z-axis direction may be orthogonal to the X-axis direction and the Y-axis direction of the three-dimensional XYZ coordinate system. The plurality of word lines WL1 to WLn may be located between two or more drain selection lines DSL1 and DSL2 and the source selection line SSL.

[0053] The gate stacks GST may be "horizontally" separated from each other in the X-axis direction by slits SI between the gate stacks, which are located in the YZ plane. The X-axis width of the separation space DSM may be sized, shaped and arranged to be smaller than the X-direction width of the slit SI in the X-direction.

[0054] When viewed in the Z direction, the separation space of one or both of the DSM space and the slit SI may have a shape that may be substantially linear, sawtooth, wavy, or sinusoidal. The X-axis width of each of the separation structure DSM and the slit SI may be changed differently according to design rules.

[0055] The source select line SSL according to an embodiment may be disposed closer to the peripheral circuit PC than the two or more drain select lines DSL1 and DSL2 .

[0056] The semiconductor memory device 10 may include a source line SL between a gate stack GST and a peripheral circuit PC and a plurality of bit lines BL spaced farther from the peripheral circuit PC than the source line SL. The gate stack GST may be located between the plurality of bit lines BL and the source line SL.

[0057] Figure 4 It is shown Figure 1 A vertical cross-sectional view of a memory cell array.

[0058] Reference Figure 4 In the memory cell array, the lower structure U and the upper structure T may be bonded to each other. The source line SL may be located on the top of the upper structure T.

[0059] The upper structure T may include two gate stacks GST, such as Figure 3 Depicted in Figure 4 In both figures, the gate stacks are separated from each other by slits SI.

[0060] like Figure 4 As shown, the upper structure T may include "vertical" and substantially columnar channel structures CH, each of which passes through the stacked layers of the gate stack. The upper structure also includes a substantially columnar memory layer ML formed around the outer surface or "sidewall" of each channel structure CH. The bit line identified by reference numeral 41 is located below the gate stack GST and above the first connection structure C1.

[0061] The gate stack GST includes interlayer insulating layers ILD and conductive pattern layers CP1 to CPn alternately stacked with each other in a vertical (ie, Z-axis) direction. Figure 4 The conductive pattern layer CP in FIG. 1 is cross-hatched.

[0062] Each of the conductive pattern layers CP1 to CPn may be made of various conductive materials such as a doped silicon layer, a metal layer, a metal silicide layer, and a barrier layer, and may include two or more types of conductive materials. For example, each of the conductive pattern layers CP1 to CPn may include tungsten and a titanium nitride (TiN) layer surrounding the surface of the tungsten. Tungsten may be a low-resistance metal, and its resistance may be less than that of the conductive pattern layers CP1 to CPn. The titanium nitride (TiN) layer may be a barrier layer, and may prevent direct contact between tungsten and the interlayer insulating layer ILD.

[0063] Still refer to Figure 4 , the select line SL is directly above and in contact with the uppermost interlayer insulating layer ILD at the “top” of the gate stack. Figure 4 In the embodiment, the conductive pattern layer CP1 is the lowest conductive pattern layer CP in the gate stack and is "sandwiched" between two interlayer insulating layers ILD. Therefore, CP1 is the conductive pattern layer vertically farthest from the selection line SL. The conductive pattern layer CP1 can be used as a drain selection line DSL.

[0064] Among all the conductive pattern layers CP1 to CPn, the Z-axis height of the first (and lowest) conductive pattern layer CP1 in the gate stack is "higher" than the Z-axis height of the bit line 41. In contrast, the Z-axis height of the "highest" conductive pattern layer CPn is several ILD / CP layer pairs above CP1 and is separated from the selection line SL by the uppermost interlayer insulating layer ILD. Therefore, the CPn layer is separated from the selection line SL by one interlayer insulating layer ILD.

[0065] In another embodiment not shown, two or more conductive pattern layers CP adjacent to the bit line 41 and stacked continuously may be used as a drain selection line. Among the conductive pattern layers CP1 to CPn, the nth conductive pattern layer CPn adjacent to the source line SL may be used as a source selection line SSL. In another embodiment not shown, two or more conductive pattern layers CP adjacent to the source line SL and stacked continuously may be used as a source selection line SSL. Conductive pattern layers (e.g., CP2 to CPn-1) adjacent to each other in the vertical direction and located between the drain selection line DSL and the source selection line SSL may be used as the conductive pattern layers (e.g., CP2 to CPn-1) described above with reference to Figure 2 Word lines WL1 to WLn are described.

[0066] In various embodiments, the channel structure CH passes through the gate stack GST in a vertical direction. One end of the channel structure CH may be formed to protrude or extend “over” the “top” of the gate stack GST.

[0067] The channel structure CH may be hollow and may have a circular horizontal cross-sectional shape. The longitudinal portion inside the channel structure CH is cylindrical and empty. The empty longitudinal portion of the channel structure CH is a void. The void should therefore be interpreted as an empty space in the center or innermost part of the channel structure CH. For claim construction purposes, the void therefore includes a substantially cylindrical empty space inside the channel structure CH.

[0068] In a preferred embodiment, the void has a substantially circular horizontal cross-sectional shape with a geometric central axis substantially parallel to Figure 4 The void is preferably formed around the geometric center axis of the channel structure CH. The void is also surrounded or substantially surrounded by the core insulating layer 11. The void is therefore regarded as being located in the "central region" of the channel structure.

[0069] The void is considered to have an upper portion and a lower portion. A cylindrical plug-shaped doped semiconductor layer 13 is located near the bottom of the void and below the hollow tubular core insulating layer 11. Another hollow tubular channel layer 15 surrounds and contacts the outer surface of the hollow tubular core insulating layer 11. The hollow tubular channel layer 15 also surrounds and contacts the plug-shaped doped semiconductor layer 13.

[0070] The void is located inside the core insulating layer 11. The void and the core insulating layer 11 around the void should extend upward in the Z direction from a height just below the lowest conductive pattern layer CP1 in the gate stack to a height just above the highest conductive pattern layer CPn in the gate stack. The void and the core insulating layer 11 thus extend through the gate stack.

[0071] For example, the gap may extend from a position lower than at least one or more conductive pattern layers that can be used as source selection lines to a position of multiple conductive pattern layers that can be used as word lines or a position of at least one or more conductive pattern layers that can be used as drain selection lines. The channel layer 15 is used as a channel region of a cell string corresponding thereto. The channel layer 15 may be formed of a semiconductor material. As an embodiment, the channel layer 15 may include a silicon layer. Dopants may be implanted into the uppermost portion of the channel layer 15 (i.e., the portion of the channel layer corresponding to the source selection transistor) by an ion implantation process. The channel structure CH may be formed to protrude beyond the interlayer insulating layer ILD located at the uppermost portion of the gate stack GST.

[0072] The memory layer ML may be formed to surround the surface of the channel structure CH. The memory layer ML may include a tunnel insulating layer TI surrounding the channel layer 15 of the channel structure CH, a data storage layer DS surrounding the tunnel insulating layer TI, and a blocking insulating layer BI surrounding the data storage layer DS. The memory layer ML may extend in a direction perpendicular to the channel structure CH and may extend shorter than the channel layer 15. That is, the memory layer ML may be formed to have a height lower than that of the channel layer 15. That is, the height of the channel layer 15 may be higher than that of the memory layer ML. The memory layer ML may be formed at the same height as the interlayer insulating layer ILD located at the uppermost portion of the gate stack GST. The memory layer ML may be defined as a component included in the channel structure CH.

[0073] The bit line 41 may be located under the two gate stacks GST and may be electrically connected to the channel structure CH through a contact plug 39 “vertically” passing through the plurality of insulating layers 21, 25, and 27. The bit line 41 may be spaced apart from the substrate SUB by the first and second insulating structures 51 and 81.

[0074] The first connection structure 1st_CS may include a first insulating structure 51 and a first connection structure C1 formed inside the first insulating structure 51. The first connection structure C1 may include various conductive pattern layers 63, 65, and 67. The first insulating structure 51 may include two or more insulating layers 51A to 51D stacked between the bit line 41 and the second insulating structure 81.

[0075] The lower structure U may include a complementary metal oxide semiconductor (CMOS) circuit structure CMOS including a plurality of transistors TR formed on a substrate SUB. The lower structure U may further include a second connection structure 2nd_CS formed on the CMOS circuit structure CMOS.

[0076] The second connection structure 2nd_CS may include a second insulating structure 81 formed on the substrate SUB and a second connection structure C2 formed inside the second insulating structure 81. Each of the second connection structures C2 may include various conductive pattern layers 83, 85, 87, 89, and 91 embedded in the second insulating structure 81. The second insulating structure 81 may include two or more insulating layers 81A to 81D sequentially stacked.

[0077] The upper structure T and the lower structure U may be bonded to each other by a conventional bonding process. For example, the exposed conductive pattern layer 67 of the first connection structure CS of the upper structure T and the exposed conductive pattern layer 91 of the second connection structure 2nd_CS of the lower structure U may be positioned to face each other and may be bonded to each other. The conductive pattern layer 67 and the conductive pattern layer 91 may be defined as a bonding metal.

[0078] As described above, the source line SL may be located on the upper structure T. The source line SL may be made of a material such as a dopant polysilicon layer or a metal material having low resistance.

[0079] FIG. 5A to FIG. 5F , Figure 6 , Figure 7 as well as FIG. 8A to FIG. 8D is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the present disclosure.

[0080] FIG. 5A to FIG. 5F is a cross-sectional view showing a step of forming a memory cell array, a first line array, and a first connection structure on a first substrate.

[0081] Reference Figure 5A , the first material layers 111 and the second material layers 113 may be alternately stacked layer by layer on the first substrate 101 .

[0082] The first substrate 101 may be a material having an etching rate different from that of the first material layer 111 and the second material layer 113. In one implementation, the first substrate 101 may include silicon.

[0083] The first material layer 111 may be an insulating material and is used to provide a reference Figure 4 The second material layer 113 may be a material having an etching rate different from that of the first material layer 111, such as silicon oxide or silicon nitride.

[0084] The properties of the first material layer 111 and the properties of the second material layer 113 can be changed. For example, the first material layer 111 can be Figure 4 The insulating material of the interlayer insulating layer ILD described above, the second material layer 113 may be Figure 4 The conductive materials of the conductive pattern layers CP1 to CPn are described.

[0085] Reference Figure 5B , a first mask pattern 121 having a first opening 125 may be formed on a stacked structure made of a first material layer 111 and a second material layer 113. A channel hole 115 may be formed through the first opening 125 of the first mask pattern 121, passing through the first material layer 111 and the second material layer 113. The depth of the channel hole 115 may extend "downward" into the first substrate 101 to a partial depth. The etching method and etching material used to form the channel hole 115 may determine the horizontal cross-sectional shape of the channel hole. Therefore, the horizontal cross-sectional shape may be made or formed into a circular or elliptical shape or even a rectangular shape.

[0086] In one method of forming the channel hole, the channel hole 115 may be formed using a first etching material. The first etching material may etch the first material layer 111 and the second material layer 113 faster than the first etching material may etch the first substrate 101. As a result, the width of the end of the channel hole 115 extending into the first substrate 101 may be formed to be narrower than the width of the channel hole 115 passing through the first material layer 111 and the second material layer 113.

[0087] Reference Figure 5C , a memory layer 137 and a channel structure 147 may be formed inside the channel hole 115 through a deposition process. Sidewalls of the channel structure 147 and ends of the channel structure 147 extending into the first substrate 101 may be surrounded by the memory layer 137.

[0088] Forming a memory "layer" 137 composed of materials deposited above the "vertical" surface of the channel hole 115 may include "stacking" a blocking insulating layer 135, a data storage layer 133, and a tunnel insulating layer 131 in sequence above the vertical surface of the channel hole 115. Therefore, the various layers "stacked" above the surface of the vertically oriented channel hole 115 can be viewed as thin cylinders, with the various layers continuously "lining" or covering the inner surface of the channel hole 115. Therefore, the memory layer 137 can be viewed as lining the channel hole. The blocking insulating layer 135, the data storage layer 133, and the tunnel insulating layer 131 can be the same as those described above with reference to Figure 4 The blocking insulating layer BI, the data storage layer DS and the tunnel insulating layer TI are described as being of the same material.

[0089] The channel structure 147 may be formed by forming a channel layer 141 on the inner surface of the innermost layer of the memory layer 137. The channel layer 141 may include a semiconductor layer serving as a channel region. For example, the channel layer 141 may include undoped polysilicon.

[0090] The channel layer 141 may also be viewed as providing a lining for a central region of the channel hole 115 , which may include a hollow portion or region not filled by the channel layer 141 , which is the void described above.

[0091] When the channel layer 141 is formed as a liner, forming the channel structure 147 can fill the central area of ​​the channel hole 115 with the core insulating layer 143 on the channel layer 141, and a void can be formed inside the core insulating layer 143. The void can be formed so that it extends upward in the Z direction from a height at or near the lower end of the channel hole 115 inside the first substrate 101 in the gate stack to the upper end of the channel hole 115, thereby passing through (i.e., extending through) both the first material layer 111 and the second material layer 113. For example, the void can be formed by extending from a height below the lowest source selection line in the gate stack to a height above the highest height of the gate stack. In other words, the void can be formed to extend from a height below the height of the subsequently formed source selection line to the height of the subsequently formed drain selection line.

[0092] During the process of filling the central region of the channel hole 115 with the core insulating layer 143, a void may be formed by first filling the open portion of the channel hole 115 before the lower end of the channel hole 115 is completely filled. Thereafter, a portion of the core insulating layer 143 may be etched to define a recessed region in a portion of the central region of the channel hole 115, and the recessed region may be filled with the doped semiconductor layer 145.

[0093] The core insulating layer 143 may be a metal oxide. The doped semiconductor layer 145 may be a conductive dopant. The conductive dopant may include an n-type dopant for junction and a p-type dopant for counter doping.

[0094] Reference Figure 5D , can be removed Figure 5C The first mask pattern 121 is shown followed by forming a first insulating layer 151. Slits 153 may then be formed.

[0095] The slit 153 may pass through the first insulating layer 151 , and may pass through the stacked structure of the first material layer 111 and the second material layer 113 . Figure 5D The slit 153 in corresponds to Figure 4 The slit SI shown.

[0096] The horizontal space 155 is created by selectively removing the second material layer 113 exposed through the slit 153. The horizontal space 155 thus created is located between the first material layers 111.

[0097] Reference Figure 5E , filling the slit 153 with the third material layer 157 Figure 5D The horizontal space 155 shown. The third material layer 157 is the above reference Figure 4 The third material layer 157 substantially “fills” the horizontal space 155 . The third material layer 157 also surrounds and contacts the sidewalls of the memory layer 137 and the channel structure 147 .

[0098] As described above, the gate stack 150 may be formed on the first substrate 101 by replacing the second material layer 113 as a sacrificial layer with the third material layer 157 as a conductive pattern layer. The gate stack 150 may include a structure in which the first material layer 111 is an interlayer insulating layer ILD and the third material layer 157 is a conductive pattern layer CPm. The ILD and CPm layers are alternately stacked on each other.

[0099] As described above, the gate stack 150 layer is penetrated by the channel structure 147. The channel structure 147 may extend into the first substrate 101. The memory layer 137 may extend from between the channel structure 147 and the gate stack 150 to between the end of the channel structure 147 and the first substrate 101.

[0100] The third material layers 157 including or "constituting" conductive pattern layers may be used as drain select lines SL, word lines WLm, and source select lines SSL. For example, one of the third material layers 157 formed as conductive pattern layers may be used as a source select line SSL.

[0101] Refer to the above FIG. 5A to FIG. 5E The process described above forms a first substrate 101 including Figure 2 The memory block of the plurality of cell strings CS1 and CS2 described above. Each cell string may include a drain selection transistor DST, memory cells MC1 to MCn, and a source selection transistor SST connected in series, as described above with reference to Figure 2 Described above. Figure 2 The drain selection transistor DST, the memory cells MC1 to MCn, and the source selection transistor SST described may be defined in Figure 5E The channel structure 147 shown is an intersection with the third material layer 157 as a conductive pattern layer, and can be connected in series through the channel structure 147 .

[0102] Next, a sidewall insulating layer 161 may be formed to cover the sidewalls of the gate stack 150 . Thereafter, a second insulating layer 163 filling the inside of the slit 153 and extending to cover the sidewall insulating layer 161 and the first insulating layer 151 may be formed.

[0103] Reference Fig. 5F , a third insulating layer 171 may be formed on the second insulating layer 163. Subsequently, a contact plug 173 may be formed through the third insulating layer 171 or through the third insulating layer 171 and the second insulating layer 163. The contact plug 173 may extend to contact the channel structure 147.

[0104] Subsequently, a first line array 175 may be formed. The first line array 175 may be a bit line connected to the contact plug 173. Thereafter, a first insulating structure 181 covering the first line array 175 may be formed. The first insulating structure 181 may include two or more insulating layers 181A to 181D. First connection structures 185, 189, 191, and 193 may be buried inside the first insulating structure 181, and the first connection structures 185, 189, 191, and 193 may be electrically connected through a contact plug (not shown).

[0105] The first connection structures 185, 189, 191, and 193 may be made of a first bonding metal 193. The connection structure preferably has a surface exposed to the outside of the first insulating structure 181.

[0106] Figure 6 is a vertical cross-sectional view of a portion of the lower portion U, illustrating the step of forming a complementary metal oxide semiconductor (CMOS) circuit and a second connection structure on a second substrate.

[0107] Reference Figure 6 , a plurality of transistors 200 configuring a CMOS circuit are formed on a second substrate 201 .

[0108] The second substrate 201 may be a bulk silicon substrate, a silicon-on-insulator substrate, a germanium substrate, a germanium-on-insulator substrate, a silicon-germanium substrate, or an epitaxial layer formed by a selective epitaxial growth method.

[0109] Each transistor 200 may be formed in an active region of a second substrate 201 separated by an isolation layer 203. Each transistor 200 may include a gate insulating layer 207 and a gate electrode 209 stacked on the active region corresponding thereto, and junctions 205a and 205b formed on both sides of the gate electrode 209 in the active region. The junctions 205a and 205b may include conductive dopants to implement the transistors corresponding thereto. The junctions 205a and 205b may include at least one of an n-type dopant or a p-type dopant.

[0110] After forming a plurality of transistors 200 , a second connection structure 220 connected to the transistors 200 configuring the CMOS circuit and a second insulation structure 211 covering the second connection structure 220 and the transistors 200 may be formed.

[0111] The second insulating structure 211 may include two or more insulating layers 211A to 211D. The second connection structure 220 may be buried in the second insulating structure 211. Each second connection structure 220 may include a plurality of conductive pattern layers 213, 215, 217, 219, 221, and 223. The second insulating structure 211 and the second connection structure 220 are not limited to the examples shown in the drawings and may be variously changed.

[0112] The conductive pattern layers 213 , 215 , 217 , 219 , 221 , and 223 included in each of the second connection structures 220 may include a second bonding metal 223 having a surface exposed outside the second insulation structure 211 .

[0113] Figure 7 is a vertical cross-sectional view of a gate stack, illustrating a step of bonding a first connection structure and a second connection structure to each other.

[0114] Reference Figure 7 The first substrate 101 and the second substrate 201 are aligned so that the first bonding metal 193 on the first substrate 101 and the second bonding metal 223 on the second substrate 201 can contact each other. The first bonding metal 193 and the second bonding metal 223 may include various metals, and may include, for example, copper.

[0115] Thereafter, the first bonding metal 193 and the second bonding metal 223 are bonded to each other. To this end, the first bonding metal 193 and the second bonding metal 223 may be hardened after heat is applied to the first bonding metal 193 and the second bonding metal 223. The present disclosure is not limited thereto, and various processes for connecting the first bonding metal 193 and the second bonding metal 223 may be introduced.

[0116] FIG. 8A to FIG. 8D is a vertical cross-sectional view showing a step of forming source lines connected to a plurality of cell strings on a gate stack 150 .

[0117] Reference Fig. 8A , can be removed Figure 7 The first substrate 101 is shown. When the first substrate 101 is removed, the memory layer 137 may be used as an etch stop layer. Therefore, the portion of the channel structure 147 that protrudes above the top surface 801 of the gate stack 150 may be protected by the memory layer 137.

[0118] In addition, during the process of removing the first substrate 101 , the thickness of the first material layer located at the uppermost portion of the gate stack 150 may be reduced.

[0119] Reference Figure 8B , by performing an ion implantation process while the portion of the channel structure 147 protruding above the “top” surface or uppermost surface of the gate stack is covered by the memory layer 137, dopants are implanted in the channel layer 141 serving as the channel of the source select transistor, thereby forming a junction region.

[0120] Due to the void inside the channel structure 147 of the region adjacent to the source selection transistor, ions implanted during the ion implantation process may pass through the channel layer 141, the core insulating layer 143, and the void, and may be implanted into a region other than the target region of the channel layer 141. In order to suppress the ion implantation, the ion implantation process is performed in a state where the protruding channel structure 147 is covered by the memory layer 137.

[0121] Thereafter, the junction region is activated by performing a local heat treatment process using a laser. The target region of the heat treatment process may include the junction region of the channel layer 141 where the dopant is implanted.

[0122] Reference Figure 8C , the channel layer 141 may be exposed by removing the memory layer 137 protruding above the gate stack 150. The exposed channel layer 141 may protrude above the top 801 of the gate stack 150. The upper surface height of the memory layer 137 may be equal to or less than the upper surface height of the gate stack 150.

[0123] Reference Fig.8D , forming a source layer 231 on the entire gate stack structure including the exposed surface of the channel layer 141 (at Figure 3 and Figure 4 The source layer 231 may have a single-layer or multi-layer structure. For example, the source layer 231 may include a first source layer and a second source layer, the first source layer may be formed of a doped polysilicon layer doped with a dopant, and the second source layer may be formed of a metal material having a low resistance. For example, the second source layer may be formed of titanium nitride (TiN) or tungsten (W) to reduce resistance. In addition, the second source layer may be formed using copper (Cu) and may be configured by further including tantalum (Ta) or tantalum nitride (TaN) as a barrier layer on the upper and lower surfaces of the second source layer.

[0124] 9A to 9D is a vertical cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present disclosure.

[0125] 9A to 9D is shown in reference FIG. 8A to FIG. 8D A vertical cross-sectional view of another embodiment of a process step for forming source lines connected to a plurality of cell strings on a gate stack 150 is depicted.

[0126] Reference Fig.9A , can be removed Figure 7 The first substrate 101 is shown. When the first substrate 101 is removed, the memory layer 137 can be used as an etch stop layer. Therefore, the channel structure 147 that protrudes "over" the gate stack 150 or protrudes "over" or "on top" of the gate stack 150 can be protected by the memory layer 137.

[0127] In addition, during the process of removing the first substrate 101 , the thickness of the first material layer located at the uppermost portion of the gate stack 150 may be reduced.

[0128] Reference Fig. 9B , the channel layer 141 may be exposed by removing the memory layer 137 protruding “above” or “beyond” the gate stack 150. The exposed channel layer 141 may protrude above the gate stack 150. The upper surface height of the memory layer 137 may be equal to or lower than the upper surface height of the gate stack 150.

[0129] Thereafter, spacers 233 are formed on the sides or “sidewalls” of the protruding portions of the channel structures 147. For example, the spacers 233 may be formed by forming a spacer layer along the surface of the protruding channel structures 147 and performing an etching process so that the spacer layer remains only on the sides or sidewalls of the protruding channel structures 147. The spacers 233 may be formed of polysilicon.

[0130] Reference Fig. 9C By performing an ion implantation process in a state where a spacer 233 is formed on a sidewall of the protruding channel structure 147 , a dopant is implanted in the channel layer 141 serving as a channel of the source select transistor, thereby forming a junction region.

[0131] Due to the void inside the channel structure 147 of the region adjacent to the source selection transistor, ions implanted during the ion implantation process may pass through the channel layer 141, the core insulating layer 143, and the void, and may be implanted into a region other than the target region of the channel layer 141. By forming the spacer 233 on the sidewall of the protruding channel structure 147, ions implanted during the ion implantation process may be prevented from passing through the channel structure 147 and being implanted into a region other than the target region.

[0132] Thereafter, the junction region is activated by performing a local heat treatment process using a laser. The target region of the heat treatment process may include the junction region of the channel layer 141 implanted with the dopant.

[0133] Reference Fig.9D , in removing Fig. 9C After forming the spacers 233 , a source layer 231 is formed on the entire structure including the exposed surface of the channel layer 141 .

[0134] The source layer 231 may have a single layer or a multilayer structure. For example, the source layer 231 may include a first source layer and a second source layer, the first source layer may be formed of a doped polysilicon layer doped with a dopant, and the second source layer may be formed of a metal material having a low resistance. For example, the second source layer may be formed of titanium nitride (TiN) or tungsten (W) to reduce resistance. In addition, the second source layer may be formed using copper (Cu), and may be configured by further including tantalum (Ta) or tantalum nitride (TaN) as a barrier layer on the upper and lower surfaces of the second source layer.

[0135] As another example, Fig. 9C The spacer 233 may remain and may be used as a first source layer.

[0136] FIG. 10A to FIG. 10D is a vertical cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present disclosure.

[0137] FIG. 10A to FIG. 10D is shown in reference FIG. 8A to FIG. 8D A vertical cross-sectional view of another embodiment of a process step for forming source lines connected to a plurality of cell strings on a gate stack 150 is depicted.

[0138] Reference Fig. 10A , can be removed Figure 7 The first substrate 101 is shown. When the first substrate 101 is removed, the memory layer 137 may be used as an etch stop layer. Therefore, the channel structure 147 protruding above the gate stack 150 may be protected by the memory layer 137.

[0139] In addition, during the process of removing the first substrate 101 , the thickness of the first material layer located at the uppermost portion of the gate stack 150 may be reduced.

[0140] Reference Fig. 10B , the channel layer 141 may be exposed by removing the memory layer 137 protruding above the gate stack 150. The exposed channel layer 141 may protrude above the gate stack 150. The upper surface height of the memory layer 137 may be equal to or lower than the upper surface height of the gate stack 150.

[0141] Thereafter, a first source layer 235 may be formed along the entire surface including the protruding channel structure 147. The first source layer 235 may be formed of a doped polysilicon layer doped with a dopant. Since the first source layer 235 is formed along the surface of the protruding channel structure 147, the first source layer 235 may include a portion extending in a vertical direction along the sidewall of the protruding channel structure 147.

[0142] Thereafter, a spacer 237 is formed on a sidewall of the first source layer 235 extending in a vertical direction along a sidewall of the protruding channel structure 147. The spacer 237 may be formed of an oxide layer.

[0143] Reference Fig. 10C By performing an ion implantation process in a state where the first source layer 235 and the spacer 237 are formed on the sidewalls of the protruding channel structure 147 , dopants are implanted in the channel layer 141 serving as a channel of the source select transistor, thereby forming a junction region.

[0144] Due to the void inside the channel structure 147 of the region adjacent to the source select transistor, ions implanted during the ion implantation process may pass through the channel layer 141, the core insulating layer 143, and the void, and may be implanted into a region other than the target region of the channel layer 141. By forming the first source layer 235 and the spacer 237 on the sidewall of the protruding channel structure 147, ions implanted during the ion implantation process may be prevented from passing through the channel structure 147 and being implanted into a region other than the target region.

[0145] Thereafter, the junction region is activated by performing a local heat treatment process using a laser. The target region of the heat treatment process may include the junction region of the channel layer 141 implanted with the dopant.

[0146] Reference Fig. 10D , in removing Fig. 10C After forming the spacer 237 , a second source layer 239 is formed on the first source layer 235 .

[0147] The second source layer 239 may be formed of a metal material having low resistance. For example, the second source layer 239 may be formed of titanium nitride (TiN) or tungsten (W) to reduce resistance. In addition, the second source layer 239 may be formed using copper (Cu) and may be configured by further including tantalum (Ta) or tantalum nitride (TaN) as a barrier layer on the upper and lower surfaces of the second source layer.

[0148] FIG. 11A to FIG. 11D is a vertical cross-sectional view illustrating a method of manufacturing a semiconductor memory device according to another embodiment of the present disclosure.

[0149] FIG. 11A to FIG. 11D is shown in reference FIG. 8A to FIG. 8D A vertical cross-sectional view of another embodiment of a process step for forming source lines connected to a plurality of cell strings on a gate stack 150 is depicted.

[0150] Reference Fig.11A , can be removed Figure 7The first substrate 101 is shown. When the first substrate 101 is removed, the memory layer 137 may be used as an etch stop layer. Therefore, the channel structure 147 protruding above the gate stack 150 may be protected by the memory layer 137.

[0151] In addition, during the process of removing the first substrate 101 , the thickness of the first material layer located at the uppermost portion of the gate stack 150 may be reduced.

[0152] Reference Fig. 11B The data storage layer 133 is exposed by removing the outermost blocking insulating layer 135 located at the memory layer 137 protruding above the gate stack 150 and exposed.

[0153] Thereafter, a spacer 233 is formed on the exposed data storage layer 133. The spacer 233 may be formed according to an area selective deposition (ASD) method. The spacer 233 may include silicon oxycarbide (SiOC).

[0154] Reference Fig. 11C , by performing an ion implantation process in a state where a tunnel insulating layer 131 , a data storage layer 133 , and a spacer 233 are formed on the sidewalls of the protruding channel structure 147 , dopants are implanted in the channel layer 141 serving as a channel of the source select transistor, thereby forming a junction region.

[0155] Due to the void inside the channel structure 147 of the region adjacent to the source selection transistor, ions implanted during the ion implantation process may pass through the channel layer 141, the core insulating layer 143, and the void, and may be implanted into a region other than the target region of the channel layer 141. By performing the ion implantation process in a state where the tunnel insulating layer 131, the data storage layer 133, and the spacer 233 are formed on the sidewalls of the protruding channel structure 147, ions may be prevented from passing through the channel structure 147 and being implanted into a region other than the target region.

[0156] Thereafter, the junction region is activated by performing a local heat treatment process using a laser. The target region of the heat treatment process may include the junction region of the channel layer 141 implanted with the dopant.

[0157] Reference Fig.11D , remove Fig. 11C Thereafter, the exposed data storage layer 133 and the tunnel insulating layer 131 are removed to expose the channel structure 147 protruding above the gate stack 150.

[0158] Thereafter, a source layer 231 is formed on the entire structure including the protruding channel structure 147 .

[0159] The source layer 231 may have a single layer or a multilayer structure. For example, the source layer 231 may include a first source layer and a second source layer, the first source layer may be formed of a doped polysilicon layer doped with a dopant, and the second source layer may be formed of a metal material having a low resistance. For example, the second source layer may be formed of titanium nitride (TiN) or tungsten (W) to reduce resistance. In addition, the second source layer may be formed using copper (Cu), and may be configured by further including tantalum (Ta) or tantalum nitride (TaN) as a barrier layer on the upper and lower surfaces of the second source layer.

[0160] Fig.12 11 is a block diagram showing a configuration of a memory system 1100 according to an embodiment of the present disclosure.

[0161] Reference Fig.12 , the memory system 1100 includes a semiconductor memory device 1120 and a memory controller 1110 .

[0162] The semiconductor memory device 1120 may be a multi-chip package configured by a plurality of flash memory chips. Figures 1 to 4 A semiconductor memory device is described.

[0163] The memory controller 1110 may be configured to control the semiconductor memory device 1120, and may include a static random access memory (SRAM) 1111, a central processing unit (CPU) 1112, a host interface 1113, an error correction block 1114, and a memory interface 1115. The SRAM 1111 is used as an operation memory of the CPU 1112, the CPU 1112 performs an overall control operation for data exchange of the memory controller 1110, and the host interface 1113 includes a data exchange protocol of a host connected to the memory system 1100. In addition, the error correction block 1114 detects and corrects errors included in data read from the semiconductor memory device 1120, and the memory interface 1115 performs an interface with the semiconductor memory device 1120. In addition, the memory controller 1110 may further include a read-only memory (ROM) storing code data for interfacing with the host.

[0164] The above-mentioned memory system 1100 may be a memory card or a solid state disk (SSD) in which the semiconductor memory device 1120 and the memory controller 1110 are combined. For example, when the memory system 1100 is an SSD, the memory controller 1110 may communicate with the outside (e.g., a host) through one of various interface protocols such as a universal serial bus (USB), a multimedia card (MMC), a peripheral component interconnect-express (PCI-E), a serial advanced technology attachment (SATA), a parallel advanced technology attachment (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESD), and an integrated drive electronics (IDE).

[0165] Fig.13 is a block diagram showing a configuration of a computing system according to an embodiment.

[0166] Reference Fig.13 The computing system 1200 according to an embodiment or the present disclosure may include a CPU 1220 electrically connected to a system bus 1260, a random access memory (RAM) 1230, a user interface 1240, a modem 1250, and a memory system 1210. In addition, when the computing system 1200 is a mobile device, a battery for supplying an operating voltage to the computing system 1200 may be further included, and an application chipset, a camera image processor (CIS), a mobile DRAM, and the like may be further included.

[0167] The computing system 1200 may further include a memory system 1210 , and the memory system 1210 may include a memory controller 1211 and a semiconductor memory device 1212 .

[0168] The memory controller 1211 is configured to control the semiconductor memory device 1212, and the semiconductor memory device 1212 may be a multi-chip package configured by a plurality of flash memory chips. Figures 1 to 4 A semiconductor memory device is described.

[0169] Although the detailed description of the present disclosure describes specific embodiments, various changes and modifications may be made without departing from the scope and technical spirit of the present disclosure. Therefore, the scope of the present disclosure should not be limited to the above embodiments, but should be determined by the equivalents of the claims of the present disclosure and the following claims.

[0170] CROSS-REFERENCE TO RELATED APPLICATIONS

[0171] This application claims the priority of Korean Patent Application No. 10-2023-0163379 filed on November 22, 2023 in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor memory device, comprising: A gate stack comprising interlayer insulating layers and conductive pattern layers alternately stacked in a first direction, wherein the alternately stacked interlayer insulating layers and conductive pattern layers are supported by a substrate; a channel structure extending through the gate stack in the first direction, the channel structure having a protruding end extending above a top surface of the gate stack; a memory layer surrounding the channel structure; as well as a source layer formed on the gate stack, Wherein, the channel structure comprises: a core insulation layer having a hollow central region and including voids; and a channel layer surrounding the core insulating layer, The gap in the core insulating layer extends upward along the first direction from a height lower than the lowest conductive pattern layer to a height higher than the highest conductive pattern layer.

2. The semiconductor memory device according to claim 1, wherein The source layer comprises: a first source layer formed on an upper portion of the gate stack and around the protruding end of the channel structure; and A second source layer is formed on the first source layer.

3. The semiconductor memory device according to claim 2, wherein: At least a portion of the first source layer contacts an upper portion of the channel layer.

4. The semiconductor memory device according to claim 2, wherein: The first source layer is doped polysilicon.

5. The semiconductor memory device according to claim 2, wherein: The second source layer is a low-resistance metal.

6. The semiconductor memory device according to claim 1, wherein: The channel layer includes a junction in a region adjacent to at least one conductive pattern layer corresponding to a source select line.

7. A method for manufacturing a semiconductor memory device, the method comprising the steps of: A memory cell array is formed on a first substrate, the memory cell array comprising: a gate stack including interlayer insulating layers and conductive pattern layers alternately stacked on each other; The memory cell array further includes a core insulating layer orthogonally passing through a layer including the gate stack and having an end portion extending into the first substrate; a channel layer surrounding the sidewalls and the end of the core insulating layer; and a memory layer extending from between the channel layer and the gate stack to between an end of the channel layer and the first substrate, The method further comprises the following steps: removing the first substrate to expose the memory layer; forming a junction at an upper end of the channel layer by performing an ion implantation process; and An end portion of the channel layer is exposed by etching the exposed memory layer.

8. The method according to claim 7, wherein: The step of forming the memory cell array further includes forming a void extending upward through the gate stack from a height below a lowermost conductive pattern layer in the gate stack to a height above a top surface of the gate stack.

9. The method according to claim 7, further comprising the steps of: The junction is activated by performing a local heat treatment process using a laser after the ion implantation process.

10. The method according to claim 7, further comprising the steps of: After exposing the end portion of the channel layer, a source layer is formed on the entire structure including the exposed end portion of the channel layer.

11. The method according to claim 10, wherein: The step of forming the source layer comprises the following steps: forming a first source layer on the entire structure including the exposed end portion of the channel layer; and A second source layer is formed on the first source layer.

12. The method according to claim 11, wherein: The first source layer is doped polysilicon, and the second source layer is a low resistance metal.

13. A method for manufacturing a semiconductor memory device, the method comprising the steps of: A memory cell array is formed on a first substrate, the memory cell array comprising: a gate stack including interlayer insulating layers and conductive pattern layers alternately stacked in a vertical direction; a core insulating layer passing through the gate stack and having an end extending into the first substrate; a channel layer surrounding the sidewalls and the end of the core insulating layer; and a memory layer extending from between the channel layer and the gate stack to between an end of the channel layer and the first substrate, The method further comprises the following steps: removing the first substrate to expose the memory layer; exposing an end of the channel layer by removing the exposed memory layer; forming a spacer on a sidewall of an end portion of the channel layer; and A junction is formed at an upper end of the channel layer by performing an ion implantation process.

14. The method according to claim 13, wherein: The step of forming the spacer comprises the following steps: forming a spacer layer on the entire structure including an end portion of the channel layer; and An etching process is performed so that the spacer layer remains only on the end sidewalls of the channel layer.

15. The method according to claim 13, wherein: The spacer includes polysilicon.

16. The method according to claim 13, further comprising the steps of: After forming the junction, a source layer is formed on the entire structure including an end portion of the channel layer.

17. The method according to claim 16, further comprising the steps of: Before forming the source layer, the spacer is removed.

18. A method for manufacturing a semiconductor memory device, the method comprising the steps of: forming a memory cell array on a first substrate so that the memory cell array includes a gate stack including an interlayer insulating layer and a conductive pattern layer alternately stacked in a vertical direction, a core insulating layer passing through the gate stack and having an end extending into the first substrate, a channel layer surrounding a sidewall and the end of the core insulating layer, and a memory layer extending from between the channel layer and the gate stack to between the end of the channel layer and the first substrate; The method further comprises the following steps: removing the first substrate to expose the memory layer; exposing an end of the channel layer by removing the exposed memory layer; forming a first source layer along a surface of the entire structure including an exposed end portion of the channel layer; forming a spacer on a side wall of the first source layer extending in the vertical direction along a side wall of an end portion of the channel layer; and A junction is formed at an upper end of the channel layer by performing an ion implantation process.

19. The method according to claim 18, wherein: The spacer is a metal oxide.

20. The method according to claim 18, further comprising the steps of: After forming the junction, removing the spacer; and A second source layer is formed on the first source layer.

21. The method according to claim 20, wherein: The first source layer is doped polysilicon, and the second source layer is a low resistance metal.

22. A method for manufacturing a semiconductor memory device, the method comprising the steps of: forming a memory cell array on a first substrate so that the memory cell array includes a gate stack including an interlayer insulating layer and a conductive pattern layer alternately stacked in a vertical direction, a core insulating layer passing through the gate stack and having an end extending into the first substrate, a channel layer surrounding a sidewall and the end of the core insulating layer, and a memory layer configured by a blocking insulating layer extending from between the channel layer and the gate stack to between the end of the channel layer and the first substrate, a data storage layer, and a tunnel insulating layer; removing the first substrate to expose the memory layer; exposing the data storage layer by removing the blocking insulating layer of the exposed memory layer; forming a spacer on a surface of the data storage layer; as well as A junction is formed at an upper end of the channel layer by performing an ion implantation process.

23. The method according to claim 22, wherein: The spacer is formed by an area selective deposition (ASD) method.

24. The method according to claim 22, wherein: The spacer includes silicon oxycarbide SiOC.

25. The method according to claim 22, further comprising the steps of: After forming the junction, removing the spacer; exposing an end portion of the channel layer by removing the exposed data storage layer and the tunnel insulating layer; and A source layer is formed on the entire structure including an end portion of the channel layer.

26. The method according to claim 25, wherein: The step of forming the source layer comprises the following steps: forming a first source layer on the entire structure including the exposed end portion of the channel layer; and A second source layer is formed on the first source layer.

27. The method according to claim 26, wherein: The first source layer is doped polysilicon, and the second source layer is a low resistance metal.

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