Memory device and manufacturing method thereof

Abstract

The invention provides a memory device and a manufacturing method thereof. The memory device includes: a semiconductor substrate having a first surface; the plurality of conductive connecting parts extend into the semiconductor substrate from the first surface, and any two adjacent conductive connecting parts are arranged at intervals; the spin-orbit torque layers are arranged on the sides, away from the semiconductor substrate, of the conductive connecting parts at intervals, and each spin-orbit torque layer is connected with at least two adjacent conductive connecting parts in series; and the plurality of magnetic tunnel junctions are positioned on one side, far away from the conductive connecting part, of the spin-orbit torque layer, and the plurality of magnetic tunnel junctions are in one-to-one correspondence with the plurality of spin-orbit torque layers. According to the invention, in the process of forming the magnetic tunnel junction, over-etching can be carried out on the magnetic tunnel junction and over-etching can be carried out on the spin-orbit torque layer without stopping on the spin-orbit torque layer, so that an etching window is enlarged, and the etching yield of a device can be improved.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a memory device and a manufacturing method thereof. Background Art

[0002] SOT-MTJ devices are one of the core structural types of MRAM products. Compared with STT-MTJ devices, SOT-MTJ devices have the characteristics of fast writing speed, unlimited erasing and read-write separation. An obvious structural feature of SOT-MTJ devices is that there is a SOT track layer with a thickness of only a few nanometers under the free layer of the magnetic tunnel junction. The SOT track layer provides an independent channel for the write current and read-write separation. However, due to the limitation of the SOT track layer on MTJ etching (etching needs to stop at the SOT track layer), the current SOT-MRAM industrialization still faces the following problems:

[0003] 1. When performing MTJ etching, it is necessary to stop precisely at the SOT track layer. The etching window is too small, resulting in low device yield due to redeposition.

[0004] 2. The width and length of the useless SOT track layers on both sides of the MTJ result in low writing efficiency;

[0005] 3. SOT-MRAM has a 2T1R structure (where 2T stands for two transistors and 1R stands for a resistor), and the current required for the SOT track layer write channel is relatively large. Too large a transistor leads to an excessively large bit area.

[0006] Therefore, a new storage device is urgently needed to solve at least one of the above technical problems. Summary of the invention

[0007] The main purpose of the present invention is to provide a memory device and a method for manufacturing the same, so as to solve at least one of the problems of smaller etching window, larger bit cell area and smaller component density in the prior art.

[0008] In order to achieve the above-mentioned purpose, according to one aspect of the present invention, there is provided a storage device, comprising: a semiconductor substrate having a first surface; a plurality of conductive connection parts extending from the first surface into the semiconductor substrate, and any two adjacent conductive connection parts are arranged at intervals; a plurality of spin-orbit torque layers are arranged at intervals on a side of the conductive connection part away from the semiconductor substrate, and each spin-orbit torque layer connects at least two adjacent conductive connection parts in series; a plurality of magnetic tunnel junctions are located on a side of the spin-orbit torque layer away from the conductive connection part, and the plurality of magnetic tunnel junctions correspond one-to-one to the plurality of spin-orbit torque layers.

[0009] Further, the conductive connection portion has an exposed surface located in the first surface, and the spin-orbit torque layer has a second surface close to the conductive connection portion, and the second surface covers a portion of the exposed surface.

[0010] Further, the exposed surface and the second surface have an overlapping area, and the ratio of the overlapping area to the area of ​​the second surface is less than or equal to 60%.

[0011] Furthermore, the multiple conductive connection parts include a first conductive channel, a second conductive channel and at least one connection part, and the at least one connection part is located between the first conductive channel and the second conductive channel. The storage device also includes: a first bottom electrode, located on a side of the first conductive channel away from the spin-orbit torque layer; and a second bottom electrode, located on a side of the second conductive channel away from the spin-orbit torque layer.

[0012] Further, the material of the connecting portion includes ferromagnetic material.

[0013] Furthermore, the storage device also includes: multiple hard mask layers, located on a side of the magnetic tunnel junction away from the spin-orbit torque layer, and the multiple hard mask layers correspond one-to-one to the multiple magnetic tunnel junctions; multiple first electrode structures, located on a side of the hard mask layer away from the magnetic tunnel junction, and the multiple first electrode structures correspond one-to-one to the multiple hard mask layers.

[0014] Furthermore, the materials of the plurality of spin-orbit torque layers are independently selected from any one of heavy metal materials, antiferromagnetic materials and topological materials.

[0015] Further, in the case where the magnetic tunnel junction is a perpendicularly magnetized magnetic tunnel junction, a vertical projection of the magnetic tunnel junction on the first surface is any one of a circle, an ellipse and a rectangle.

[0016] Further, in the case where the magnetic tunnel junction is an in-plane magnetized magnetic tunnel junction, a vertical projection of the magnetic tunnel junction on the first surface is an ellipse or a rectangle.

[0017] According to another aspect of the present invention, a method for manufacturing a memory device is provided, comprising: providing a semiconductor substrate having a first surface; forming a plurality of conductive connection portions spaced apart on the first surface, the plurality of conductive connection portions extending from the first surface into the semiconductor substrate; forming a plurality of spin-orbit torque layers spaced apart on a side of the conductive connection portions away from the semiconductor substrate, and the plurality of spin-orbit torque layers connecting the plurality of conductive connection portions in series; forming a plurality of magnetic tunnel junctions on a side of the spin-orbit torque layer away from the conductive connection portions, and the plurality of magnetic tunnel junctions correspond one-to-one to the plurality of spin-orbit torque layers.

[0018] Furthermore, the step of forming multiple spin-orbit torque layers and multiple magnetic tunnel junctions includes: sequentially forming stacked spin-orbit torque material layers and magnetic storage material layers on the first surface of the semiconductor substrate; removing part of the spin-orbit torque material layer and part of the magnetic storage material layer located on the side of each conductive connection away from the semiconductor substrate, so that the remaining spin-orbit torque material layer forms a spin-orbit torque layer, and so that the remaining magnetic storage material layer forms a magnetic tunnel junction, and each spin-orbit torque layer is connected in series to at least two adjacent conductive connections.

[0019] By applying the technical solution of the present invention, a storage device is provided, which may include a plurality of conductive connection parts arranged in pairs, a plurality of spin-orbit moment layers arranged in pairs, and a plurality of magnetic tunnel junctions arranged in pairs, wherein the number of the plurality of magnetic tunnel junctions is consistent with the number of the plurality of spin-orbit moment layers, the plurality of conductive connection parts extend from a first surface into a semiconductor substrate, the plurality of spin-orbit moment layers are arranged on a side of the conductive connection parts away from the semiconductor substrate, and the plurality of spin-orbit moment layers are connected in series to at least two adjacent conductive connection parts, so that through the present application, in the process of forming a magnetic tunnel junction, it is not necessary to stop on the spin-orbit moment layer, that is, the magnetic tunnel junction can be over-etched and the spin-orbit moment layer can be etched, thereby increasing the etching window and improving the etching yield of the device. Furthermore, since each magnetic tunnel junction can correspond to a spin-orbit torque layer, the width and length of the spin-orbit torque layers on both sides of the magnetic tunnel junction can be reduced, so that the size of the magnetic tunnel junction and the spin-orbit torque layer is similar, and the resistance of the adjacent region of the adjacent magnetic tunnel junction is reduced, thereby improving the write efficiency of the storage device and reducing the write current of the storage device. Furthermore, through the present application, the number of CMOS of the storage device can also be reduced, thereby saving the area of ​​the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the accompanying drawings:

[0021] Figure 1 A schematic diagram showing a cross-sectional structure of a memory device according to an embodiment of the present invention is shown.

[0022] Figure 2 A schematic cross-sectional structure diagram of a memory device according to another embodiment of the present invention is shown;

[0023] Figure 3 Shows the formation Figure 1 A schematic cross-sectional structure diagram of a substrate having a first bottom electrode and a second bottom electrode is provided in the manufacturing method of the memory device shown;

[0024] Figure 4 Shown in Figure 3 A schematic cross-sectional structure diagram of a plurality of conductive connection parts formed on the substrate shown;

[0025] Figure 5 Shown in Figure 4 A schematic cross-sectional structure diagram of a spin-orbit torque material layer, a magnetic storage material layer and a hard mask material layer formed on a first surface of a semiconductor substrate shown;

[0026] Figure 6 Shown in Figure 5 A schematic cross-sectional structure diagram of etching a spin-orbit torque layer, a magnetic tunnel junction and a hard mask layer on a substrate shown;

[0027] Figure 7 Shown in Figure 6 A schematic cross-sectional structure diagram of an insulating protective layer and a dielectric protective layer formed on the substrate shown;

[0028] Figure 8 Shown in Figure 7 A schematic cross-sectional structure diagram of an electrode material layer formed on a substrate shown;

[0029] Fig. 9 Shown in Figure 8 A schematic cross-sectional structure diagram of a first electrode structure formed on a substrate is shown.

[0030] The above drawings include the following reference numerals:

[0031] 1011, first bottom electrode; 1012, second bottom electrode; 102, insulating dielectric layer; 1031, first conductive channel; 1032, second conductive channel; 104, connecting portion; 105, spin-orbit torque material layer; 1051, spin-orbit torque layer; 106, magnetic storage material layer; 1061, magnetic tunnel junction; 107, hard mask material layer; 1071, hard mask layer; 108, insulating protection layer; 109, dielectric protection layer; 110, electrode material layer; 1101, first electrode structure; 111, top interconnect structure; 30, first conductive portion; 31, second conductive portion; 32, third conductive portion. DETAILED DESCRIPTION

[0032] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0033] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0034] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present invention described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0035] As described in the background technology, in the prior art, due to the limitation of the SOT track layer on MTJ etching (etching needs to stop at the SOT track layer), the current SOT-MRAM industrialization still faces at least one of the following problems: when performing MTJ etching, it is necessary to stop precisely at the SOT track layer, so the etching window is too small, which can easily cause the device yield to be low due to redeposition (redep); or the width and length of the useless SOT track layer on both sides of the MTJ lead to low writing efficiency; and SOT-MRAM is a 2T1R (where 2T represents two transistors (Transistor) and 1R represents a resistor (Resistor)) structure, and the current required for the SOT track layer write channel is large, and the transistor is too large, resulting in a large bit area. In order to solve at least one technical problem among the above problems, the present application provides a memory device and a method for manufacturing the same.

[0036] According to one aspect of the present application, a storage device is provided, such as Figure 1As shown, the storage device includes: a semiconductor substrate having a first surface; a plurality of conductive connection parts 100 extending from the first surface into the semiconductor substrate, and any two adjacent conductive connection parts 100 are arranged at intervals; a plurality of spin-orbit torque layers 1051 are arranged at intervals on a side of the conductive connection part 100 away from the semiconductor substrate, and each spin-orbit torque layer 1051 connects at least two adjacent conductive connection parts 100 in series; a plurality of magnetic tunnel junctions 1061 are located on a side of the spin-orbit torque layer 1051 away from the conductive connection part 100, and the plurality of magnetic tunnel junctions 1061 correspond one-to-one to the plurality of spin-orbit torque layers 1051.

[0037] Specifically, the plurality of conductive connection parts 100 in the above-mentioned memory device may include two, three or more.

[0038] Specifically, each of the plurality of conductive connection portions 100 extends from the first surface of the semiconductor substrate into the semiconductor substrate, and any two of the plurality of conductive connection portions 100 are spaced apart and independent of each other.

[0039] Specifically, in a direction perpendicular to the first surface, the extension lengths of any two conductive connection parts 100 among the plurality of conductive connection parts 100 may be the same or different.

[0040] Optionally, the plurality of conductive connecting parts 100 may be arranged at intervals along the same direction. For example, when the plurality of conductive connecting parts 100 include three, the plurality of conductive connecting parts 100 have a plurality of exposed surfaces located in the first surface, and the plurality of exposed surfaces may be distributed on the same straight line. Alternatively, when the plurality of conductive connecting parts 100 include four spaced apart, the plurality of exposed surfaces of the plurality of conductive connecting parts 100 in the first surface may be distributed on the same straight line. It should be noted that the plurality of conductive connecting parts 100 include but are not limited to the two, three and four given above, and may also be more.

[0041] Optionally, the plurality of conductive connecting parts 100 may be arranged at intervals along a plurality of different directions. For example, when the plurality of conductive connecting parts 100 include three arranged at intervals, the plurality of conductive connecting parts 100 have a plurality of exposed surfaces located in the first surface, and the plurality of exposed surfaces may be distributed on different sides of a triangle; or for example, when the plurality of conductive connecting parts 100 include four arranged at intervals, the plurality of exposed surfaces of the plurality of conductive connecting parts 100 in the first surface may be distributed in an array in the first surface. It should be noted that the plurality of conductive connecting parts 100 include but are not limited to the two, three and four given above, and may also be more.

[0042] Specifically, each spin-orbit torque layer 1051 is located on a side of any conductive connection portion 100 away from the semiconductor substrate, and each spin-orbit torque layer 1051 contacts any two spaced-apart spin-orbit torque layers 1051 , thereby connecting the above-mentioned any two spaced-apart spin-orbit torque layers 1051 in series.

[0043] Exemplarily, when a storage device includes two conductive connecting parts 100, the storage device may include a spin-orbit torque layer 1051, and the spin-orbit torque layer 1051 is connected in series with the two conductive connecting parts 100; when a storage device includes three conductive connecting parts 100 arranged at intervals, the storage device may include two spin-orbit torque layers 1051 arranged at intervals, and only one of the conductive connecting parts 100 is contacted and connected by the two spin-orbit torque layers 1051 arranged at intervals at the same time, so that the two spin-orbit torque layers 1051 arranged at intervals are connected in series. The spin-orbit torque layer 1051 is connected in series to the three conductive connection parts 100 set at intervals. When a storage device includes four conductive connection parts 100 set at intervals, the storage device may include three spin-orbit torque layers 1051 set at intervals, and only each different conductive connection part 100 in two conductive connection parts 100 set at intervals is contacted and connected by the two spin-orbit torque layers 1051 set at intervals at the same time, so that the three spin-orbit torque layers 1051 set at intervals are connected in series to the four conductive connection parts 100 set at intervals.

[0044] Optionally, when a storage device includes four conductive connection parts 100 arranged at intervals, the storage device may also include two spin-orbit torque layers 1051 arranged at intervals, and only one conductive connection part 100 is contacted and connected by the two spin-orbit torque layers 1051 arranged at intervals at the same time, so that the two spin-orbit torque layers 1051 arranged at intervals are connected in series to the four conductive connection parts 100 arranged at intervals.

[0045] It should be noted that the above-mentioned multiple conductive connecting parts 100 include but are not limited to the two, three and four given above, and can also be more. Correspondingly, the above-mentioned spin-orbit torque layer 1051 can include but are not limited to the one, two and three given above, and can also be more.

[0046] Specifically, in a memory device, the number of magnetic tunnel junctions 1061 can be consistent with the number of spin-orbit torque layers 1051, and the vertical projection of each magnetic tunnel junction 1061 can be located on the side surface of the spin-orbit torque layer 1051 away from the conductive connection 100. It can be understood that the vertical projection can completely overlap with the side surface of the spin-orbit torque layer 1051 away from the conductive connection 100, or the area of ​​the vertical projection can be smaller than the area of ​​the side surface of the spin-orbit torque layer 1051 away from the conductive connection 100.

[0047] In the above embodiment, a storage device may include a plurality of conductive connection parts 100 arranged at intervals of two, a plurality of spin-orbit torque layers 1051 arranged at intervals of two, and a plurality of magnetic tunnel junctions 1061 arranged at intervals of two. The number of the plurality of magnetic tunnel junctions 1061 is consistent with the number of the plurality of spin-orbit torque layers 1051. The plurality of conductive connection parts 100 extend from the first surface into the semiconductor substrate. The plurality of spin-orbit torque layers 1051 are arranged on a side of the conductive connection part 100 away from the semiconductor substrate, and the plurality of spin-orbit torque layers 1051 are connected in series to at least two adjacent conductive connection parts 100. Thus, through the present application, in the process of forming the magnetic tunnel junction 1061, there is no need to stop on the spin-orbit torque layer 1051, that is, the magnetic tunnel junction 1061 can be over-etched and the spin-orbit torque layer 1051 can be over-etched, thereby increasing the etching window and improving the etching yield of the device. Furthermore, since each magnetic tunnel junction 1061 may correspond to a spin-orbit torque layer 1051, the width and length of the spin-orbit torque layer 1051 on both sides of the magnetic tunnel junction 1061 may be reduced, so that the size of the magnetic tunnel junction 1061 and the spin-orbit torque layer 1051 are similar, and the resistance of the adjacent region of the adjacent magnetic tunnel junction 1061 is reduced, thereby improving the write efficiency of the storage device and reducing the write current of the storage device. Furthermore, through the present application, the number of CMOS of the storage device can also be reduced, thereby saving the area of ​​the storage device.

[0048] In order to make each spin-orbit torque layer 1051 connect in series at least two conductive connection parts 100 arranged at intervals, as shown in FIG. Figure 1 As shown, in some optional embodiments, the conductive connection part 100 has an exposed surface located in the first surface, and the spin-orbit torque layer 1051 has a second surface close to the conductive connection part 100, and the second surface covers a portion of the exposed surface.

[0049] Wherein, on the basis of the second surface covering part of the exposed surface, in order to make the memory device more easily electrically flipped, in some optional embodiments, the exposed surface and the second surface have an overlapping area, and the ratio of the overlapping area to the area of ​​the second surface is less than or equal to 60%. It should be noted that the overlapping area described in this embodiment is the sum of the exposed surfaces of the two spin-orbit torque layers 1051 covered by the same spin-orbit torque layer 1051.

[0050] Alternatively, if Figure 1 As shown, in order to connect multiple magnetic tunnel junctions 1061 in the storage device in series and realize data writing of the storage device, in some optional embodiments, the multiple conductive connection parts 100 include a first conductive channel 1031, a second conductive channel 1032 and at least one connection part 104, at least one connection part 104 is located between the first conductive channel 1031 and the second conductive channel 1032, and the storage device also includes: a first bottom electrode 1011, located on the side of the first conductive channel 1031 away from the spin-orbit torque layer 1051; a second bottom electrode 1012, located on the side of the second conductive channel 1032 away from the spin-orbit torque layer 1051.

[0051] Specifically, in the case where the above-mentioned connecting portion 104 includes multiple connecting portions 104, the multiple connecting portions 104 can be connected in series through multiple spin-orbit torque layers 1051, and the multiple connecting portions 104 connected in series by multiple spin-orbit torque layers 1051 include two connecting portions 104 connected in series to two different ends, that is, one connecting portion 104 connected in series to one of the ends can be connected in series to the above-mentioned first conductive channel 1031 through a spin-orbit torque layer 1051, and the other connecting portion 104 connected in series to the other end can be connected in series to the above-mentioned second conductive channel 1032 through a spin-orbit torque layer 1051.

[0052] Among them, on the basis that the above-mentioned multiple conductive connection parts 100 include the first conductive channel 1031, the second conductive channel 1032 and at least one connection part 104, in order to realize the zero magnetic field reversal of the magnetic tunnel junction 1061, in some optional embodiments, the material of the connection part 104 may include a ferromagnetic material. In addition, it is easy to think that in order to simplify the manufacturing process of the memory device, in other embodiments, the materials of the above-mentioned multiple conductive connection parts 100 may all include a ferromagnetic material. Exemplarily, on the basis that the above-mentioned multiple conductive connection parts 100 include the first conductive channel 1031, the second conductive channel 1032 and at least one connection part 104, the materials of the above-mentioned first conductive channel 1031 and the second conductive channel 1032 may also include a ferromagnetic material. Exemplarily, the above-mentioned ferromagnetic material may include but is not limited to iron (Fe), nickel (Ni), cobalt (Co), cobalt iron (CoFe), cobalt iron boron (CoFeB), nickel iron (NiFe), iron chromium cobalt (FeCrCo), aluminum nickel cobalt (AlNiCo) and neodymium iron boron (NdFeB), etc.

[0053] In other optional embodiments, such as Figure 2As shown, on the basis that the plurality of conductive connection parts 100 include a first conductive channel 1031, a second conductive channel 1032 and at least one connection part 104, and the memory device further includes a first bottom electrode 1011 and a second bottom electrode 1012, so that the first bottom electrode 1011 is located on a side of the first conductive channel 1031 away from the spin-orbit moment layer 1051, and the second bottom electrode 1012 is located on a side of the second conductive channel 1032 away from the spin-orbit moment layer 1051, in order to further reduce the distance between the first conductive channel 1031 and the connection part 104 close to the first conductive channel 1031, and reduce the size of the spin-orbit moment layer 1051 of the first conductive channel 1031 and the connection part 104 close to the first conductive channel 1031 connected in series, the first conductive channel 1031 may include a first conductive part 30, a second conductive part 31 and a third conductive part 32 that are electrically connected, wherein the first conductive part 30 is in direct contact with the first bottom electrode 1011, and the The first vertical projection of the first conductive portion 30 on the first bottom electrode 1011 is located in the surface of the first bottom electrode 1011, the second conductive portion 31 can be located on a side of the first conductive portion 30 away from the first bottom electrode 1011, and on the same horizontal plane as the surface of the first bottom electrode 1011 on the side close to the first conductive portion 30, the second conductive portion 31 has a second vertical projection on the horizontal plane, at least part of the second vertical projection is located outside the side surface of the first bottom electrode 1011 close to the first conductive portion 30, and the second conductive portion 31 corresponding to at least part of the second vertical projection is located on a side close to the at least one connecting portion 104, the third conductive portion 32 can extend from the first surface to a side surface of the second conductive portion 31, so that the third conductive portion 32, the second conductive portion 31 and the first conductive portion 30 are electrically connected, and the shortest distance between the at least one connecting portion 104 and the third conductive portion 32 is smaller than the shortest distance between the at least one connecting portion 104 and the first conductive portion 30.

[0054] Similarly, if Figure 2As shown, the second conductive channel 1032 may also include a first conductive portion 30, a second conductive portion 31 and a third conductive portion 32 that are electrically connected, and the first conductive portion 30 is in direct contact with the second bottom electrode 1012, and a first vertical projection of the first conductive portion 30 on the second bottom electrode 1012 is located in the surface of the second bottom electrode 1012, and the second conductive portion 31 may be located on a side of the first conductive portion 30 away from the second bottom electrode 1012, and on the same horizontal plane as the surface of the second bottom electrode 1012 close to the first conductive portion 30, the second conductive portion 31 has a second vertical projection on the horizontal plane, and the The second vertical projection has at least a portion that does not overlap with the surface of the second bottom electrode 1012 on one side close to the first conductive portion 30, and the second conductive portion 31 corresponding to the at least portion of the second vertical projection is located on a side close to the at least one connecting portion 104, and the third conductive portion 32 can extend from the first surface to a side surface of the second conductive portion 31, so that the third conductive portion 32, the second conductive portion 31 and the first conductive portion 30 are electrically connected, and the shortest distance between at least one connecting portion 104 and the third conductive portion 32 is smaller than the shortest distance between the at least one connecting portion 104 and the first conductive portion 30.

[0055] As can be seen from the above, in the case where the memory device includes only one magnetic tunnel junction 1061, the memory device may include a spin-orbit torque layer 1051 located on a semiconductor substrate, a first conductive connection portion 100 and a second conductive connection portion 100 spaced apart in the semiconductor substrate, and a first bottom electrode 1011 and a second bottom electrode 1012 spaced apart in the semiconductor substrate, wherein the first bottom electrode 1011 is located on a side of the first conductive connection portion 100 away from the spin-orbit torque layer 1051, the second bottom electrode 1012 is located on a side of the second conductive connection portion 100 away from the spin-orbit torque layer 1051, and the spin-orbit torque layer 1051 is connected in series with the first conductive connection portion 100. 100 and the second conductive connection part 100, the magnetic tunnel junction 1061 is located on the side of the spin-orbit torque layer 1051 away from the first conductive connection part 100 and the second conductive connection part 100, and the above-mentioned first conductive connection part 100 and the second conductive connection part 100 can independently include an electrically connected first conductive part 30, a second conductive part 31 and a third conductive part 32, and the connection relationship between the first conductive part 30, the second conductive part 31 and the third conductive part 32 corresponding to the first bottom electrode 1011 and the connection relationship between the first conductive part 30, the second conductive part 31 and the third conductive part 32 corresponding to the second bottom electrode 1012 have been relatedly described in the present application and will not be repeated here.

[0056] The plurality of conductive connection parts 100 may be made of a low-resistivity metal material, for example, silver (Ag), copper (Cu), gold (Au), tungsten (W), etc.

[0057] The shapes of the vertical projections of the first conductive channel 1031, the second conductive channel 1032 and the at least one connecting portion 104 on the surface of the semiconductor substrate may include but are not limited to a circle and a rectangle, and the shapes of the vertical projections of the first conductive channel 1031, the second conductive channel 1032 and the at least one connecting portion 104 on the surface of the semiconductor substrate may be the same or different. Exemplarily, the shapes of the vertical projections of the first conductive channel 1031 and the second conductive channel 1032 on the surface of the semiconductor substrate may be a circle, and the shapes of the vertical projections of the at least one connecting portion 104 on the surface of the semiconductor substrate may be a rectangle.

[0058] In some optional embodiments, the storage device may also include multiple hard mask layers 1071 and multiple first electrode structures 1101, and in order to produce the magnetic tunnel junction 1061 and prevent etching from damaging the magnetic tunnel junction 1061, the multiple hard mask layers 1071 may be located on the side of the magnetic tunnel junction 1061 away from the spin-orbit torque layer 1051, and the multiple hard mask layers 1071 correspond one-to-one to the multiple magnetic tunnel junctions 1061; and in order to write and read data of the storage device, the multiple first electrode structures 1101 are located on the side of the hard mask layer 1071 away from the magnetic tunnel junction 1061, and the multiple first electrode structures 1101 correspond one-to-one to the multiple hard mask layers 1071.

[0059] In some optional embodiments, since the material of the spin-orbit torque layer 1051 needs to have magnetic properties to achieve effective control of the spin, the materials of the multiple spin-orbit torque layers 1051 can be independently selected from any one of heavy metal materials, antiferromagnetic materials and topological materials. Exemplarily, the above-mentioned heavy metal materials can be selected from any one or more of platinum (Pt), tungsten (W), tantalum (Ta), tungsten-tantalum alloy (WTax), platinum cobalt oxide (PtCoO), platinum magnesium oxide (PtMgO), gold-platinum alloy (AuPt), platinum-chromium alloy (PtCr), platinum-hafnium alloy (PtHf) and platinum-titanium alloy (PtTi). Exemplarily, the above-mentioned antiferromagnetic material can be selected from any one or more of platinum-manganese alloy (PtMn), iridium-manganese alloy (IrMn) and manganese-gold alloy (Mn 2 Exemplarily, the topological material may be selected from bismuth antimony alloy (BiSb) or bismuth selenium alloy (BiSe).

[0060] The magnetic tunnel junction 1061 may include a free layer, a tunnel barrier layer and a reference layer which are stacked together, wherein the free layer is in contact with the spin-orbit torque layer 1051. In some optional embodiments, when the magnetic tunnel junction 1061 is a vertically magnetized magnetic tunnel junction 1061, the vertical projection of the magnetic tunnel junction 1061 on the first surface may be any one of a circle, an ellipse and a rectangle.

[0061] In some optional embodiments, when the magnetic tunnel junction 1061 is an in-plane magnetized magnetic tunnel junction 1061 , in order to simplify the manufacturing process, the vertical projection of the magnetic tunnel junction 1061 on the first surface may be an ellipse or a rectangle.

[0062] Optionally, in other optional embodiments, the vertical projection of the above-mentioned magnetic tunnel junction 1061 on the first surface may also include but are not limited to circle, ellipse and rectangle, etc., and the magnetic tunnel junction 1061 may be an in-plane magnetized magnetic tunnel junction 1061 or a perpendicularly magnetized magnetic tunnel junction 1061.

[0063] In the case where the storage device includes any multiple of a magnetic tunnel junction 1061, a spin-orbit torque layer 1051, a hard mask layer 1071 and a first electrode structure 1101, in order to protect the conductive connection 100, the magnetic tunnel junction 1061, the spin-orbit torque layer 1051, the hard mask layer 1071 and the first electrode structure 1101, in some optional embodiments, an insulating protective layer 108 may be covered between adjacent spin-orbit torque layers 1051, on the sidewalls of the magnetic tunnel junction 1061 and the sidewalls of the hard mask layer 1071, and a dielectric protective layer 109 may be formed on a side of the insulating thin protective layer away from the conductive connection 100, on a side of the insulating protective layer 108 away from the magnetic tunnel junction 1061, and on a side of the insulating protective layer 108 away from the hard mask layer 1071. Optionally, the materials of the insulating protection layer 108 and the dielectric protection layer 109 may include but are not limited to silicon nitride and silicon carbide, and the materials of the insulating protection layer 108 and the dielectric protection layer 109 may be the same or different.

[0064] Furthermore, in order to achieve electrical connectivity, Figure 1 and Figure 2 As shown, the memory device may further include a top interconnect structure 111 , and the top interconnect structure 111 is located on a side of the first electrode structure 1101 away from the magnetic tunnel junction 1061 .

[0065] According to another aspect of the present application, the applicant of the present application also provides a method for manufacturing a memory device to form the memory device described in any of the above embodiments, wherein the manufacturing method may include: providing a semiconductor substrate having a first surface; forming a plurality of conductive connection parts 100 spaced apart on the first surface, such as Figure 4 As shown, a plurality of conductive connection parts 100 extend from the first surface into the semiconductor substrate; a plurality of spin-orbit torque layers 1051 are formed at intervals on a side of the conductive connection part 100 away from the semiconductor substrate, and the plurality of spin-orbit torque layers 1051 are connected in series to the plurality of conductive connection parts 100, such as Figure 6 As shown; a plurality of magnetic tunnel junctions 1061 are formed on the side of the spin-orbit torque layer 1051 away from the conductive connection portion 100, and the plurality of magnetic tunnel junctions 1061 correspond one-to-one to the plurality of spin-orbit torque layers 1051, as shown Figure 6 shown.

[0066] That is, through the above-mentioned manufacturing method of the present application, multiple spin-orbit torque layers 1051 can be connected in series with multiple conductive connection parts 100, so that in the process of forming the magnetic tunnel junction 1061, it is not necessary to stop on the spin-orbit torque layer 1051, that is, the magnetic tunnel junction 1061 can be over-etched and the spin-orbit torque layer 1051 can be over-etched, thereby increasing the etching window and improving the etching yield of the device. And further, since each magnetic tunnel junction 1061 can correspond to a spin-orbit torque layer 1051, the width and length of the spin-orbit torque layer 1051 on both sides of the magnetic tunnel junction 1061 can be reduced, so that the size of the magnetic tunnel junction 1061 and the spin-orbit torque layer 1051 is similar, and the resistance of the adjacent area of ​​the adjacent magnetic tunnel junction 1061 is reduced, thereby improving the write efficiency of the storage device and reducing the write current of the storage device. Further, through the present application, the number of CMOS of the storage device can also be reduced, thereby saving the area of ​​the storage device.

[0067] The exemplary embodiments of the method for making the memory device provided according to the present invention will be described in more detail below. However, these exemplary embodiments can be implemented by a variety of different forms, and should not be interpreted as being limited to the embodiments set forth herein. It should be understood that these embodiments are provided to make the disclosure of the present application thorough and complete, and to fully convey the conception of these exemplary embodiments to those of ordinary skill in the art.

[0068] Specifically, in order to form the above-mentioned memory device, as Figure 3 As shown, an insulating dielectric layer 102 having a first bottom electrode 1011 and a second bottom electrode 1012 may be provided first, and the first bottom electrode 1011 and the second bottom electrode 1021 penetrate the insulating dielectric layer 102, as shown in FIG. Figure 3shown.

[0069] Specifically, an insulating dielectric material layer can be further deposited on one side surface of the insulating dielectric layer 102, so that the insulating dielectric material layer covers the exposed surface of the first conductive channel 1031 and the exposed surface of the second conductive channel 1032. Then, an etching process can be used to etch away part of the insulating dielectric material located on the insulating dielectric layer 102, so as to form a plurality of grooves arranged at intervals, and at least one of the plurality of grooves penetrates the insulating dielectric material layer to the insulating dielectric layer 102, one of the plurality of grooves penetrates the insulating dielectric material layer to the first conductive channel 1031, and one of the plurality of grooves penetrates the insulating dielectric material layer to the second conductive channel 1032. Then, a conductive material can be deposited on a side of the insulating dielectric material layer away from the insulating dielectric layer 102, so that the conductive material at least fills the plurality of grooves, so as to form a first conductive channel 1031 corresponding to the first bottom electrode layer, a second conductive channel 1032 corresponding to the second bottom electrode layer, and at least one connecting portion 104 corresponding to at least one groove penetrating the insulating dielectric layer 102, as shown in FIG. Figure 4 Optionally, after depositing the conductive material, chemical mechanical planarization may be used to remove the conductive material outside the plurality of grooves to form the first conductive channel 1031 , the second conductive channel 1032 and the at least one connecting portion 104 .

[0070] Specifically, after forming the above-mentioned multiple conductive connection parts, the substrate can be a semiconductor substrate, and the semiconductor substrate has a first surface, and the first surface has an exposed surface of multiple conductive connection parts. Further, in order to make the multiple spin-orbit torque layers 1051 connect at least two adjacent conductive connection parts in series, in some optional embodiments, the step of forming multiple spin-orbit torque layers 1051 and multiple magnetic tunnel junctions 1061 includes: sequentially forming stacked spin-orbit torque material layers 105 and magnetic storage material layers 106 on the first surface of the semiconductor substrate, such as Figure 5 Optionally, a hard mask material layer 107 may be formed on a side of the magnetic storage material layer 106 away from the spin-orbit torque material layer 105, as shown in FIG. Figure 5 As shown. Then, part of the spin-orbit torque material layer 105 and part of the magnetic storage material layer 106 located on the side of each conductive connection away from the semiconductor substrate can be removed, so that the remaining spin-orbit torque material layer 105 forms a spin-orbit torque layer 1051, and the remaining magnetic storage material layer 106 forms a magnetic tunnel junction 1061, and each spin-orbit torque layer 1051 is connected in series to at least two adjacent conductive connections, as shown. Figure 6Optionally, in the case where a hard mask material layer 107 is formed on the side of the magnetic storage material layer 106 away from the spin-orbit torque material layer 105, a portion of the hard mask material layer 107 may be removed so that the remaining hard mask material layer 107 forms a hard mask layer 1071, as shown in FIG. Figure 6 Optionally, the spin-orbit torque material layer 105, the magnetic storage material layer 106 and the hard mask material layer 107 may be formed by physical or chemical vapor deposition. Optionally, the spin-orbit torque layer 1051, the magnetic tunnel junction 1061 and the hard mask layer 1071 may be formed by ion beam etching or reactive ion etching.

[0071] Specifically, Figure 7 As shown, in order to protect the spin-orbit torque layer 1051, the magnetic tunnel junction 1061 and the hard mask layer 1071 and to isolate the conductive connection from contact with the outside world, an insulating protective layer 108 can be formed on the side of the conductive connection away from the first electrode layer and the second electrode layer and on the sidewalls of the spin-orbit torque layer 1051, the sidewalls of the magnetic tunnel junction 1061 and the sidewalls of the hard mask layer 1071, and a dielectric protective layer 109 is formed on the side of the insulating protective layer 108 away from the magnetic tunnel junction 1061.

[0072] Specifically, in order to form a plurality of first electrode structures 1101, and to make each first electrode structure 1101 located on a side of the hard mask layer 1071 away from the magnetic tunnel junction 1061, and the number of the plurality of first electrode structures 1101 is consistent with the number of the plurality of magnetic tunnel junctions 1061, firstly, an electrode material layer 110 may be formed on a side of the hard mask layer 1071 away from the magnetic tunnel junction 1061, such as Figure 8 As shown, the electrode material layer 110 can be etched to form a plurality of first electrode structures 1101 spaced apart from each other, and each first electrode structure 1101 is arranged in contact with a hard mask layer 1071, as shown in FIG. Fig. 9 As shown, a dielectric material can be filled on the side of the dielectric protection layer 109 away from the semiconductor substrate so that the dielectric material completely covers the first electrode structure 1101, and then a plurality of top through holes penetrating the first electrode structure 1101 can be formed by etching. The plurality of top through holes correspond to the plurality of first electrode structures 1101 one by one, and when a conductive material is deposited, the plurality of top through holes are connected to form a top interconnection structure 111, thereby achieving electrical connectivity, as shown in FIG. Figure 1 shown.

[0073] From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects:

[0074] A storage device may include a plurality of conductive connection parts arranged in pairs, a plurality of spin-orbit moment layers arranged in pairs, and a plurality of magnetic tunnel junctions arranged in pairs, the number of the plurality of magnetic tunnel junctions is consistent with the number of the plurality of spin-orbit moment layers, the plurality of conductive connection parts extend from the first surface into the semiconductor substrate, the plurality of spin-orbit moment layers are arranged on the side of the conductive connection part away from the semiconductor substrate, and the plurality of spin-orbit moment layers are connected in series to at least two adjacent conductive connection parts, so that through the present application, in the process of forming the magnetic tunnel junction, it is not necessary to stop on the spin-orbit moment layer, that is, the magnetic tunnel junction can be overetched and the spin-orbit moment layer can be overetched, thereby increasing the etching window and improving the etching yield of the device. Furthermore, since each magnetic tunnel junction can correspond to a spin-orbit moment layer, the width and length of the spin-orbit moment layers on both sides of the magnetic tunnel junction can be reduced, so that the size of the magnetic tunnel junction and the spin-orbit moment layer is similar, and the resistance of the adjacent region of the adjacent magnetic tunnel junction is reduced, thereby improving the write efficiency of the storage device and reducing the write current of the storage device. Furthermore, through the present application, the number of CMOS in the storage device can be reduced, thereby saving the area of ​​the storage device.

[0075] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A storage device, It is characterized in that include: A semiconductor substrate having a first surface; A plurality of conductive connection parts extending from the first surface into the semiconductor substrate, and any two adjacent conductive connection parts are arranged at intervals; A plurality of spin-orbit torque layers are arranged at intervals on a side of the conductive connection portion away from the semiconductor substrate, and each of the spin-orbit torque layers is connected in series to at least two adjacent conductive connection portions; A plurality of magnetic tunnel junctions are located on a side of the spin-orbit torque layer away from the conductive connection portion, and the plurality of magnetic tunnel junctions correspond to the plurality of spin-orbit torque layers one by one.

2. The memory device according to claim 1, It is characterized in that The conductive connection portion has an exposed surface located in the first surface, and the spin-orbit torque layer has a second surface close to the conductive connection portion, wherein the second surface covers a portion of the exposed surface.

3. The memory device according to claim 2, It is characterized in that The exposed surface and the second surface have an overlapping area, and a ratio of the overlapping area to an area of ​​the second surface is less than or equal to 60%.

4. The memory device according to any one of claims 1 to 3, It is characterized in that The plurality of conductive connection parts include a first conductive channel, a second conductive channel, and at least one connection part, wherein the at least one connection part is located between the first conductive channel and the second conductive channel, and the memory device further includes: A first bottom electrode, located on a side of the first conductive channel away from the spin-orbit torque layer; The second bottom electrode is located at a side of the second conductive channel away from the spin-orbit torque layer.

5. The memory device according to claim 4, It is characterized in that The material of the connecting part includes ferromagnetic material.

6. The memory device according to any one of claims 1 to 3, It is characterized in that The storage device further comprises: A plurality of hard mask layers are located on a side of the magnetic tunnel junction away from the spin-orbit torque layer, and the plurality of hard mask layers correspond to the plurality of magnetic tunnel junctions one by one; A plurality of first electrode structures are located on a side of the hard mask layer away from the magnetic tunnel junction, and the plurality of first electrode structures correspond to the plurality of hard mask layers one by one.

7. The memory device according to any one of claims 1 to 3, It is characterized in that The materials of the plurality of spin-orbit torque layers are independently selected from any one of heavy metal materials, antiferromagnetic materials and topological materials.

8. The memory device according to any one of claims 1 to 3, It is characterized in that In the case where the magnetic tunnel junction is a perpendicularly magnetized magnetic tunnel junction, a vertical projection of the magnetic tunnel junction on the first surface is any one of a circle, an ellipse and a rectangle.

9. The memory device according to any one of claims 1 to 3, It is characterized in that In the case where the magnetic tunnel junction is an in-plane magnetized magnetic tunnel junction, a vertical projection of the magnetic tunnel junction on the first surface is an ellipse or a rectangle.

10. A method for manufacturing a memory device according to any one of claims 1 to 9, It is characterized in that include: Providing a semiconductor substrate having a first surface; forming a plurality of conductive connection portions spaced apart from each other on the first surface, wherein the plurality of conductive connection portions extend from the first surface into the semiconductor substrate; A plurality of spin-orbit torque layers are formed at intervals on a side of the conductive connection portion away from the semiconductor substrate, and the plurality of spin-orbit torque layers are connected in series to the plurality of conductive connection portions; A plurality of magnetic tunnel junctions are formed on a side of the spin-orbit torque layer away from the conductive connection portion, and the plurality of magnetic tunnel junctions correspond one-to-one to the plurality of spin-orbit torque layers.

11. The method according to claim 10, It is characterized in that The steps of forming a plurality of the spin-orbit torque layers and a plurality of the magnetic tunnel junctions include: Sequentially forming a stacked spin-orbit torque material layer and a magnetic storage material layer on the first surface of the semiconductor substrate; Part of the spin-orbit torque material layer and part of the magnetic storage material layer located on the side of each conductive connection away from the semiconductor substrate are removed so that the remaining spin-orbit torque material layer forms the spin-orbit torque layer, and the remaining magnetic storage material layer forms the magnetic tunnel junction, and each spin-orbit torque layer connects at least two adjacent conductive connections in series.

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