Bidirectional ESD diode and manufacturing method thereof

Abstract

The invention provides a bidirectional ESD diode and a manufacturing method thereof. The bidirectional ESD diode comprises a substrate of a first doping type; the buried layer is located in the substrate and has a second doping type; the at least 2N unit structures are located in the substrate, and each unit structure comprises a first doping region with a first doping type and a second doping region with a second doping type, and the first doping region and the second doping region extend from the upper surface of the substrate to the interior of the substrate; the isolation region is at least positioned between every two adjacent unit structures; wherein the isolation region at least extends to the upper surface of the buried layer from the upper surface of the substrate, and N is a positive integer greater than or equal to 1. Compared with the prior art, the method has the advantages that the illumination step can be reduced, that is, the process step can be simplified, and the trigger voltage of the bidirectional ESD diode can be greatly reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to a bidirectional ESD diode and a manufacturing method thereof. Background Art

[0002] The electrostatic discharge (ESD) phenomenon of integrated circuits is an instantaneous process in which a large amount of charge is poured into the integrated circuit from the outside when the chip is floating. Since the internal resistance of the integrated circuit chip is very low, when the ESD phenomenon occurs, an instantaneous high peak current will be generated, and a large amount of Joule heat will be generated, which will cause the integrated circuit chip to be invalid. Therefore, it is very important to use high-performance bidirectional ESD diodes and their manufacturing methods to discharge electrostatic charges.

[0003] Figure 1 It is a bidirectional ESD diode in the prior art, such as Figure 1 As shown, the bidirectional ESD diode in the prior art is a five-layer structure, and the N-EPI (or P-EPI) in the middle layer is used to control the capacitance of the structure. The entire structure is similar to a bidirectional back-to-back diode from top to bottom. Because there is a reverse bias structure of the PN junction in the diode structure in the prior art, that is, Figure 1 The PN junction between N+ and PW, and the PN junction between N+ substrate and PBL, usually, the trigger voltage of the pole tube structure will be greater than 4-5V. Such a bidirectional structure has a high trigger voltage and is difficult to be used in applications that require a low trigger voltage. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a bidirectional ESD diode and a manufacturing method thereof, so as to solve the problem of high triggering voltage of the bidirectional ESD diode in the prior art.

[0005] In a first aspect, the present application provides a bidirectional ESD diode, a substrate of a first doping type; a buried layer of a second doping type located in the substrate; and at least 2N unit structures located in the substrate, the unit structures comprising: a first doping region of the first doping type and a second doping region of the second doping type extending from the upper surface of the substrate and into the interior thereof; an isolation region located at least between each two adjacent unit structures; wherein the isolation region extends from the upper surface of the substrate at least to the upper surface of the buried layer; and N is a positive integer greater than or equal to 1.

[0006] In other embodiments, the width of the buried layer is the same as the width of the substrate.

[0007] In other embodiments, the isolation region extends from the upper surface of the substrate to below the buried layer.

[0008] In other embodiments, it also includes: an isolation region between the first unit structure and a first edge of the bidirectional ESD diode adjacent to the first unit structure, and an isolation region between the 2Nth unit structure and a second edge of the bidirectional ESD diode adjacent to the 2Nth unit structure, wherein the isolation region extends from the upper surface of the substrate at least to the upper surface of the buried layer, and the 2N unit structures are arranged in sequence, with the first edge and the second edge arranged opposite to each other.

[0009] In other embodiments, the distance between the upper surface of the buried layer and the upper surface of the substrate is 8-20 um.

[0010] In other embodiments, the distance between two adjacent unit structures is 2-5 um.

[0011] In other embodiments, when N=1, two unit structures are arranged sequentially, the first doped region in the first unit structure is electrically connected to the second doped region in the second unit structure and led to the first input / output terminal, and the second doped region in the first unit structure is electrically connected to the first doped region in the second unit structure and led to the second input / output terminal.

[0012] In other embodiments, when N is greater than or equal to 2, for the 2N unit structures arranged in sequence, the second doping region in the previous unit structure is electrically connected to the first doping region in the adjacent subsequent unit structure; wherein the second doping region in the Nth unit structure is electrically connected to the first doping region in the N+1th unit structure and led to the second input / output terminal; the first doping region in the first unit structure is electrically connected to the second doping region in the 2Nth unit structure and led to the first input / output terminal.

[0013] In other embodiments, it also includes: an interlayer dielectric layer covering the upper surface of the substrate, wherein the interlayer dielectric layer exposes the upper surfaces of the first doped region and the second doped region; an ohmic connection layer located on the upper surfaces of the first doped region and the second doped region; a metal layer located above the interlayer dielectric layer, wherein the metal layer is used to electrically connect the second doped region in the Nth unit structure with the first doped region in the N+1th unit structure; and is used to electrically connect the first doped region in the first unit structure with the second doped region in the 2Nth unit structure.

[0014] In other embodiments, it further includes: a pad structure located above the metal layer, wherein the pad structure is used to electrically connect the bidirectional ESD diode to the outside.

[0015] In the second aspect, the present application also provides a method for manufacturing a bidirectional ESD diode, the method comprising: providing a substrate having a first doping type; forming a buried layer having a second doping type in the substrate; forming 2N unit structures in the substrate, wherein the unit structure comprises: a first doping region having the first doping type and a second doping region having the second doping type extending from the upper surface of the substrate and into the interior thereof; forming at least one isolation region between every two adjacent unit structures in the substrate, the isolation region extending from the upper surface of the substrate at least to the upper surface of the buried layer; N is a positive integer greater than or equal to 1.

[0016] In other embodiments, the method further includes: the isolation region extending from the upper surface of the substrate to below the buried layer.

[0017] In other embodiments, the method further includes: forming an isolation region between a first unit structure and a first edge of the bidirectional ESD diode adjacent to the first unit structure, and forming an isolation region between a 2Nth unit structure and a second edge of the bidirectional ESD diode adjacent to the 2Nth unit structure, wherein the 2N unit structures are arranged in sequence with the first edge and the second edge arranged opposite to each other, and the isolation region extends from the upper surface of the substrate at least to the upper surface of the buried layer.

[0018] In other embodiments, the method further includes: forming an interlayer dielectric layer covering the substrate on the upper surface of the substrate, wherein the interlayer dielectric layer exposes the upper surfaces of the first doped region and the second doped region; forming an ohmic connection layer on the upper surfaces of the first doped region and the second doped region; forming a metal layer above the interlayer dielectric layer, wherein the metal layer is used to electrically connect the second doped region in the Nth unit structure with the first doped region in the N+1th unit structure; and is used to electrically connect the first doped region in the first unit structure with the second doped region in the 2Nth unit structure.

[0019] In other embodiments, the method further includes: forming a pad structure above the metal layer, wherein the pad structure is used to electrically connect the bidirectional ESD diode to the outside.

[0020] In other embodiments, the distance between the upper surface of the buried layer and the upper surface of the substrate is 8-20 um.

[0021] Compared with the prior art, the present application omits the epitaxial layer (N-EPI) and the well region (PW), which can reduce the illumination steps, that is, the process steps can be simplified; in addition, in the bidirectional ESD diode structure in the prior art, there is a reverse bias structure of the PN junction, that is, Figure 1The PN junction between N+ and PW, and the PN junction between N+substrate and PBL, due to the existence of the reverse PN junction, the trigger voltage of the bidirectional ESD diode is usually greater than 4-5V; in this embodiment, it is equivalent to connecting one, two or three forward-conducting diodes in both directions between the first input / output terminal I / O-1 and the second input / output terminal I / O-2, and the forward-conducting voltage of the diode is about 0.7V, that is, the trigger voltage of the bidirectional ESD diode in this application is 0.7V or 1.4V or 2.1V. Compared with the prior art, the trigger voltage of the bidirectional ESD diode is greatly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Shown is a cross-sectional view of a bidirectional ESD diode in the prior art;

[0023] Figure 2 Shown is a schematic diagram of a bidirectional ESD diode according to a first embodiment of the present invention;

[0024] Figure 3 Shown is a cross-sectional view of a bidirectional ESD diode according to a first embodiment of the present invention;

[0025] Figure 4 A cross-sectional view showing a bidirectional ESD diode according to another embodiment of the present invention;

[0026] Figure 5 A cross-sectional view showing a bidirectional ESD diode according to another embodiment of the present invention;

[0027] Figure 6 Shown is a schematic diagram of a bidirectional ESD diode according to a fourth embodiment of the present invention;

[0028] Figure 7 A cross-sectional view showing a bidirectional ESD diode according to another embodiment of the present invention;

[0029] Figure 8 A cross-sectional view showing a bidirectional ESD diode according to another embodiment of the present invention;

[0030] Figures 9a-9d A cross-sectional view showing a manufacturing method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0032] The present application provides a bidirectional ESD diode, a substrate of a first doping type; a buried layer of a second doping type located in the substrate; and at least 2N unit structures located in the substrate, the unit structures comprising: a first doping region of the first doping type and a second doping region of the second doping type extending from the upper surface of the substrate and into the interior thereof; an isolation region located at least between two adjacent unit structures; wherein the isolation region extends from the upper surface of the substrate at least to the upper surface of the buried layer; and N is a positive integer greater than or equal to 1.

[0033] In the first aspect, the present application embodiment provides a bidirectional ESD diode. For details, please refer to Figure 2 and Figure 3 , Figure 2 This is a schematic diagram of a bidirectional ESD diode according to a first embodiment of the present invention. Figure 3 It is a cross-sectional view of the bidirectional ESD diode of the first embodiment of the present invention. In this embodiment, the bidirectional ESD diode includes a substrate 101 of a first doping type, and also includes a buried layer 102 located in the substrate 101, and the buried layer 102 has a second doping type, and also includes two unit structures located in the substrate. Wherein, the unit structure includes a first doping region 103 with a first doping type and a second doping region 104 with a second doping type located in the substrate 101; wherein, the first doping region 103 and the second doping region 104 extend from the surface of the substrate 101 and into the interior of the substrate 101; the bidirectional ESD diode also includes an isolation region 105 located between the first unit structure and the second unit structure, wherein the isolation region 105 extends from the surface of the substrate 101 to the interior of the substrate 101, and the isolation region 105 extends from the upper surface of the substrate to at least the upper surface of the buried layer 102.

[0034] Optionally, the substrate 101 is composed of silicon, for example. In this embodiment, the substrate 101 is preferably a high-resistance substrate. If the doping concentration of the substrate 101 is too low, leakage may occur. If the doping concentration of the substrate 101 is too high, it will affect the capacitance of the device. Therefore, in this embodiment of the application, the doping concentration of the substrate 101 is preferably 1×10 13 cm -3 ~1×10 14 cm -3 .

[0035] Optionally, in this example, the buried layer 102 is implanted into the substrate 101 by high energy implantation, wherein the concentration of the buried layer 102 is set at 1×10 15 cm -3 ~1×10 20 cm-3 Preferably, the doping concentration of the buried layer 102 is set to 1×10 18 cm -3 In other embodiments, the buried layer 102 may be implanted into the substrate 101 in other ways, and the implantation method of the buried layer 102 is not limited herein. In this embodiment, the buried layer 102 is used to isolate the first doped region 103 located on the surface of the substrate 101 from the substrate 101 located below the buried layer 102.

[0036] Optionally, the isolation structure 105 may include a trench and an insulating material filled in the trench, and the insulating material may be an oxide.

[0037] Optionally, in the first unit structure, the first doping region 103 and the second doping region 104 form a first diode, and in the second unit structure, the first doping region 103 and the second doping region 104 form a second diode. The doping concentration of the first doping region 103 and the second doping region 104 is set to 1×10 18 cm -3 ~1×10 21 cm -3 .

[0038] In this embodiment, the first doped region 103 in the first unit structure is electrically connected to the second doped region 104 in the second unit structure and is led to the first input / output terminal I / O-1, and the second doped region 104 in the first unit structure is electrically connected to the first doped region 103 in the second unit structure and is led to the second input / output terminal I / O-2.

[0039] Optionally, if the distance between two adjacent unit structures is relatively close, the parasitic resistance can be reduced, but the parasitic capacitance will be increased. If the distance between two adjacent unit structures is relatively far, the parasitic capacitance can be reduced, but the parasitic resistance will be increased. Preferably, in the present application, the distance between two adjacent unit structures is set to 2-5um. In this way, the parasitic capacitance and parasitic resistance are better compromised, ensuring the performance of the bidirectional ESD diode.

[0040] In other embodiments, the width of the buried layer 102 is the same as the width of the substrate 101. Since the width of the buried layer 102 is the same as the width of the substrate 101, that is, the buried layer 102 is injected into the entire substrate 101, this step does not require light irradiation, which can greatly save the manufacturing cost of the chip.

[0041] In other embodiments, Figure 4 As shown, the isolation region 105 extends from the upper surface of the substrate to below the buried layer 102. Figure 4 Shown is a cross-sectional view of a bidirectional ESD diode of another embodiment of the present invention; the isolation region 105 extends to below the buried layer 102, and is used to divide the buried layer 102 into multiple sections. In other embodiments, the bidirectional ESD diode also includes an isolation region 108 located between a first unit structure and a first edge of the bidirectional ESD diode adjacent to the first unit structure, and an isolation region 109 located between a 2Nth unit structure and a second edge of the bidirectional ESD diode adjacent to the 2Nth unit structure, wherein the isolation region 108 and the isolation region 109 extend from the upper surface of the substrate at least to the upper surface of the buried layer, and the 2N unit structures are arranged in sequence, with the first edge and the second edge arranged opposite to each other. In other embodiments, the isolation region 108 and the isolation region 109 may also extend from the upper surface of the substrate at least to below the buried layer.

[0042] Since the buried layer 102 is divided into multiple sections, the capacitance of the parasitic capacitance between the first input / output terminal I / O-1I / O-1I / O-1 and the second input / output terminal I / O-2 will become smaller, and for the bidirectional ESD diode, the smaller the parasitic capacitance, the smaller the impact of the bidirectional ESD diode on high-speed signal transmission. Specifically, the isolation region 105, the isolation region 108 and the isolation region 109 all extend below the buried layer 102, that is, the buried layer 102 is divided into multiple sections by the isolation region 105, the isolation region 108 and the isolation region 109, and its parasitic capacitance includes: in the first unit structure, a first parasitic capacitance C1 is formed between the first doped region 103 and the second doped region 104 (shown by the dotted line in the figure); in the second unit structure, a first parasitic capacitance C1 is formed between the first doped region 103 and the second doped region 104 C2; a third parasitic capacitor C3 formed between the upper surface of the buried layer 102 between the isolation region 108 and the isolation region 105 and the substrate 101; a fourth parasitic capacitor C4 formed between the lower surface of the buried layer 102 and the substrate 101; a fifth parasitic capacitor C5 formed between the lower surface of the buried layer 102 between the isolation region 109 and the isolation region 105 and the substrate 101; a sixth parasitic capacitor C6 formed between the upper surface of the buried layer 102 and the substrate 101. The total parasitic capacitance C11 between the first input / output terminal I / O-1 and the second input / output terminal I / O-2 is C1+C2+C3 / / C4 / / C5 / / C6, wherein C3 / / C4 / / C5 / / C6 represents the third parasitic capacitance C3, the fourth parasitic capacitance C4, the fifth parasitic capacitance C5 and the sixth parasitic capacitance C6 connected in series. If C3 / / C4 / / C5 / / C6 is represented by Cn, the third parasitic capacitance C3, the fourth parasitic capacitance C4, the fifth parasitic capacitance C5 and the sixth parasitic capacitance C6 are connected in series. The capacitance of the fifth parasitic capacitor C5 and the sixth parasitic capacitor C6 connected in series is the sum of the reciprocals of the sum of the capacitances of the respective parasitic capacitors, that is, the reciprocal of the capacitance of the third parasitic capacitor C3, the fourth parasitic capacitor C4, the fifth parasitic capacitor C5 and the sixth parasitic capacitor C6 connected in series is equal to the reciprocal of the third parasitic capacitor C3 plus the reciprocal of the fourth parasitic capacitor C4 plus the reciprocal of the fifth parasitic capacitor C5 plus the reciprocal of the sixth parasitic capacitor C6, that is, 1 / Cn=1 / C3+1 / C4+1 / C5+1 / C6. The total capacitance after the series connection is less than the capacitance of a single parasitic capacitor.

[0043] In the first embodiment, the isolation region 108, the isolation region 105 and the isolation region 109 extend to the upper surface of the buried layer 102, that is, when the isolation region 108, the isolation region 105 and the isolation region 109 do not divide the buried layer 102 into multiple sections, the total parasitic capacitance C22 between the first input / output terminal I / O-1 and the second input / output terminal I / O-2 is C1+C2+C3 / / C6, wherein C3 / / C6 represents the third parasitic capacitor C3 and the sixth parasitic capacitor C6 connected in series. If C3 / / C6 is represented by Cm, the capacitance of the third parasitic capacitor C3 and the sixth parasitic capacitor C6 after being connected in series is the sum of the reciprocals of the sums of the capacitances of the various parasitic capacitors, that is, the reciprocal of the capacitance of the third parasitic capacitor C3 and the sixth parasitic capacitor C6 after being connected in series is equal to the reciprocal of the third parasitic capacitor C3 plus the reciprocal of the sixth parasitic capacitor C6, that is, 1 / Cn=1 / C3+1 / C6. The total capacitance after series connection is less than the capacitance of a single parasitic capacitor.

[0044] From the above analysis, it can be seen that the capacitance of the parasitic capacitor C22 is greater than the capacitance of the parasitic capacitor C11. The isolation area 108, the isolation area 105 and the isolation area 109 extending to the upper surface of the buried layer 102 are relatively large compared to the isolation area 108, the isolation area 105 and the isolation area 109 extending to the bottom of the buried layer 102. Preferably, the isolation area 108, the isolation area 105 and the isolation area 109 extend to the bottom of the buried layer 102, which can better reduce the impact on high-speed signal transmission. In other words, the isolation area divides the buried layer 102 into multiple sections as a preferred solution.

[0045] In other embodiments, the bidirectional ESD diode further includes an interlayer dielectric layer (not shown) covering the upper surface of the substrate 101, wherein the interlayer dielectric layer exposes the upper surfaces of the first doped region 103 and the second doped region 104. The material of the interlayer dielectric layer is one or more of silicon oxide and silicon nitride.

[0046] In other embodiments, the bidirectional ESD diode further includes an ohmic connection layer located on the upper surfaces of the first doping region 103 and the second doping region 104. The ohmic connection layer is a metal silicide, and specifically, the metal silicide includes one or more of germanium silicide, selenium silicide, and gallium silicide.

[0047] In other embodiments, the bidirectional ESD diode further includes a metal layer located above the interlayer dielectric layer, the metal layer being used to electrically connect the second doped region in the unit structure with the first doped region in the unit structure adjacent thereto, and being used to electrically connect the first doped region in the first unit structure with the second doped region in the last unit structure. In this embodiment, the unit structures are arranged in sequence from left to right in the substrate 101. If the first unit structure from the left is defined as the first unit structure, then the rightmost unit structure is the last unit structure. Otherwise, the rightmost unit structure is the first unit structure, and the leftmost unit structure is the last unit structure. Specifically, the second doped region 104 in the first unit structure is electrically connected to the first doped region 103 in the second unit structure through the first metal layer 107, and the first doped region 103 in the first unit structure is electrically connected to the second doped region 104 in the second unit structure through the second metal layer 106. In this embodiment, the metal layer includes a first metal layer 107 and a second metal layer 106. In other embodiments, the number of metal layers is not limited. That is, the electrical connection between the second doping region 104 in the first unit structure and the first doping region 103 in the second unit structure, and the electrical connection between the first doping region 103 in the first unit structure and the second doping region 104 in the second unit structure can be completed in one metal structure. Alternatively, the electrical connection between the second doping region 104 in the first unit structure and the first doping region 103 in the second unit structure, and the electrical connection between the first doping region 103 in the first unit structure and the second doping region 104 in the second unit structure can be completed through three or four metal structures.

[0048] In other embodiments, the bidirectional ESD diode further includes a pad structure (not shown in the figure) located above the metal layer, and the pad structure is used to electrically connect the bidirectional ESD diode to the outside.

[0049] In other embodiments, the distance between the upper surface of the buried layer 102 and the upper surface of the substrate is 8 to 20 um. In other embodiments, the depth of the buried layer 102 in the substrate 101 can be designed according to requirements. The depth of the buried layer 102 should be such that the second doping region 104 located on the surface of the substrate 101 cannot penetrate the buried layer 102. Preferably, the depth of the buried layer can be 12 um. In addition, in this example, the buried layer 102 can be injected into the entire substrate, that is, the width of the buried layer is the same as the width of the substrate. In this way, the step of injecting the buried layer 102 does not require a mask, which can save lighting costs.

[0050] The first doping type is one of N-type and P-type, and the second doping type is the other of the N-type and P-type.

[0051] Compared with the prior art, the present application omits the epitaxial layer (N-EPI) and the well region (PW), which can greatly reduce the process steps, improve production efficiency and reduce costs. In addition, in the bidirectional ESD diode structure in the prior art, there is a reverse bias structure of the PN junction, that is, Figure 1 The PN junction between N+ and PW, and the PN junction between N+substrate and PBL, due to the existence of the reverse PN junction, the trigger voltage of the bidirectional ESD diode in the prior art is usually greater than 4-5V; in this embodiment, it is equivalent to connecting a diode in both directions between the first input / output terminal I / O-1 and the second input / output terminal I / O-2, and the forward conduction voltage of the diode is about 0.7V, that is, the trigger voltage of the bidirectional ESD diode in this application is 0.7V. Compared with the prior art, the trigger voltage of the bidirectional ESD diode is greatly reduced.

[0052] In other embodiments, Figure 5 As shown, Figure 5 Shown is a cross-sectional view of a bidirectional ESD diode according to another embodiment of the present invention; different from the first embodiment, two spaced-apart isolation regions 105 are arranged between two adjacent unit structures, and the two spaced-apart isolation regions 105 extend from the upper surface of the substrate to below the buried layer.

[0053] Similarly, in this embodiment, it is equivalent to bidirectionally connecting a diode between the first input / output terminal I / O-1 and the second input / output terminal I / O-2, and the forward conduction voltage of the diode is about 0.7 V, that is, the trigger voltage of the bidirectional ESD diode in this application is 0.7 V. Compared with the prior art, the trigger voltage of the bidirectional ESD diode is greatly reduced.

[0054] When the unit structure includes 2N units, and N is greater than or equal to 2, in every two unit structures adjacent to each other from left to right, the second doping region in the previous unit structure is electrically connected to the first doping region in the next unit structure; wherein the second doping region in the Nth unit structure is electrically connected to the first doping region in the N+1th unit structure and is led to the second input / output terminal; the first doping region in the first unit structure is electrically connected to the second doping region in the 2Nth unit structure and is led to the first input / output terminal.

[0055] Please refer to Figure 6 and Figure 7 , Figure 6 This is a schematic diagram of a bidirectional ESD diode according to a fourth embodiment of the present invention; Figure 7is a cross-sectional view of a bidirectional ESD diode according to a fourth embodiment of the present invention, and is described by taking N equal to 2 as an example; Figure 6 and Figure 7 Bidirectional ESD diodes and Figure 2 and Figure 4 The difference between the bidirectional ESD diodes is, Figure 7 The bidirectional ESD diode includes 4 identical unit structures, and the other structures are basically the same and will not be described in detail here. Specifically, the bidirectional ESD diode includes a substrate 101, and also includes a buried layer 102 located in the substrate 101, and the buried layer 102 has a second doping type, and also includes four unit structures located in the substrate. Among them, the unit structure includes a first doping region 103 with a first doping type and a second doping region 104 with a second doping type located in the substrate 101; wherein the first doping region 103 and the second doping region 104 extend from the surface of the substrate 101 and into the interior of the substrate 101; the unit structure also includes two isolation regions 105 from the outside of the first doping region 103 and the second doping region 104, wherein the isolation region 105 is located on the surface of the substrate 101 and extends into the interior of the substrate 101, and the isolation region 105 extends to the bottom of the buried layer 102 and isolates the buried layer 102. In the first unit structure, the first doping region 103 and the second doping region 104 form a first diode, in the second unit structure, the first doping region 103 and the second doping region 104 form a second diode, in the third unit structure, the first doping region 103 and the second doping region 104 form a third diode, and in the fourth unit structure, the first doping region 103 and the second doping region 104 form a fourth diode. In addition, the second doping region 104 in the first unit structure is electrically connected to the first doping region 103 in the second unit structure; the second doping region 104 in the second unit structure is electrically connected to the first doping region 103 in the third unit structure, and is led to the second input / output terminal I / O-2; the second doping region 104 in the third unit structure is electrically connected to the first doping region 103 in the fourth unit structure; the first doping region 103 in the first unit structure is electrically connected to the second doping region 104 in the fourth unit structure, and is led to the first input / output terminal I / O-1.

[0056] Compared with the prior art, in this embodiment, two diodes are connected in series bidirectionally between the first input / output terminal I / O-1 and the second input / output terminal I / O-2, wherein the forward conduction voltage of one diode is about 0.7V, and the forward conduction voltage of two diodes connected in series is about 1.4V, that is, the trigger voltage of the bidirectional ESD diode in this application is 1.4V. Compared with the prior art, the trigger voltage of the bidirectional ESD diode is greatly reduced.

[0057] In other embodiments, the number of the unit structures may be 6, that is, three diodes are connected in series bidirectionally between the first input / output terminal I / O-1 and the second input / output terminal I / O-2. The forward conduction voltage of one diode is about 0.7V, and the forward conduction voltage of three diodes connected in series is about 2.1V, that is, the trigger voltage of the bidirectional ESD diode in this application is 2.1V.

[0058] In other embodiments, the number of the unit structures may also be 8, that is, four diodes are bidirectionally connected in series between the first input / output terminal I / O-1 and the second input / output terminal I / O-2. The forward conduction voltage of one diode is about 0.7V, and the forward conduction voltage of four diodes in series is about 2.8V, that is, the trigger voltage of the bidirectional ESD diode in this application is 2.8V.

[0059] In the application, there is no restriction on the number of the unit structures, and the number of the appropriate unit structures can be selected according to the value of the applied voltage.

[0060] In other embodiments, Figure 8 As shown, Figure 8 A cross-sectional view of a bidirectional ESD diode according to another embodiment of the present invention is shown; different from the third embodiment, two isolation regions 105 spaced apart are arranged between two adjacent unit structures, and the two isolation regions 105 spaced apart extend from the upper surface of the substrate to below the buried layer.

[0061] Similarly, in this embodiment, it is equivalent to connecting two diodes in series bidirectionally between the first input / output terminal I / O-1 and the second input / output terminal I / O-2, wherein the forward conduction voltage of one diode is about 0.7 V, and the forward conduction voltage of two diodes in series is about 1.4 V, that is, the trigger voltage of the bidirectional ESD diode in this application is 1.4 V. Compared with the prior art, the trigger voltage of the bidirectional ESD diode is greatly reduced.

[0062] In a second aspect, the present application embodiment provides a method for manufacturing a bidirectional ESD diode. For details, please refer to Figures 9a to 9d , Figures 9a-9d A cross-sectional view showing a method for manufacturing a bidirectional ESD diode according to an embodiment of the present invention.

[0063] like Figures 9a to 9d As shown, a substrate 101 having a first doping type is provided;

[0064] Optionally, the substrate 101 is composed of silicon, for example. In this embodiment, the substrate 101 is preferably a high-resistance substrate. If the doping concentration of the substrate 101 is too low, leakage may occur. If the doping concentration of the substrate 101 is too high, it will affect the capacitance of the device. Therefore, in this embodiment of the application, the doping concentration of the substrate 101 is preferably 1×10 13 cm -3 ~1×10 14 cm -3 .

[0065] A buried layer 102 having a second doping type is formed in the substrate 101. In this embodiment, the buried layer 102 is implanted into the substrate 101 by high energy implantation, wherein the concentration of the buried layer 102 is set at 1×10 15 cm -3 ~1×10 20 cm -3 Preferably, the doping concentration of the buried layer 102 is set to 1×10 18 cm -3 In other embodiments, the buried layer 102 may be implanted into the substrate 101 in other ways, and the formation method of the buried layer 102 is not limited here.

[0066] 2N unit structures are formed in the substrate 101, wherein the unit structure includes: a first doping region 103 with a first doping type and a second doping region 104 with a second doping type, which are located on the upper surface of the substrate 101 and extend into the interior thereof; and further includes forming at least one isolation region 105 in the substrate 101, wherein the isolation region 105 is located at least between two adjacent unit structures, and the isolation region 105 extends from the upper surface of the substrate 101 to the interior thereof and at least extends to the upper surface of the buried layer 102; the method for forming the unit structure includes: forming a first doping region 103 with a first doping type and a second doping region 104 with a second doping type on the upper surface of the substrate 101; in this embodiment, a high-energy implantation method is used to implant the first doping region 103 with a first doping type and the second doping region 104 with a second doping type into the substrate 101, wherein the concentrations of the first doping region 103 and the second doping region 104 are set at 1×10 18 cm -3 ~1×10 21 cm -3 In other embodiments, other methods may be used to form the first doping region 103 and the second doping region 104 in the substrate 101, and the formation method of the first doping region 103 and the second doping region 104 is not limited here.

[0067] N is a positive integer greater than or equal to 1. Specifically, the 2N unit structures may be 2 unit structures, such as Figure 3 and Figure 4 and Figure 5 The bidirectional ESD diode shown in FIG. 1 can also be a 4-unit structure, such as Figure 7 and Figure 8 The bidirectional ESD diode shown in the figure can also have 6 or 8 unit structures. In the present application, the number of unit structures is not limited. In the present embodiment, the formation of 4 unit structures is taken as an example for explanation.

[0068] In the first unit structure, the first doping region 103 and the second doping region 104 form a first diode, and in the second unit structure, the first doping region 103 and the second doping region 104 form a second diode.

[0069] Forming the isolation structure 105 may include two steps of forming a trench and filling the trench with an insulating material, wherein the insulating material may be an oxide. In other embodiments, the isolation region 105 extends below the buried layer 102 to isolate the buried layer 102 .

[0070] In other embodiments, forming the isolation structure 105 may also include forming a trench and filling a layer of insulating material on the bottom wall of the side wall in the trench, wherein the insulating material may be an oxide, and then filling the trench with a layer of insulating material on the bottom wall of the side wall with polysilicon material.

[0071] In other embodiments, the method for forming a bidirectional ESD diode further includes: forming an interlayer dielectric layer covering the substrate 101 on the upper surface of the substrate 101, wherein the interlayer dielectric layer exposes the upper surfaces of the first doped region 103 and the second doped region 104. The material of the interlayer dielectric layer is one or more of silicon oxide and silicon nitride.

[0072] In other embodiments, the method for forming a bidirectional ESD diode further includes: forming an ohmic connection layer on the upper surface of the first doping region 103 and the second doping region 104. The ohmic connection layer is a metal silicide, and specifically, the metal silicide includes one or more of germanium silicide, selenium silicide, and gallium silicide.

[0073] In other embodiments, the method for forming a bidirectional ESD diode also includes: forming a metal layer above the interlayer dielectric layer, wherein the metal layer is used to electrically connect the second doped region in the unit structure with the first doped region in the unit structure adjacent thereto, and to electrically connect the first doped region in the first unit structure with the second doped region in the last unit structure.

[0074] In other embodiments, the bidirectional ESD diode also includes a metal layer located above the interlayer dielectric layer, and the metal layer is used to electrically connect the second doped region in the unit structure with the first doped region in the unit structure adjacent thereto, and to electrically connect the first doped region in the first unit structure with the second doped region in the last unit structure.

[0075] The unit structures are arranged from left to right in the substrate 101. If the first unit structure from the left is defined as the first unit structure, then the rightmost unit structure is the last unit structure. In other words, the rightmost unit structure is the first unit structure and the leftmost unit structure is the last unit structure.

[0076] In this embodiment, specifically, the second doping region 104 in the first unit structure is electrically connected to the first doping region 103 in the second unit structure through a metal connection structure located in the first metal layer 107; the second doping region 104 in the second unit structure is electrically connected to the first doping region 103 in the third unit structure through a metal connection structure located in the first metal layer 107, and is led to the second input / output terminal I / O-2; the second doping region 104 in the third unit structure is electrically connected to the first doping region 103 in the fourth unit structure through a metal connection structure located in the first metal layer 107; the first doping region 103 in the first unit structure is electrically connected to the second doping region 104 in the fourth unit structure through a metal connection structure located in the second metal layer 106, and is led to the first input / output terminal I / O-1. In this example, the metal layer includes a first metal layer 107 and a second metal layer 106. In other embodiments, there is no limitation on the number of metal layers. That is, the electrical connection between the first doping region 103 and the second doping region 104 in the above-mentioned unit structure may be completed in one layer of metal structure, or the electrical connection between the first doping region 103 and the second doping region 104 in the above-mentioned unit structure may be completed through three or four layers of metal structure.

[0077] In this embodiment, the distance between the upper surface of the buried layer 102 and the upper surface of the substrate is 8 to 20 um. In other embodiments, the depth of the buried layer 102 in the substrate 101 can be designed according to requirements, and the depth of the buried layer 102 should be such that the second doped region 104 located on the surface of the substrate 101 cannot penetrate the buried layer 102. Preferably, the depth of the buried layer can be 12 um. In addition, in this example, the buried layer 102 can be injected into the entire substrate, so that the step of injecting the buried layer 102 does not require a mask, which can save the mask cost.

[0078] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A bidirectional ESD diode, characterized in that: include: a substrate of a first doping type; a buried layer having a second doping type in the substrate; as well as at least 2N unit structures located in the substrate, the unit structures comprising: a first doping region having a first doping type and a second doping region having a second doping type extending from the upper surface of the substrate and into the interior thereof; At least one isolation region between every two adjacent unit structures; The isolation region extends from the upper surface of the substrate at least to the upper surface of the buried layer, and N is a positive integer greater than or equal to 1.

2. The bidirectional ESD diode according to claim 1, characterized in that: The width of the buried layer is the same as that of the substrate.

3. The bidirectional ESD diode according to claim 1, characterized in that: The isolation region extends from the upper surface of the substrate to below the buried layer.

4. The bidirectional ESD diode according to claim 1, characterized in that: Also includes: an isolation region between a first unit structure and a first edge of the bidirectional ESD diode adjacent to the first unit structure, and an isolation region between a 2Nth unit structure and a second edge of the bidirectional ESD diode adjacent to the 2Nth unit structure, The isolation region at least extends from the upper surface of the substrate to the upper surface of the buried layer, 2N unit structures are arranged in sequence, and the first edge and the second edge are arranged opposite to each other.

5. The bidirectional ESD diode according to claim 1, characterized in that: The distance between the upper surface of the buried layer and the upper surface of the substrate is 8-20 um.

6. The bidirectional ESD diode according to claim 1, characterized in that: The distance between two adjacent unit structures is 2-5 um.

7. The bidirectional ESD diode according to claim 1, characterized in that: When N=1, of the two unit structures arranged sequentially, the first doped region in the first unit structure is electrically connected to the second doped region in the second unit structure and led to the first input / output terminal, and the second doped region in the first unit structure is electrically connected to the first doped region in the second unit structure and led to the second input / output terminal.

8. The bidirectional ESD diode according to claim 1, characterized in that: When N is greater than or equal to 2, for the 2N unit structures arranged in sequence, the second doping region in the previous unit structure is electrically connected to the first doping region in the adjacent subsequent unit structure; wherein the second doping region in the Nth unit structure is electrically connected to the first doping region in the N+1th unit structure and is led to the second input / output terminal; the first doping region in the first unit structure is electrically connected to the second doping region in the 2Nth unit structure and is led to the first input / output terminal.

9. The bidirectional ESD diode according to claim 1, characterized in that: Also includes: an interlayer dielectric layer covering the upper surface of the substrate, wherein the interlayer dielectric layer exposes the upper surfaces of the first doped region and the second doped region; an ohmic connection layer located on upper surfaces of the first doping region and the second doping region; A metal layer located above the interlayer dielectric layer, wherein the metal layer is used to electrically connect the second doped region in the Nth unit structure with the first doped region in the N+1th unit structure; and is used to electrically connect the first doped region in the first unit structure with the second doped region in the 2Nth unit structure.

10. The bidirectional ESD diode according to claim 9, characterized in that: Also includes: A pad structure is located above the metal layer, and the pad structure is used for electrically connecting the bidirectional ESD diode to the outside.

11. A method for manufacturing a bidirectional ESD diode, characterized in that: The method comprises: providing a substrate having a first doping type; forming a buried layer having a second doping type in the substrate; Forming 2N unit structures in the substrate, wherein the unit structures include: a first doping region having a first doping type and a second doping region having a second doping type extending from the upper surface of the substrate to the inside thereof; forming at least one isolation region between every two adjacent unit structures in the substrate, wherein the isolation region extends from the upper surface of the substrate to at least the upper surface of the buried layer; N is a positive integer greater than or equal to 1.

12. The manufacturing method according to claim 11, characterized in that: The method further comprises: The isolation region extends from the upper surface of the substrate to below the buried layer.

13. The manufacturing method according to claim 11, characterized in that: The method further comprises: forming an isolation region between a first unit structure and a first edge of the bidirectional ESD diode adjacent to the first unit structure, and forming an isolation region between a 2Nth unit structure and a second edge of the bidirectional ESD diode adjacent to the 2Nth unit structure, Among them, 2N unit structures are arranged in sequence, the first edge and the second edge are arranged opposite to each other, and the isolation region extends from the upper surface of the substrate at least to the upper surface of the buried layer.

14. The manufacturing method according to claim 11, characterized in that: The method further comprises: forming an interlayer dielectric layer covering the substrate on the upper surface of the substrate, wherein the interlayer dielectric layer exposes the upper surfaces of the first doped region and the second doped region; forming an ohmic connection layer on upper surfaces of the first doping region and the second doping region; A metal layer is formed above the interlayer dielectric layer, wherein the metal layer is used to electrically connect the second doped region in the Nth unit structure with the first doped region in the N+1th unit structure; and is used to electrically connect the first doped region in the first unit structure with the second doped region in the 2Nth unit structure.

15. The manufacturing method according to claim 14, characterized in that: The method further comprises: A pad structure is formed above the metal layer, wherein the pad structure is used to electrically connect the bidirectional ESD diode to the outside.

16. The manufacturing method according to claim 11, characterized in that: The distance between the upper surface of the buried layer and the upper surface of the substrate is 8-20 um.

Images