Groove type Schottky barrier diode and manufacturing method thereof

Abstract

The present invention relates to a trench-type Schottky barrier diode and a manufacturing method thereof, the trench-type Schottky barrier diode comprising: a substrate having a first conductivity type; the first conductive type layer is located on the substrate, and the doping concentration of the first conductive type layer is smaller than that of the substrate; the groove structure extends from the front surface of the first conductive type layer to the substrate; the trench structure comprises a conductive material, and further comprises a dielectric layer surrounding the conductive material from the side surface and the bottom surface; a Schottky barrier layer on the first conductivity type layer and the trench structure; the second conductive type region is located below the groove structure, the top of the second conductive type region is in direct contact with the bottom of the dielectric layer, and the bottom of the second conductive type region is separated from the substrate by part of the first conductive type layer. According to the invention, the forward conduction voltage drop of the device can be reduced, and the reverse voltage withstanding characteristic can be maintained at the same time.

Description

Technical Field

[0001] The invention relates to the field of semiconductor manufacturing, in particular to a trench type Schottky barrier diode, and also to a manufacturing method of the trench type Schottky barrier diode. Background Art

[0002] Schottky barrier diode (SBD) is generally a metal-semiconductor device made of Schottky metal as the positive electrode and N-type semiconductor as the negative electrode, using the potential barrier formed on the contact surface of the two to have the rectifying property. There are a large number of electrons in N-type semiconductors, while there are only a very small number of free electrons in metals, so electrons will diffuse from N-type semiconductors with high concentrations to metals with low concentrations. There are no holes in metals, so there is no diffusion movement of holes from metals to N-type semiconductors. As electrons continue to diffuse from N-type semiconductors to metals, the electron concentration on the surface of N-type semiconductors gradually decreases, and the surface electrical neutrality is destroyed, so a potential barrier is formed, and its electric field direction is from N-type semiconductors to metals. However, under the action of this electric field, electrons in the metal will also drift from the metal to the N-type semiconductor, thereby weakening the electric field formed by the diffusion movement. When a space charge region of a certain width is established, the electron drift movement caused by the electric field and the electron diffusion movement caused by different concentrations reach a relative balance, and a Schottky barrier is formed. Schottky barrier diode is a low-power, ultra-high-speed semiconductor device. The most notable features are the extremely short reverse recovery time and reduced forward conduction voltage.

[0003] In recent years, trench structures have been used in the production of Schottky barrier diodes. Trench Schottky barrier diodes have two main advantages: first, the traditional planar structure is prone to surface breakdown, which poses a challenge to the reliability of the device, while the trench Schottky barrier diode overcomes this shortcoming of the planar structure; second, the trench Schottky barrier diode uses the charge balance principle to increase the breakdown voltage of the device.

[0004] The forward conduction characteristics of trench Schottky diodes affect their performance as power devices. It is generally believed that the lower the forward conduction voltage drop, the better the device characteristics. However, the two parameters of forward conduction voltage drop and reverse withstand voltage are usually in a contradictory relationship. The pursuit of a lower forward conduction voltage drop usually leads to a decrease in reverse withstand voltage, while increasing the reverse withstand voltage easily leads to an increase in the forward conduction voltage drop. Summary of the invention

[0005] Based on this, it is necessary to provide a trench Schottky barrier diode that can take into account both forward conduction voltage drop and reverse withstand voltage and a manufacturing method thereof.

[0006] A trench-type Schottky barrier diode comprises: a substrate having a first conductivity type; a first conductivity type layer located on the substrate, the doping concentration of the first conductivity type layer being less than the doping concentration of the substrate; a trench structure extending from a first surface of the first conductivity type layer toward the substrate, the first surface being a side of the first conductivity type layer facing away from the substrate; the trench structure comprising a conductive material and also comprising a dielectric layer surrounding the conductive material from the side and bottom; a Schottky barrier layer located on the first conductivity type layer; a second conductivity type region located below the trench structure, the top of the second conductivity type region being in direct contact with the bottom of the dielectric layer, and the bottom of the second conductivity type region being separated from the substrate by a portion of the first conductivity type layer; the first conductivity type and the second conductivity type being opposite conductivity types.

[0007] In the above trench-type Schottky barrier diode, the PN junction formed by the second conductive type region and the first conductive type layer can withstand reverse withstand voltage, so it has a strong reverse withstand voltage capability. And because the trench depth reaches the second conductive type region, the drift region resistance will be reduced to a certain extent when the device is forward-conducted, resulting in a reduction in the forward conduction voltage drop of the device.

[0008] In one of the embodiments, the distance between the bottom of the dielectric layer and the top of the substrate is no greater than 20 microns.

[0009] In one embodiment, the thickness of the second conductive type region is less than 20 micrometers, and the thickness direction is the direction from the first conductive type layer to the substrate.

[0010] In one of the embodiments, it further includes: a front electrode located on the Schottky barrier layer; and a back electrode located on a side of the substrate away from the first conductive type layer.

[0011] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0012] In one embodiment, the substrate is a silicon substrate.

[0013] In one embodiment, the first conductive type layer is a silicon epitaxial layer.

[0014] In one of the embodiments, the conductive material is polysilicon of a first conductivity type.

[0015] In one embodiment, the dielectric layer is made of silicon oxide.

[0016] In one embodiment, the doping concentration of the substrate is 10 18 ~10 21 / cm3 。

[0017] In one embodiment, the doping concentration of the first conductivity type layer is 10 14 ~10 17 / cm 3 。

[0018] In one of the embodiments, the depth of the trench structure is more than 75% of the thickness of the first conductivity type layer.

[0019] A method for manufacturing a trench-type Schottky barrier diode, comprising: obtaining a wafer, the wafer having a substrate of a first conductivity type and a first conductivity type layer on the substrate, the doping concentration of the first conductivity type layer being less than that of the substrate; forming a trench in the first conductivity type layer; doping the bottom of the trench to form a second conductivity type region below the trench, the bottom of the trench reaching the top of the second conductivity type region, and the bottom of the second conductivity type region being separated from the substrate by a part of the first conductivity type layer; forming a dielectric layer on the inner surface of the trench; filling the trench with the formed dielectric layer with a conductive material; and forming a Schottky barrier layer on the first conductivity type layer.

[0020] In the above method for manufacturing a trench-type Schottky barrier diode, the PN junction formed by the second conductivity type region and the first conductivity type layer can withstand reverse breakdown voltage, so it has a strong reverse breakdown voltage withstand ability. And since the trench depth reaches the second conductivity type region, the drift region resistance will be reduced to a certain extent when the device conducts forward, resulting in a reduction in the forward conduction voltage drop of the device.

[0021] In one embodiment, the depth of the trench formed in the step of forming a trench in the first conductivity type layer is more than 75% of the thickness of the first conductivity type layer.

[0022] In one embodiment, the step of doping the bottom of the trench includes implanting ions of a second conductivity type into the bottom of the trench by ion implantation, and the implantation energy is 50 kev to 200 kev.

[0023] In one embodiment, after the step of implanting ions of a second conductivity type into the bottom of the trench by ion implantation, the method further includes a step of heat-treating the wafer, and after the heat treatment, the thickness of the second conductivity type region is less than 20 microns, and the thickness direction is from the first conductivity type layer to the substrate.

[0024] In one embodiment, the doping concentration of the substrate is 10 18 ~10 21 / cm 3.

[0025] In one embodiment, the doping concentration of the first conductive type layer is 10 14 ~10 17 / cm 3 .

[0026] In one of the embodiments, the distance between the bottom of the trench and the top of the substrate is no more than 20 microns.

[0027] In one embodiment, the substrate is a silicon substrate.

[0028] In one embodiment, the first conductive type layer is a silicon epitaxial layer.

[0029] In one of the embodiments, the conductive material is polysilicon of a first conductivity type.

[0030] In one embodiment, the dielectric layer is made of silicon oxide.

[0031] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood.

[0033] Figure 1 is a schematic cross-sectional structure diagram of a trench Schottky barrier diode in one embodiment of the present application;

[0034] Figure 2a This is a simulation diagram of the electric field distribution of a trench Schottky barrier diode according to an embodiment of the present application. Figure 2b A simulation diagram of the breakdown current trend of a trench Schottky barrier diode according to an embodiment of the present application;

[0035] Figure 3a It is the electric field distribution simulation diagram of the trench Schottky barrier diode of the comparative example, Figure 3b A simulation diagram of the breakdown current trend of a trench Schottky barrier diode of a comparative example;

[0036] Figure 4 is a flow chart of a method for manufacturing a trench Schottky barrier diode in one embodiment of the present application;

[0037] Figure 5a to Figure 5d Is adopted Figure 4Schematic diagram of the cross section of the device during the process of manufacturing a trench Schottky barrier diode using the method shown. DETAILED DESCRIPTION

[0038] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0040] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0041] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0042] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0043] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0044] The semiconductor field vocabulary used in this article is technical vocabulary commonly used by technical personnel in this field. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0045] It is difficult to balance the forward conduction voltage drop and reverse withstand voltage of trench-type Schottky diodes. An exemplary trench-type Schottky diode adopts a deep trench structure, extending the trench to pass through the bottom of the drift region and contacting the substrate, thereby achieving the purpose of reducing body resistance and reducing forward conduction voltage drop. However, since the bottom of the trench is in contact with the high-concentration substrate, reverse breakdown is easily caused. Another exemplary trench-type Schottky diode introduces a P-type doped floating plate structure between the bottom of the trench and the substrate to improve the reverse breakdown characteristics. However, the forward conduction voltage drop of this trench-type Schottky diode is relatively high.

[0046] The present application is dedicated to reducing the forward conduction voltage drop of a trench Schottky diode while maintaining the reverse withstand voltage characteristic. Figure 11 is a schematic cross-sectional view of a trench Schottky barrier diode in an embodiment of the present application. The trench Schottky barrier diode includes a substrate 170, a first conductive type layer 160, at least one second conductive type region 150, a Schottky barrier layer 120 and at least one trench structure.

[0047] The substrate 170 has a first conductivity type. The first conductivity type layer 160 is located on the substrate 170, and the doping concentration of the first conductivity type layer 160 is less than the doping concentration of the substrate 170. The first conductivity type layer 160 serves as a drift region of the device. The trench structure extends from the first surface of the first conductivity type layer 160 (i.e., the side away from the substrate 170) to the substrate 170. The trench structure includes a conductive material 140, and a dielectric layer 130 surrounding the conductive material 140 from the side and bottom. That is, the trench structure includes a dielectric layer 130 formed on the inner surface of the trench, and a conductive material 140 filled in the trench. The dielectric layer 130 is used for insulation isolation. The second conductivity type region 150 is located directly below the trench, and the top of the second conductivity type region 150 is in direct contact with the bottom of the dielectric layer 130, and the bottom of the second conductivity type region 150 is separated from the substrate 170 by a portion of the first conductivity type layer 160. The Schottky barrier layer 120 is located on the first conductive type layer 160. Figure 1 In the embodiment shown, the first conductivity type is N type, and the second conductivity type is P type. Further, the substrate 170 is an N+ silicon substrate, the first conductivity type layer 160 is an N-silicon epitaxial layer, and the second conductivity type region 150 is a P type doped region.

[0048] In the above trench-type Schottky barrier diode, the PN junction formed by the second conductive type region 150 and the first conductive type layer 160 can withstand reverse withstand voltage, so it has a strong reverse withstand voltage capability. And because the trench depth reaches the second conductive type region 150, the drift region resistance will be reduced to a certain extent when the device is forward-conducted, resulting in a reduction in the forward conduction voltage drop of the device.

[0049] In one embodiment of the present application, the distance between the bottom of the dielectric layer 130 and the top of the substrate 170 is no greater than 20 microns. The trench depth is set deeper, but a position for forming the second conductive type region 150 is left between the trench bottom and the top of the substrate 170 .

[0050] In one embodiment of the present application, the thickness of the second conductive type region 150 is less than 20 micrometers, and the thickness direction is the direction from the first conductive type layer 160 to the substrate 170, that is, Figure 1 Further, the thickness of the second conductive type region 150 is not less than 0.1 micrometer.

[0051] In one embodiment of the present application, the trench structure is a deep trench structure, and the depth of the trench structure is greater than 75% of the thickness of the first conductive type layer 160 .

[0052] exist Figure 1 In the illustrated embodiment, the trench Schottky barrier diode further includes a front electrode 110 located on the Schottky barrier layer 120, and a back electrode 180 located on the bottom surface of the substrate 170. In one embodiment of the present application, the front electrode 110 is an anode, and the back electrode 180 is a cathode. In one embodiment of the present application, the front electrode 110 is a metal film composed of one or more of AlSiCu, Ti, Ni, and Ag. In one embodiment of the present application, the back electrode 180 is a metal film composed of one or more of Ti, Ni, and Ag.

[0053] In one embodiment of the present application, the conductive material 140 is polysilicon of the first conductivity type. In one embodiment of the present application, the material of the dielectric layer 130 is silicon oxide, such as silicon dioxide. In one embodiment of the present application, the Schottky barrier layer 120 is a metal silicide formed by reacting at least one metal (i.e., Schottky metal layer) of Ti, Pt, Ni, Cr, W, Mo, and Co with the first conductivity type layer 160 through heat treatment. A Schottky metal layer is also formed on the trench structure. The Schottky barrier layer 120 forms a Schottky contact with the first conductivity type layer 160 below.

[0054] Figure 2a This is a simulation diagram of the electric field distribution of a trench Schottky barrier diode according to an embodiment of the present application. Figure 3a It is the electric field distribution simulation diagram of the trench Schottky barrier diode of the comparative example, namely Abs(Electric Field(ElectricField-Vector))[V*cm^-1], Figure 2a The bottom two lines are 6.0E+01 and 1.1E-07. Figure 3a The bottom two lines of scale are 6.0E+01 and 2.3E-07. Figure 2b This is a simulation diagram of the breakdown current trend of a trench Schottky barrier diode according to an embodiment of the present application. Figure 3bIt is a simulation diagram of the breakdown current trend of the trench Schottky barrier diode of the comparative example, that is, Abs (TotalCurrent Density (Total Current Density-Vector)) [A*cm^-2]. The bottom of the trench of the comparative example is separated from the second conductive type region (P-type doped region) by the first conductive type layer (drift region). The simulated reverse breakdown voltage of the comparative example is 54.18V, while the reverse breakdown voltage obtained by the simulation of the embodiment of the present application is 57.89V. It can be seen that the structure in which the top of the second conductive type region 150 of the embodiment of the present application is in direct contact with the bottom of the dielectric layer 130 can improve the depletion capacity of the device during reverse withstand voltage and increase the reverse breakdown voltage (reverse withstand voltage) of the device. Figure 2a , Figure 2b , Figure 3a , Figure 3b The X-axis is the size in microns, and the Y-axis is the coordinate in the thickness direction in microns.

[0055] Figure 4 1 is a flow chart of a method for manufacturing a trench Schottky barrier diode in an embodiment of the present application, comprising the following steps:

[0056] S410, obtaining a wafer having a substrate and a first conductive type layer formed thereon.

[0057] Reference Figure 5a , a first conductive type layer 160 is formed on the substrate 170. In one embodiment of the present application, step S410 includes growing a lightly doped silicon epitaxial layer as the first conductive type layer 160 on the provided silicon substrate 170. In one embodiment of the present application, the doping concentration of the substrate is 10 18 ~10 21 / cm 3 In one embodiment of the present application, the doping concentration of the first conductive type layer 160 is 10 14 ~10 17 / cm 3 .

[0058] S420 , forming a trench in the first conductive type layer.

[0059] In one embodiment of the present application, a groove is formed in the first conductive type layer 160 by an etching process. Further, before etching, an oxide layer (such as a silicon dioxide layer) may be deposited on the first conductive type layer 160. Then, the first conductive type layer 160 is formed by an etching process. Figure 5bA hard mask layer 192, such as a silicon nitride layer, is formed on the first conductive type layer 160 (not shown). The formation of the hard mask layer 192 before etching can protect the cleanliness of the upper surface of the first conductive type layer 160. The thickness of the hard mask layer 192 can be set according to the etching requirements. Thereafter, a photoresist layer 194 is formed on the hard mask layer 192 by photolithography. Specifically, after a photoresist is coated on the hard mask layer 192, the photoresist is exposed through a corresponding photomask, and after development, a photoresist layer 194 exposing an injection window is formed. Then, the hard mask layer 192 is etched using the photoresist layer 194 as an etching barrier layer, so that the hard mask layer 192 below the injection window can be removed, while the hard mask layer 192 covering the position of the photoresist layer 194 is retained. Finally, the oxide layer and the first conductive type layer 160 are etched downward to form a groove 131, see Figure 5b .

[0060] In one embodiment of the present application, the distance between the bottom of the trench 131 and the top of the substrate 170 is no greater than 20 micrometers.

[0061] In one embodiment of the present application, the trench 131 is a deep trench, and the depth of the trench is greater than 75% of the thickness of the first conductive type layer 160 .

[0062] S430, doping the bottom of the trench to form a second conductivity type region below the trench.

[0063] In one embodiment of the present application, step S430 is to inject ions of the second conductivity type into the bottom of the trench 131 through an ion implantation process to form a second conductivity type region 150. In one embodiment of the present application, the implantation energy is 50kev to 200kev. In one embodiment of the present application, after the second conductivity type ions are implanted, a step of heat treating the wafer is also included. After the thermal annealing treatment, the implanted second conductivity type ions further diffuse in the first conductivity type layer 160 to form a second conductivity type region 150. In one embodiment of the present application, the first conductivity type is N type and the second conductivity type is P type.

[0064] S440 , forming a dielectric layer on the inner surface of the trench.

[0065] In one embodiment of the present application, an oxide layer is formed on the inner surface of the trench 131 by thermal oxidation to serve as the dielectric layer 130 .

[0066] S450 , filling the trench with a conductive material.

[0067] In one embodiment of the present application, step S450 is to deposit polysilicon of the first conductivity type into the trench 131 as the conductive material 140 .

[0068] S460 , forming a Schottky barrier layer on the first conductive type layer.

[0069] In one embodiment of the present application, after step S450 and before step S460, a step of removing the conductive material 140 outside the groove 131 by chemical mechanical polishing (CMP) is further included. After the conductive material 140 is planarized, the structure shown in 5c is obtained.

[0070] In one embodiment of the present application, step S460 includes:

[0071] S462 , depositing a Schottky metal layer on the first conductive type layer 160 and the conductive material 140 .

[0072] In one embodiment of the present application, the Schottky metal layer includes at least one metal of Ti, Pt, Ni, Cr, W, Mo, and Co.

[0073] S464 , through heat treatment, the Schottky metal layer and the first conductive type layer 160 react to form a metal silicide as the Schottky barrier layer 120 .

[0074] In one embodiment of the present application, the heat treatment in step S464 adopts a rapid thermal annealing process. Figure 5d .

[0075] In the manufacturing method of the trench type Schottky barrier diode, the PN junction formed by the second conductive type region 150 and the first conductive type layer 160 can withstand reverse withstand voltage, so it has a strong reverse withstand voltage capability. And because the trench depth reaches the second conductive type region 150, the drift region resistance will be reduced to a certain extent when the device is forward-conducted, resulting in a reduction in the forward conduction voltage drop of the device.

[0076] In one embodiment of the present application, after step S460, the steps of forming a front electrode 9 on the Schottky barrier layer 120 and forming a back electrode 10 on the bottom surface (lower surface) of the substrate 170 are also included, see Figure 1 Specifically, metal can be sputtered on the lower surface of the substrate 170 and the upper surface of the Schottky barrier layer 120 to form a cathode and an anode, respectively. In one embodiment of the present application, the front electrode 110 is a metal film composed of one or more of AlSiCu, Ti, Ni, and Ag. In one embodiment of the present application, the back electrode 180 is a metal film composed of one or more of Ti, Ni, and Ag.

[0077] In one embodiment of the present application, the thickness of the second conductive type region 150 is less than 20 micrometers. Further, the thickness of the second conductive type region 150 is not less than 0.1 micrometers.

[0078] The manufacturing method of the trench Schottky barrier diode of the present application is based on the same inventive concept as the trench Schottky barrier diode. For the contents not specifically described in the manufacturing method of the trench Schottky barrier diode, please refer to the introduction of the trench Schottky barrier diode in the previous text.

[0079] It should be understood that, although the various steps in the flowchart of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0080] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0081] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0082] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A trench type Schottky barrier diode, It is characterized in that include: a substrate having a first conductivity type; A first conductive type layer, located on the substrate, wherein the doping concentration of the first conductive type layer is lower than the doping concentration of the substrate; A groove structure extending from a first surface of the first conductive type layer toward the substrate, the first surface being a side of the first conductive type layer facing away from the substrate; the groove structure comprises a conductive material and a dielectric layer surrounding the conductive material from the side and bottom surfaces; A Schottky barrier layer, located on the first conductive type layer; A second conductive type region, located below the trench structure, with a top of the second conductive type region directly contacting the bottom of the dielectric layer, and a bottom of the second conductive type region being separated from the substrate by a portion of the first conductive type layer; The first conductivity type and the second conductivity type are opposite conductivity types.

2. The trench Schottky barrier diode according to claim 1, It is characterized in that The distance between the bottom of the dielectric layer and the top of the substrate is no greater than 20 microns.

3. The trench Schottky barrier diode according to claim 1 or 2, It is characterized in that The thickness of the second conductive type region is less than 20 micrometers, and the thickness direction is the direction from the first conductive type layer to the substrate.

4. The trench Schottky barrier diode according to claim 1, It is characterized in that Also includes: A front electrode, located on the Schottky barrier layer; The back electrode is located on a side of the substrate facing away from the first conductive type layer.

5. The trench Schottky barrier diode according to claim 1, It is characterized in that The first conductivity type is N type, and the second conductivity type is P type.

6. A method for manufacturing a trench Schottky barrier diode, include: Obtaining a wafer, wherein the wafer is formed with a substrate of a first conductivity type and a first conductivity type layer on the substrate, wherein a doping concentration of the first conductivity type layer is less than a doping concentration of the substrate; forming a groove in the first conductive type layer; Doping the bottom of the trench to form a second conductive type region below the trench, wherein the bottom of the trench reaches the top of the second conductive type region, and the bottom of the second conductive type region is separated from the substrate by a portion of the first conductive type layer; forming a dielectric layer on an inner surface of the trench; Filling the trench where the dielectric layer has been formed with a conductive material; A Schottky barrier layer is formed on the first conductive type layer.

7. The method for manufacturing a trench Schottky barrier diode according to claim 6, It is characterized in that The step of doping the bottom of the trench includes implanting ions of the second conductivity type into the bottom of the trench by ion implantation, with an implantation energy of 50kev to 200kev.

8. The method for manufacturing a trench Schottky barrier diode according to claim 7, It is characterized in that After the step of injecting the second conductive type ions into the bottom of the groove by ion implantation, the step also includes heat treating the wafer. After the heat treatment, the thickness of the second conductive type area is less than 20 microns, and the thickness direction is the direction from the first conductive type layer to the substrate.

9. The method for manufacturing a trench Schottky barrier diode according to claim 6, It is characterized in that The doping concentration of the substrate is 10 18 ~10 21 / cm 3 , and / or the doping concentration of the first conductive type layer is 10 14 ~10 17 / cm 3 .

10. The method for manufacturing a trench Schottky barrier diode according to claim 6, It is characterized in that The distance between the bottom of the trench and the top of the substrate is no greater than 20 micrometers.

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