Semiconductor structure and manufacturing method thereof

Abstract

The invention provides a semiconductor structure and a manufacturing method thereof, and the method comprises the steps: forming a first N-type drift region and a second N-type drift region with relatively high concentration based on a first photomask, and then forming a first P-type drift region, a second P-type drift region and a P-type doping adjustment region based on a second photomask, the P-type doping adjusting region is located in the second N-type drift region to partially neutralize the N-type doping ions in the corresponding region, and one end, facing the first N-type drift region, of the P-type doping adjusting region is connected with one end, facing the first N-type drift region, of the second N-type drift region. According to the manufacturing method, different photomasks and ion implantation combinations are utilized, non-uniform doping distribution of the drift region is formed under the condition that the photomasks and the ion implantation steps are not additionally added, the relatively low-concentration doping region can ensure that the first peak value of the substrate current is within the HCI reliability safety range, and the performance of the device is improved. And the doped region with relatively high concentration can prevent the depletion region from further expanding to the drain end, and inhibit a second peak value of the substrate current formed by the kirk effect.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] When the current density exceeds the impurity concentration in the drift region, the electric field peak is transferred to the near-drain end, the equipotential lines are very dense in the direction of the drain, and the electric field strength at the drain end increases greatly. This phenomenon is called the Kirk effect.

[0003] High voltage (HV) devices such as lateral double diffused MOSFET (LDMOS) are susceptible to the Kirk effect due to their high breakdown voltage characteristics. sub -V g (substrate current - gate voltage) will find that in addition to the traditional hot carrier injection (HCI) peak, when the gate voltage is equal to the power supply voltage (V g = VDD), a second peak due to the Kirk effect appears. The reason is that when the gate voltage V g and drain current I d When the value increases, the position of the maximum electric field in the channel moves to the drain depletion region, causing enhanced impact ionization.

[0004] The Kirk effect will cause the breakdown voltage of the device to decrease in the on state and reduce the safe operating area. Increasing the ion implantation concentration in the drift region of HVMOS can improve the Kirk effect, but the increase in the drift region doping concentration will worsen the I sub The first peak of the device reliability risk increases.

[0005] Therefore, how to improve the structure of high voltage devices and their preparation methods to suppress the I formed by the Kirk effect without increasing the cost and ensuring the reliability of the device? sub The second peak value has become an important technical problem that needs to be solved urgently by technicians in this field.

[0006] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0007] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a semiconductor structure and a method for manufacturing the same, which is used to solve the problem that it is difficult to suppress the I2C generated by the Kirk effect in high-voltage devices without increasing the cost and ensuring the reliability of the devices in the prior art. sub The problem with the second peak.

[0008] To achieve the above-mentioned object and other related objects, the present invention provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0009] Providing a semiconductor layer, and forming a first N-type drift region and a second N-type drift region spaced apart in a horizontal direction in the semiconductor layer based on a first mask;

[0010] Based on a second photomask, a first P-type drift region, a second P-type drift region and a P-type doping adjustment region are formed in the semiconductor layer, wherein the first P-type drift region is located on a side of the first N-type drift region away from the second N-type drift region and is adjacent to the first N-type drift region, the second P-type drift region is located on a side of the second N-type drift region away from the first N-type drift region and is adjacent to the second N-type drift region, the P-type doping adjustment region is located in the second N-type drift region to partially neutralize N-type doping ions in the second N-type drift region in a corresponding region, one end of the P-type doping adjustment region facing the first N-type drift region is connected to one end of the second N-type drift region facing the first N-type drift region, and one end of the P-type doping adjustment region away from the first N-type drift region is spaced a preset distance from one end of the second N-type drift region away from the first N-type drift region;

[0011] forming a gate structure on the semiconductor layer, the gate structure comprising a stacked gate dielectric layer and a gate conductive layer, the gate dielectric layer horizontally extending from a portion of the upper surface of the first N-type drift region to the upper surface of the P-type doping adjustment region;

[0012] An N-type heavily doped source region is formed on the upper surface layer of the first N-type drift region, an N-type heavily doped drain region is formed on the upper surface layer of the second N-type drift region, and a P-type heavily doped body lead-out region is formed on the upper surface layer of the first P-type drift region and the upper surface layer of the second P-type drift region.

[0013] Optionally, the N-type ion doping dose of the first N-type drift region and the second N-type drift region is the same, the P-type ion doping dose of the first P-type drift region and the second P-type drift region is the same, and the P-type ion doping dose of the first P-type drift region and the second P-type drift region is less than the N-type ion doping dose of the first N-type drift region and the second N-type drift region.

[0014] Optionally, forming a first N-type drift region and a second N-type drift region spaced apart in a horizontal direction in the semiconductor layer based on a first mask comprises the following steps:

[0015] forming a first photoresist layer on the semiconductor layer;

[0016] Patterning the first photoresist layer based on the first photomask to obtain a first opening and a second opening spaced apart in a horizontal direction in the first photoresist layer;

[0017] The semiconductor layer is implanted with N-type ions using the patterned first photoresist layer as a mask to obtain the first N-type drift region located below the first opening and the second N-type drift region located below the second opening.

[0018] Optionally, the N-type ion implantation includes one or more ion implantation processes, the total dose range of the N-type ion implantation is 1E12 atoms per square centimeter to 1E14 atoms per square centimeter, and the energy range of the N-type ion implantation is 10KeV-1000KeV.

[0019] Optionally, forming a first P-type drift region, a second P-type drift region and a P-type doping adjustment region in the semiconductor layer based on a second photomask comprises the following steps:

[0020] forming a second photoresist layer on the semiconductor layer;

[0021] Patterning the second photoresist layer based on the second photomask to obtain a third opening, a fourth opening, and a fifth opening spaced apart in a horizontal direction in the second photoresist layer, wherein the third opening is located at a side of the first N-type drift region away from the second N-type drift region, the fourth opening exposes an upper surface of an end of the second N-type drift region close to the first N-type drift region, and the fifth opening is located at a side of the second N-type drift region away from the first N-type drift region;

[0022] The semiconductor layer is implanted with P-type ions using the patterned second photoresist layer as a mask to obtain the first P-type drift region below the third opening, the P-type doping adjustment region below the fourth opening, and the second P-type drift region below the fifth opening.

[0023] Optionally, the P-type ion implantation includes one or more ion implantation processes, and the energy range of the P-type ion implantation is 10KeV-1000KeV.

[0024] Optionally, before forming a first N-type drift region and a second N-type drift region spaced apart in a horizontal direction in the semiconductor layer based on a first mask, the step of forming a P-well and an isolation structure in the semiconductor layer is also included, and the first N-type drift region, the second N-type drift region, the first P-type drift region and the second P-type drift region formed subsequently are all located in the P-well and have a bottom surface lower than a bottom surface of the isolation structure.

[0025] Optionally, the isolation structure includes a first isolation portion and a second isolation portion, the first isolation portion is located at the junction of a portion of the second N-type drift region that is not partially neutralized by the P-type doping adjustment region and the P-type doping adjustment region, and the second isolation portion is located at the junction of the second N-type drift region and the second P-type drift region.

[0026] Optionally, the isolation structure includes a third isolation portion and a fourth isolation portion, the third isolation portion is located on a side of the first P-type drift region away from the first N-type drift region, and a portion of the first P-type drift region extends horizontally to below the third isolation portion, and the fourth isolation portion is located on a side of the second P-type drift region away from the second N-type drift region, and a portion of the second P-type drift region extends horizontally to below the fourth isolation portion.

[0027] The present invention also provides a semiconductor structure, comprising:

[0028] Semiconductor layer,

[0029] A first N-type drift region and a second N-type drift region are located in the semiconductor layer and are spaced apart in a horizontal direction;

[0030] A first P-type drift region, a second P-type drift region and a P-type doping adjustment region are located in the semiconductor layer, the first P-type drift region is located on a side of the first N-type drift region away from the second N-type drift region and is adjacent to the first N-type drift region, the second P-type drift region is located on a side of the second N-type drift region away from the first N-type drift region and is adjacent to the second N-type drift region, the P-type doping adjustment region is located in the second N-type drift region to partially neutralize N-type doping ions in the second N-type drift region in a corresponding area, one end of the P-type doping adjustment region facing the first N-type drift region is connected to one end of the second N-type drift region facing the first N-type drift region, and one end of the P-type doping adjustment region away from the first N-type drift region is spaced a preset distance from one end of the second N-type drift region away from the first N-type drift region;

[0031] A gate structure, located on the semiconductor layer, the gate structure comprising a stacked gate dielectric layer and a gate conductive layer, the gate dielectric layer horizontally extending from a portion of the upper surface of the first N-type drift region to the upper surface of the P-type doping adjustment region;

[0032] An N-type heavily doped source region, located on an upper surface layer of the first N-type drift region;

[0033] An N-type heavily doped drain region, located on an upper surface layer of the second N-type drift region;

[0034] The P-type heavily doped body lead-out region is located on the upper surface layer of the first P-type drift region and the upper surface layer of the second P-type drift region.

[0035] As described above, the method for manufacturing the semiconductor structure of the present invention first forms the first and second N-type drift regions with relatively high concentrations based on a first mask, and then forms the first and second P-type drift regions and a P-type doping adjustment region based on a second mask, the P-type doping adjustment region is located in the second N-type drift region to partially neutralize the N-type doping ions in the second N-type drift region in the corresponding area, one end of the P-type doping adjustment region facing the first N-type drift region is connected to one end of the second N-type drift region facing the first N-type drift region, and one end of the P-type doping adjustment region away from the first N-type drift region is spaced a preset distance from one end of the second N-type drift region away from the first N-type drift region. The present invention utilizes different combinations of photomasks and ion implantation to form an uneven doping distribution in the drift region without adding additional photomasks and ion implantation steps, wherein a low-doped drift region is formed below the gate dielectric layer to suppress the maximum electric field in the region and ensure that the first peak value of the substrate current is within the HCI reliability safety range; a high-doped region is formed in the drift region close to the drain to prevent the depletion region from further expanding toward the drain end and suppress the second peak value of the substrate current formed by the Kirk effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a schematic diagram showing a structure obtained after forming a high-voltage region P-well and an isolation structure in a semiconductor layer in a method for manufacturing a high-voltage device.

[0037] Figure 2 It is a schematic diagram showing a structure obtained after forming a first N-type drift region and a second N-type drift region in a high-voltage region P-well in a method for manufacturing a high-voltage device.

[0038] Figure 3 It is a schematic diagram showing a structure obtained after forming a first P-type drift region and a second P-type drift region in a high-voltage region P well in a method for manufacturing a high-voltage device.

[0039] Figure 4 It shows a schematic diagram of the structure obtained after forming a high-voltage region gate dielectric layer, a gate conductive layer, a source / drain region and a body lead-out region in a method for manufacturing a high-voltage device.

[0040] Figure 5 The I of a high voltage device manufactured by a method for manufacturing a high voltage device is shown. sub -V G Graph.

[0041] Figure 6 The V of the high-voltage NMOS device is shown as the doping dose of the N-type drift region at the baseline doping dose, increased doping dose, and reduced doping dose. D -I D curve.

[0042] Figure 7 The I of the high-voltage NMOS device is shown as the doping dose of the N-type drift region at the baseline doping dose, increased doping dose, and reduced doping dose. sub -V g curve.

[0043] Figure 8 It is a process flow chart of the method for manufacturing the semiconductor structure of the present invention.

[0044] Fig. 9 It is a schematic diagram showing the structure obtained after forming the first N-type drift region and the second N-type drift region according to the method for manufacturing the semiconductor structure of the present invention.

[0045] Fig.10 It is a schematic diagram showing the structure obtained after forming the first P-type drift region, the second P-type drift region and the P-type doping adjustment region according to the manufacturing method of the semiconductor structure of the present invention.

[0046] Fig.11 It is a schematic diagram showing the structure obtained after forming a gate structure according to the method for manufacturing a semiconductor structure of the present invention.

[0047] Fig.12 It is a schematic diagram showing the structure obtained after forming source / drain regions and body lead-out regions according to the method for manufacturing the semiconductor structure of the present invention.

[0048] Component number description

[0049] 101 Semiconductor layer

[0050] 102 High voltage region P well

[0051] 103 Isolation Structure

[0052] 104 first patterned photoresist layer

[0053] 105 First N-type drift region

[0054] 106 Second N-type drift region

[0055] 107 second patterned photoresist layer

[0056] 108 First P-type drift region

[0057] 109 Second P-type drift region

[0058] 110 High voltage region gate dielectric layer

[0059] 111 gate conductive layer

[0060] 112 N-type heavily doped source region

[0061] 113 N-type heavily doped drain region

[0062] 114 P-type heavily doped body lead-out region

[0063] Steps S1 to S4

[0064] 201 Semiconductor layer

[0065] 202 First N-type drift region

[0066] 203 Second N-type drift region

[0067] 204 P-well

[0068] 205 Isolation Structure

[0069] 2051 First Isolation Department

[0070] 2052 Second Isolation Department

[0071] 2053 The Third Isolation Department

[0072] 5054 The Fourth Isolation Department

[0073] 206 first photoresist layer

[0074] 207 First Opening

[0075] 208 Second Opening

[0076] 209 First P-type drift region

[0077] 210 Second P-type drift region

[0078] 211 P-type doping adjustment region

[0079] 212 second photoresist layer

[0080] 213 The Third Opening

[0081] 214 The Fourth Opening

[0082] 215 The Fifth Opening

[0083] 216 gate dielectric layer

[0084] 217 gate conductive layer

[0085] 218 N-type heavily doped source region

[0086] 219 N-type heavily doped drain region

[0087] 220 P-type heavily doped body lead-out region DETAILED DESCRIPTION

[0088] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0089] See also Figures 1 to 12 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0090] See also Figures 1 to 4 , which is a structural schematic diagram of various steps of a method for manufacturing a high-voltage device, wherein at least the following steps are included:

[0091] (1) Figure 1 As shown, a semiconductor layer 101 is first provided, and a high voltage region P well 102 and an isolation structure 103 are formed in the semiconductor layer 101 .

[0092] (2) Figure 2 As shown, a first N-type drift region 105 and a second N-type drift region 106 are formed in the high-voltage region P-well 102 based on the first patterned photoresist layer 104 .

[0093] (3) Figure 3 As shown, a first P-type drift region 108 and a second P-type drift region 109 are formed in the high-voltage region P well 102 based on the second patterned photoresist layer 107 .

[0094] (4) Figure 4 As shown, a high-voltage region gate dielectric layer 110 is formed on the semiconductor layer 101, and the high-voltage region gate dielectric layer 110 horizontally extends from a portion of the surface of the first N-type drift region 105 to a portion of the surface of the second N-type drift region 106, and then a gate conductive layer 111 located on the high-voltage region gate dielectric layer 110, an N-type heavily doped source region 112 located on the upper surface of the first N-type drift region 105, an N-type heavily doped drain region 113 located on the upper surface of the second N-type drift region 106, and a P-type heavily doped body lead-out region 114 located on the upper surface of the first P-type drift region 108 and the upper surface of the second P-type drift region 109 are formed. In some embodiments, it can also include forming a lightly doped region between the gate edge and the source region, and between the gate edge and the drain region by ion implantation, so as to form impurities with a gradient between the source and drain regions and the channel to improve the short channel effect.

[0095] See also Figure 5 , which shows the I of the high voltage device made by the above method. sub -V G Curve, visible I sub It has a first peak and a second peak, wherein the first peak is caused by the hot carrier injection effect, and the second peak is when the gate voltage is equal to the power supply voltage (V G = VDD) is caused by the Kirk effect. The reason is that when the gate voltage V G and drain current I D When the voltage increases, the maximum electric field position in the channel moves to the drain depletion region, causing the impact ionization to be enhanced. The Kirk effect will cause the breakdown voltage of the device to decrease in the on state and the safe operating area to shrink.

[0096] See also Figure 6 , showing the V of the high-voltage NMOS device when the doping dose of the N-type drift region is the baseline doping dose, the increased doping dose, and the reduced doping dose. D -I D Curve, where VD is leakage and ID is leakage current.

[0097] See also Figure 7 , showing the I of the high-voltage NMOS device when the doping dose of the N-type drift region is the baseline doping dose, the increased doping dose, and the reduced doping dose. sub -V g The curve shows that the horizontal axis Vg is the gate voltage and the vertical axis Isub is the substrate current. It can be seen that increasing the ion implantation concentration in the drift region of HVMOS can improve the I caused by the Kirk effect. sub The second peak, but the increase of drift region doping concentration will worsen I sub The first peak of the device reliability risk increases.

[0098] The inventors of this application have improved the manufacturing method of high-voltage devices through a lot of analysis and research, and can suppress the second peak of the substrate current formed by the Kirk effect without adding extra costs and ensuring the reliability of the device. It should be pointed out that the "high voltage" mentioned in the present invention is a relative concept, relative to "low voltage" and "medium voltage", in which the power supply voltage of the low-voltage device is lower than the power supply voltage of the high-voltage device, and the specific voltage value is not particularly limited. For example, in one embodiment, the power supply voltage of the low-voltage device is 1.1V, the power supply voltage of the high-voltage device is 5V, and the power supply voltage of the medium-voltage device is between the low-voltage device and the high-voltage device. In another embodiment, the power supply voltage of the low-voltage device is 1.1V, the power supply voltage of the high-voltage device is 32V, and the device with a power supply voltage of 5V or 8V is counted as a medium-voltage device.

[0099] See also Figure 8, which is a process flow chart of a method for manufacturing a semiconductor structure of the present invention, comprises the following steps:

[0100] S1: providing a semiconductor layer, and forming a first N-type drift region and a second N-type drift region spaced apart in a horizontal direction in the semiconductor layer based on a first mask;

[0101] S2: forming a first P-type drift region, a second P-type drift region and a P-type doping adjustment region in the semiconductor layer based on a second photomask, wherein the first P-type drift region is located on a side of the first N-type drift region away from the second N-type drift region and is adjacent to the first N-type drift region, the second P-type drift region is located on a side of the second N-type drift region away from the first N-type drift region and is adjacent to the second N-type drift region, the P-type doping adjustment region is located in the second N-type drift region to partially neutralize N-type doping ions in the second N-type drift region in a corresponding area, one end of the P-type doping adjustment region facing the first N-type drift region is connected to one end of the second N-type drift region facing the first N-type drift region, and one end of the P-type doping adjustment region away from the first N-type drift region is spaced a preset distance from one end of the second N-type drift region away from the first N-type drift region;

[0102] S3: forming a gate structure on the semiconductor layer, the gate structure comprising a stacked gate dielectric layer and a gate conductive layer, the gate dielectric layer horizontally extending from a portion of the upper surface of the first N-type drift region to the upper surface of the P-type doping adjustment region;

[0103] S4: forming an N-type heavily doped source region on the upper surface layer of the first N-type drift region, forming an N-type heavily doped drain region on the upper surface layer of the second N-type drift region, and forming a P-type heavily doped body lead-out region on the upper surface layer of the first P-type drift region and the upper surface layer of the second P-type drift region.

[0104] The following will be combined Figure 9-12 Each step of the method for manufacturing the semiconductor structure of the present invention is described in detail.

[0105] First see Fig. 9 , performing the step S1: providing a semiconductor layer 201 , and forming a first N-type drift region 202 and a second N-type drift region 203 spaced apart in a horizontal direction in the semiconductor layer 201 based on a first mask.

[0106] As an example, before forming the first N-type drift region 202 and the second N-type drift region 203 spaced apart in the horizontal direction in the semiconductor layer 201 based on the first mask, the step of forming a P-well 204 and an isolation structure 205 in the semiconductor layer 201 is also included. The first N-type drift region 202 and the second N-type drift region 203 formed subsequently are both located in the P-well 204 and have a bottom surface lower than a bottom surface of the isolation structure 205.

[0107] Specifically, the isolation structure 205 is used to define the active area. The isolation structure 205 can be a shallow trench isolation (STI) structure or other suitable isolation structure (such as silicon local oxidation isolation LOCOS). Different device regions, different transistors in the same device region, or different doping regions of the same transistor are isolated from each other through the isolation structure 205.

[0108] As an example, forming the first N-type drift region 202 and the second N-type drift region 203 spaced apart in the horizontal direction in the semiconductor layer based on the first mask includes the following steps:

[0109] (1) forming a first photoresist layer 206 on the semiconductor layer 201 by spin coating or other suitable methods;

[0110] (2) performing photolithography processes such as exposure and development based on the first photomask (not shown) to pattern the first photoresist layer 206 to obtain first openings 207 and second openings 208 spaced apart in a horizontal direction in the first photoresist layer 206;

[0111] (3) Using the patterned first photoresist layer 206 as a mask, N-type ion implantation is performed on the semiconductor layer 201 to obtain the first N-type drift region 202 located below the first opening 207 and the second N-type drift region 203 located below the second opening 208 .

[0112] Specifically, the total dose of the N-type ion implantation is greater than the conventional dose, that is, greater than Figure 1-Figure 4 The corresponding scheme (I sub -V G Curve I sub The total dose used when forming the first N-type drift region 105 and the second N-type drift region 106 in the step (having a first peak and a second peak), for example, when the conventional dose is a, the total dose of the N-type ion implantation in this step can be 2a or other suitable doses, which can be adjusted according to the device performance requirements.

[0113] As an example, the total dose of the N-type ion implantation is not higher than 10 times of the conventional dose (or reference dose), because too high a concentration will result in a decrease in the breakdown voltage.

[0114] In some embodiments, the N-type ion implantation in this step includes one or more ion implantation processes, the total dose range of the N-type ion implantation is 1E12 atoms per square centimeter to 1E14 atoms per square centimeter, and the energy range of the N-type ion implantation is 10KeV-1000KeV.

[0115] As an example, the N-type ion implantation uses a Group V element such as phosphorus (P) or arsenic (As).

[0116] Please see again Fig.10 , performing the step S2: forming a first P-type drift region 209, a second P-type drift region 210 and a P-type doping adjustment region 211 in the semiconductor layer 201 based on a second mask (not shown), wherein the first P-type drift region 209 is located on a side of the first N-type drift region 202 away from the second N-type drift region 203 and is adjacent to the first N-type drift region 202, and the second P-type drift region 210 is located on a side of the second N-type drift region 203 away from the first N-type drift region 202 and is adjacent to the second N-type drift region 203 The P-type doping adjustment region 211 is located in the second N-type drift region 203 to partially neutralize the N-type doping ions in the corresponding area of ​​the second N-type drift region 203, one end of the P-type doping adjustment region 211 facing the first N-type drift region 202 is connected to one end of the second N-type drift region 203 facing the first N-type drift region 202, and one end of the P-type doping adjustment region 211 away from the first N-type drift region 202 is spaced a preset distance from one end of the second N-type drift region 203 away from the first N-type drift region 202.

[0117] As an example, forming the first P-type drift region 209 , the second P-type drift region 210 and the P-type doping adjustment region 211 in the semiconductor layer 201 based on the second mask includes the following steps:

[0118] (1) forming a second photoresist layer 212 on the semiconductor layer 201 by spin coating or other suitable methods;

[0119] (2) performing photolithography processes such as exposure and development based on the second photomask (not shown) to pattern the second photoresist layer 212, thereby obtaining a third opening 213, a fourth opening 214, and a fifth opening 215 which are arranged in a horizontal direction at intervals in the second photoresist layer 212, wherein the third opening 213 is located on a side of the first N-type drift region 202 away from the second N-type drift region 203, the fourth opening 214 exposes an upper surface of an end of the second N-type drift region 203 close to the first N-type drift region 202, and the fifth opening 215 is located on a side of the second N-type drift region 203 away from the first N-type drift region 202;

[0120] (3) Using the patterned second photoresist layer 212 as a mask, P-type ion implantation is performed on the semiconductor layer 212 to obtain the first P-type drift region 210 located below the third opening 2213, the P-type doping adjustment region 211 located below the fourth opening 214, and the second P-type drift region 210 located below the fifth opening 215.

[0121] As an example, the P-type ion implantation includes one or more ion implantation processes, and boron (B) or boron fluoride (BF 2 ) and other group III elements, the energy range of the P-type ion implantation is 10KeV-1000KeV, the first P-type drift region 209 and the second P-type drift region 210 are both located in the P-well 204 and the bottom surface is lower than the bottom surface of the isolation structure 205.

[0122] As an example, the isolation structure 205 includes a first isolation portion 2051 and a second isolation portion 2052, wherein the first isolation portion 2051 is located at the junction of a portion of the second N-type drift region 203 that is not partially neutralized by the P-type doping adjustment region 211 and the P-type doping adjustment region 211, and the second isolation portion 2052 is located at the junction of the second N-type drift region 203 and the second P-type drift region 210.

[0123] As an example, when patterning the second photoresist layer 212, the position and size of the fourth opening 214 are controlled so that the fourth opening 214 exposes the second N-type drift region 203 located in the area below the gate dielectric layer (to be produced in subsequent steps). At the same time, the side wall of the fourth opening 214 away from the first N-type drift region 202 is located on the first isolation portion 2051, so that the interface between the area where the second N-type drift region 203 is partially neutralized by the P-type doping adjustment region 211 and the area where the second N-type drift region 203 is not neutralized does not exceed the end of the first isolation portion 2051 facing the second P-type drift region 210, thereby avoiding affecting the subsequently formed N-type heavily doped drain region 219.

[0124] As an example, the isolation structure 205 also includes a third isolation portion 2053 and a fourth isolation portion 2054, the third isolation portion 2053 is located on a side of the first P-type drift region 209 away from the first N-type drift region 202, and a portion of the first P-type drift region 209 extends horizontally to below the third isolation portion 2053, and the fourth isolation portion 2054 is located on a side of the second P-type drift region 210 away from the second N-type drift region 203, and a portion of the second P-type drift region 210 extends horizontally to below the fourth isolation portion 2053.

[0125] Specifically, the purpose of forming the P-type doping adjustment region 211 is to make the final second N-type drift region 203 non-uniformly doped in the lateral direction, wherein the final second N-type drift region 203 located below the gate dielectric layer is a relatively low dose / relatively low concentration region, ensuring that the first peak of the substrate current is within the HCI reliability safety range, while the region near the drain of the second N-type drift region 203 is not neutralized and is still a relatively high concentration region, which can suppress the second peak of the substrate current formed by the Kirk effect. At the same time, the first N-type drift region 202 is still maintained at a relatively high concentration doping, further improving device performance.

[0126] In some embodiments, after forming the P-type doping adjustment region 211, the area where the second N-type drift region 203 is partially neutralized (i.e., the area located below the gate structure 2) is also non-uniformly doped in the vertical direction, for example, with a gradient gradually increasing from top to bottom, i.e., the surface concentration is the lowest.

[0127] As an example, the N-type ion doping dosage of the first N-type drift region 202 and the second N-type drift region 203 is the same, the P-type ion doping dosage of the first P-type drift region 209 and the second P-type drift region 210 is the same, and the P-type ion doping dosage of the first P-type drift region 209 and the second P-type drift region 210 is less than the N-type ion doping dosage of the first N-type drift region 202 and the second N-type drift region 203 to avoid the N-type drift region in the area where the P-type doping adjustment region 211 is located from being inverted.

[0128] Specifically, the formation of the additionally added P-type doping adjustment region 211 in the present invention does not require an increase in the number of masks and additional process steps. It only requires changing the implantation region of the P-type drift region on the mask, opening the region of the second N-type drift region 203 located below the gate dielectric layer (not yet formed at this time), injecting the ion implantation dose when forming the P-type drift region into the region to neutralize the N-type impurities in the region. For example, when the ion implantation dose of the N-type drift region is 2a and the ion implantation dose of the P-type drift region is b, the net N-type doping dose of the region of the second N-type drift region 203 neutralized by the P-type doping adjustment region 211 is 2a-b. If the conventional doping dose a of the N-type drift region is equivalent to the doping dose b of the P-type drift region, the net N-type doping dose of the region of the second N-type drift region 203 neutralized by the P-type doping adjustment region 211 is approximately a.

[0129] It should be further pointed out that, the P-type ion implantation area increased by the P-type doping adjustment region 211 should, in theory, make the end of the P-type doping adjustment region 211 toward the first N-type drift region 202 completely overlap with the end of the second N-type drift region 203 toward the first N-type drift region 202. However, because the diffusion rates of different elements are different, the end of the P-type doping adjustment region 211 toward the first N-type drift region 202 may slightly fail to reach or exceed the end of the second N-type drift region 203 toward the first N-type drift region 202.

[0130] Please see again Fig.11 , perform the step S3: use chemical vapor deposition, physical vapor deposition or other suitable methods to form a gate structure on the semiconductor layer 201, the gate structure includes a stacked gate dielectric layer 216 and a gate conductive layer 217, and the gate dielectric layer 216 horizontally extends from a portion of the upper surface of the first N-type drift region 202 to the upper surface of the P-type doping adjustment region 211.

[0131] As an example, the gate dielectric layer 216 can be made of silicon oxide or other suitable materials, and its thickness can be set according to the actual voltage resistance requirements of the device. There is no specific limitation here. The material of the gate conductive layer 217 can be polysilicon or other suitable materials.

[0132] As an example, the gate dielectric layer 216 also horizontally extends to a portion of the upper surface of the first isolation portion 2051 .

[0133] Please see again Fig.12 , execute step S4: use ion implantation, annealing and other doping processes to form an N-type heavily doped source region 218 on the upper surface of the first N-type drift region 202, form an N-type heavily doped drain region 219 on the upper surface of the second N-type drift region 203 (the unneutralized region), and form a P-type heavily doped body lead-out region 220 on the upper surface of the first P-type drift region 209 and the upper surface of the second P-type drift region 210.

[0134] Thus, a semiconductor structure is manufactured, which includes a semiconductor layer 201, a first N-type drift region 202, a second N-type drift region 203, a first P-type drift region 209, a second P-type drift region 210, a P-type doping adjustment region 211, a gate structure, an N-type heavily doped source region 218, an N-type heavily doped drain region 219 and a P-type heavily doped body lead-out region 220, wherein the first N-type drift region 202 and the second N-type drift region 203 are located in the semiconductor layer 201 and are arranged in a horizontal direction at intervals, and the first P-type drift region 209 is arranged at an intervals of 1 / 2. The first P-type drift region 209, the second P-type drift region 210 and the P-type doping adjustment region 211 are located in the semiconductor layer 201, the first P-type drift region 209 is located on a side of the first N-type drift region 202 away from the second N-type drift region 203 and is adjacent to the first N-type drift region 202, the second P-type drift region 210 is located on a side of the second N-type drift region 203 away from the first N-type drift region 202 and is adjacent to the second N-type drift region 203, and the P-type doping adjustment region 211 is located on a side of the second N-type drift region 203 away from the first N-type drift region 202 and is adjacent to the second N-type drift region 203. The gate structure is located on the semiconductor layer 201, and the gate structure is formed on the semiconductor layer 201. The gate structure is located on the semiconductor layer 201, and the gate structure is formed on the semiconductor layer 201. The gate structure is located on the semiconductor layer 201, and the gate structure is formed on the semiconductor layer 201. The gate structure is located on the semiconductor layer 201, and the gate structure is formed on the semiconductor layer 201. The gate structure is located on the semiconductor layer 201, and the gate structure is formed on the semiconductor layer 201. The gate structure is located on the semiconductor layer 201, and the gate structure is formed on the semiconductor layer 201. The gate structure includes a stacked gate dielectric layer 216 and a gate conductive layer 217, wherein the gate dielectric layer 216 horizontally extends from a portion of the upper surface of the first N-type drift region 202 to the upper surface of the P-type doping adjustment region 211, the N-type heavily doped source region 218 is located on the upper surface layer of the first N-type drift region 202, the N-type heavily doped drain region 219 is located on the upper surface layer of the second N-type drift region 203, and the P-type heavily doped body lead-out region 220 is located on the upper surface layer of the first P-type drift region 209 and the upper surface layer of the second P-type drift region 210.

[0135] Specifically, due to the presence of the P-type doping adjustment region 211 in the semiconductor structure, the second N-type drift region 203 is non-uniformly doped as a whole, specifically, the portion located below the gate dielectric layer 216 is a relatively low concentration region (wherein some N-type impurities are neutralized by the P-type doping adjustment region 211), ensuring that the first peak value of the substrate current is within the HCI reliability safety range, while the region close to the N-type heavily doped drain region 219 is not neutralized and is still a relatively high concentration region, which can suppress the second peak value of the substrate current formed by the Kirk effect. At the same time, the first N-type drift region 202 where the N-type heavily doped source region 218 is located is still maintained at a relatively high concentration doping, which can further improve device performance.

[0136] As an example, the semiconductor structure can be used as a high-voltage device, such as a high-voltage LDMOS, and applied in power electronics, communications, automotive electronics and other fields.

[0137] In summary, the method for manufacturing a semiconductor structure of the present invention first forms the first and second N-type drift regions with relatively high concentrations based on a first mask, and then forms the first and second P-type drift regions and a P-type doping adjustment region based on a second mask, the P-type doping adjustment region is located in the second N-type drift region to partially neutralize the N-type doping ions in the second N-type drift region in the corresponding area, one end of the P-type doping adjustment region facing the first N-type drift region is connected to one end of the second N-type drift region facing the first N-type drift region, and one end of the P-type doping adjustment region away from the first N-type drift region is separated by a preset distance from one end of the second N-type drift region away from the first N-type drift region. The present invention uses different combinations of photomasks and ion implantation to form an uneven doping distribution in the drift region without adding additional photomasks and ion implantation steps, wherein a low-doped drift region is formed below the gate dielectric layer to suppress the maximum electric field in the region and ensure that the first peak of the substrate current is within the HCI reliability safety range; a high-doped region is formed in the drift region near the drain to prevent the depletion region from further expanding toward the drain end and suppress the second peak of the substrate current formed by the Kirk effect. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0138] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a semiconductor structure, It is characterized in that The following steps are involved: Providing a semiconductor layer, and forming a first N-type drift region and a second N-type drift region spaced apart in a horizontal direction in the semiconductor layer based on a first mask; Based on a second photomask, a first P-type drift region, a second P-type drift region and a P-type doping adjustment region are formed in the semiconductor layer, wherein the first P-type drift region is located on a side of the first N-type drift region away from the second N-type drift region and is adjacent to the first N-type drift region, the second P-type drift region is located on a side of the second N-type drift region away from the first N-type drift region and is adjacent to the second N-type drift region, the P-type doping adjustment region is located in the second N-type drift region to partially neutralize N-type doping ions in the second N-type drift region in a corresponding region, one end of the P-type doping adjustment region facing the first N-type drift region is connected to one end of the second N-type drift region facing the first N-type drift region, and one end of the P-type doping adjustment region away from the first N-type drift region is spaced a preset distance from one end of the second N-type drift region away from the first N-type drift region; forming a gate structure on the semiconductor layer, the gate structure comprising a stacked gate dielectric layer and a gate conductive layer, the gate dielectric layer horizontally extending from a portion of the upper surface of the first N-type drift region to the upper surface of the P-type doping adjustment region; An N-type heavily doped source region is formed on the upper surface layer of the first N-type drift region, an N-type heavily doped drain region is formed on the upper surface layer of the second N-type drift region, and a P-type heavily doped body lead-out region is formed on the upper surface layer of the first P-type drift region and the upper surface layer of the second P-type drift region.

2. The method for manufacturing a semiconductor structure according to claim 1, Features: The N-type ion doping dosage of the first N-type drift region and the second N-type drift region is the same, the P-type ion doping dosage of the first P-type drift region and the second P-type drift region is the same, and the P-type ion doping dosage of the first P-type drift region and the second P-type drift region is less than the N-type ion doping dosage of the first N-type drift region and the second N-type drift region.

3. The method for manufacturing a semiconductor structure according to claim 1, It is characterized in that Forming a first N-type drift region and a second N-type drift region spaced apart in a horizontal direction in the semiconductor layer based on a first mask comprises the following steps: forming a first photoresist layer on the semiconductor layer; Patterning the first photoresist layer based on the first photomask to obtain a first opening and a second opening spaced apart in a horizontal direction in the first photoresist layer; The semiconductor layer is implanted with N-type ions using the patterned first photoresist layer as a mask to obtain the first N-type drift region located below the first opening and the second N-type drift region located below the second opening.

4. The method for manufacturing a semiconductor structure according to claim 3, Features: The N-type ion implantation includes one or more ion implantation processes, the total dose range of the N-type ion implantation is 1E12 atoms per square centimeter to 1E14 atoms per square centimeter, and the energy range of the N-type ion implantation is 10KeV-1000KeV.

5. The method for manufacturing a semiconductor structure according to claim 1, It is characterized in that Forming a first P-type drift region, a second P-type drift region and a P-type doping adjustment region in the semiconductor layer based on a second mask comprises the following steps: forming a second photoresist layer on the semiconductor layer; Patterning the second photoresist layer based on the second photomask to obtain a third opening, a fourth opening, and a fifth opening spaced apart in a horizontal direction in the second photoresist layer, wherein the third opening is located at a side of the first N-type drift region away from the second N-type drift region, the fourth opening exposes an upper surface of an end of the second N-type drift region close to the first N-type drift region, and the fifth opening is located at a side of the second N-type drift region away from the first N-type drift region; The semiconductor layer is implanted with P-type ions using the patterned second photoresist layer as a mask to obtain the first P-type drift region below the third opening, the P-type doping adjustment region below the fourth opening, and the second P-type drift region below the fifth opening.

6. The method for manufacturing a semiconductor structure according to claim 5, Features: The P-type ion implantation includes one or more ion implantation processes, and the energy range of the P-type ion implantation is 10KeV-1000KeV.

7. The method for manufacturing a semiconductor structure according to claim 1, It is characterized in that Before forming a first N-type drift region and a second N-type drift region spaced apart in a horizontal direction in the semiconductor layer based on a first mask, the method also includes a step of forming a P-well and an isolation structure in the semiconductor layer. The first N-type drift region, the second N-type drift region, the first P-type drift region and the second P-type drift region formed subsequently are all located in the P-well and have a bottom surface lower than a bottom surface of the isolation structure.

8. The method for manufacturing a semiconductor structure according to claim 7, Features: The isolation structure includes a first isolation portion and a second isolation portion, the first isolation portion is located at the junction of a portion of the second N-type drift region that is not partially neutralized by the P-type doping adjustment region and the P-type doping adjustment region, and the second isolation portion is located at the junction of the second N-type drift region and the second P-type drift region.

9. The method for manufacturing a semiconductor structure according to claim 7, Features: The isolation structure includes a third isolation portion and a fourth isolation portion, the third isolation portion is located on a side of the first P-type drift region away from the first N-type drift region, and a portion of the first P-type drift region extends horizontally to below the third isolation portion, and the fourth isolation portion is located on a side of the second P-type drift region away from the second N-type drift region, and a portion of the second P-type drift region extends horizontally to below the fourth isolation portion.

10. A semiconductor structure, It is characterized in that include: Semiconductor layer, A first N-type drift region and a second N-type drift region are located in the semiconductor layer and are spaced apart in a horizontal direction; A first P-type drift region, a second P-type drift region and a P-type doping adjustment region are located in the semiconductor layer, the first P-type drift region is located on a side of the first N-type drift region away from the second N-type drift region and is adjacent to the first N-type drift region, the second P-type drift region is located on a side of the second N-type drift region away from the first N-type drift region and is adjacent to the second N-type drift region, the P-type doping adjustment region is located in the second N-type drift region to partially neutralize N-type doping ions in the second N-type drift region in a corresponding area, one end of the P-type doping adjustment region facing the first N-type drift region is connected to one end of the second N-type drift region facing the first N-type drift region, and one end of the P-type doping adjustment region away from the first N-type drift region is spaced a preset distance from one end of the second N-type drift region away from the first N-type drift region; A gate structure, located on the semiconductor layer, the gate structure comprising a stacked gate dielectric layer and a gate conductive layer, the gate dielectric layer horizontally extending from a portion of the upper surface of the first N-type drift region to the upper surface of the P-type doping adjustment region; An N-type heavily doped source region, located on an upper surface layer of the first N-type drift region; An N-type heavily doped drain region, located on an upper surface layer of the second N-type drift region; The P-type heavily doped body lead-out region is located on the upper surface layer of the first P-type drift region and the upper surface layer of the second P-type drift region.

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