Preparation method of two-dimensional gate-all-around transistor, two-dimensional gate-all-around transistor and chip
By preparing a two-dimensional semiconductor-outer gate dielectric ring gate heterojunction in the transistor and forming a ring gate electrode and source/drain contact area, the problems of transistor short channel effect and performance degradation are solved, and a high-performance and low-power two-dimensional ring gate transistor is achieved.
Patent Information
- Application Number
- CN202510011666.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-04
- Publication Date
- 2025-05-23
AI Technical Summary
In the prior art, transistors face short-channel effects, performance degradation and process reliability problems, especially when the technical nodes are further reduced, which has become a challenge that the industry cannot ignore.
The two-dimensional semiconductor-outer gate dielectric ring gate heterojunction is prepared by a controlled oxidation process or atomic layer deposition process, and the back electrode is prepared on the processing substrate to form the ring gate electrode and source/drain contact area, and achieve efficient integration through plasma etching and in-situ formation.
Through this method, the preparation of two-dimensional ring gate transistors is realized, the problems of short channel effect and performance degradation are solved, the performance and process reliability of the transistor are improved, and the requirements of the Amy Node for low-power and high-performance transistors are met.
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Figure CN120035160A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a two-dimensional ring-gate transistor, a two-dimensional ring-gate transistor and a chip. Background Art
[0002] With the continuous advancement of integrated circuit technology, the feature size of silicon-based complementary metal oxide semiconductor (CMOS) transistors has continued to shrink, leading to an exponential increase in transistor density. This development trend has driven the transformation of CMOS devices from traditional two-dimensional planar structures to three-dimensional fin field-effect transistors (FinFETs), and has been successfully extended to 5-nanometer process nodes. However, as the technology nodes are further reduced, the short channel effect, performance degradation, and process reliability issues faced by FinFET devices have become increasingly prominent, becoming a challenge that the industry cannot ignore. Summary of the invention
[0003] The present invention provides a method for preparing a two-dimensional ring-gate transistor, a two-dimensional ring-gate transistor and a chip, which are used to solve the defects of transistor short channel effect, performance degradation and process reliability in the prior art. The two-dimensional ring-gate transistor of the present invention meets the requirements of the angstrom node for low power consumption and high performance transistors.
[0004] The present invention provides a method for preparing a two-dimensional ring-gate transistor, comprising: preparing a back electrode on a processed substrate; preparing a two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction by a controlled oxidation process or an atomic layer deposition process; the two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction comprises a two-dimensional semiconductor channel and an outer gate dielectric; the outer gate dielectric completely covers the outside of the two-dimensional semiconductor channel; the two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction is arranged on the back electrode; a ring-gate electrode is formed on a first region of the two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction, and the ring-gate electrode The back electrode fully covers the two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction in the first region; the source / drain contact region is etched on the second region and the third region of the two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction, and the source / drain contact region is the region where the upper outer gate dielectric is etched on the two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction; the upper outer gate dielectric is the outer gate dielectric on the side away from the back electrode; the first region is located between the second region and the third region; the source / drain is formed in situ on the source / drain contact region.
[0005] According to a method for preparing a two-dimensional ring-gate transistor provided by the present invention, the controllable oxidation process is a combination of one or more of UV-assisted ozone oxidation, thermal-assisted oxidation and oxygen plasma oxidation processes; the reaction initiation mode of the atomic layer deposition process is thermal initiation or plasma initiation.
[0006] According to a method for preparing a two-dimensional ring-gate transistor provided by the present invention, the method for preparing the two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction includes: preparing the two-dimensional semiconductor channel on a growth substrate; oxidizing the two-dimensional semiconductor channel in stages in an oxidation generating device, with the temperature and oxidation time of each stage being different, so that the generated outer gate dielectric conformally covers the outside of the two-dimensional semiconductor channel; or, depositing the two-dimensional semiconductor channel in an atomic layer deposition device, and controlling the temperature and deposition time so that the generated outer gate dielectric conformally covers the outside of the two-dimensional semiconductor channel.
[0007] According to a method for preparing a two-dimensional ring-gate transistor provided by the present invention, the material of the two-dimensional semiconductor channel is a combination of one or more of ionic layered bismuth-based semiconductor materials, transition metal chalcogenides and indium selenide; the material of the outer gate dielectric is a combination of one or more of ionic layered bismuth-based dielectric materials, hafnium oxide, aluminum oxide, zirconium oxide and lanthanum oxide.
[0008] According to a method for preparing a two-dimensional ring-gate transistor provided by the present invention, the material of the ring-gate electrode is a combination of one or more of gold, silver, copper, titanium, palladium, platinum, aluminum, graphene, graphite, and carbon nanotubes.
[0009] According to a method for preparing a two-dimensional ring-gate transistor provided by the present invention, the etching process of the source / drain contact region adopts plasma etching, and the type of plasma is a combination of one or more of argon plasma, oxygen plasma, and air plasma.
[0010] According to a method for preparing a two-dimensional ring-gate transistor provided by the present invention, the material of the source / drain is a combination of one or more of gold, silver, copper, titanium, palladium, antimony, bismuth, scandium, yttrium and iron.
[0011] A method for preparing a two-dimensional ring-gate transistor provided by the present invention also includes: preparing a multi-layer stacked ring-gate transistor by a fixed-point transfer method.
[0012] The present invention also provides a two-dimensional ring-gate transistor, which is prepared by using the above-mentioned method for preparing the two-dimensional ring-gate transistor.
[0013] The present invention also provides a chip, comprising the above-mentioned two-dimensional ring-gate transistor.
[0014] The present invention provides a method for preparing a two-dimensional ring-gate transistor, a two-dimensional ring-gate transistor and a chip, firstly preparing a back electrode on a processing substrate; adopting a controlled oxidation process or an atomic layer deposition process to prepare a two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction; the two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction includes a two-dimensional semiconductor channel and an outer gate dielectric; setting the two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction on the back electrode; forming a ring-gate electrode on the first region of the two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction, and the ring-gate electrode and the back electrode fully cover the two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction in the first region; etching a source / drain contact region on the second region and the third region of the two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction; forming a source / drain in situ on the source / drain contact region. The two-dimensional ring-gate transistor of the present invention meets the requirements of the angstrom node for low-power, high-performance transistors. BRIEF DESCRIPTION OF THE DRAWINGS
[0015] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0016] Figure 1 It is a schematic flow chart of a method for preparing a two-dimensional ring-gate transistor provided by the present invention.
[0017] Figure 2 This is one of the principle schematic diagrams of a method for preparing a two-dimensional ring-gate transistor provided by the present invention.
[0018] Figure 3 This is the second principle schematic diagram of a method for preparing a two-dimensional ring-gate transistor provided by the present invention.
[0019] Figure 4 This is the third principle schematic diagram of a method for preparing a two-dimensional ring-gate transistor provided by the present invention.
[0020] Figure 5 This is the fourth principle schematic diagram of a method for preparing a two-dimensional ring-gate transistor provided by the present invention.
[0021] Figure 6 This is the fifth principle schematic diagram of a method for preparing a two-dimensional ring-gate transistor provided by the present invention.
[0022] Figure 7 This is the sixth principle schematic diagram of a method for preparing a two-dimensional ring-gate transistor provided by the present invention.
[0023] Figure 8This is one of the performance test schematic diagrams of a two-dimensional ring-gate transistor provided by the present invention.
[0024] Fig. 9 This is the second performance test schematic diagram of a two-dimensional ring-gate transistor provided by the present invention.
[0025] Reference numerals: 1: processed substrate; 2: back electrode; 3: two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction; 31 two-dimensional semiconductor channel; 32: outer gate dielectric; 4: ring-gate electrode; 5: source; 6: drain. DETAILED DESCRIPTION
[0026] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0027] The purpose of the present invention is to address the bottleneck of the "power consumption wall" of advanced nodes, construct a two-dimensional semiconductor-gate dielectric ring-gate heterojunction with an atomically flat interface based on high-mobility two-dimensional semiconductors, and based on this, develop a method for preparing a ring-gate transistor, create a low-power two-dimensional ring-gate transistor, and realize the combination of new channel materials and new device architectures.
[0028] As a new type of three-dimensional device, the Gate-All-Around Field-Effect Transistor (GAAFET) has a ring-gate structure that fully covers all four sides, which can effectively reduce device power consumption and improve integration density. It has the following advantages: it has a higher number of effective gates and gate control efficiency, reducing device power consumption; it can use the vertical dimension to achieve three-dimensional integration and improve chip integration density; it is easy to maintain a larger driving current per unit area and improve computing power.
[0029] The two-dimensional gate-all-around transistor (2D GAAFET) fully combines the advantages of new device architecture and new channel materials, provides the best electrostatic gate control efficiency, reduces transistor energy consumption, and provides additional freedom and flexibility for performance improvement. The present invention adopts conformal, lossless, and flat two-dimensional semiconductor-external gate dielectric gate-all-around heterojunction 3 integration methods, which can improve crystal performance and reduce transistor power consumption, and is compatible with the large-scale gate-all-around transistor processing technology required by the Angstrom node.
[0030] Please refer to Figure 1 , Figure 1 A schematic flow chart of a method for preparing a two-dimensional ring-gate transistor provided by the present invention.
[0031] Please refer to Figure 2 , Figure 2 One of the principle schematic diagrams of a method for preparing a two-dimensional ring-gate transistor provided by the present invention.
[0032] The present invention provides a method for preparing a two-dimensional gate-all-around transistor, comprising: 101 : Prepare a back electrode 2 on the processed substrate 1 .
[0033] In this embodiment, a processing substrate 1 is provided for preparing a two-dimensional all-around gate transistor. A back electrode 2 is prepared on the processing substrate 1 by a patterning process for subsequent preparation of the two-dimensional all-around gate transistor.
[0034] The processing substrate 1 can be a commercial substrate (Si, SiO 2 , sapphire) and the present invention is not particularly limited herein.
[0035] The present invention can be patterned by ultraviolet lithography, direct writing or electron beam lithography, and after development, metal deposition is performed by electron beam evaporation, thermal evaporation and other means. The deposited metal includes but is not limited to a combination of one or more of gold (Au), titanium (Ti), palladium (Pd), platinum (Pt) and aluminum (Al), and the deposition thickness is 0.3nm-20nm. Then, the stripping is completed in hot acetone and dried in a nitrogen atmosphere to obtain the back electrode 2 for subsequent ring-gate transistor processing.
[0036] It should be mentioned that the back electrode 2 made of metallic materials such as graphene, graphite and carbon nanotubes (CNTs) is also within the protection scope of the present invention.
[0037] 102: A two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction 3 is prepared by a controlled oxidation process or an atomic layer deposition process; the two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction 3 includes a two-dimensional semiconductor channel 31 and an outer gate dielectric 32; the outer gate dielectric 32 completely covers the outside of the two-dimensional semiconductor channel 31.
[0038] As a preferred embodiment, the controllable oxidation process is a combination of one or more of UV-assisted ozone oxidation, thermal-assisted oxidation and oxygen plasma oxidation processes; the reaction initiation method of the atomic layer deposition process is thermal initiation or plasma initiation.
[0039] As a preferred embodiment, the preparation method of the two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction 3 includes: preparing a two-dimensional semiconductor channel 31 on a growth substrate; oxidizing the two-dimensional semiconductor channel 31 in stages in an oxidation generating device, with the temperature and oxidation time of each stage being different, so that the generated outer gate dielectric 32 conformally covers the outside of the two-dimensional semiconductor channel 31; or, depositing the two-dimensional semiconductor channel 31 in an atomic layer deposition device, and controlling the temperature and deposition time so that the generated outer gate dielectric 32 conformally covers the outside of the two-dimensional semiconductor channel 31.
[0040] As a preferred embodiment, the material of the two-dimensional semiconductor channel 31 is a combination of one or more of ionic layered bismuth-based semiconductor materials, transition metal chalcogenides and indium selenide; the material of the outer gate dielectric 32 is a combination of one or more of ionic layered bismuth-based dielectric materials, hafnium oxide, aluminum oxide, zirconium oxide and lanthanum oxide.
[0041] In this embodiment, a two-dimensional semiconductor channel 31 is prepared on a growth substrate. The material of the two-dimensional semiconductor channel 31 includes an ionic layered bismuth-based semiconductor material (Bi 2 O 2 X, X=S, Se, Te) or any combination thereof, but the present invention is not limited thereto.
[0042] Based on the two-dimensional semiconductor channel 31 grown upright from the substrate, a controlled oxidation process (such as an ozone oxidation process (wherein the generation of ozone includes but is not limited to ultraviolet assisted initiation, discharge initiation or direct introduction)) is performed to prepare a two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction 3. Specifically, the growth substrate on which the two-dimensional semiconductor channel 31 is grown is placed in the center of the Novascan ultraviolet-ozone generator for staged oxidation, and the temperature and oxidation time of each stage are different. First, ultraviolet-ozone oxidation is performed at room temperature for 1-60 minutes, so that the oxidation reaction is evenly initiated at the edge, and a conformally coated oxidized edge is first formed, that is, the outer gate dielectric 32 of the subsequent ring-gate transistor. Then the temperature is raised to 80-150°C, and ultraviolet ozone-assisted oxidation is performed for 30s-600s, so that the oxidation reaction proceeds layer by layer, and conformal heterogeneous integration of the native gate dielectric and the channel is achieved. Finally, the temperature is raised to 200°C-400°C, and ultraviolet ozone assisted oxidation is performed for 5s-30s, so that the oxidation reaction proceeds rapidly at high temperature, the purpose of which is to repair defects and lattice damage through thermal annealing and optimize the semiconductor-gate dielectric interface. The two-dimensional semiconductor-outer gate dielectric ring gate heterojunction 3 of the present invention includes a two-dimensional semiconductor channel 31 part and an outer gate dielectric 32 part, and the two parts should have an atomically flat interface and strict and complete coating, and the outer gate dielectric 32 is completely coated on the outside of the two-dimensional semiconductor channel 31. The material of the outer gate dielectric 32 includes an ionic layered bismuth-based dielectric material (Bi 2 XO y ,X=S,Se,Te,y=5,6) or any combination thereof, having a high dielectric constant, but the present invention is not limited thereto.
[0043] It should be mentioned that other oxidation strategies, such as thermal oxidation process (wherein oxygen comes from air, argon-oxygen mixture, nitrogen-oxygen mixture or other external introduction), oxygen plasma oxidation (wherein the source of oxygen plasma includes but is not limited to discharge initiation and direct introduction) are also within the scope of protection of the present invention.
[0044] The reaction pressure of the controlled oxidation process may be 100 Torr-760 Torr, and the reaction temperature may be 25° C.-500° C., which are not particularly limited in the present invention.
[0045] Based on transition metal chalcogenide and indium selenide (InSe), an atomic layer deposition (ALD) process is performed to form an outer gate dielectric 32. The temperature during the deposition process can be 50°C-500°C, and the reaction initiation method can be thermal initiation or plasma initiation. The deposited outer gate dielectric 32 includes but is not limited to hafnium oxide (HfO 2 )、Alumina(Al 2 O 3 )、ZrO 2 )、Lanthanum oxide(La2 O 3 ) or a combination of one or more of ).
[0046] Thermally induced atomic layer deposition is a process in which a precursor (such as Ir(acac)) is heated to cause a chemical reaction on the substrate surface. 3 , Al(CH 3 ) 3 The precursor is chemically adsorbed on the active position of the substrate surface. The remaining precursor in the gas phase or adsorbed on the surface of the reaction chamber is taken out of the reaction chamber by the inert gas to form a new saturated active surface. 2 , NH 3 , water vapor, etc.) are transported to the reaction chamber to undergo adsorption or chemical reactions with the active groups on the active surface. Finally, an inert gas is introduced to remove the excess gas phase reaction substances, and finally a new solid film is formed. After multiple cycles of cyclic deposition, a film of a predetermined thickness can be obtained.
[0047] Plasma initiation is to stimulate or decompose the reaction gas through plasma, enhance the activity of chemical reaction, and achieve thin film growth at a lower temperature. Specific methods include plasma enhanced atomic layer deposition (PE-ALD) and remote plasma atomic layer deposition (RP-ALD).
[0048] Plasma-enhanced atomic layer deposition (PE-ALD) uses high-temperature electrons in plasma to dissociate reactants and provide active groups required for the reaction. The reactants are generated in the gas phase and provide energy to the deposition surface through ion bombardment, thereby enhancing the surface reaction rate.
[0049] In remote plasma atomic layer deposition (RP-ALD), the plasma source is separated from the deposition area, which can reduce direct damage of the plasma to the substrate.
[0050] 103 : Disposing the two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction 3 on the back electrode 2 .
[0051] Please refer to Figure 3 , Figure 3 The second schematic diagram of the principle of the method for preparing a two-dimensional ring-gate transistor provided by the present invention.
[0052] In this embodiment, after preparing the back electrode 2 on the processed substrate 1, the two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction 3 is placed on the back electrode 2 by transfer. Both glue-free transfer and polymer-assisted transfer can be used for the placement of the ring-gate heterojunction. It is worth noting that when polymer-assisted transfer is used, room temperature UV-ozone cleaning is required to ensure that the interface is clean and reliable.
[0053] 104: A ring gate electrode 4 is formed on the first region of the two-dimensional semiconductor-outer gate dielectric ring gate heterojunction 3, and the ring gate electrode 4 and the back electrode 2 fully cover the two-dimensional semiconductor-outer gate dielectric ring gate heterojunction 3 in the first region.
[0054] As a preferred embodiment, the material of the ring gate electrode 4 is a combination of one or more of gold, silver, copper, titanium, palladium, platinum, aluminum, graphene, graphite, and carbon nanotubes.
[0055] Please refer to Figure 4 , Figure 4 The third schematic diagram of the principle of the method for preparing a two-dimensional ring-gate transistor provided by the present invention.
[0056] In this embodiment, after the back electrode 2 and the two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction 3 are arranged on the processed substrate 1, the ring-gate electrode 4 is formed on the first region of the two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction 3. Specifically, patterning is performed by ultraviolet lithography, direct writing or electron beam lithography to define the back electrode 2. After development, metal deposition is performed by conformal means such as physical vapor deposition (PVD) and atomic layer deposition (ALD). The deposited metal includes but is not limited to one or any combination of gold (Au), silver (Ag), copper (Cu), titanium (Ti), palladium (Pd), platinum (Pt) and aluminum (Al). The deposition thickness is 10nm-200nm. After the above deposition is completed, the ring-gate electrode 4 is obtained by stripping in hot acetone and drying in a nitrogen atmosphere. It should be mentioned that the ring-gate electrode 4 and the back electrode 2 fully cover the two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction 3 in the first region. The ring gate electrode 4 made of metallic materials such as graphene, graphite and carbon nanotubes (CNTs) is also within the protection scope of the present invention.
[0057] 105: Etching source 5 / drain 6 contact regions on the second region and the third region of the two-dimensional semiconductor-external gate dielectric ring-gate heterojunction 3, the source 5 / drain 6 contact region being the region where the upper outer gate dielectric 32 is etched away on the two-dimensional semiconductor-external gate dielectric ring-gate heterojunction 3; the upper outer gate dielectric 32 is the outer gate dielectric 32 on the side facing away from the back electrode 2; the first region is located between the second region and the third region.
[0058] As a preferred embodiment, the etching process of the source 5 / drain 6 contact region adopts plasma etching, and the type of plasma is a combination of one or more of argon plasma, oxygen plasma, and air plasma.
[0059] Please refer to Figure 5 , Figure 5 The fourth schematic diagram of the principle of the method for preparing a two-dimensional ring-gate transistor provided by the present invention.
[0060] In this embodiment, after forming the ring gate electrode 4 on the first region of the two-dimensional semiconductor-external gate dielectric ring gate heterojunction 3, the source 5 / drain 6 contact region is etched on the second region and the third region of the two-dimensional semiconductor-external gate dielectric ring gate heterojunction 3, and the upper outer gate dielectric 32 of the region is selectively etched to expose the internal semiconductor channel; the upper outer gate dielectric 32 is the outer gate dielectric 32 on the side away from the back electrode 2. Specifically, the source 5 / drain 6 region is patterned and defined by ultraviolet lithography, direct writing or electron beam lithography, and the etching process is carried out by low-power soft plasma with a power of 1-300W. The plasma type includes but is not limited to one or any combination of argon plasma, oxygen plasma and air plasma, and the etching time is 0.5s-300s.
[0061] 106: In-situ forming the source 5 / drain 6 on the source 5 / drain 6 contact region.
[0062] As a preferred embodiment, the material of the source 5 / drain 6 is a combination of one or more of gold, silver, copper, titanium, palladium, antimony, bismuth, scandium, yttrium and iron.
[0063] Please refer to Figure 6 , Figure 6 The fifth schematic diagram of the principle of the method for preparing a two-dimensional ring-gate transistor provided by the present invention.
[0064] In this embodiment, after the definition of the source 5 / drain 6 region and the corresponding etching process are completed, the source 5 / drain 6 metal deposition is performed in situ. Specifically, the metal deposition is performed by electron beam evaporation, physical vapor deposition (PVD), atomic layer deposition (ALD) and other deposition methods, and the deposited metals include but are not limited to gold (Au), silver (Ag), copper (Cu), titanium (Ti), palladium (Pd), antimony (Sb), bismuth (Bi), scandium (Sc), yttrium (Y) and iron (Fe) One or any combination of several, the deposition thickness is 10nm-200nm. After completing the above deposition, the metal source 5 / drain 6 electrode is obtained by stripping in hot acetone and drying in a nitrogen atmosphere. It should be mentioned that after the etching process is completed and the metal deposition process is performed, the sample should not be exposed to the atmosphere to avoid introducing contamination.
[0065] The method for preparing a two-dimensional ring-gate transistor provided in this embodiment is suitable for using ionic layered bismuth-based semiconductor materials (Bi 2 O 2By utilizing the in-situ oxidation strategy of its native gate dielectric, the heterogeneous integration of high-mobility two-dimensional semiconductors and ring-gate dielectrics is conformally realized, thereby improving crystal performance and reducing transistor power consumption, and being compatible with the large-scale ring-gate transistor processing technology required for the Angstrom node.
[0066] As a preferred embodiment, it also includes: preparing a multi-layer stacked ring-gate transistor by a fixed-point transfer method.
[0067] Please refer to Figure 7 , Figure 7 The sixth schematic diagram of the principle of the method for preparing a two-dimensional ring-gate transistor provided by the present invention.
[0068] In this embodiment, the two-dimensional ring-gate transistor can prepare a multi-layer structure by point-to-point transfer of multi-layer stacking to further improve the integration and performance of the transistor, and is compatible with the monolithic three-dimensional integrated transistor architecture of the Angstrom node.
[0069] Please refer to Figure 8 , Figure 8 This is one of the performance test schematic diagrams of a two-dimensional ring-gate transistor provided by the present invention.
[0070] Please refer to Fig. 9 , Fig. 9 The second schematic diagram of performance testing of a two-dimensional ring-gate transistor provided by the present invention.
[0071] In this embodiment, the output characteristic curve of the two-dimensional ring-gate transistor shows good ohmic contact. Under a longer channel length, the on-state current density exceeds 200 μA μm -1 The transfer characteristic curve shows good switching characteristics. In the driving voltage window of 0.6 V, the switching ratio exceeds 10. 7 , the off-state current density is as low as 100 fA μm -1 , Subthreshold Swing (SS) as low as 65 mV dec -1 , close to the thermodynamic limit at room temperature (60 mV dec -1 ) The two-dimensional ring-gate transistor provided by the present invention is described below. The preparation method of the two-dimensional ring-gate transistor described below and the two-dimensional ring-gate transistor described above can refer to each other.
[0072] The present invention also provides a two-dimensional ring-gate transistor, which is prepared by using the above-mentioned method for preparing the two-dimensional ring-gate transistor.
[0073] The present embodiment also provides a two-dimensional ring-gate transistor, which includes a processed substrate 1, a back electrode 2, a two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction 3, a ring-gate electrode 4, and a source 5 / drain 6. Among them, the back electrode 2 is prepared on the processed substrate 1; the two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction 3 is prepared by a controlled oxidation process or an atomic layer deposition process; the two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction 3 includes a two-dimensional semiconductor channel 31 and an outer gate dielectric 32; the outer gate dielectric 32 is fully coated on the outside of the two-dimensional semiconductor channel 31; the two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction 3 is set on the back electrode 2; the ring-gate electrode 4 is formed on the first region of the two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction 3, and the ring-gate electrode 4 and the back electrode 2 are in contact with each other. A two-dimensional semiconductor-external gate dielectric ring-gate heterojunction 3 is fully covered in one area; a source 5 / drain 6 contact area is etched on the second area and the third area of the two-dimensional semiconductor-external gate dielectric ring-gate heterojunction 3, and the source 5 / drain 6 contact area is the area where the upper outer gate dielectric 32 is etched away on the two-dimensional semiconductor-external gate dielectric ring-gate heterojunction 3; the upper outer gate dielectric 32 is the outer gate dielectric 32 on the side away from the back electrode 2; the first area is located between the second area and the third area; the source 5 / drain 6 is formed in situ on the source 5 / drain 6 contact area.
[0074] The high dielectric constant outer gate dielectric 32 is made of a high mobility ionic layered bismuth-based semiconductor material (Bi 2 O 2 The two layers have an atomically flat interface, which ensures an extremely low defect density level in the semiconductor-gate dielectric interface and gives full play to the advantages of the ring-gate architecture, such as high gate control efficiency, large gate control area, and low static power consumption.
[0075] In addition, the two-dimensional ring-gate transistor provided by the present invention can prepare a multi-layer structure by layer-by-layer transfer stacking to further improve the integration and performance of the transistor, and is compatible with the monolithic three-dimensional integrated transistor architecture of the Angstrom node.
[0076] The chip provided by the present invention is described below. The chip described below and the method for preparing the two-dimensional ring-gate transistor described above can be referred to each other.
[0077] The present invention also provides a chip, comprising the above-mentioned two-dimensional ring-gate transistor.
[0078] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for preparing a two-dimensional gate-all-around transistor, characterized in that: include: preparing a back electrode on the processed substrate; A two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction is prepared by a controlled oxidation process or an atomic layer deposition process; the two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction includes a two-dimensional semiconductor channel and an outer gate dielectric; the outer gate dielectric completely covers the outside of the two-dimensional semiconductor channel; Disposing the two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction on the back electrode; Forming a ring gate electrode on the first region of the two-dimensional semiconductor-outer gate dielectric ring gate heterojunction, wherein the ring gate electrode and the back electrode fully cover the two-dimensional semiconductor-outer gate dielectric ring gate heterojunction in the first region; Etching a source / drain contact region on the second region and the third region of the two-dimensional semiconductor-external gate dielectric all-around gate heterojunction, wherein the source / drain contact region is a region where the upper outer gate dielectric is etched away on the two-dimensional semiconductor-external gate dielectric all-around gate heterojunction; the upper outer gate dielectric is the outer gate dielectric on the side away from the back electrode; and the first region is located between the second region and the third region; A source / drain is formed in-situ on the source / drain contact region.
2. The method for preparing a two-dimensional gate-all-around transistor according to claim 1, characterized in that: The controllable oxidation process is a combination of one or more of UV-assisted ozone oxidation, thermal-assisted oxidation and oxygen plasma oxidation processes; the reaction initiation method of the atomic layer deposition process is thermal initiation or plasma initiation.
3. The method for preparing a two-dimensional gate-all-around transistor according to claim 1, characterized in that: The method for preparing the two-dimensional semiconductor-outer gate dielectric ring-gate heterojunction comprises: Preparing the two-dimensional semiconductor channel on a growth substrate; The two-dimensional semiconductor channel is oxidized in stages in an oxidation generating device, with the temperature and oxidation time of each stage being different, so that the generated outer gate dielectric conformally covers the outside of the two-dimensional semiconductor channel; or, The two-dimensional semiconductor channel is deposited in an atomic layer deposition device, and the temperature and deposition time are controlled so that the generated outer gate dielectric conformally covers the entire outside of the two-dimensional semiconductor channel.
4. The method for preparing a two-dimensional gate-all-around transistor according to claim 1, characterized in that: The material of the two-dimensional semiconductor channel is a combination of one or more of ionic layered bismuth-based semiconductor materials, transition metal chalcogenides and indium selenide; the material of the outer gate dielectric is a combination of one or more of ionic layered bismuth-based dielectric materials, hafnium oxide, aluminum oxide, zirconium oxide and lanthanum oxide.
5. The method for preparing a two-dimensional gate-all-around transistor according to claim 1, characterized in that: The material of the ring gate electrode is one or more combinations of gold, silver, copper, titanium, palladium, platinum, aluminum, graphene, graphite, and carbon nanotubes.
6. The method for preparing a two-dimensional gate-all-around transistor according to claim 1, characterized in that: The etching process of the source / drain contact region adopts plasma etching, and the type of plasma is a combination of one or more of argon plasma, oxygen plasma, and air plasma.
7. The method for preparing a two-dimensional gate-all-around transistor according to claim 1, characterized in that: The material of the source / drain is one or more of gold, silver, copper, titanium, palladium, antimony, bismuth, scandium, yttrium and iron.
8. The method for preparing a two-dimensional gate-all-around transistor according to any one of claims 1 to 7, characterized in that: Also includes: The multilayer stacked ring-gate transistor is prepared by a fixed-point transfer method.
9. A two-dimensional ring-gate transistor, characterized in that: The two-dimensional gate-all-around transistor is prepared by the method for preparing the two-dimensional gate-all-around transistor according to any one of claims 1 to 8.
10. A chip, characterized in that: Includes the two-dimensional ring-gate transistor as described in claim 9.