High electron mobility transistor with integrated diode

Abstract

The invention relates to a high electron mobility transistor with an integrated diode. A semiconductor device (200) includes a substrate (210 and optionally 212 and 214), a semiconductor layer stack (220, 230 and optionally 212 and 214) on the substrate, and a gate (242), a source (244) and a drain (246) formed on or in the semiconductor layer stack. The semiconductor layer stack may include a non-silicon channel layer (220) and a barrier layer (230) on the channel layer (220). At least one of the substrate or the stack of semiconductor layers includes a diode (218), a first terminal of the diode (218) electrically coupled to the source (244), and a second terminal of the diode (218) electrically coupled to the drain (246).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of and priority to U.S. Provisional Application No. 63 / 601,315, filed on November 21, 2023, entitled “Avalanche-Capable GaN Power Transistor,” which is assigned to the present assignee and is incorporated herein by reference in its entirety for all purposes. Technical Field

[0003] The present application relates to high electron mobility transistors with an integrated diode. Background Art

[0004] A high electron mobility transistor (HEMT) may include a heterojunction formed using different semiconductor materials, wherein a channel may be formed near the heterojunction. The channel may be turned on or off by applying an appropriate voltage level on a gate structure. Gallium nitride (GaN)-based HEMT devices generally have high breakdown field, high electron mobility, low resistance, high current, faster switching speed, high thermal conductivity, and excellent reverse recovery performance, and thus may be suitable for applications where low loss and high efficiency performance are desired, such as power electronics (e.g., power switches), radio frequency (RF) circuits, etc. Summary of the invention

[0005] This Summary is provided to introduce examples of the disclosed concepts in a simplified form that are further described below in the Detailed Description including the provided drawings.

[0006] According to certain aspects, a semiconductor device may include a substrate, a semiconductor layer stack on the substrate, and a gate, a source, and a drain formed on or in the semiconductor layer stack. The semiconductor layer stack may include a non-silicon channel layer and a barrier layer on the channel layer. At least one of the substrate or the semiconductor layer stack includes a diode, a first terminal of the diode electrically coupled to the source, and a second terminal of the diode electrically coupled to the drain.

[0007] According to certain aspects, a method may include: forming a semiconductor layer stack on a substrate, the semiconductor layer stack including a non-silicon channel layer and a barrier layer in the channel layer, wherein at least one of the substrate or the semiconductor layer stack includes a diode; forming a gate on a side of the barrier layer opposite to the channel layer; forming a source on or in the semiconductor layer stack, the source electrically coupled to a first terminal of the diode; and forming a drain on or in the semiconductor layer stack, the drain electrically coupled to a second terminal of the diode.

[0008] The foregoing summary of the invention has been quite extensively summarized various features of the examples of the present disclosure so that the following detailed description can be better understood. Additional features and advantages of such examples will be described below. The present summary is not intended to identify the key or essential features of the claimed subject matter, nor is it intended to be used alone to determine the scope of the claimed subject matter. The subject matter should be understood by reference to the appropriate parts of the entire specification of the present disclosure, any or all of the drawings and each claim. The foregoing and other features and examples will be described in more detail below in the following specification, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Illustrative examples are described in detail below with reference to the following figures.

[0010] Figure 1A is a cross-sectional view of an example of a high electron mobility transistor (HEMT).

[0011] Figure 1B is a schematic diagram of an example of a semiconductor device including a HEMT and a diode.

[0012] Figure 2 is a cross-sectional view of an example of a semiconductor device including a HEMT and a diode on the same semiconductor die.

[0013] Figure 3A and 3B is a cross-sectional view of an example of a semiconductor device including a HEMT and a diode on the same semiconductor die.

[0014] Figures 4A to 4E Description Manufacturing Figure 3A and 3B An example of a process for a semiconductor device.

[0015] Figure 5A and 5B is a cross-sectional view of an example of a semiconductor device including a HEMT and a diode on the same semiconductor die.

[0016] Figures 6A to 6E Description Manufacturing Figure 5A and 5B An example of a process for a semiconductor device.

[0017] Fig. 7A and 7B is a cross-sectional view of an example of a semiconductor device including a HEMT and a diode on the same semiconductor die.

[0018] Figures 8A to 8F Description Manufacturing Fig. 7A and 7B An example of a process for a semiconductor device.

[0019] Fig. 9A and9B is a cross-sectional view of an example of a semiconductor device including a HEMT and a diode on the same semiconductor die.

[0020] Figures 10A to 10F Description Manufacturing Fig. 9A and 9B An example of a process for a semiconductor device.

[0021] Fig.11A and 11B is a cross-sectional view of an example of a semiconductor device including a HEMT and a diode on the same semiconductor die.

[0022] Figures 12A to 12D Description Manufacturing Fig.11A and 11B An example of a process for a semiconductor device.

[0023] Fig.13A and 13B is a cross-sectional view of an example of a semiconductor device including a HEMT and a diode on the same semiconductor die.

[0024] Figures 14A to 14D Description Manufacturing Fig.13A and 13B An example of a process for a semiconductor device.

[0025] Fig.15 is a cross-sectional view of an example of a semiconductor device including a HEMT and a Schottky diode on the same semiconductor die.

[0026] Fig.16 Contains graphs illustrating simulation results of the breakdown of different GaN-based transistors.

[0027] Fig.17 A schematic diagram is included illustrating an example of the operation of a GaN-based transistor including an integrated diode.

[0028] Fig.18A and 18B Description During switching operation Fig.17 The schematic diagram shows the simulation results of the circuit.

[0029] Fig.19 A flow chart is included that illustrates an example of a process for fabricating a semiconductor device including a HEMT and a diode on the same semiconductor die.

[0030] The drawings and the accompanying detailed description are provided to understand the features of the various examples and do not limit the scope of the appended claims. The examples illustrated in the drawings and described in the accompanying specific embodiments can be easily used as the basis for modifying or designing other examples within the scope of the appended claims. Those skilled in the art will easily recognize from the following description that alternative embodiments of the structures and methods described can be adopted without departing from the principles of the present disclosure or the benefits of the claims. Where possible, the same reference numerals can be used to refer to the same elements shared in the drawings. Drawings are drawn to clearly illustrate the relevant elements or features, and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0031] The present disclosure relates generally to semiconductor devices. In some examples, the semiconductor device includes a high electron mobility transistor (HEMT) and a diode integrated on the same semiconductor die. In some examples, the diode is or otherwise acts as an avalanche diode that can provide avalanche capability. Many benefits and advantages can be achieved through monolithic integration, such as low parasitic resistance and inductance, no additional packaging or additional bonding to a PCB, shorter response time, tunable avalanche energy level, lower cost, smaller device, etc., as described in more detail below.

[0032] A GaN-based field effect transistor, such as a GaN-based HEMT, may include a heterojunction formed by a channel layer (e.g., a GaN layer) and a barrier layer (e.g., an aluminum gallium nitride (AlGaN) layer). A high-density two-dimensional electron gas (2DEG) may be formed at the heterojunction to act as a conductive channel. For example, the 2DEG may have a value greater than about 1.0×10 13 cm -2 GaN-based HEMTs are attractive for high frequency and high power applications due to, for example, their high breakdown field, high electron mobility, low static resistance, and high thermal conductivity.

[0033] In high voltage applications and applications where repeated avalanche breakdown may be required (e.g., automotive electrical control units), it may be desirable for power devices to have avalanche diodes with recoverable breakdown capabilities to protect the power devices from damage that may otherwise be caused by high voltages. When the high electric field applied by a high reverse bias voltage is high enough to accelerate minority carriers to ionize atoms in the lattice, the diode may experience avalanche breakdown at a high reverse bias voltage, where the carriers generated by the ionization may ionize more atoms to cause a chain reaction that may significantly increase the current without significantly increasing the voltage across the diode. Avalanche breakdown is reversible when the applied voltage is lower than the breakdown voltage. Therefore, an avalanche diode may clamp the voltage across the circuit and / or divert current from the circuit, thereby protecting the circuit from high voltage and current surges that may otherwise cause irreversible and catastrophic breakdown, such as dielectric breakdown. Avalanche diodes may have a lower doping density and therefore a wider depletion region. Silicon metal oxide semiconductor field effect transistors (MOSFETs) have diffusion regions (drain / source) and substrates of opposite polarity, and the pn junction between the diffusion regions and the substrate provides a body diode that can act as an avalanche diode. However, a lateral HEMT may not have such a diffusion region, and therefore may not have a diode with recoverable breakdown capability to protect the HEMT from high voltage and / or high current. Therefore, for example, during unclamped inductive switching (UIS) testing, the HEMT may be permanently (irreversibly) damaged.

[0034] In some examples disclosed herein, a semiconductor device may include a substrate, a semiconductor layer stack on the substrate, and a gate, a source, and a drain formed on or in the semiconductor layer stack. The semiconductor layer stack may include a HEMT formed of a non-silicon channel layer and a barrier layer on the channel layer. At least one of the substrate or the semiconductor layer stack may include a diode formed therein, wherein a first terminal of the diode may be electrically coupled to a source, and a second terminal of the diode may be electrically coupled to a drain. The diode may act as an avalanche diode with recoverable breakdown capability to protect the semiconductor device from high voltage and / or high current. The substrate may include, for example, silicon, silicon carbide, silicon on insulator (SOI), sapphire, gallium nitride (GaN), engineered GaN, or another semiconductor material having a band gap wider than that of silicon. The channel layer may include, for example, GaN, AlGaN, or indium aluminum nitride (InAlN).

[0035] In some examples, the diode may be formed in the substrate. For example, the diode may be a vertical diode formed by a p-doped semiconductor layer and an n-doped semiconductor layer in the substrate (e.g., along the thickness direction of the semiconductor substrate), or may be a lateral diode formed by a doped semiconductor layer and an oppositely doped semiconductor region in the doped semiconductor layer (e.g., perpendicular to the thickness direction of the semiconductor substrate). In some examples, the diode may be formed in a semiconductor layer stack, such as a vertical diode formed by a p-doped semiconductor layer and an n-doped semiconductor layer in a semiconductor layer stack. The doped semiconductor layer may be formed in a substrate or a semiconductor layer stack by, for example, epitaxial growth and / or ion implantation. The doped semiconductor region may be formed by, for example, ion implantation in a selected region of the doped semiconductor layer. In some examples, the diode may be a Schottky diode formed by a semiconductor layer and a Schottky metal contact.

[0036] The semiconductor device disclosed herein including a HEMT and a monolithically integrated diode may have avalanche capability for high voltage / current surge protection and may be used in applications requiring repeated avalanche breakdown, such as in some automotive electrical control units. Due to the monolithic integration, the interconnect between the monolithically integrated HEMT and the diode may have much lower parasitic resistance and inductance than a device in which the diode is external to the chip or semiconductor die containing the HEMT. Therefore, the device may have a shorter response time during switching and may be more suitable for high-speed switching. The avalanche breakdown voltage or energy level of the avalanche diode may be tuned by, for example, tuning the doping density or doping profile of the two terminals of the diode and / or the size of the two terminals of the diode (e.g., the thickness of the lightly doped semiconductor layer of the diode). Because no additional packaging or board-level bonding processes are required, the cost of manufacturing the device may be lower.

[0037] Various features are described below with reference to the drawings. The illustrated examples may not have all aspects or advantages shown. An aspect or advantage described in conjunction with a particular example is not necessarily limited to that example, and may be practiced in any other example, even if not so illustrated or not explicitly described. In addition, the methods described herein may be described in a particular order of operations, but other methods according to other examples may be implemented with various other orders of more or fewer operations (e.g., including different serial or parallel performance of various operations).

[0038] Various examples are described herein. Although specific examples may illustrate various aspects of the features generally described above, examples may incorporate any combination of the features generally described above (which are described in more detail in the following examples). For ease of reference, three-dimensional xyz axes are illustrated in some of the figures. Some cross-sectional views of various semiconductor devices herein may be general depictions for illustrating various aspects or concepts regarding such semiconductor devices. More specifically, some drain contact structures illustrated in the cross-sectional views may not necessarily accurately depict the structure of such drain contact contacts, except to the extent described herein. The description of these drain contact structures is to illustrate various aspects or concepts regarding those drain contact structures.

[0039] Various examples are described in the context of HEMTs. Some examples may be implemented in an enhancement mode lateral HEMT for high voltage (e.g., about 650V to about 1,200V) applications or low to medium voltage (e.g., about 10V to about 100V, or about 10V to about 200V) applications. In other examples, the semiconductor device may include a bidirectional field effect transistor (FET), a gate-controlled Schottky barrier diode (e.g., a gate-to-drain shorting structure or a gate-to-source shorting structure), or the like. Some examples may be implemented with any epitaxial structure, any field plate and / or ohmic contact structure, a planar or three-dimensional structure (e.g., a fin structure), and / or various other modifications.

[0040] For illustration purposes, some of the examples disclosed herein may focus on Group III nitride based devices, such as GaN based HEMTs. However, the present disclosure is not limited to GaN based HEMTs and may be applied to other devices including heterostructures formed of other semiconductor materials (e.g., other Group III nitrides or other Group III-V semiconductor materials), where the heterostructures may induce 2DEG at the heterojunction interface.

[0041] In the following description, for the purpose of explanation, specific details are set forth in order to provide a thorough understanding of the examples of the present disclosure. However, it will be apparent that various embodiments can be practiced without these specific details. For example, devices, systems, structures, assemblies, integrated circuits, and other components can be shown as components in block diagram form to avoid confusing the examples with unnecessary details. In other cases, well-known devices, processes, systems, structures, and techniques can be shown without the necessary details to avoid confusing the examples. The figures and descriptions are not intended to be limiting. The terms and expressions that have been adopted in the present disclosure are used as descriptive and non-restrictive terms, and when using such terms and expressions, it is not intended to exclude any equivalents of the features or parts thereof shown and described. The word "example" is used herein to mean "serving as an example, example, or illustration". Any embodiment or design described as an "example" herein is not necessarily interpreted as being preferred or advantageous over other embodiments or designs.

[0042] GaN-based HEMTs include a heterostructure that can induce a two-dimensional electron gas (2DEG) at the interface between two GaN-based materials with different band gaps. In one example, the heterostructure can be composed of a GaN layer and an Al x Ga (1-x) N layer is formed, where x is the concentration of aluminum. The GaN layer may have a higher concentration than Al x Ga (1-x) The N layer has a narrow band gap, and the Al x Ga (1-x) The N layer may be referred to as a barrier layer due to its wider bandgap. Due to the bandgap mismatch, large conduction band offset, and spontaneous and piezoelectric polarization characteristics of the III-nitride layer, a high-mobility 2DEG may be generated in the GaN layer near the interface of the heterostructure to form a conductive channel in the GaN layer (hence it is referred to as a channel layer). Compared to silicon-based transistors, GaN-based transistors typically have a high breakdown electric field, high electron mobility, low on-state resistance, high current, faster switching speed, high thermal conductivity, and excellent reverse recovery performance, and may therefore be more suitable for applications where low loss and high efficiency performance may be desired, such as power electronic devices (e.g., power switches).

[0043] A GaN-based transistor may include a gate structure located between a source structure and a drain structure. The drain structure may include a metal contact that may be directly or indirectly (e.g., by tunneling) coupled to a channel layer and may form an ohmic contact with the channel layer. The source structure may include a metal contact that may be directly or indirectly coupled to a channel layer and may form an ohmic contact with the channel layer. Depending on the architecture of the gate structure, the GaN-based transistor may be an enhancement mode high electron mobility transistor (e-HEMT) or a depletion mode high electron mobility transistor (d-HEMT). For example, the gate structure of an e-HEMT may include a p-GaN layer formed above a barrier layer and a gate electrical contact (metal electrode) formed on the p-GaN layer, which together form a p-GaN gate structure. The p-GaN layer of the gate structure may be doped with, for example, magnesium (Mg), which is an acceptor that may make the GaN layer p-type or p-doped. The p-GaN layer may deplete electrons in the 2DEG channel under the p-GaN gate structure, so that when a gate drive voltage is not applied to the gate electrical contact, the conductive path between the source and the drain may be disabled, and thus the e-HEMT may be turned off. When a positive voltage higher than the gate threshold voltage is applied to the gate electrical contact, the gate structure may attract electrons, so that the 2DEG under the gate structure may be filled with electrons, thereby turning on the e-HEMT. In contrast, the gate structure of the d-HEMT may include an insulator layer (e.g., a dielectric layer) above the barrier layer and a gate electrical contact (e.g., a metal electrode) on the insulator layer. When a voltage signal is not applied to the gate electrical contact, the 2DEG under the gate structure may not be depleted, so that even in the absence of a positive gate voltage, a conductive path in the channel layer between the drain structure and the source structure may be enabled. The d-HEMT may be turned off by applying a negative gate voltage to the gate electrical contact to deplete electrons from the 2DEG under the gate structure. In some applications, such as switch-mode power applications (eg, power switches), e-HEMTs may be used instead of d-HEMTs, for example, to reduce leakage current, lower power losses, simplify drive circuits, and / or improve device stability.

[0044] Figure 1A 1 is a cross-sectional view of an example of a high electron mobility transistor (HEMT) 100. In the illustrated example, the HEMT 100 is an enhancement mode GaN-based transistor, which includes a substrate 110, a channel layer 120, a barrier layer 130, a gate structure, a source structure, and a drain structure. The substrate 110 may include, for example, a silicon substrate, a silicon carbide substrate, a semiconductor on insulator (SOI) substrate, a sapphire substrate, a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an engineered GaN substrate (Qromis TMThe channel layer 120 may be a semiconductor material having a band gap wider than that of silicon, or any other suitable substrate. In one example, the substrate 110 may include a bulk silicon substrate, and may further include one or more transition layers or buffer layers of suitable materials to accommodate the lattice mismatch between the substrate 110 and the channel layer 120 (e.g., to reduce or minimize the generation and / or propagation of lattice defects in the channel layer 120). For example, the transition layer or buffer layer may have a gradient concentration of one or more elements in a surface normal direction (e.g., z-direction) of the substrate 110 to gradually change the lattice constant.

[0045] The channel layer 120 and the barrier layer 130 may be epitaxially grown on the substrate 110 to form a heterostructure, which may induce a 2DEG 122 near the interface between the channel layer 120 and the barrier layer 130 due to their different band structures. The 2DEG 112 may conduct current in a two-dimensional plane (e.g., an xy plane). In some examples, the channel layer 120 may be a portion of the substrate 110. The channel layer 120 may include, for example, a GaN layer, an AlGaN layer, or an InAlN layer. In some examples, the material of the channel layer 120 may include an unintentionally doped material, such as a material doped by diffusion of a dopant from another layer, or include an intrinsic material. The barrier layer 130 may include, for example, an AlGaN layer. Other materials may also be used for the channel layer 120 and the barrier layer 130. For example, the channel layer 120 may include indium aluminum gallium nitride (InAlN). i Al j Ga 1-i-j N) (where 0≤i≤1, 0≤j≤1, and 0≤i+j≤1), and the barrier layer 130 may include indium aluminum gallium nitride (In k Al l Ga 1-k-l N) (where 0≤k≤1, 0≤l≤1, and 0≤k+l≤1).

[0046] The gate structure of the HEMT 100 may include a gate semiconductor layer 140 above the upper surface of the barrier layer 130. In some examples, the gate semiconductor layer 140 may include a p-doped semiconductor layer. For example, the gate semiconductor layer 140 may include a GaN layer, or more generally, an In m Al n Ga 1-m-nN layer (where 0≤m<1, 0≤n<1 and 0≤m+n≤1). The p-type dopant used to dope the gate semiconductor layer 140 may include magnesium (Mg), carbon (C), zinc (Zn), etc., or a combination thereof. In an example where the gate semiconductor layer 140 includes GaN doped with a p-type dopant, the gate semiconductor layer 140 may be referred to as a p-GaN layer. In some examples, the concentration of the electrically activated dopant in the gate semiconductor layer 140 may be equal to or greater than about 1×10 17 cm -3 In some examples, the concentration may be equal to or greater than about 1×10 18 cm -3 . In other examples, other materials, dopants, and / or concentrations may be used. The gate semiconductor layer 140 may be formed by epitaxial growth and selective etching using an etch mask, or may be formed by selective area growth using a growth mask. The etch mask or growth mask may define the shape and size of the gate semiconductor layer 140. The doping density and thickness of the p-doped gate semiconductor layer 140 and the thickness of the barrier layer 130 below the gate semiconductor layer 140 may be selected so that the p-doped gate semiconductor layer 140 may deplete the 2DEG 122 below the gate semiconductor layer 140, so that the HEMT 100 is turned off without a positive gate voltage and can be turned on by applying a positive voltage to the gate structure.

[0047] A gate electrical contact 142 may be formed over the gate semiconductor layer 140 to apply a gate voltage to the gate semiconductor layer 140. The gate electrical contact 142 may be electrically coupled to a gate drive circuit through electrical interconnects such as conductive traces and / or vias (now shown). In some examples, the gate electrical contact 142 may extend laterally beyond the gate semiconductor layer 140 to form a gate field plate, for example to reduce current collapse and dynamic on-state resistance and increase breakdown voltage. The gate electrical contact 142 may include one or more metal and / or metal alloy materials having high electrical conductivity.

[0048] At the source region of the HEMT 100, a source electrical contact 144 may extend through the barrier layer 130 and contact the source region of the channel layer 120. The source electrical contact 144 may include a metal or a metal alloy and may form a low barrier metal-to-semiconductor contact (e.g., an ohmic contact) with the channel layer 120. In some examples, the source electrical contact 144 may not extend through the barrier layer 130 and may be electrically coupled to the source region of the channel layer 120 by, for example, a tunneling effect. In some examples, one or more source field plates may be formed and may be coupled to the source electrical contact 144. The source field plates may be used to reduce current collapse and dynamic on-state resistance, and / or increase the breakdown voltage of the HEMT 100.

[0049] At the drain region of the HEMT 100, a drain electrical contact 146 may extend through the barrier layer 130 and contact the drain region of the channel layer 120. The drain electrical contact 146 may include a metal or a metal alloy and may form a low-barrier metal-to-semiconductor contact (e.g., an ohmic contact) with the channel layer 120. In some examples, the drain electrical contact 146 may not extend through the barrier layer 130 and may be electrically coupled to the source region of the channel layer 120 by, for example, a tunneling effect.

[0050] Each of the gate electrical contact 142, the source electrical contact 144, and the drain electrical contact 146 may include, for example, titanium (Ti), titanium tungsten (TiW), titanium nitride (TiN), nickel (Ni), platinum (Pt), tantalum nitride (TaN), copper (Cu), tungsten (W), gold (Au), aluminum (Al), an alloy, or a combination thereof. In some examples, the alloy may include, for example, titanium tungsten aluminum (TiWAl) or titanium aluminum nitride (TiAlN), or a combination thereof.

[0051] In some examples, HEMT 100 may include one or more dielectric layers ( Figure 1A The one or more dielectric layers may include a dielectric material (not shown) that isolates and protects the gate structure, the drain structure, and the source structure. The one or more dielectric layers may include the same dielectric material or different dielectric materials deposited in one or more deposition processes. For example, the one or more dielectric layers may include oxide-based materials or nitride-based materials, such as silicon oxide (e.g., phosphosilicate glass (PSG)), aluminum oxide, silicon nitride, etc. In some examples, the one or more dielectric layers may further include one or more etch stop layers, such as silicon nitride (SiN), etc., for controlling the etching depth of the etching process (e.g., for patterning dielectric or metal layers).

[0052] In some examples, electrical contacts or other metal electrical interconnects in the HEMT 100 may each include one or more metal barrier layers and / or one or more adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc., or a combination thereof) between a metal material (e.g., Al, Cu, W, etc., or a combination thereof) and one or more dielectric layers. The one or more metal barrier layers may prevent metal atoms from diffusing into the one or more dielectric layers. The one or more adhesion layers may be used to improve adhesion of the metal material to the dielectric material of the one or more dielectric layers to reduce or avoid defects and reliability issues, such as interface delamination.

[0053] As described above, in high voltage applications and applications where repeated avalanche breakdown may be required (e.g., automotive electrical control units), it may be desirable for power devices to have avalanche diodes with recoverable breakdown capabilities to protect power devices from high voltage damage. When the high electric field applied by the high reverse bias voltage is high enough to accelerate minority carriers to ionize atoms in the lattice, the avalanche diode may experience avalanche breakdown at a high reverse bias voltage, where the carriers generated by the ionization may ionize more atoms to cause a chain reaction that may significantly increase the current without significantly increasing the voltage across the diode. Avalanche breakdown is reversible when the applied voltage is lower than the breakdown voltage. Therefore, the avalanche diode may clamp the voltage across the circuit and / or divert current from the circuit, thereby protecting the circuit from high voltage and current surges that may otherwise cause irreversible and catastrophic breakdown, such as dielectric breakdown. Avalanche diodes may typically have a lower doping density and therefore a wider depletion region.

[0054] Silicon MOSFETs may have an inherent pn junction body diode that may act as an avalanche diode. Figure 1A As shown in , unlike a MOSFET transistor, the HEMT 100 formed by the epitaxial growth of the channel layer 120 and the barrier layer 130 may not have a built-in avalanche diode with recoverable breakdown capability to protect the HEMT from high voltage and / or high current. Therefore, during an unclamped inductive switching (UIS) test, the HEMT may be permanently (irreversibly) damaged. In some examples, to prevent irreversible and catastrophic breakdown (e.g., dielectric breakdown) and to provide repetitive avalanche breakdown capability, a discrete diode made of a material different from that of the HEMT (e.g., a silicon-based diode on a silicon die) may be bonded to the HEMT die by board-level or die-level bonding to form a device having the HEMT and the avalanche diode in the same package or on the same board.

[0055] Figure 1B1 is a schematic diagram of an example of a device including a HEMT 100 and a diode 102. An anode of the diode 102 may be electrically coupled to a source electrical contact 144 of the HEMT 100, and a cathode of the diode 102 may be electrically coupled to a drain electrical contact 146 of the HEMT 100. When the HEMT 100 is turned on, the voltage difference between the drain terminal and the source terminal of the HEMT 100 may be low, a reverse bias voltage may be applied to the diode 102, and thus the diode 102 may prevent current from flowing through the diode 102. When the voltage level applied to the drain terminal of the HEMT 100 is higher than the voltage level applied to the source terminal and the HEMT 100 is turned off, the diode 102 may be reverse biased to prevent current from flowing from the drain terminal of the HEMT 100 to the source terminal through the diode 102. When a reverse bias voltage applied to the diode 102 is greater than the avalanche breakdown voltage of the diode 102 while the HEMT 100 is turned off, the diode 102 may undergo an avalanche breakdown, wherein a high current may flow from the drain terminal of the HEMT 100 to the source terminal of the HEMT 100 through the diode 102, and the voltage difference between the drain terminal and the source terminal of the HEMT 100 may be clamped at about the avalanche breakdown voltage of the diode 102. The breakdown voltage of the HEMT 100 may be higher than the avalanche breakdown voltage of the diode 102, and thus a voltage applied across the HEMT 100 may not reach the breakdown voltage of the HEMT 100 to cause damage to the HEMT 100. When the voltage difference between the drain terminal and the source terminal of the HEMT 100 is lower than the avalanche breakdown voltage of the diode 102, the diode 102 may stop conducting. Therefore, the reversible avalanche breakdown of the diode 102 may protect the HEMT 100 from high voltage and / or current surges. As explained above, it is advantageous to integrate the HEMT 100 and the diode 102 on the same semiconductor die to reduce the parasitic inductance, resistance, and / or capacitance of the interconnects between the HEMT 100 and the diode 102, which can reduce the response time of the device to facilitate high-speed switching applications. Integrating the HEMT 100 and the diode 102 on the same semiconductor die can also reduce the overall cost and overall size of the device.

[0056] According to a specific example, a semiconductor device may include a substrate, a semiconductor layer stack on the substrate, and a gate, a source, and a drain formed on or in the semiconductor layer stack. The semiconductor layer stack may include a HEMT formed by a non-silicon channel layer and a barrier layer on the channel layer. At least one of the substrate or the semiconductor layer stack may include a diode formed therein, wherein a first terminal of the diode may be electrically coupled to a source, and a second terminal of the diode may be electrically coupled to a drain. The diode may act as an avalanche diode with recoverable breakdown capability to protect the semiconductor device from high voltage and / or high current. The substrate may include, for example, silicon, silicon carbide, SOI, sapphire, GaN, engineered GaN, or another semiconductor material having a band gap wider than that of silicon. The channel layer may include, for example, GaN, AlGaN, or InAlN.

[0057] In some examples, the diode may be formed in the substrate. For example, the diode may be a vertical diode formed by a p-doped semiconductor layer and an n-doped semiconductor layer in the substrate, or may be a lateral diode formed by a doped semiconductor layer and an oppositely doped semiconductor region in the doped semiconductor layer. In some examples, the diode may be formed in a semiconductor layer stack, such as a vertical diode formed by a p-doped semiconductor layer and an n-doped semiconductor layer in the semiconductor layer stack. The doped semiconductor layer may be formed in the substrate or the semiconductor layer stack by, for example, epitaxial growth and / or ion implantation. The doped semiconductor region may be formed by, for example, ion implantation in a selected region of the doped semiconductor layer. In some examples, the diode may be a Schottky diode formed by a semiconductor layer and a Schottky metal contact.

[0058] Figure 2 2 is a cross-sectional view of an example of a semiconductor device 200 including a HEMT 240 and a diode on the same semiconductor die. In the illustrated example, the semiconductor device 200 includes: a substrate 210; a semiconductor layer stack including at least a channel layer 220 and a barrier layer 230; and a diode 218 formed in the substrate 210 or the semiconductor layer stack. The HEMT 240 may be formed of the channel layer 220, the barrier layer 230, a gate structure 242, a source structure 244, and a drain structure 246. The HEMT 240 may be Figure 1B In an example of HEMT 100, diode 218 may be Figure 1B An example of a diode 102 .

[0059] The source structure 244 may be electrically coupled to the anode of the diode 218 through a low resistance and low inductance connection, and the drain structure 246 may be electrically coupled to the cathode of the diode 218 through a low resistance and low inductance connection. The channel layer 220 of the HEMT 240 may include a non-silicon material, such as GaN, AlGaN, or InAlN. In one example, the channel layer 220 may include undoped GaN, and the barrier layer 230 may include AlGaN. The channel layer 220 and the barrier layer 230 may form a heterostructure, which may induce a 2DEG 222 at the interface between the channel layer 220 and the barrier layer 230 due to the different band structures of the channel layer 220 and the barrier layer 230. The HEMT 240 may be an enhancement mode high electron mobility transistor or a depletion mode high electron mobility transistor. For example, the gate structure 242 may be similar to the gate structure of the HEMT 100, so that the HEMT 240 may be an enhancement mode high electron mobility transistor.

[0060] The substrate 210 may be similar to the substrate 110 and may include, for example, a silicon substrate, a silicon carbide substrate, an SOI substrate, a sapphire substrate, a GaN substrate, a GaAs substrate, an engineered GaN substrate (QST substrate), a substrate including another semiconductor material having a band gap wider than that of silicon, or any other suitable substrate. In one example, the substrate 210 may include a bulk silicon substrate and may include one or more transition layers or buffer layers of suitable materials to accommodate the lattice mismatch between the silicon substrate and the channel layer 220, as described above with respect to, for example, Figure 1A described.

[0061] The diode 218 may be in the substrate 210 or the semiconductor layer stack, and may include a lateral diode or a vertical diode. In some examples, the diode 218 may be a silicon diode. In some examples, the diode 218 may be a diode formed of a GaN-based material. A first terminal (e.g., an anode) of the diode 218 may be electrically coupled to a source structure 244 of the HEMT 240, and a second terminal (e.g., a cathode) of the diode 218 may be electrically coupled to a drain structure 246 of the HEMT 240. In some examples, the diode 218 may be formed of a p-doped semiconductor layer (or a region of a semiconductor layer) and an n-doped semiconductor layer (or a region of a semiconductor layer). The material, doping density, and / or size of the semiconductor layer (or region) may be selected so that the diode 218 may have a desired avalanche breakdown voltage, for example, equal to or greater than the rated voltage of the semiconductor device 200, but less than the breakdown voltage of the HEMT 240. Thus, the diode 218 may protect the HEMT 240 from irreversible catastrophic breakdown under a high reverse bias voltage.

[0062] In some examples, substrate 210 may include a first semiconductor layer 212 (eg, n + The n-doped silicon layer+ type semiconductor layer, or for example p + The p-doped silicon layer + type semiconductor layer) and a second semiconductor layer 214 (e.g., a p-type semiconductor layer such as a p-doped silicon layer, or an n-type semiconductor layer such as an n-doped silicon layer), wherein the diode 218 may be a vertical diode (e.g., having a Figure 2 In some examples, the heavily doped region 216 may be formed in the second semiconductor layer 214 and may be used to form a low resistance contact between the source structure 244 and the second semiconductor layer 214. In some examples, the first semiconductor layer 212 may be an anode of the diode 218 and the second semiconductor layer 214 may be a cathode of the diode 218. In some examples, the first semiconductor layer 212 may be a cathode of the diode 218 and the second semiconductor layer 214 may be an anode of the diode 218.

[0063] In some examples, the diode 218 can be a lateral diode (eg, having a diode along the Figure 2 The second semiconductor layer 214 may include a p-doped semiconductor layer, and the second semiconductor layer may include a p-doped semiconductor layer, and the n-doped ... + The doped region may be formed in the second semiconductor layer 214 to form a lateral diode with the second semiconductor layer 214. In another example, the second semiconductor layer 214 may include an n-doped semiconductor layer, and a p-doped semiconductor layer. + A doped region may be formed in the second semiconductor layer 214 to form a lateral diode with the second semiconductor layer 214 .

[0064] In some examples, the first semiconductor layer 212 and the second semiconductor layer 214 may be part of a semiconductor layer stack and may include doped epitaxial layers (eg, GaN layers) grown on the substrate 210 to form a vertical GaN-based diode. In one example, the first semiconductor layer 212 may be p + doped GaN layer, and the second semiconductor layer 214 may be an n-doped GaN layer. In one example, the first semiconductor layer 212 may be an n-doped GaN layer. + In one example, the first semiconductor layer 212 may be a p-doped GaN layer, and the second semiconductor layer 214 may be an n-doped GaN layer. + In another example, the first semiconductor layer 212 may be an n-doped GaN layer, and the second semiconductor layer 214 may be a p-doped GaN layer. + Doped GaN layer.

[0065] The semiconductor device disclosed herein including a HEMT and a monolithically integrated diode may have avalanche capability for high voltage / current surge protection and may be used in applications requiring repeated avalanche breakdown, such as in some automotive electrical control units. Compared to devices including board-level or package-level integrated avalanche diodes, the semiconductor device disclosed herein may have much lower parasitic resistance and inductance due to monolithic integration. Therefore, the device may have a shorter response time during switching and may be more suitable for high-speed switching. The avalanche breakdown voltage or energy level of the avalanche diode may be tuned by, for example, tuning the doping density or doping profile of the two terminals of the diode and / or the size of the two terminals of the diode (e.g., the thickness of the lightly doped semiconductor layer of the diode). Because no additional packaging or board-level bonding processes are required (e.g., connecting the HEMT to an off-chip diode), the cost of manufacturing the device may be lower.

[0066] Figure 3A and 3B 3 is a cross-sectional view of an example of a semiconductor device 300 including a HEMT and a diode on the same semiconductor die. In the illustrated example, the semiconductor device 300 includes a substrate including a high resistivity silicon substrate 310, an n + doped silicon layer 320 and p-doped silicon layer 322. In some examples, silicon substrate 310 may be undoped or lightly p-doped. High resistivity silicon substrate 310 may be part of a reduced surface field (RESURF) structure that may produce a higher avalanche breakdown voltage. The vertical diode may be composed of n + The p-doped silicon layer 320 and the p-doped silicon layer 322 are formed. + The doping density, doping profile, and / or thickness of the p-doped silicon layer 320 and the p-doped silicon layer 322 are determined to achieve a desired avalanche breakdown voltage of the vertical silicon diode. + The doped region 324 may be formed in the p-doped silicon layer 322 to reduce the contact resistance with the p-doped silicon layer 322 .

[0067] The semiconductor layer stack 330 may be formed on the substrate by, for example, epitaxial growth. The semiconductor layer stack 330 may include at least a channel layer and a barrier layer that may form a heterostructure with a 2DEG channel at the interface of the heterostructure. For example, the channel layer may include GaN and the barrier layer may include AlGaN. A gate structure 340, a source structure 342, and a drain structure 344 may then be formed on or in the semiconductor layer stack 330 to form a HEMT including a channel layer and a barrier layer.

[0068] As described above, in some examples, the gate structure 340 may include a gate electrical contact (metal electrode) above the barrier layer, and the HEMT may be a depletion-mode high electron mobility transistor. In some examples, the gate structure 340 may include a p-doped semiconductor layer (e.g., a p-GaN layer) formed on the barrier layer and a gate electrical contact formed on the p-doped semiconductor layer, and the HEMT may be an enhancement-mode high electron mobility transistor.

[0069] The source structure 342 may be formed on and / or in the semiconductor layer stack 330 and may be electrically coupled to the channel layer by physical contact or tunneling. The source structure 342 may include or may be electrically coupled to at least one source deep contact 343 formed at one or more regions of the semiconductor device 300 and extending through the semiconductor layer stack 330 to contact the p-type semiconductor device 300. + doped region 324. Therefore, the source structure 342 can be connected through at least one source deep contact 343 and the p-doped silicon layer 322. + The doped region 324 is electrically coupled to the p-doped silicon layer 322 so that the resistance between the source structure 342 of the diode and the p-doped silicon layer 322 can be low.

[0070] The drain structure 344 may also be formed on and / or in the semiconductor layer stack 330 and may be electrically coupled to the channel layer by physical contact or by tunneling. The drain structure 344 may include or may be electrically coupled to at least one drain deep contact 345 formed at one or more regions of the semiconductor device 300 and extending through the semiconductor layer stack 330 and the p-doped silicon layer 322 to contact the n-doped diode. + The drain deep contact 345 may be surrounded by an isolation layer 346 to isolate the drain deep contact 345 from the p-doped silicon layer 322 so that the drain structure 344 can be electrically coupled to the n-type diode. + The p-doped silicon layer 320 and the source structure 342 can be electrically coupled to the p-doped silicon layer 322 of the diode. The isolation layer 346 can include a dielectric material such as silicon dioxide, silicon nitride, aluminum oxide, or the like.

[0071] As described above, the gate electrical contacts of the gate structure 340, the source structure 342, the source deep contact 343, the drain structure 344, and the drain deep contact 345 may include, for example, Cu, W, Au, Al, Ti, Ni, Pt, a metal alloy, or a combination thereof. In some examples, one or more metal barrier layers and / or one or more adhesion layers (e.g., TiN, TaN, etc., or a combination thereof) may be formed between the dielectric and / or semiconductor material and the metal material of the gate electrical contacts of the gate structure 340, the source structure 342, the source deep contact 343, the drain structure 344, and the drain deep contact 345.

[0072] Figures 4A to 4E Description of the invention Manufacturing a semiconductor device such as Figure 3A and 3B An example of a process of manufacturing a semiconductor device 300 is shown. Figure 4A A high resistivity silicon substrate 310 is shown, which may be undoped or lightly doped with a p-type dopant and thus may have a high resistivity. The p-type dopant may include, for example, one or more Group III elements such as boron (B), aluminum (Al), gallium (Ga), indium (In), etc.

[0073] like Figure 4B As shown in + Ion implantation (eg, using an ion beam) and dopant activation form n-type dopants in the silicon substrate 310. + doped silicon layer 320. In some examples, n + The doped silicon layer 320 may be an n-type dopant formed by doping the silicon substrate 310 with an n-type dopant that may be a heavy atom and resists diffusion during subsequent high temperature processes, or by any other method for forming an NBL layer. + The n-type dopant may include, for example, one or more Group V elements, such as phosphorus (P), arsenic (As), antimony (Sb), etc. The n-type dopant may include, for example, one or more Group V elements, such as phosphorus (P), arsenic (As), antimony (Sb), etc. + After doping the silicon layer 320, p-type ion implantation and dopant activation may be performed to convert n + The top layer of the doped silicon layer 320 is changed to a p-doped silicon layer 322. The p-type dopant may include, for example, B, Al, Ga, In, etc. Thus, a vertical silicon diode may be formed by the p-doped silicon layer 322 and the bottom n-doped silicon layer 322. + A doped silicon layer 320 is formed. + The doping density, doping profile and / or thickness of the p-doped silicon layer 320 and the p-doped silicon layer 322 are determined to achieve a desired avalanche breakdown voltage of the vertical silicon diode. + When the doping density of the p-doped silicon layer 320 or the p-doped silicon layer 322 is reduced and / or when the thickness of the p-doped silicon layer 322 is increased, the avalanche breakdown voltage of the vertical silicon diode can be increased. Regions of the p-doped silicon layer 322 can be heavily doped with a p-type dopant to form a p-type dopant. + The region 324 is doped, thereby reducing the contact resistance with the p-doped silicon layer 322 .

[0074] Figure 4CThe semiconductor layer stack 330 is shown to be formed on a silicon substrate 310 including a vertical silicon diode formed therein. The semiconductor layer stack 330 may be formed, for example, by epitaxially growing a channel layer (e.g., a GaN layer) of the HEMT and then epitaxially growing a barrier layer (e.g., an AlGaN layer) of the HEMT on the channel layer. In some examples, one or more buffer layers may be grown on the silicon substrate 310 prior to growing the channel layer. The epitaxial layers of the semiconductor layer stack 330 may be grown using, for example, vapor phase epitaxy (VPE), liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), or metal organic chemical vapor deposition (MOCVD).

[0075] like Figure 4D As shown in , the gate structure 340, source structure 342, and drain structure 344 of the HEMT may be formed on and / or in the semiconductor layer stack 330. As described above, in some examples, the gate structure 340 may include a p-doped semiconductor layer (e.g., a p-GaN layer) formed on the barrier layer and a gate electrical contact formed on the p-doped semiconductor layer, so that the HEMT may be an enhancement-mode HEMT. In some examples, the gate structure 340 may include a gate electrical contact (metal electrode) formed above the barrier layer, and the HEMT may be a depletion-mode HEMT. The source structure 342 and the drain structure 344 may be formed on and / or in the semiconductor layer stack 330, and may be electrically coupled to the channel layer of the HEMT by physical contact or tunneling. As described above, the gate structure 340, the source structure 342, and the drain structure 344 may include, for example, Cu, W, Au, Al, Ti, Ni, Pt, a metal alloy, or a combination thereof.

[0076] Figure 4E At least one source deep contact 343 is shown to be formed to electrically couple the source structure 342 to an anode (e.g., p-doped silicon layer 322) of a silicon diode formed in the silicon substrate 310. The source deep contact 343 may extend through the semiconductor layer stack 330 to contact the p-doped silicon layer 322. + The doped region 324 forms a low resistance metal-semiconductor contact. At least one drain deep contact 345 may be formed to stack to a cathode (eg, n + The drain deep contact 345 may extend through the semiconductor layer stack 330 and the p-doped silicon layer 322 to contact the n-doped silicon layer 320. +The doped silicon layer 320 forms a low resistance metal-semiconductor contact. An isolation layer 346 may be formed in the semiconductor layer stack 330 and the p-doped silicon layer 322 to electrically isolate the drain deep contact 345 from at least the p-doped silicon layer 322. In one example, the semiconductor layer stack 330 and the p-doped silicon layer 322 may be etched at the drain region to form one or more trenches, a dielectric material may be deposited to fill the one or more trenches, the dielectric material in the central region of each trench may be removed to form a hole surrounded by the isolation layer 346, and a metal material may be deposited into the hole to form the drain deep contact 345 surrounded by the isolation layer 346.

[0077] Figure 5A and 5B 5 is a cross-sectional view of an example of a semiconductor device 500 including a HEMT and a diode on the same semiconductor die. In the illustrated example, the semiconductor device 500 includes a substrate including a high resistivity p-type silicon substrate 510 and a p-type silicon substrate 520 formed in the p-type silicon substrate 510. + Doping region 512 and n + The lateral silicon diode can be made of a p-type silicon substrate 510 and an n-type silicon substrate 514. + Doped region 514 is formed. P-type silicon substrate 510 and n-type + The doping density and doping profile of the doping region 514 are adjusted to achieve a desired avalanche breakdown voltage of the lateral silicon diode.

[0078] The semiconductor layer stack 520 may be formed on the p-type silicon substrate 510 by, for example, epitaxial growth. The semiconductor layer stack 520 may include at least a channel layer and a barrier layer that may form a heterostructure with a 2DEG channel at the interface of the heterostructure. For example, the channel layer may include GaN and the barrier layer may include AlGaN. A gate structure 530, a source structure 532, and a drain structure 534 may then be formed on or in the semiconductor layer stack 520 to form a HEMT including a channel layer and a barrier layer.

[0079] As described above, in some examples, the gate structure 530 may include a gate electrical contact (metal electrode) above the barrier layer, and the HEMT may be a depletion-mode high electron mobility transistor. In some examples, the gate structure 530 may include a p-doped semiconductor layer (e.g., a p-GaN layer) formed on the barrier layer and a gate electrical contact formed on the p-doped semiconductor layer, and the HEMT may be an enhancement-mode high electron mobility transistor.

[0080] The source structure 532 may be formed on and / or in the semiconductor layer stack 520 and may be electrically coupled to the channel layer by physical contact or tunneling. The source structure 532 may include or may be electrically coupled to at least one source deep contact 533 formed at one or more regions of the semiconductor device 500 and extending through the semiconductor layer stack 520 to contact the p-type semiconductor device 500. + doped region 512. Therefore, the source structure 532 can be connected to the p-type silicon substrate 510 through at least one source deep contact 533 and the p-type silicon substrate 510. + The doped region 512 is electrically coupled to the p-type silicon substrate 510 so that the resistance between the source structure 532 of the lateral silicon diode and the p-type silicon substrate 510 can be low.

[0081] The drain structure 534 may also be formed on and / or in the semiconductor layer stack 520 and may be electrically coupled to the channel layer by physical contact or by tunneling. The drain structure 534 may include or may be electrically coupled to at least one drain deep contact 535 formed at one or more regions of the semiconductor device 500 and extending through the semiconductor layer stack 520 to contact the n-type transistor of the lateral silicon diode. + doped region 514, so that the drain structure 534 of the lateral silicon diode is connected to the n + The resistance between the doped regions 514 may be small.

[0082] As described above, the gate electrical contacts of the gate structure 530, the source structure 532, the source deep contact 533, the drain structure 534, and the drain deep contact 535 may include, for example, Cu, W, Au, Al, Ti, Ni, Pt, a metal alloy, or a combination thereof. In some examples, one or more metal barrier layers and / or one or more adhesion layers (e.g., TiN, TaN, etc., or a combination thereof) may be formed between the dielectric and / or semiconductor material and the metal material of the gate electrical contacts of the gate structure 530, the source structure 532, the source deep contact 533, the drain structure 534, and the drain deep contact 535. In the semiconductor device 500, the source deep contact 533 and the drain deep contact 535 may have the same depth and may be manufactured using the same process.

[0083] Figures 6A to 6E Description of the invention Manufacturing a semiconductor device such as Figure 5A and 5B An example of a process for a semiconductor device 500 is shown. Fig. 6A A p-type silicon substrate 510 is shown, which can be formed by doping a silicon substrate with a p-type dopant such as B, Al, Ga, In, etc. Figure 6B As shown in FIG. 5 , the first region of the p-type silicon substrate 510 may be heavily doped with a p-type dopant (eg, B, Al, Ga, In, etc.) to form a p-type silicon substrate.+ The p-type silicon substrate 510 may be heavily doped with an n-type dopant (eg, P, As, Sb, etc.) to form an n-type dopant region 512. + doped region 514. In one example, p + Doping region 512 and n + The doped regions 514 may be formed by ion implantation and dopant activation processes. + Doping region 514 is formed. n + The doping density and doping profile of the doping region 514 and the p-type silicon substrate 510 are adjusted to achieve the desired avalanche breakdown voltage of the lateral silicon diode. + When the doping density of the doped region 514 or the p-type silicon substrate 510 is reduced, the avalanche breakdown voltage of the lateral silicon diode may be increased.

[0084] Figure 6C The semiconductor layer stack 520 is shown to be formed on a p-type silicon substrate 510 including a lateral silicon diode formed therein. The semiconductor layer stack 520 may be formed, for example, by epitaxially growing a channel layer (e.g., a GaN layer) of the HEMT and then epitaxially growing a barrier layer (e.g., an AlGaN layer) of the HEMT on the channel layer. In some examples, one or more buffer layers may be grown on the p-type silicon substrate 510 prior to growing the channel layer. The epitaxial layers of the semiconductor layer stack 520 may be grown using, for example, VPE, LPE, MBE, or MOCVD.

[0085] like Fig.6D As shown in , the gate structure 530, source structure 532, and drain structure 534 of the HEMT may be formed on and / or in the semiconductor layer stack 520. As described above, in some examples, the gate structure 530 may include a p-doped semiconductor layer (e.g., a p-GaN layer) formed on the barrier layer and a gate electrical contact formed on the p-doped semiconductor layer, so that the HEMT may be an enhancement-mode HEMT. In some examples, the gate structure 530 may include a gate electrical contact (metal electrode) formed above the barrier layer, and the HEMT may be a depletion-mode HEMT. The source structure 532 and the drain structure 534 may be formed on and / or in the semiconductor layer stack 520, and may be electrically coupled to the channel layer of the HEMT through physical contact or tunneling. As described above, the gate structure 530, the source structure 532, and the drain structure 534 may include a metal material, such as Cu, W, Au, Al, Ti, Ni, Pt, a metal alloy, or a combination thereof.

[0086] Fig. 6EAt least one source deep contact 533 may be formed to electrically couple the source structure 532 to the anode of the silicon diode (eg, the p-type silicon substrate 510). The source deep contact 533 may extend through the semiconductor layer stack 520 to contact the p-type silicon substrate 510. + Doped region 512 forms a low resistance metal-semiconductor contact. At least one drain deep contact 535 may be formed to electrically couple drain structure 534 to a cathode (eg, n + The drain deep contact 535 may extend through the semiconductor layer stack 520 to contact the n + Doped regions 514 form low resistance metal-semiconductor contacts. Source deep contact 533 and drain deep contact 535 can be formed using the same fabrication process, such as semiconductor etching and metal deposition, at least because both contacts penetrate the same thickness of semiconductor layer stack 520 .

[0087] Fig. 7A and 7B 7 is a cross-sectional view of an example of a semiconductor device 700 including a HEMT and a diode on the same semiconductor die. In the illustrated example, the semiconductor device 700 may include a substrate including a low-resistivity silicon substrate 710 and an n-doped silicon layer 720. The low-resistivity silicon substrate 710 may be heavily p-doped. In some examples, the n-doped silicon layer 720 may be epitaxially grown on the low-resistivity silicon substrate 710 and may be lightly doped. The n-doped silicon layer 720 may have a high resistivity compared to the silicon substrate 710. In some examples, the n-doped silicon layer 720 may include n + doped region 722. The vertical diode can be formed by an n-doped silicon layer 720 and a heavily p-doped low resistivity silicon substrate 710. The n-doped silicon layer 720 and the p-doped low resistivity silicon substrate 710 can be selected. + The doping density and doping profile of the doped low-resistivity silicon substrate 710 and / or the thickness of the n-doped silicon layer 720 are adjusted to achieve a desired avalanche breakdown voltage of the vertical silicon diode.

[0088] The semiconductor layer stack 730 may be formed on the substrate by, for example, epitaxial growth. The semiconductor layer stack 730 may include at least a channel layer and a barrier layer that may form a heterostructure with the 2DEG channel at the interface of the heterostructure. For example, the channel layer may include GaN and the barrier layer may include AlGaN. A gate structure 740, a source structure 742, and a drain structure 744 may then be formed on or in the semiconductor layer stack 730 to form a HEMT including a channel layer and a barrier layer. + Due to the large voltage maintained by the reverse biased pn junction between the doped low-resistivity silicon substrate 710 and the n-doped silicon layer 720 , the vertical electric field in the semiconductor layer stack 730 (eg, during avalanche breakdown) may be reduced.

[0089] In some examples, the gate structure 740 may include a gate electrical contact (metal electrode) above the barrier layer, and the HEMT may be a depletion-mode high electron mobility transistor. In some examples, the gate structure 740 may include a p-doped semiconductor layer (e.g., a p-GaN layer) formed on the barrier layer and a gate electrical contact formed on the p-doped semiconductor layer, and the HEMT may be an enhancement-mode high electron mobility transistor.

[0090] The source structure 742 may be formed on and / or in the semiconductor layer stack 730 and may be electrically coupled to the channel layer of the HEMT by physical contact or tunneling. The source structure 742 may include or may be electrically coupled to at least one source deep contact 743 formed at one or more regions of the semiconductor device 700 and extending through the semiconductor layer stack 730 and the n-doped silicon layer 720 to contact the p-doped silicon layer. + The source structure 742 can be electrically coupled to the p-type silicon substrate 710 by at least one source deep contact 743. + Doped low resistivity silicon substrate 710. The source deep contact 743 may be surrounded by an isolation layer 746 to isolate the source deep contact 743 from at least the n-doped silicon layer 720. The isolation layer 746 may include a dielectric material such as silicon dioxide, silicon nitride, aluminum oxide, or the like.

[0091] The drain structure 744 may also be formed on and / or in the semiconductor layer stack 730 and may be electrically coupled to the channel layer by physical contact or by tunneling. The drain structure 744 may include or may be electrically coupled to at least one drain deep contact 745 formed at one or more regions of the semiconductor device 700 and extending through the semiconductor layer stack 730 to contact the n-doped silicon layer 720. + The doped region 722 can reduce the contact resistance between the drain structure 744 of the diode and the n-doped silicon layer 720 .

[0092] The gate electrical contacts of the gate structure 740, the source structure 742, the source deep contact 743, the drain structure 744, and the drain deep contact 745 may include, for example, Cu, W, Au, Al, Ti, Ni, Pt, a metal alloy, or a combination thereof. In some examples, one or more metal barrier layers and / or one or more adhesion layers (e.g., TiN, TaN, etc., or a combination thereof) may be formed between the dielectric and / or semiconductor material and the metal material of the gate electrical contacts of the gate structure 740, the source structure 742, the source deep contact 743, the drain structure 744, and the drain deep contact 745.

[0093] Figures 8A to 8F Description of the invention Manufacturing a semiconductor device such as Fig. 7A and 7BAn example of a process for a semiconductor device 700 is shown. Fig. 8A A low resistivity silicon substrate 710 is shown which may be heavily doped with p-type dopants such as B, Al, Ga, In, etc. Figure 8B As shown in FIG. 1 , an n-doped silicon layer 720 may be formed on a silicon substrate 710 by, for example, epitaxial growth using, for example, VPE, LPE, MBE, or MOCVD. In some examples, an n-type dopant may be incorporated into the n-doped silicon layer 720 during the epitaxial growth. In some examples, an n-type dopant may be implanted after the epitaxial growth to form the n-doped silicon layer 720. A vertical silicon diode may be formed by a heavy p + The doped silicon substrate 710 and the n-doped silicon layer 720 are formed. The doping density and doping profile of the silicon substrate 710 and the n-doped silicon layer 720 and / or the thickness of the n-doped silicon layer 720 can be tuned to achieve a desired avalanche breakdown voltage of the vertical silicon diode. + Ion implantation and dopant activation may be performed at a region of the n-doped silicon layer 720 to form an n-doped silicon layer. + Doped region 722, such as Figure 8C As shown in FIG. n-doped silicon layer 720 and n + The n-type dopant in the doped region 722 may include, for example, P, As, Sb, etc.

[0094] Fig.8D The semiconductor layer stack 730 is shown to be formed on a silicon substrate 710 including a vertical silicon diode formed therein. The semiconductor layer stack 730 may be formed, for example, by epitaxially growing a channel layer (e.g., a GaN layer) of the HEMT and then epitaxially growing a barrier layer (e.g., an AlGaN layer) of the HEMT on the channel layer. In some examples, one or more buffer layers may be grown on the n-doped silicon layer 720 prior to growing the channel layer. The epitaxial layers of the semiconductor layer stack 730 may be grown using, for example, VPE, LPE, MBE, or MOCVD.

[0095] like Fig. 8EAs shown in , the gate structure 740, source structure 742, and drain structure 744 of the HEMT may be formed on and / or in the semiconductor layer stack 730. As described above, in some examples, the gate structure 740 may include a p-doped semiconductor layer (e.g., a p-GaN layer) formed on the barrier layer and a gate electrical contact formed on the p-doped semiconductor layer, so that the HEMT may be an enhancement-mode HEMT. In some examples, the gate structure 740 may include a gate electrical contact (metal electrode) formed above the barrier layer, and the HEMT may be a depletion-mode HEMT. The source structure 742 and the drain structure 744 may be formed on and / or in the semiconductor layer stack 730, and may be electrically coupled to the channel layer of the HEMT through physical contact or tunneling. As described above, the gate structure 740, the source structure 742, and the drain structure 744 may include, for example, Cu, W, Au, Al, Ti, Ni, Pt, a metal alloy, or a combination thereof.

[0096] Figure 8F At least one drain deep contact 745 can be formed to electrically couple the drain structure 744 to the cathode (e.g., n-doped silicon layer 720) of the vertical silicon diode. The drain deep contact 745 can extend through the semiconductor layer stack 730 to contact the n-doped silicon layer 720. + Doped region 722 forms a low resistance metal-semiconductor contact. At least one source deep contact 743 may be formed to electrically couple source structure 742 to an anode (eg, p + The source deep contact 743 may extend through the semiconductor layer stack 730 and the n-doped silicon layer 720 to contact the p-doped low resistivity silicon substrate 710. + The doped low-resistivity silicon substrate 710 forms a low-resistance metal-semiconductor contact. An isolation layer 746 may be formed in the semiconductor layer stack 730 and the n-doped silicon layer 720 to electrically isolate the source deep contact 743 from at least the n-doped silicon layer 720. In one example, the semiconductor layer stack 730 and the n-doped silicon layer 720 may be etched at the source region to form one or more trenches, a dielectric material may be deposited to fill the one or more trenches, the dielectric material in the central region of each trench may be removed to form a hole surrounded by the isolation layer 746, and a metal material may be deposited into the hole to form the source deep contact 743 surrounded by the isolation layer 746.

[0097] Fig. 9A and 9B9 is a cross-sectional view of an example of a semiconductor device 900 including a HEMT and a diode on the same semiconductor die. In the illustrated example, the semiconductor device 900 includes a substrate including a low-resistivity silicon substrate 910 and an n-doped silicon layer 920. The low-resistivity silicon substrate 910 may be heavily doped with a p-type dopant. In some examples, the n-doped silicon layer 920 may be epitaxially grown on the low-resistivity silicon substrate 910 and may be lightly doped. In some examples, the n-doped silicon layer 920 may include n-doped silicon layers formed therein. + Doped region 922 and p + doped region 924. The lateral diode can be made of p + The doped region 924 and the n-doped silicon layer 920 are formed. In some examples, the vertical diode can be formed by the n-doped silicon layer 920 and the p-doped silicon layer 920. + A doped low resistivity silicon substrate 910 is formed. The n-doped silicon layer 920 and the p-doped silicon layer 920 may be selected. + Doped region 924 (or p + The doping density and doping profile of the n-doped low-resistivity silicon substrate 910 and / or the thickness of the n-doped silicon layer 920 are adjusted to achieve a desired avalanche breakdown voltage of the silicon diode.

[0098] The semiconductor layer stack 930 may be formed on the substrate by, for example, epitaxial growth. The semiconductor layer stack 930 may include at least a channel layer and a barrier layer that may form a heterostructure with a 2DEG channel at the interface of the heterostructure. For example, the channel layer may include GaN and the barrier layer may include AlGaN. A gate structure 940, a source structure 942, and a drain structure 944 may then be formed on or in the semiconductor layer stack 930 to form a HEMT including a channel layer and a barrier layer.

[0099] In some examples, the gate structure 940 may include a gate electrical contact (metal electrode) above the barrier layer, and the HEMT may be a depletion-mode high electron mobility transistor. In some examples, the gate structure 940 may include a p-doped semiconductor layer (e.g., a p-GaN layer) formed on the barrier layer and a gate electrical contact formed on the p-doped semiconductor layer, and the HEMT may be an enhancement-mode high electron mobility transistor.

[0100] The source structure 942 may be formed on and / or in the semiconductor layer stack 930 and may be electrically coupled to the channel layer of the HEMT by physical contact or tunneling. The source structure 942 may include or may be electrically coupled to at least one source deep contact 943 formed at one or more regions of the semiconductor device 900 and extending through the semiconductor layer stack 930 to contact the p-type semiconductor device 900. + doped region 924. Thus, the source structure 942 may be electrically coupled to the p +Doped region 924. In some examples, one or more source deep contacts can be formed to electrically couple source structure 942 to low-resistivity silicon substrate 910.

[0101] The drain structure 944 may also be formed on and / or in the semiconductor layer stack 930 and may be electrically coupled to the channel layer of the HEMT by physical contact or by tunneling. The drain structure 944 may include or may be electrically coupled to at least one drain deep contact 945 formed at one or more regions of the semiconductor device 900 and extending through the semiconductor layer stack 930 to contact the n-doped silicon layer 920. + Doping region 922 can reduce the contact resistance between the drain structure 944 of the diode and the n-doped silicon layer 920. In semiconductor device 900, source deep contact 943 and drain deep contact 945 can have the same depth (eg, the thickness of semiconductor layer stack 930) and can be manufactured using the same process.

[0102] The gate electrical contacts of the gate structure 940, source structure 942, source deep contact 943, drain structure 944, and drain deep contact 945 may include, for example, Cu, W, Au, Al, Ti, Ni, Pt, metal alloys, or combinations thereof. In some examples, one or more metal barrier layers and / or one or more adhesion layers (e.g., TiN, TaN, etc., or combinations thereof) may be formed between the dielectric and / or semiconductor material and the metal material of the gate electrical contacts of the gate structure 940, source structure 942, source deep contact 943, drain structure 944, and drain deep contact 945.

[0103] Fig. 9A and 9B The examples shown in may also include reduced surface field (RESURF) structural features that can produce higher avalanche breakdown voltages. Fig. 9A and 9B In the case where the substrate 910 is p + When a doped low resistivity substrate and an n-type epitaxial layer (e.g., n-doped silicon layer 920) are sequentially grown on top of the substrate, the substrate 910 may also be a RESURF structure when a specific thickness and doping of the n-doped silicon layer 920 are met. Vertical depletion and lateral depletion may interact with each other to achieve a more uniform electric field distribution, so that the increase of the surface field slows down with high voltage.

[0104] Figures 10A to 10F Description Manufacturing Fig. 9A and 9B An example of a process for a semiconductor device 900 is shown. Fig. 10A A low resistivity silicon substrate 910 is shown which may be heavily doped with p-type dopants such as B, Al, Ga, In, etc. Fig. 10BAs shown in FIG. 1 , an n-doped silicon layer 920 may be formed on a silicon substrate 910 by, for example, epitaxial growth using, for example, MOCVD, VPE, LPE, or MBE. In some examples, an n-type dopant may be incorporated into the n-doped silicon layer 920 during the epitaxial growth. In some examples, an n-type dopant may be implanted after the epitaxial growth to form the n-doped silicon layer 920. A vertical silicon diode may be formed by p + A doped silicon substrate 910 and an n-doped silicon layer 920 are formed. The doping density and doping profile of the silicon substrate 910 and the n-doped silicon layer 920 and / or the thickness of the n-doped silicon layer 920 can be tuned to achieve a desired avalanche breakdown voltage of the vertical silicon diode. + Ion implantation and dopant activation may be performed at a region of the n-doped silicon layer 920 to form an n-doped silicon layer. + Doped region 922, such as Fig. 10C As shown in FIG. n-doped silicon layer 920 and n + The n-type dopant in the doping region 922 may include, for example, P, As, Sb, etc. Fig. 10C As shown in + Ion implantation and dopant activation may be performed at regions of the n-doped silicon layer 920 to form p-doped silicon layers. + doped region 924. A lateral silicon diode can be made of p + The doped region 924 and the n-doped silicon layer 920 are formed. The n-doped silicon layer 920 and the p-doped silicon layer 920 can be tuned. + The doping density and doping profile of the doping region 924 are adjusted to achieve a desired avalanche breakdown voltage of the lateral silicon diode.

[0105] Fig. 10D The semiconductor layer stack 930 is shown to be formed on the n-doped silicon layer 920. The semiconductor layer stack 930 can be formed by, for example, epitaxially growing a channel layer (e.g., a GaN layer) of the HEMT and then epitaxially growing a barrier layer (e.g., an AlGaN layer) of the HEMT on the channel layer. In some examples, one or more buffer layers can be grown on the n-doped silicon layer 920 before growing the channel layer. The epitaxial layers of the semiconductor layer stack 930 can be grown using, for example, VPE, LPE, MBE, or MOCVD.

[0106] like Fig. 10EAs shown in , the gate structure 940, source structure 942, and drain structure 944 of the HEMT may be formed on and / or in the semiconductor layer stack 930. As described above, in some examples, the gate structure 940 may include a p-doped semiconductor layer (e.g., a p-GaN layer) formed on the barrier layer and a gate electrical contact formed on the p-doped semiconductor layer, so that the HEMT may be an enhancement-mode HEMT. In some examples, the gate structure 940 may include a gate electrical contact (metal electrode) formed above the barrier layer, and the HEMT may be a depletion-mode HEMT. The source structure 942 and the drain structure 944 may be formed on and / or in the semiconductor layer stack 930, and may be electrically coupled to the channel layer of the HEMT by physical contact or tunneling. As described above, the gate structure 940, the source structure 942, and the drain structure 944 may include, for example, Cu, W, Au, Al, Ti, Ni, Pt, a metal alloy, or a combination thereof.

[0107] Fig.10F At least one source deep contact 943 may be formed to electrically couple the source structure 942 to the anode of the lateral silicon diode (eg, p + The source deep contact 943 may extend through the semiconductor layer stack 930 to contact the p + Doped region 924 forms a low resistance metal-semiconductor contact. At least one drain deep contact 945 may be formed to pass through n + The doped region 922 electrically couples the drain structure 944 to the cathode (n-doped silicon layer 920) of the lateral silicon diode. For example, the drain deep contact 945 may extend through the semiconductor layer stack 930 to contact the n-doped silicon layer 920. + Doped regions 922 form low resistance metal-semiconductor contacts. Source deep contacts 943 and drain deep contacts 945 may be formed using the same fabrication process, such as semiconductor etching and metal deposition.

[0108] exist Figures 3A to 10F In the examples shown in , the base silicon substrate used to form the silicon diode can be lightly p-doped or heavily p-doped. In some examples, the base silicon substrate used to form the silicon diode can be lightly n-doped or heavily n-doped. Compared with n-type silicon substrates, p-type silicon substrates may be more popular and more widely adopted due to lower cost and wafer sliding resistance. In some examples, an avalanche diode can be formed in a semiconductor layer stack including a non-silicon channel layer and a barrier layer, rather than in a silicon substrate.

[0109] Fig.11A and 11B1 is a cross-sectional view of an example of a semiconductor device 1100 including a HEMT and a diode on the same semiconductor die. In the illustrated example, the semiconductor device 1100 includes a substrate 1110, which may include, for example, a silicon substrate, a silicon carbide substrate, an SOI substrate, a sapphire substrate, a GaN substrate, a GaAs substrate, an engineered GaN substrate (e.g., a QST substrate), a substrate including another semiconductor material having a bandgap wider than that of silicon, or any other suitable substrate.

[0110] The semiconductor layer stack may be formed on the substrate 1110 by epitaxial growth techniques such as MOCVD, VPE, LPE, or MBE. Fig.11A and 11B In the example shown in FIG. , the semiconductor layer stack may include p + doped GaN layer 1120, p-doped GaN layer 1130, n-doped GaN layer 1140, + The vertical GaN-based diode can be composed of a p-doped GaN layer 1130 and an n-doped GaN layer 1140, a conductive shielding structure 1150, a channel layer 1160, and a barrier layer 1162. + The p-type dopant used to dope the GaN layer may include, for example, Mg, Ca, Zn, or Be. The n-type dopant used to dope the GaN layer may include, for example, Si or Ge. The dopant may be incorporated into the GaN layer and activated during epitaxial growth, so ion implantation may not be required to form the doped GaN layer. The p-doped GaN layer 1130 and n-doped GaN layer 1140 may be selected. + The doping density, doping profile and / or thickness of the doped GaN layer 1140 are adjusted to achieve a desired avalanche breakdown voltage of the vertical GaN-based diode. Fig.11A and 11B The example shown in allows all-GaN integration of GaN HEMTs and vertical GaN diodes, which can simplify the manufacturing process. For example, diode production does not require additional doping of the substrate 1110.

[0111] The conductive shielding structure 1150 may include, for example, a p-GaN layer or another voltage-maintaining insulator. For example, the conductive shielding structure 1150 may be heavily doped with carbon to become semi-insulating, or p-doped with a deep acceptor level (e.g., Ev+0.9 eV). Another example of the conductive shielding structure 1150 may be a conductive layer filled with charge. Examples of conductive shielding structures or conductive back barriers are described in U.S. Patent Application No. 18 / 326,698, entitled “INTEGRATED DEVICES WITH CONDUCTIVE BARRIER STRUCTURE,” filed on May 31, 2023, and U.S. Patent Application No. 18 / 534,056, entitled “INTEGRATED DEVICES WITH CONDUCTIVE BARRIER STRUCTURE,” filed on December 8, 2023, the entire contents of which are incorporated herein by reference. In some examples, the conductive shielding structure 1150 includes an aluminum gallium nitride (AlGaN) layer, an aluminum nitride (AlN) layer, an aluminum antimony nitride (AlSbN) layer, or an aluminum indium nitride (AlInN) layer, for example, as a confinement layer, and includes a gallium nitride (GaN) layer, for example, as a low bandgap energy material layer. In an example in which the conductive barrier isolation layer 1150 includes a gallium nitride (GaN) layer, the conductive shielding structure 1150 may be referred to as a conductive GaN barrier structure. Other materials may be implemented for one or more layers of the conductive barrier structure. In some examples, the material of the conductive shielding structure 1150 is or includes an intrinsic (e.g., undoped) material. In some examples, the material of the conductive shielding structure 1150 includes a doped material. In some examples, the confinement layer and the low bandgap energy material layer may be doped with carbon, magnesium, etc. In some examples, the confinement layer may be doped with magnesium and the low bandgap energy material layer may be doped with carbon. Other dopants may be implemented in the conductive shielding structure 1150. The confinement layer may be doped with a uniform dopant concentration, or may be doped with a laterally dopant gradient concentration (eg, having a concentration gradient along the x or y axis) to introduce IR drop and charge depletion.

[0112] The channel layer 1160 may include, for example, an undoped GaN layer. The barrier layer 1162 may include, for example, an AlGaN layer. In some examples, one or more buffer layers may be grown on the substrate 1110 before growing the semiconductor layer stack. The conductive shielding structure 1150 may shield the channel layer 1160 from the p-doped GaN layer 1130 and the n-doped GaN layer 1130 that form the vertical diode as described above during an avalanche event. + The influence of high voltage in the doped GaN layer 1140 is to mitigate the back-gate effect on the HEMT.

[0113] A gate structure 1170, a source structure 1172, and a drain structure 1174 may then be formed on or in the semiconductor layer stack to form a HEMT including a channel layer 1160 and a barrier layer 1162. In some examples, the gate structure 1170 may include a gate electrical contact (metal electrode) over the barrier layer 1162, and the HEMT may be a depletion-mode high electron mobility transistor. In some examples, the gate structure 1170 may include a p-doped semiconductor layer (e.g., a p-GaN layer) formed on the barrier layer 1162 and a gate electrical contact formed on the p-doped semiconductor layer, and the HEMT may be an enhancement-mode high electron mobility transistor.

[0114] The source structure 1172 may be formed on and / or in the semiconductor layer stack and may be electrically coupled to the channel layer 1160 of the HEMT by physical contact or tunneling. The source structure 1172 may include or may be electrically coupled to at least one source deep contact 1173 formed at one or more regions of the semiconductor device 1100 and extending through the barrier layer 1162, the channel layer 1160, the conductive shield structure 1150, the n-type semiconductor layer 1160, the conductive shield structure 1150, the n-type semiconductor layer 1160, the conductive shield structure 1150, the n-type semiconductor layer 1160, the conductive shield structure 1150, the conductive shield structure 116 ... + The p-doped GaN layer 1140 and the p-doped GaN layer 1130 are in contact with the p + doped GaN layer 1120. Therefore, the source structure 1172 can be electrically coupled to the p-type GaN layer 1120 through at least one source deep contact 1173. + The source deep contact 1173 may be surrounded by an isolation layer 1176 to separate the source deep contact 1173 from at least n + The doped GaN layer 1140 is isolated. The isolation layer 1176 may include a dielectric material such as silicon dioxide, silicon nitride, aluminum oxide, etc.

[0115] The drain structure 1174 may also be formed on and / or in the semiconductor layer stack and may be electrically coupled to the channel layer 1160 of the HEMT by physical contact or by tunneling. The drain structure 1174 may include or may be electrically coupled to at least one drain deep contact 1175 formed at one or more regions of the semiconductor device 1100 and extending through the barrier layer 1162, the channel layer 1160, and the conductive shield structure 1150 to contact the n + The GaN layer 1140 is doped.

[0116] The gate electrical contacts of the gate structure 1170, the source structure 1172, the source deep contact 1173, the drain structure 1174, and the drain deep contact 1175 may include, for example, Cu, W, Au, Al, Ti, Ni, Pt, a metal alloy, or a combination thereof. In some examples, one or more metal barrier layers and / or one or more adhesion layers (e.g., TiN, TaN, etc., or a combination thereof) may be formed between the dielectric and / or semiconductor material and the metal material of the gate electrical contacts of the gate structure 1170, the source structure 1172, the source deep contact 1173, the drain structure 1174, and the drain deep contact 1175.

[0117] Figures 12A to 12D Description Manufacturing Fig.11A and 11B An example of a process for a semiconductor device 1100 is shown. Fig. 12A A substrate 1110 is shown, which may include, for example, a silicon substrate, a silicon carbide substrate, an SOI substrate, a sapphire substrate, a GaN substrate, a GaAs substrate, an engineered GaN substrate (e.g., a QST substrate), a substrate including another semiconductor material having a band gap wider than that of silicon, or any other suitable substrate. In one example, the substrate 1110 may be a silicon substrate. The substrate 1110 may be doped or undoped.

[0118] Fig. 12B A semiconductor layer stack is shown epitaxially grown on a substrate 1110. The semiconductor layer stack may be grown using, for example, MOCVD, VPE, LPE, or MBE techniques, and may include, for example, p + doped GaN layer 1120, p-doped GaN layer 1130, n-doped GaN layer 1140, + doped GaN layer 1140, channel layer 1160 and barrier layer 1162. In some examples, the semiconductor layer stack may further include n + A conductive shielding structure 1150 is provided between the p-doped GaN layer 1140 and the channel layer 1160. The vertical GaN-based diode can be formed by the p-doped GaN layer 1130 and the n-doped GaN layer 1140. + The p-type dopant used to dope the GaN layer may include, for example, Mg, Ca, Zn, or Be. The n-type dopant used to dope the GaN layer may include, for example, Si or Ge. The dopant may be incorporated into the GaN layer and activated during epitaxial growth, so ion implantation may not be required to form the doped GaN layer. The p-doped GaN layer 1130 and n-doped GaN layer 1140 may be tunable. + The doping density, doping profile and / or thickness of the doped GaN layer 1140 are determined to achieve a desired avalanche breakdown voltage of the vertical GaN-based diode. The channel layer 1160 may include, for example, an undoped GaN layer. The barrier layer 1162 may include, for example, an AlGaN layer. In some examples, one or more buffer layers may be grown on the substrate 1110 before growing the semiconductor layer stack.

[0119] like Fig. 12C As shown in , the gate structure 1170, source structure 1172, and drain structure 1174 of the HEMT may be formed on and / or in the semiconductor layer stack. As described above, in some examples, the gate structure 1170 may include a p-doped semiconductor layer (e.g., a p-GaN layer) formed on the barrier layer 1162 and a gate electrical contact formed on the p-doped semiconductor layer, so that the HEMT may be an enhancement-mode HEMT. In some examples, the gate structure 1170 may include a gate electrical contact (metal electrode) formed above the barrier layer 1162, and the HEMT may be a depletion-mode HEMT. The source structure 1172 and the drain structure 1174 may be formed on and / or in the semiconductor layer stack, and may be electrically coupled to the channel layer 1160 of the HEMT through physical contact or tunneling. As described above, the gate structure 1170 , the source structure 1172 , and the drain structure 1174 may include, for example, Cu, W, Au, Al, Ti, Ni, Pt, metal alloys, or combinations thereof.

[0120] Fig.12D At least one drain deep contact 1175 may be formed to electrically couple the drain structure 1174 to the cathode (eg, n + The drain deep contact 1175 may extend through the barrier layer 1162 and the channel layer 1160 to contact the n-doped GaN layer 1140. + The doped GaN layer 1140 forms a low resistance metal-semiconductor contact. At least one source deep contact 1173 may be formed to pass through the p + The doped GaN layer 1120 electrically couples the source structure 1172 to the anode of the vertical GaN-based diode (eg, the p-doped GaN layer 1130). The source deep contact 1173 may extend through the barrier layer 1162, the channel layer 1160, the n + The p-doped GaN layer 1140 and the p-doped GaN layer 1130 are connected to the p-doped GaN layer 1140. + The doped GaN layer 1120 forms a low resistance metal-semiconductor contact. An isolation layer 1176 may be formed in the semiconductor layer stack to separate the source deep contact 1173 from at least n + The doped GaN layer 1140 is electrically isolated. In one example, the semiconductor layer stack can be etched at the source region to form one or more trenches, a dielectric material can be deposited to fill the one or more trenches, the dielectric material in the central region of each trench can be removed to form a hole surrounded by the isolation layer 1176, and a metal material can be deposited into the hole to form a source deep contact 1173 surrounded by the isolation layer 1176.

[0121] Fig.13A and 13B1 is a cross-sectional view of an example of a semiconductor device 1300 including a HEMT and a diode on the same semiconductor die. In the illustrated example, the semiconductor device 1300 includes a substrate 1310, which may include, for example, a silicon substrate, a silicon carbide substrate, an SOI substrate, a sapphire substrate, a GaN substrate, a GaAs substrate, an engineered GaN substrate (e.g., a QST substrate), a substrate including another semiconductor material having a bandgap wider than that of silicon, or any other suitable substrate. The substrate 1310 may be doped or undoped.

[0122] The semiconductor layer stack may be formed on the substrate 1310 by an epitaxial growth process such as MOCVD, VPE, LPE, or MBE. Fig.13A and 13B In the example shown in FIG. , the semiconductor layer stack may include n + doped GaN layer 1320, n-doped GaN layer 1330, p-doped GaN layer 1340 + doped GaN layer 1340, channel layer 1350 and barrier layer 1352. The vertical GaN-based diode can be made of p + The p-type dopant used to dope the GaN layer may include, for example, Mg, Ca, Zn, or Be. The n-type dopant used to dope the GaN layer may include, for example, Si or Ge. The dopant may be incorporated into the GaN layer and activated during epitaxial growth, so ion implantation may not be required to form the doped GaN layer. + The doping density, doping profile and / or thickness of the doped GaN layer 1340 and the n-doped GaN layer 1330 are determined to achieve a desired avalanche breakdown voltage of the vertical GaN-based diode. The channel layer 1350 may include, for example, an undoped GaN layer. The barrier layer 1352 may include, for example, an AlGaN layer. In some examples, one or more buffer layers may be grown on the substrate 1310 before growing the semiconductor layer stack.

[0123] exist Fig.13A and 13B In the example shown in FIG. 1 , an n-type dopant is formed on the substrate 1310 due to material properties, such as the lower activation energy of the n-type dopant compared to the p-type dopant. + The doping process when doping the GaN layer 1320 may be more complicated than forming a p-type GaN layer on the substrate 1110. + The doping process when doping the GaN layer 1120 is simpler and more efficient. Fig.13A and 13B Can be omitted Fig.11A and 11B The conductive shielding structure 1150 is formed by the n-doped GaN layer 1330 and the p-doped GaN layer 1330 under high drain bias. + The np-doped GaN layer 1340 is formed +The junction is reverse biased and will therefore block voltage. Most high voltages can be applied across a reverse biased np + junction instead of going down across the GaN buffer layer, thus reducing the back-gate effect on the HEMT.

[0124] A gate structure 1360, a source structure 1362, and a drain structure 1364 may then be formed on or in the semiconductor layer stack to form a HEMT including a channel layer 1350 and a barrier layer 1352. In some examples, the gate structure 1360 may include a gate electrical contact (metal electrode) over the barrier layer 1352, and the HEMT may be a depletion-mode high electron mobility transistor. In some examples, the gate structure 1360 may include a p-doped semiconductor layer (e.g., a p-GaN layer) formed on the barrier layer 1352 and a gate electrical contact formed on the p-doped semiconductor layer, and the HEMT may be an enhancement-mode high electron mobility transistor.

[0125] The source structure 1362 may be formed on and / or in the semiconductor layer stack and may be electrically coupled to the channel layer 1350 of the HEMT by physical contact or tunneling. The source structure 1362 may include or may be electrically coupled to at least one source deep contact 1363 formed at one or more regions of the semiconductor device 1300 and extending through the barrier layer 1352 and the channel layer 1350 to contact the p-type semiconductor device 1300. + doped GaN layer 1340. Thus, source structure 1362 may be electrically coupled to p through at least one source deep contact 1363. + The GaN layer 1340 is doped.

[0126] The drain structure 1364 may also be formed on and / or in the semiconductor layer stack and may be electrically coupled to the channel layer 1350 of the HEMT by physical contact or by tunneling. The drain structure 1364 may include or may be electrically coupled to at least one drain deep contact 1365 formed at one or more regions of the semiconductor device 1300 and extending through the barrier layer 1352, the channel layer 1350, the p-type transistor 1350, and the like. + The n-doped GaN layer 1340 and the n-doped GaN layer 1330 are connected to the n-doped GaN layer 1340. + The GaN layer 1320 is doped. The drain deep contact 1365 may be surrounded by an isolation layer 1366 to separate the drain deep contact 1365 from at least p + The doped GaN layer 1340 is isolated. The isolation layer 1366 may include a dielectric material such as silicon dioxide, silicon nitride, aluminum oxide, etc.

[0127] The gate electrical contacts of the gate structure 1360, the source structure 1362, the source deep contact 1363, the drain structure 1364, and the drain deep contact 1365 may include, for example, Cu, W, Au, Al, Ti, Ni, Pt, a metal alloy, or a combination thereof. In some examples, one or more metal barrier layers and / or one or more adhesion layers (e.g., TiN, TaN, etc., or a combination thereof) may be formed between the dielectric and / or semiconductor material and the metal material of the gate electrical contacts of the gate structure 1360, the source structure 1362, the source deep contact 1363, the drain structure 1364, and the drain deep contact 1365.

[0128] Figures 14A to 14D Description Manufacturing Fig.13A and 13B An example of a process for a semiconductor device 1300 is shown. Fig.14A A substrate 1310 is shown, which may include, for example, a silicon substrate, a silicon carbide substrate, an SOI substrate, a sapphire substrate, a GaN substrate, a GaAs substrate, an engineered GaN substrate (e.g., a QST substrate), a substrate including another semiconductor material having a band gap wider than that of silicon, or any other suitable substrate. In one example, the substrate 1310 may be a silicon substrate. The substrate 1310 may be doped or undoped.

[0129] Fig. 14B A semiconductor layer stack is shown epitaxially grown on substrate 1310. The semiconductor layer stack may be grown using, for example, MOCVD, VPE, LPE, or MBE techniques, and may include, for example, n + doped GaN layer 1320, n-doped GaN layer 1330, p-doped GaN layer 1340 + doped GaN layer 1340, channel layer 1350, and barrier layer 1352. In some examples, the semiconductor layer stack may also include p + An electrical isolation layer between the doped GaN layer 1340 and the channel layer 1350. A vertical GaN-based diode can be made of p + The p-type dopant used to dope the GaN layer may include, for example, Mg, Ca, Zn, or Be. The n-type dopant used to dope the GaN layer may include, for example, Si or Ge. The dopant may be incorporated into the GaN layer and activated during epitaxial growth, so ion implantation may not be required to form the doped GaN layer. The n-doped GaN layer 1330 and the p-doped GaN layer 1340 may be tunable. + The doping density, doping profile and / or thickness of the doped GaN layer 1340 are determined to achieve a desired avalanche breakdown voltage of the vertical GaN-based diode. The channel layer 1350 may include, for example, an undoped GaN layer. The barrier layer 1352 may include, for example, an AlGaN layer. In some examples, one or more buffer layers may be grown on the substrate 1310 before growing the semiconductor layer stack.

[0130] like Fig. 14C As shown in , the gate structure 1360, source structure 1362, and drain structure 1364 of the HEMT may be formed on and / or in the semiconductor layer stack. As described above, in some examples, the gate structure 1360 may include a p-doped semiconductor layer (e.g., a p-GaN layer) formed on the barrier layer 1352 and a gate electrical contact formed on the p-doped semiconductor layer, so that the HEMT may be an enhancement-mode HEMT. In some examples, the gate structure 1360 may include a gate electrical contact (metal electrode) formed above the barrier layer 1352, and the HEMT may be a depletion-mode HEMT. The source structure 1362 and the drain structure 1364 may be formed on and / or in the semiconductor layer stack, and may be electrically coupled to the channel layer 1350 of the HEMT through physical contact or tunneling. As described above, the gate structure 1360, the source structure 1362, and the drain structure 1364 may include, for example, Cu, W, Au, Al, Ti, Ni, Pt, metal alloys, or combinations thereof.

[0131] Fig.14D At least one source deep contact 1363 may be formed to electrically couple the source structure 1362 to the anode of a vertical GaN-based diode (eg, p + The source deep contact 1363 may extend through the barrier layer 1352 and the channel layer 1350 to contact the p + The doped GaN layer 1340 forms a low resistance metal-semiconductor contact. At least one drain deep contact 1365 may be formed to pass through the n + The doped GaN layer 1320 electrically couples the drain structure 1364 to the cathode of the vertical GaN-based diode (eg, the n-doped GaN layer 1330). The drain deep contact 1365 may extend through the barrier layer 1352, the channel layer 1350, the p-type GaN layer 1330, and the p-type GaN layer 1330. + The doped GaN layer 1340 and the n-doped GaN layer 1330 are connected to the n-doped GaN layer 1340. + The doped GaN layer 1320 forms a low resistance metal-semiconductor contact. An isolation layer 1366 may be formed in the semiconductor layer stack to separate the drain deep contact 1365 from at least the p + The doped GaN layer 1340 is electrically isolated. In one example, the semiconductor layer stack can be etched at the drain region to form one or more trenches, a dielectric material can be deposited to fill the one or more trenches, the dielectric material in the central region of each trench can be removed to form a hole surrounded by the isolation layer 1366, and a metal material can be deposited into the hole to form a drain deep contact 1365 surrounded by the isolation layer 1366.

[0132] Although the examples described above include silicon or GaN-based pn junction diodes monolithically integrated with the HEMT, other avalanche diodes may also be monolithically integrated with the HEMT to provide avalanche capability. For example, the avalanche diode may be a silicon Schottky diode, a GaN-based Schottky diode, a SiC-based pn junction diode, a SiC Schottky diode, or another diode formed using another semiconductor material and / or a metal material.

[0133] Fig.15 1 is a cross-sectional view of an example of a semiconductor device 1500 including a HEMT and a diode on the same semiconductor die. In the illustrated example, the semiconductor device 1500 includes a substrate 1510, which may include silicon, GaN, SiC, or another semiconductor material. The substrate 1510 may be lightly doped with a p-type dopant. + The doped region 1512 may be formed at a region of the substrate 1510 by, for example, p-type ion implantation and dopant activation. The semiconductor layer stack 1520 may be formed on the substrate 1510 by, for example, epitaxial growth. The semiconductor layer stack 1520 may include at least a channel layer and a barrier layer that may form a heterostructure with a 2DEG channel at the interface of the heterostructure. For example, the channel layer may include GaN and the barrier layer may include AlGaN. A gate structure 1530, a source structure 1532, and a drain structure 1534 may then be formed on or in the semiconductor layer stack 1520 to form a HEMT including a channel layer and a barrier layer. The gate electrical contacts of the gate structure 1530, the source structure 1532, and the drain structure 1534 may include, for example, Cu, W, Au, Al, Ti, Ni, Pt, a metal alloy, or a combination thereof.

[0134] In some examples, the gate structure 1530 may include a gate electrical contact (metal electrode) above the barrier layer, and the HEMT may be a depletion-mode high electron mobility transistor. In some examples, the gate structure 1530 may include a p-doped semiconductor layer (e.g., a p-GaN layer) formed on the barrier layer and a gate electrical contact formed on the p-doped semiconductor layer, and the HEMT may be an enhancement-mode high electron mobility transistor.

[0135] The source structure 1532 may be formed on and / or in the semiconductor layer stack 1520 and may be electrically coupled to the channel layer of the HEMT through physical contact or tunneling. The source structure 1532 may include or may be electrically coupled to at least one source deep contact formed at one or more regions of the semiconductor device 1500 and extending through the semiconductor layer stack 1520 to contact the p-type semiconductor device 1500. + The doped region 1512 forms a low resistance contact. Therefore, the source structure 1532 can be connected to the source electrode through at least one deep source contact and p +The doped region 1512 is electrically coupled to the p-doped substrate 1510 so that the resistance between the source structure 1532 and the substrate 1510 can be small.

[0136] A drain structure 1534 may also be formed on and / or in the semiconductor layer stack 1520 and may be electrically coupled to the channel layer of the HEMT by physical contact or by a tunneling effect. The drain structure 1534 may include or may be electrically coupled to at least one drain deep contact formed at one or more regions of the semiconductor device 1500 and extending through the semiconductor layer stack 1520 to contact the p-doped substrate 1510. The drain deep contact and the p-doped substrate 1510 may form a Schottky diode 1502. The drain deep contact may be isolated from the semiconductor layer stack 1520 by an isolation layer 1536, which may include, for example, a dielectric material such as silicon dioxide, silicon nitride, aluminum oxide, etc.

[0137] Fig.16 Contains graphs illustrating simulation results of the breakdown of different GaN-based transistors. Fig.16 16 is a current-voltage (IV) curve of a silicon avalanche diode including a p-doped silicon layer having a thickness of about 10 μm. Due to the thin p-doped silicon layer, the silicon avalanche diode may have a low avalanche breakdown voltage. The avalanche breakdown voltage of the silicon avalanche diode may be changed by, for example, changing the doping density (and therefore the length of the depletion region) and / or the thickness of the lightly doped semiconductor layer. For example, when the thickness of the p-doped silicon layer of the silicon avalanche diode is about 200 μm, the avalanche breakdown voltage of the silicon avalanche diode may be increased to between about 600 V and 700 V, as shown by IV curve 1620.

[0138] Fig.16 Also shown is an IV curve 1630 of a GaN HEMT without an integrated avalanche diode when the GaN HEMT is turned off. The GaN HEMT may have a high breakdown voltage. As shown by IV curve 1640, when a silicon avalanche diode having a p-doped silicon layer having a thickness of about 200 μm is integrated with the GaN HEMT, the breakdown voltage of the integrated device may be similar to the avalanche breakdown voltage of a standalone silicon avalanche diode shown by IV curve 1620, for example, between about 600 V and 700 V. Thus, the avalanche diode may provide an avalanche breakdown capability to the integrated device.

[0139] Fig.17A schematic diagram 1700 is included that illustrates an example of the operation of a GaN-based transistor 1710 including an integrated diode 1720 under unclamped inductive switching conditions. Schematic diagram 1700 shows a signal source 1740 driving the gate of the GaN-based transistor 1710 through a resistor 1750. The drain of the GaN-based transistor 1710 can be coupled to a voltage source through an inductor 1730. The source of the GaN-based transistor 1710 can be connected to ground. The anode of the diode 1720 can be coupled to the source of the GaN-based transistor 1710, and the cathode of the diode 1720 can be coupled to the drain of the GaN-based transistor 1710. The supply voltage of the voltage source is labeled VDD. The current between the drain terminal and the source terminal of the GaN-based transistor 1710 (including the current flowing through the GaN-based transistor 1710 and the current flowing through the diode 1720) is labeled ID. The voltage level at the drain of the GaN-based transistor 1710 is labeled VD. The voltage level at the gate of the GaN-based transistor 1710 is labeled VG.

[0140] Fig.18A and 18B Description During switching operation Fig.17 Schematic diagram 1700 shows the simulation results of the circuit. Fig.18A The simulated VD and VG are shown on a linear scale, while Fig.18B The simulated VD and VG are shown on a logarithmic scale. In the illustrated example, the GaN-based transistor 1710 can be turned off from an on state, and the supply voltage VDD of the voltage source can be about 300V, as shown by curve 1810. Curve 1840 shows the switching of the voltage level VG from about 10V to 0V to turn off the GaN-based transistor 1710. Curve 1820 shows the change in current ID during switching when the circuit does not include diode 1720, while curve 1822 shows the change in current ID during switching when the circuit includes diode 1720.

[0141] Curve 1830 shows the change in voltage level VD during switching when the circuit does not include diode 1720, while curve 1832 shows the change in voltage level VD during switching when the circuit includes diode 1720. Curves 1830 and 1832 show that with diode 1720, the change in voltage level VD (dVD / dt) can be slower, and voltage level VD can be clamped at the breakdown voltage of diode 1720 (e.g., between about 600V and 700V). Curves 1820 and 1822 and curves 1830 and 1832 on a logarithmic scale also show that with diode 1720, VD can be lower at any given time during switching, and therefore the channel resistance R of GaN-based transistor 1710 is lower. DSON Can be lower.

[0142] Fig.191900 is included, which illustrates an example of a process for fabricating a semiconductor device including a HEMT and a diode on the same semiconductor die. Note that Fig.19 The operations described in provide specific processes for manufacturing some examples of semiconductor devices with integrated avalanche diodes disclosed herein according to specific examples. According to alternative examples, other sequences of operations may also be performed to manufacture semiconductor devices. For example, alternative examples may perform operations in different orders. In addition, Fig.19 Each operation described in the foregoing may include multiple sub-steps that may be performed in various sequences suitable for the individual operations. In addition, some operations may be added or removed depending on the specific instance. In some embodiments, two or more operations may be performed in parallel. Those of ordinary skill in the art will recognize many variations, modifications, and alternatives.

[0143] The optional operation at block 1905 of flowchart 1900 may include forming a diode on or in a substrate. In some examples, the substrate may include a semiconductor substrate, such as a silicon, GaN, engineered GaN, or SiC substrate, and the diode may be formed in the substrate by ion implantation into the substrate. In one example, Figures 3A to 4B As shown in FIG. 1 , a diode can be formed in a substrate by forming a first doped (eg, n + The first doped semiconductor layer and the second doped semiconductor layer may be formed in the substrate by, for example, ion implantation and dopant activation. In another example, the substrate (or substrate layer) may be p- or n-doped, and regions of the substrate may be oppositely doped to form a diode with other regions of the substrate, such as in, for example, Figures 5A to 6B In some examples, a region of the lightly doped semiconductor layer of the diode can be heavily doped with the same type of dopant to provide a low resistance contact with the lightly doped semiconductor layer.

[0144] In some examples, the substrate may or may not be a semiconductor substrate, and the diode may be formed on the substrate by growing one or more semiconductor layers on the substrate. For example, the substrate may be p- or n-doped, and the diode may be formed by forming (e.g., epitaxially growing) an oppositely doped semiconductor layer on the substrate, wherein the oppositely doped semiconductor layer and the substrate may form a diode, such as, for example Figures 7A to 8B In another example, the substrate may be doped or undoped, and the diode may be formed by forming (e.g., epitaxially growing) a doped semiconductor layer on the substrate and forming an oppositely doped region in the doped semiconductor layer, wherein the oppositely doped region and the doped semiconductor layer may form a diode, such as Figures 9A to 10CIn some examples, a region of the lightly doped semiconductor layer of the diode can be heavily doped with the same type of dopant to provide a low resistance contact with the lightly doped semiconductor layer.

[0145] The operation at block 1910 may include forming a semiconductor layer stack on a substrate. The semiconductor layer stack may include at least a non-silicon channel layer and a barrier layer on the channel layer. In some examples, the substrate may include a diode formed thereon or therein, as described above with respect to, for example, block 1905. In some examples, the semiconductor layer stack may include a diode formed therein. In one example, the semiconductor layer stack may include a p-type semiconductor layer formed (e.g., epitaxially grown) above the substrate and an n-type semiconductor layer formed (e.g., epitaxially grown) on the p-type semiconductor layer. + Type semiconductor layer, where n + In another example, the semiconductor layer stack may include an n-type semiconductor layer formed (e.g., epitaxially grown) above the substrate and a p-type semiconductor layer formed (e.g., epitaxially grown) on the n-type semiconductor layer. + Type semiconductor layer, where p + The n-type semiconductor layer and the n-type semiconductor layer may form a vertical diode.

[0146] The operation at block 1920 may include forming a gate on a side of the barrier layer opposite the channel layer. In some examples, the gate may include a gate electrical contact (metal electrode) over the barrier layer to form a depletion-mode high electron mobility transistor. In some examples, the gate may include a p-doped semiconductor layer (e.g., a p-GaN layer) formed on the barrier layer and a gate electrical contact formed on the p-doped semiconductor layer to form an enhancement-mode high electron mobility transistor.

[0147] The operation at block 1930 may include forming a source on and / or in the semiconductor layer stack, wherein the source may be electrically coupled to a first terminal (e.g., an anode) of the diode. The source may be electrically coupled to the channel layer by physical contact or tunneling. The source may include or may be electrically coupled to at least one source deep contact formed at one or more regions of the semiconductor device and extending in the semiconductor layer stack to contact the first terminal (e.g., an anode) of the diode, such as a p-doped or p-doped semiconductor layer. + Doping a semiconductor layer or semiconductor region. In some examples, an isolation layer can surround the source deep contact to isolate the source deep contact.

[0148] The operations at block 1940 may include forming a drain on and / or in the semiconductor layer stack, wherein the drain may be electrically coupled to a second terminal (e.g., cathode) of the diode. The drain may be electrically coupled to the channel layer by physical contact or tunneling. The drain may include or may be electrically coupled to at least one drain deep contact formed at one or more regions of the semiconductor device and extending in the semiconductor layer stack to contact the second terminal (e.g., cathode) of the diode, such as an n-doped or n-doped semiconductor layer. + doping the semiconductor layer or semiconductor region. In some examples, an isolation layer may surround the drain deep contact to isolate the drain deep contact.

[0149] In this specification, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A through the control signal generated by device A.

[0150] Additionally, in this specification, the statement “based on” means “based, at least in part, on.” Thus, if X is based on Y, then X may depend on Y and any number of other factors.

[0151] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0152] As used herein, the terms "terminal", "node", "interconnection", "pin" and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to the interconnection between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components or their ends.

[0153] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party.

[0154] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used instead with little or no change to the rest of the circuitry. For example, field effect transistors ("FETs") (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs—e.g., NPN transistors or PNP transistors), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in conjunction with the devices described herein. The transistors may be depletion mode devices, drain extension devices, enhancement mode devices, native transistors, or other types of device structure transistors. Furthermore, the devices may be implemented in / on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0155] In the claims reference may be made to the control input of a transistor and its current terminals. In the context of a FET, the control input is the gate, and the current terminals are the drain and source. In the context of a BJT, the control input is the base, and the current terminals are the collector and emitter.

[0156] Reference herein to a FET being "on" or "enabled" means that there is a conductive channel of the FET and drain current can flow through the FET. Reference herein to a FET being "off" or "disabled" means that there is no conductive channel, so drain current does not flow through the FET. However, an "off" FET can have current flowing through the body diode of the transistor.

[0157] The circuits described herein may be reconfigured to include additional components or different components to provide functionality at least partially similar to functionality available prior to component replacement. Unless otherwise specified, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described herein as a single component may alternatively be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively.

[0158] Although certain elements of the described examples are included in the integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features shown as external to the integrated circuit may be included in the integrated circuit, and / or some features shown as internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated in the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0159] Use of the phrase "ground" in the foregoing description includes chassis ground, ground line ground, floating ground, virtual ground, digital ground, universal ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification.

[0160] In this specification, unless otherwise specified, "about", "approximately" or "substantially" preceding a parameter means within + / -10% of the parameter, or if the parameter is zero, it means within a reasonable value range of about zero.

[0161] As used herein, the terms "and" and "or" may include various meanings, which are also expected to depend at least in part on the context in which such terms are used. Generally, "or", if used in association with a list such as A, B, or C, is intended to mean A, B, and C (here used in an inclusive sense), as well as A, B, or C (here used in an exclusive sense). In addition, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in a singular form, or may be used to describe a certain combination of features, structures, or characteristics. However, it should be noted that this is merely an illustrative example, and the claimed subject matter is not limited to this example. In addition, the term "at least one of", if used in association with a list such as A, B, or C, may be interpreted as meaning A, B, C, or a combination of A, B, and / or C, for example, AB, AC, BC, AA, ABC, AAB, ACC, AABBCCC, etc.

[0162] Although various examples have been described in detail, it should be understood that various changes, substitutions and modifications may be made to them without departing from the scope defined by the appended claims. The devices, structures, materials and processes discussed above are examples. Various examples may omit, replace or add various programs or components when appropriate. Moreover, the features described with respect to a specific example may be combined in various other examples. Different aspects and elements of the examples may be combined in a similar manner. Moreover, technology evolves, so many elements are examples, which do not limit the scope of the present disclosure to those specific examples.

[0163] Specific details are given in the description to provide a thorough understanding of the examples. However, examples can be practiced without these specific details. For example, well-known circuits, processes, systems, structures and techniques can be shown without unnecessary details to avoid confusing the examples. This description only provides examples and is not intended to limit the scope, applicability or configuration of the present invention. On the contrary, the previous description of the examples will provide a stimulating description for implementing various examples for those skilled in the art. Various changes can be made to the functions and configurations of the elements without departing from the spirit and scope of the present disclosure. Within the scope of the claims, modifications are possible in the described examples, and other examples are possible.

Claims

1. A semiconductor device comprising: substrate; A semiconductor layer stack on the substrate, the semiconductor layer stack comprising: Non-silicon channel layer; as well as a barrier layer on the channel layer; as well as a gate, a source and a drain formed on or in the semiconductor layer stack, Wherein at least one of the substrate or the semiconductor layer stack includes a diode, a first terminal of the diode electrically coupled to the source, and a second terminal of the diode electrically coupled to the drain.

2. The semiconductor device according to claim 1, wherein: The substrate comprises at least one of silicon, silicon carbide, silicon-on-insulator (SOI), sapphire, gallium nitride (GaN), engineered GaN, or another semiconductor material having a bandgap wider than that of silicon; and The channel layer includes at least one of GaN, AlGaN, or InAlN. The semiconductor device according to claim 1 , wherein the diode is formed in the substrate.

4. The semiconductor device according to claim 3, wherein the substrate comprises a p-type semiconductor layer and an n-type semiconductor layer forming the diode in the substrate. + type semiconductor layer, wherein the n + The p-type semiconductor layer is on a side of the p-type semiconductor layer opposite to the channel layer.

5. The semiconductor device according to claim 4, wherein: The source includes a p-type semiconductor layer electrically coupled to a + The source contact of the type region; The drain includes a terminal electrically coupled to the n + A drain contact of a semiconductor layer; as well as The semiconductor device further includes an isolation layer laterally between the drain contact and the p-type semiconductor layer and the semiconductor layer stack.

6. The semiconductor device according to claim 3, wherein: The substrate includes a p-type semiconductor layer, wherein the p-type semiconductor layer includes a p + Type area and n + type region, the p-type semiconductor layer and the n + The diode is formed in the region; The source includes a terminal electrically coupled to the p + A source contact of the type region; and The drain includes a terminal electrically coupled to the n + The drain contact of the type region. 7 . The semiconductor device according to claim 3 , wherein the substrate includes an n-type semiconductor layer and a p-type semiconductor layer, the p-type semiconductor layer being on a side of the n-type semiconductor layer opposite to the channel layer. 8 . The semiconductor device according to claim 7 , wherein the n-type semiconductor layer is an epitaxial layer grown on the p-type semiconductor layer. 9 . The semiconductor device according to claim 7 , wherein the n-type semiconductor layer has a lower doping density than the p-type semiconductor layer.

10. The semiconductor device according to claim 7, wherein: The source includes a source contact electrically coupled to the p-type semiconductor layer; The drain electrode includes an n-type semiconductor layer electrically coupled to the n-type semiconductor layer. + A drain contact to the type region; and The semiconductor device further includes an isolation layer laterally between the source contact and the n-type semiconductor layer and the semiconductor layer stack.

11. The semiconductor device according to claim 7, wherein: The n-type semiconductor layer includes a p + Type area and n + Type area; The source includes a terminal electrically coupled to the p + A source contact of the type region; and The drain includes a terminal electrically coupled to the n + The drain contact of the type region.

12. The semiconductor device according to claim 1, wherein: The semiconductor layer stack includes a p-type semiconductor layer and an n-type semiconductor layer. + type semiconductor layer, the n + The p-type semiconductor layer and the p-type semiconductor layer form the diode.

13. The semiconductor device according to claim 12, wherein the semiconductor layer stack further comprises a + Conductive shielding structure between type semiconductor layers.

14. The semiconductor device according to claim 12, wherein: The source includes a source contact electrically coupled to the p-type semiconductor layer; The drain includes a terminal electrically coupled to the n + A drain contact of a semiconductor layer; as well as The semiconductor device further includes an isolation layer, the isolation layer laterally extending between the source contact and the n + type semiconductor layers.

15. The semiconductor device according to claim 1, wherein: The semiconductor layer stack includes an n-type semiconductor layer and a p-type semiconductor layer. + type semiconductor layer, the p + The n-type semiconductor layer and the n-type semiconductor layer form the diode.

16. The semiconductor device according to claim 15, wherein: The source includes a terminal electrically coupled to the p + A source contact of a semiconductor layer; The drain includes a drain contact electrically coupled to the n-type semiconductor layer; and The semiconductor device further includes an isolation layer laterally extending between the drain contact and the p + type semiconductor layers.

17. The semiconductor device of claim 1, wherein the diode comprises a Schottky diode.

18. A method comprising: forming a semiconductor layer stack on a substrate, the semiconductor layer stack comprising a non-silicon channel layer and a barrier layer in the channel layer, wherein at least one of the substrate or the semiconductor layer stack comprises a diode; forming a gate on a side of the barrier layer opposite to the channel layer; forming a source electrode on or in the semiconductor layer stack, the source electrode being electrically coupled to a first terminal of the diode; as well as A drain is formed on or in the semiconductor layer stack, the drain being electrically coupled to a second terminal of the diode.

19. The method according to claim 18, wherein: The substrate comprises at least one of silicon, silicon carbide, silicon-on-insulator (SOI), sapphire, gallium nitride (GaN), engineered GaN, or another semiconductor material having a bandgap wider than that of silicon; and The channel layer includes at least one of GaN, AlGaN, or InAlN.

20. The method of claim 18, further comprising, before forming the semiconductor layer stack on the substrate: In the layer of the substrate, n + Type semiconductor layer; In the n + forming a p-type semiconductor layer on the substrate to form the diode; and In the p-type semiconductor layer, a p + Type area, wherein forming the drain on or in the semiconductor layer stack comprises forming a drain electrode electrically coupled to the n + The drain contact of the semiconductor layer is Wherein forming the source on or in the semiconductor layer stack includes forming a source electrode electrically coupled to the p + type region of the source contact, and The method further includes forming an isolation layer to electrically isolate the drain contact from the p-type semiconductor layer.

21. The method of claim 18, further comprising, before forming the semiconductor layer stack on the substrate: A p-doped semiconductor layer is formed in the p-doped semiconductor layer of the substrate. + Type area and n + Type area, the n + The p-type region and the p-doped semiconductor layer form the diode in the substrate, Wherein forming the source on or in the semiconductor layer stack includes forming a source electrode electrically coupled to the p + type region of the source contact, and wherein forming the drain on or in the semiconductor layer stack comprises forming a drain electrode electrically coupled to the n + The drain contact of the type region.

22. The method of claim 18, further comprising, before forming the semiconductor layer stack on the substrate: In the substrate p + An n-type semiconductor layer is formed on the p-type semiconductor layer, wherein the n-type semiconductor layer and the p-type semiconductor layer + type semiconductor layer to form the diode in the substrate; and In the n-type semiconductor layer, an n + Type area, wherein forming the drain on or in the semiconductor layer stack comprises forming a drain electrode electrically coupled to the n + Type area of ​​the drain contact, Wherein forming the source on or in the semiconductor layer stack includes forming a source electrode electrically coupled to the p + type semiconductor layer source contact, and The method further includes forming an isolation layer to electrically isolate the source contact from the n-type semiconductor layer.

23. The method of claim 18, further comprising, before forming the semiconductor layer stack on the substrate: forming an n-type semiconductor layer on the substrate; and A p-type semiconductor layer is formed in the n-type semiconductor layer. + Type area and n + Type region, the p + The n-type region and the n-type semiconductor layer form the diode in the substrate, Wherein forming the source on or in the semiconductor layer stack includes forming a source electrode electrically coupled to the p + type region of the source contact, and wherein forming the drain on or in the semiconductor layer stack comprises forming a drain electrode electrically coupled to the n + The drain contact of the type region.

24. The method of claim 18, wherein forming the semiconductor layer stack on the substrate comprises: forming a p-type semiconductor layer above the substrate; as well as An n type semiconductor layer is formed on the p type semiconductor layer. + type semiconductor layer, the n + type semiconductor layer and the p-type semiconductor layer form the diode, wherein forming the source on or in the semiconductor layer stack comprises forming a source contact electrically coupled to the p-type semiconductor layer, wherein forming the drain on or in the semiconductor layer stack comprises forming a drain electrode electrically coupled to the n + type semiconductor layer drain contact, and The method further comprises forming a source contact and a n + The isolation layer is electrically isolated from the semiconductor layer.

25. The method of claim 18, wherein forming the semiconductor layer stack on the substrate comprises: forming an n-type semiconductor layer above the substrate; as well as A p-type semiconductor layer is formed on the n-type semiconductor layer. + type semiconductor layer, the p + The n-type semiconductor layer and the n-type semiconductor layer form the diode, Wherein forming the source on or in the semiconductor layer stack includes forming a source electrode electrically coupled to the p + Type semiconductor layer source contact, wherein forming the drain on or in the semiconductor layer stack comprises forming a drain contact electrically coupled to the n-type semiconductor layer, and The method further comprises forming a drain contact and a p + The isolation layer is electrically isolated from the semiconductor layer.

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