Gapped source / drain structure of semiconductor device

Abstract

The invention relates to a void source / drain structure of a semiconductor device. The present disclosure describes a semiconductor device having a source / drain (S / D) structure with a void. The semiconductor device includes a semiconductor layer stack on a substrate, a gate structure surrounding the semiconductor layer stack, and an S / D structure on the substrate and in contact with the semiconductor layer stack. The S / D structure includes a void below a top surface of the S / D structure.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor devices, and more particularly to a source / drain structure with a gap of a semiconductor device. Background Art

[0002] As semiconductor technology advances, there is an increasing demand for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to shrink the size of semiconductor devices, such as metal oxide semiconductor field effect transistors (MOSFETs), including planar MOSFETs and fin field effect transistors (FinFETs). This scaling down increases the complexity of semiconductor manufacturing processes and increases the difficulty of process control in semiconductor devices. Summary of the invention

[0003] According to one embodiment of the present disclosure, a semiconductor device is provided, comprising: a semiconductor layer stack on a substrate; a gate structure surrounding the semiconductor layer stack; and a source / drain (S / D) structure on the substrate and in contact with the semiconductor layer stack, wherein the S / D structure comprises a gap below a top surface of the S / D structure.

[0004] According to one embodiment of the present disclosure, a semiconductor device is provided, including: a first semiconductor layer stack and a second semiconductor layer stack on a substrate; a first gate structure surrounding the first semiconductor layer stack; a second gate structure surrounding the second semiconductor layer stack; and a source / drain (S / D) structure between the first semiconductor layer stack and the second semiconductor layer stack, wherein the S / D structure includes a gap below the top surface of the S / D structure.

[0005] According to one embodiment of the present disclosure, a method for forming a semiconductor device is provided, comprising: forming a semiconductor layer stack on a substrate; depositing a source / drain (S / D) structure, the S / D structure being on the substrate and in contact with the semiconductor layer stack, wherein the S / D structure includes a gap below a top surface of the S / D structure; and forming a gate structure surrounding the semiconductor layer stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures.

[0007] Figure 1 An isometric view of a semiconductor device having a source / drain structure with a void is shown in accordance with some embodiments.

[0008] Figures 2 to 4A partial cross-sectional view of a semiconductor device having a source / drain structure with a void is shown in accordance with some embodiments.

[0009] Figure 5 is a flow chart of a method for fabricating a semiconductor device having a source / drain structure with a void according to some embodiments.

[0010] Figures 6 to 17 Partial cross-sectional views of a semiconductor device having a source / drain structure with voids at various stages of its fabrication are shown in accordance with some embodiments.

[0011] Illustrative embodiments will now be described with reference to the drawings.In the drawings, like reference numbers generally indicate identical, functionally similar, and / or structurally similar elements. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are just examples and are not intended to be limiting. For example, in the following description, forming a first feature on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. As used herein, forming a first feature on a second feature means that the first feature and the second feature are formed in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition itself does not indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Additionally, spatially relative terms (e.g., "below," "below," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in a figure relative to another element(s) or feature(s). These spatially relative terms are also intended to encompass different orientations of the device in use or operation in addition to the orientation illustrated in the figures. The device may be oriented in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0014] It should be noted that references in the specification to "one embodiment," "an embodiment," "an example embodiment," "exemplary," etc. indicate that the described embodiment may include a particular feature, structure, or characteristic, but not every embodiment may include the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of those skilled in the art to implement such feature, structure, or characteristic in conjunction with other embodiments.

[0015] It should be understood that the phraseology or terminology herein is for the purpose of description rather than limitation, so that the phraseology or terminology of the specification is interpreted by persons skilled in the relevant art(s) based on the teachings herein.

[0016] In some embodiments, the terms "about" and "substantially" may indicate that the value of a given amount varies within 20% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±20% of the value). These values ​​are examples only and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of a value as interpreted by one or more persons skilled in the relevant art(s) in accordance with the teachings herein.

[0017] With the increase of demand for lower power consumption, higher performance and smaller semiconductor devices, the size of semiconductor devices is constantly scaled down. The continuous scaling down of device size and the growing demand for device performance may require various process and material improvements, which may have multiple challenges. For example, a nanostructure transistor may have a gate structure that surrounds a channel structure to improve device performance. A nanostructure transistor may have an internal spacer to isolate the gate structure from a source / drain (S / D) structure. However, the parasitic capacitance of the S / D structure may limit the device performance of a nanostructure transistor.

[0018] Various embodiments in the present disclosure provide methods for forming a S / D structure with a gap in a semiconductor device (e.g., a nanostructure transistor) in an integrated circuit (IC) and / or other semiconductor devices. In some embodiments, the semiconductor device may include a semiconductor layer stack on a substrate. The gate structure may surround the semiconductor layer stack. The S / D structure may be formed on the substrate and in contact with the semiconductor layer stack. The S / D structure may include a gap below the top surface of the S / D structure. In some embodiments, a first ratio of the horizontal dimension of the gap to the width of the S / D structure may be in a range from about 0.1 to about 0.8, and a second ratio of the vertical dimension of the gap to the height of the S / D structure may be in a range from about 0.05 to about 0.8. By utilizing the gap in the S / D structure, the parasitic capacitance of the S / D structure may be reduced, and the device performance of the semiconductor device may be improved.

[0019] Figure 1 An isometric view of a semiconductor device 100 having an S / D structure with a void is shown in accordance with some embodiments. Figures 2 to 4 shows a cross-sectional view according to some embodiments Figure 1 FIG. 1 is a partial cross-sectional view of the semiconductor device 100 along line AA as shown. In some embodiments, Figures 2 to 4 Various embodiments of epitaxial structures with one or more gaps are shown. In some embodiments, semiconductor device 100 may include transistors 102A to 102C, such as Figure 1 As shown. In some embodiments, transistors 102A to 102C may include nanostructure transistors. Nanostructure transistors may include FinFETs, gate all-around field effect transistors (GAA FETs), nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nanoribbon transistors, and other transistors of similar structures. Nanostructure transistors may provide channels in a stacked nanosheet / nanowire configuration.

[0020] In some embodiments, transistors 102A to 102C may be n-type field effect transistors (NFETs). In some embodiments, transistors 102A to 102C may be p-type field effect transistors (PFETs). In some embodiments, any of transistors 102A to 102C may be an NFET or a PFET. Figure 1 Three transistors are shown, but semiconductor device 100 can have any number of transistors. In addition, semiconductor device 100 can be incorporated into an IC by using other structural components (e.g., conductive vias, wires, dielectric layers, passivation layers, and interconnects, which are not shown for simplicity). Unless otherwise noted, the discussion of elements of transistors 102A to 102C with the same annotations applies to each other. In addition, the same reference numerals generally represent the same, functionally similar, and / or structurally similar elements.

[0021] refer to Figures 1 to 4 , a semiconductor device 100 having transistors 102A to 102C may be formed on a substrate 104 and may be isolated by a shallow trench isolation (STI) region 106. Each of the transistors 102A to 102C may include a fin structure 108, a sidewall spacer 107, a gate structure 120, a gate spacer 114, an inner spacer 121, an S / D structure 110, an etch stop layer (ESL) 116, an interlayer dielectric (ILD) layer 118, and an S / D contact structure 130. In some embodiments, as Figures 2 to 4 As shown, transistors 102A- 102C may have nanostructures 122 - 1 , 122 - 2 , and 122 - 3 (collectively “nanostructures 122 ”) on fin structure 108 .

[0022] refer to Figures 1 to 4 , the substrate 104 may include a semiconductor material, such as silicon. In some embodiments, the substrate 104 includes a crystalline silicon substrate (e.g., a wafer). In some embodiments, the substrate 104 includes (i) an elemental semiconductor, such as germanium; (ii) a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; (iii) an alloy semiconductor, including silicon germanium carbide, silicon germanium, gallium arsenic phosphide, and / or aluminum gallium arsenide; or (iv) a combination of the foregoing. In addition, the substrate 104 may be doped, depending on the design requirements (e.g., a p-type substrate or an n-type substrate). In some embodiments, the substrate 104 may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic).

[0023] STI regions 106 can provide electrical isolation between transistors 102A to 102C, electrical isolation from adjacent transistors (not shown) on substrate 104, and / or adjacent active and passive components (not shown) integrated with substrate 104 or deposited on substrate 104. STI regions 106 can be made of dielectric materials. In some embodiments, STI regions 106 can include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric materials, and / or other suitable insulating materials. In some embodiments, STI regions 106 can include a multi-layer structure.

[0024] refer to Figures 1 to 5 , the nanostructure 122 and the fin structure 108 can be formed on the patterned portion of the substrate 104. The embodiments of the nanostructure and the fin structure disclosed herein can be patterned by any suitable method. For example, one or more photolithography processes can be used for patterning (including a double patterning process or a multi-patterning process) to obtain the nanostructure and the fin structure. The double patterning process or the multi-patterning process can combine the photolithography process and the self-alignment process to form a pattern with a smaller spacing than that obtainable using a single direct photolithography process, for example. For example, a sacrificial layer is formed on the substrate and patterned using a photolithography process. A self-alignment process can be used to form spacers along the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructure and the fin structure.

[0025] like Figures 1 to 4As shown, the nanostructure 122 and the fin structure 108 may extend along the X-axis for the transistors 102A to 102C. In some embodiments, the nanostructure 122 and the fin structure 108 may be disposed on the substrate 104. The nanostructure 122 may include a group of nanostructures 122-1, 122-2, and 122-3, which may be in the form of semiconductor layers, nanosheets, nanowires, or nanoribbons. Each nanostructure 122 may serve as a channel structure and form a channel region below the gate structure 120 of the transistors 102A to 102C. In some embodiments, the nanostructure 122 and the fin structure 108 may include a semiconductor material similar to or different from the substrate 104. In some embodiments, the nanostructure 122 and the fin structure 108 may include silicon. In some embodiments, the nanostructure 122 and the fin structure 108 may include silicon germanium. The semiconductor material of the nanostructure 122 and the fin structure 108 may be undoped or may be in-situ doped during the formation process thereof. In some embodiments, as Figures 2 to 4 As shown, the nanostructure 122 below the gate structure 120 may form a channel region of the semiconductor device 100 and represent a current-carrying channel structure of the semiconductor device 100. Figures 2 to 4 Three layers of nanostructures 122 are shown in FIG. 1 , but transistors 102A to 102C may have any number of nanostructures 122 .

[0026] refer to Figures 1 to 4 , the gate structure 120 may include a gate dielectric layer 124 and a gate electrode 112. In some embodiments, the gate dielectric layer 124 may be formed on the nanostructure 122, the fin structure 108, and the STI region 106. In some embodiments, the gate dielectric layer 124 may be a multilayer structure and may include an interface layer and a high-k dielectric layer. In some embodiments, the gate dielectric layer 124 may not include an interface layer, but include a high-k dielectric layer in direct contact with the nanostructure 122. In some embodiments, the interface layer may include silicon oxide formed by a deposition process or an oxidation process. In some embodiments, the interface layer may have a thickness ranging from about 0.1 nm to about 1.5 nm. In some embodiments, the high-k dielectric layer may include hafnium oxide, zirconium oxide, or other suitable high-k dielectric materials.

[0027] In some embodiments, Figures 1 to 4 As shown, the gate electrode 112 may be disposed on the gate dielectric layer 124. In some embodiments, the gate electrode 112 may include one or more work function metal layers and a metal filler. The one or more work function metal layers may include a work function metal to tune the threshold voltage (V t). In some embodiments, the gate electrodes 112 of the NFET and PFET devices may have the same work function metal. In some embodiments, the gate electrodes 112 of the NFET and PFET devices may have different work function metals. Figures 2 to 4 As shown, each nanostructure 122 may be surrounded by a gate structure 120, and thus, the gate structure 120 may be referred to as a "gate all around (GAA) structure", and the transistors 102A to 102C may also be referred to as "GAA FETs 102A to 102C". One or more work function metal layers may surround the nanostructure 122, and may include work function metal to tune the V of the transistors 102A to 102C. t In some embodiments, transistors 102A to 102C may include any number of work function metal layers for V t Tuning (e.g., ultra-low V t , Low V t , and standard V t ).

[0028] In some embodiments, the NFETs 102A to 102C may include an n-type work function metal layer. The n-type work function metal layer may include aluminum, titanium aluminum, titanium aluminum carbon, tantalum aluminum, tantalum aluminum carbon, tantalum silicon carbide, hafnium carbide, silicon, titanium nitride, titanium silicon nitride, or other suitable work function metals. In some embodiments, the PFETs 102A to 102C may include a p-type work function metal layer. The p-type work function metal layer may include titanium nitride, titanium silicon nitride, tantalum nitride, tungsten carbon nitride, tungsten, molybdenum, or other suitable work function metals. In some embodiments, the work function metal layer may include a single metal layer or a metal layer stack. The metal layer stack may include work function metals having work function values ​​that are equal to or different from each other. In some embodiments, the metal filler may include titanium, tantalum, aluminum, cobalt, tungsten, nickel, ruthenium, or other suitable conductive materials.

[0029] refer to Figures 1 to 4, the gate spacer 114 may be disposed on the sidewall of the gate structure 120, the sidewall spacer 107 may be disposed on the sidewall of the fin structure 108, and the internal spacer 121 may be disposed between the gate structure 120 and the S / D structure 110. The gate spacer 114, the sidewall spacer 107, and the internal spacer 121 may include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, low-k material, and combinations of the foregoing. In some embodiments, the gate spacer 114, the sidewall spacer 107, and the internal spacer 121 may include the same insulating material. In some embodiments, the gate spacer 114, the sidewall spacer 107, and the internal spacer 121 may include different insulating materials. The gate spacer 114, the sidewall spacer 107, and the internal spacer 121 may include a single layer or a stack of insulating layers. The gate spacers 114 , the sidewall spacers 107 , and the inner spacers 121 may have a low-k material having a dielectric constant less than about 3.9 (eg, about 3.5, about 3.0, or about 2.8).

[0030] The S / D structure 110 may be disposed on the fin structure 108 and in contact with the nanostructure 122. In some embodiments, the S / D structure 110 may be disposed between adjacent nanostructure 122 stacks and on opposite sides of the gate structure 120. The S / D structure 110 may be used as an S / D region of the transistors 102A to 102C. In some embodiments, the S / D structure 110 may have any geometric shape, such as a polygon, an ellipse, and a circle. In some embodiments, the S / D structure 110 may include an epitaxially grown semiconductor material, such as silicon (e.g., the same material as the substrate 104). In some embodiments, the epitaxially grown semiconductor material may include an epitaxially grown semiconductor material (e.g., silicon germanium) different from the material of the substrate 104, and stress is applied to the channel region under the gate structure 120. Since the lattice constant of such epitaxially grown semiconductor material is different from the material of the substrate 104, the channel region is strained to increase the carrier mobility in the channel region of the semiconductor device 100. The epitaxially grown semiconductor material may include: (i) semiconductor materials such as germanium and silicon; (ii) compound semiconductor materials such as gallium arsenide and aluminum gallium arsenide; or (iii) semiconductor alloys such as silicon germanium and gallium arsenide phosphide.

[0031] In some embodiments, the S / D structure 110 may include silicon and may be in-situ doped with n-type dopants (e.g., phosphorus and arsenic) during the epitaxial growth process. In some embodiments, the S / D structure 110 may include silicon, silicon germanium, germanium, or III-V materials (e.g., indium antimonide, gallium antimonide, or indium gallium antimonide), and may be in-situ doped with p-type dopants (e.g., boron, indium, and gallium) during the epitaxial growth process. In some embodiments, the S / D structure 110 may include one or more epitaxial layers, wherein each epitaxial layer may have a different composition. In some embodiments, the S / D structure 110 may have a width 110w along the X-axis in a range from about 20nm to about 40nm. In some embodiments, the S / D structure 110 may have a height 110h along the Z-axis in a range from about 50nm to about 100nm.

[0032] In some embodiments, Figures 2 to 4 As shown, S / D structure 110 may include one or more voids 111-1 and 111-2 (collectively referred to as "voids 111") below the top surface of S / D structure 110. In some embodiments, voids 111 may have any geometric shape, such as elliptical, circular, polygonal, conical, and irregular shapes. Figure 2 As shown, the S / D structure 110 may include a void 111 surrounded by the S / D structure 110. In some embodiments, the void 111 may not contact the nanostructure 122, the fin structure 108, or the internal spacer 121. In some embodiments, the void 111 may have a horizontal dimension 111w (e.g., width) in the range from about 2nm to about 20nm along the X-axis. In some embodiments, the void 111 may have a vertical dimension 111h (e.g., height) in the range from about 2nm to about 50nm along the Z-axis. In some embodiments, a first ratio of the horizontal dimension 111w to the width 110w of the S / D structure 110 may be in the range from about 0.1 to about 0.8. In some embodiments, a second ratio of the vertical dimension 111h to the height 110h of the S / D structure 110 may be in the range from about 0.05 to about 0.8. If the horizontal dimension 111w is less than about 2nm, the vertical dimension 111h is less than about 2nm, the first ratio is less than about 0.1, or the second ratio is less than about 0.05, the parasitic capacitance of the S / D structure 110 may not be reduced, and the device performance of the semiconductor device 100 may not be improved. If the horizontal dimension 111w is greater than about 20nm, the vertical dimension 111h is greater than about 50nm, the first ratio is greater than about 0.8, or the second ratio is greater than about 0.8, the resistance of the S / D structure 110 may increase, and the device performance of the semiconductor device 100 may be reduced. In some embodiments, as Figure 2As shown, a distance 111 d between the void 111 and the top surface of the fin structure 108 may be in a range from about 5 nm to about 20 nm.

[0033] In some embodiments, Figure 3 As shown, a dielectric layer 109 may be disposed on the fin structure 108 and the substrate 104, and an S / D structure 110 may be disposed on the dielectric layer 109. In some embodiments, the dielectric layer 109 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or other suitable dielectric materials. In some embodiments, the dielectric layer 109 may have a thickness 109t in a range from about 1 nm to about 15 nm. In some embodiments, the top surface of the dielectric layer 109 may be lower than the bottom surface of the bottom nanostructure 122-1 to avoid blocking the contact between the nanostructure 122 and the S / D structure 110. In some embodiments, the dielectric layer 109 may reduce the leakage current of the semiconductor device 100. If the thickness 109t is less than about 1 nm, the dielectric layer 109 may not be able to reduce the leakage current of the semiconductor device 100. In some embodiments, if the thickness 109 t is greater than about 15 nm, the dielectric layer 109 may block contact between the nanostructure 122 and the S / D structure 110 , and thus reduce driving current and degrade device performance of the semiconductor device 100 .

[0034] In some embodiments, the S / D structure may include a first void 111-1 surrounded by the S / D structure 110 and the dielectric layer 109 and a second void 111-2 surrounded by the S / D structure 110 through the dielectric layer 109. In some embodiments, the first void 111-1 and the second void 111-2 may be separated (e.g., as shown in FIG. Figure 3 In some embodiments, the first gap 111-1 and the second gap 111-2 may be merged into a single gap 111 at different locations (eg, as shown in FIG. 1 ). Fig.12 and Fig.13 As shown). In some embodiments, each of the voids 111-1 and 111-2 may have a horizontal dimension (e.g., width) in a range from about 2 nm to about 20 nm along the X-axis and a vertical dimension (e.g., height) in a range from about 2 nm to about 50 nm along the Z-axis. In some embodiments, a first ratio of the horizontal dimension to the width 110w of the S / D structure 110 may be in a range from about 0.1 to about 0.8, and a second ratio of the vertical dimension to the height 110h of the S / D structure 110 may be in a range from about 0.05 to about 0.8. These size ranges of the first void 111-1 and the second void 111-2 may reduce the parasitic capacitance of the S / D structure 110 and improve the device performance of the semiconductor device 100. In some embodiments, as Figure 3As shown, the horizontal dimension of the gap 111-1 may be greater than the horizontal dimension of the gap 111-2. The vertical dimension of the gap 111-1 may be smaller than the vertical dimension of the gap 111-2. Figure 3 As shown, void 111 - 1 may be below void 111 - 2 , and a top surface of void 111 - 2 may be lower than a bottom surface of top nanostructure 122 - 3 .

[0035] In some embodiments, Figure 4 As shown, the first S / D structure 110-1 may be disposed on the fin structure 108, the dielectric layer 113 may be disposed on the first S / D structure 110-1, and the second S / D structure 110-2 may be disposed on the dielectric layer 113. In some embodiments, the first S / D structure 110-1 and the second S / D structure 110-2 may include different types of dopants. For example, the first S / D structure 110-1 may include a p-type dopant and may be a p-type S / D structure. The second S / D structure 110-2 may include an n-type dopant and may be an n-type S / D structure. In some embodiments, the first S / D structure 110-1 may contact the bottom nanostructure 122-1 to form an S / D region of a first type nanostructure transistor (e.g., a p-type nanostructure transistor). In some embodiments, the second S / D structure 110-2 may contact the top nanostructure 122-3 to form an S / D region of a second type nanostructure transistor (e.g., an n-type nanostructure transistor) that is different from the first type.

[0036] In some embodiments, the dielectric layer 113 may be disposed between the first S / D structure 110-1 and the second S / D structure 110-2. In some embodiments, the dielectric layer 113 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or other suitable dielectric materials. In some embodiments, the dielectric layer 113 may isolate the second S / D structure 110-2 from the first S / D structure 110-1. In some embodiments, the dielectric layer 113 may have a thickness 113t in a range from about 1 nm to about 15 nm. In some embodiments, if the thickness 113t is less than about 1 nm, the dielectric layer 113 may not isolate the second S / D structure 110-2 from the first S / D structure 110-1. In some embodiments, if the thickness 113t is greater than about 15 nm, the size of the first S / D structure 110-1 and the second S / D structure 110-2 may be reduced, and thus the resistance of the S / D structures 110-1 and 110-2 may be increased, and the device performance of the semiconductor device 100 may be reduced.

[0037] In some embodiments, Figure 4As shown, the first S / D structure 110-1 may include a first void 111-1 surrounded by the first S / D structure 110-1. The second S / D structure 110-2 may include a second void 111-2 surrounded by the second S / D structure 110-2. In some embodiments, the first S / D structure 110-1 and the second S / D structure 110-2 may have a width 110w along the X-axis in a range from about 20nm to about 40nm. In some embodiments, the first S / D structure 110-1 may have a first height 110-1h along the Z-axis in a range from about 20nm to about 50nm. The second S / D structure 110-2 may have a second height 110-2h along the Z-axis in a range from about 20nm to about 50nm. In some embodiments, each of the voids 111-1 and 111-2 may have a horizontal dimension (e.g., width) in a range from about 2 nm to about 20 nm along the X-axis and a vertical dimension (e.g., height) in a range from about 2 nm to about 50 nm along the Z-axis. In some embodiments, a first ratio of the horizontal dimension to the width 110w of the S / D structures 110-1 and 110-2 may be in a range from about 0.1 to about 0.8, and a second ratio of the vertical dimension to the first height 110-1h or the second height 110-2h may be in a range from about 0.05 to about 0.8. These size ranges of the first void 111-1 and the second void 111-2 may reduce the parasitic capacitance of the first S / D structure 110-1 and the second S / D structure 110-2 and improve the device performance of the semiconductor device 100. Although Figures 2 to 4 One or two voids 111 in the S / D structure 110 are shown, but the S / D structure 110 may have any number of voids 111 .

[0038] refer to Figures 1 to 4 , the ESL 116 may be disposed on the STI region 106, the S / D structure 110, and the sidewalls of the gate spacer 114 and the sidewall spacer 107. The ESL 116 may be configured to protect the STI region 106, the S / D structure 110, and the gate structure 120 during the formation of the S / D contact structure 130 on the S / D structure 110. In some embodiments, the ESL 116 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, silicon boron nitride, silicon carbon boron nitride, or a combination of the foregoing.

[0039] ILD layer 118 may be disposed on ESL 116 over S / D structure 110 and STI region 106. ILD layer 118 may include a dielectric material deposited using a deposition method suitable for flowable dielectric materials. For example, flowable silicon oxide may be deposited using flowable chemical vapor deposition (FCVD). In some embodiments, the dielectric material may include silicon oxide.

[0040] In some embodiments, Figures 1 to 4 As shown, the semiconductor device 100 may further include an S / D contact structure 130. In some embodiments, the S / D contact structure 130 may be disposed on the S / D structure 110. In some embodiments, the S / D contact structure 130 may include a silicide layer and a metal contact (not shown). In some embodiments, the silicide layer may include a metal silicide and may provide a lower resistance interface between the metal contact and the S / D structure 110. Examples of metals for forming metal silicide include cobalt, titanium, and nickel. In some embodiments, the metal contact may include a conductive material such as tungsten, aluminum, and cobalt. In some embodiments, as Figures 1 to 4 As shown, the S / D contact structure 130 can extend through the ILD layer 118 and into the S / D structure 110. In some embodiments, the S / D contact structure 130 can extend below the top surface of the S / D structure 110 by a distance in a range from about 5 nm to about 20 nm. In some embodiments, a distance 130d along the Z-axis between the S / D contact structure 130 and the void 111 can be in a range from about 4 nm to about 20 nm. If the distance 130d is less than about 4 nm, the contact resistance between the S / D contact structure 130 and the S / D structure 110 may increase. If the distance 130d is greater than about 20 nm, the S / D contact structure 130 may not extend into the S / D structure 110, and the contact resistance between the S / D contact structure 130 and the S / D structure 110 may also increase. In some embodiments, as Figure 4 As shown, the second gap 111 - 2 may have a smaller size than the first gap 111 - 1 to satisfy the distance 130 d.

[0041] Figure 5 is a flow chart of a method 500 for fabricating a semiconductor device 100 having a S / D structure with a void, according to some embodiments. The method 500 may not be limited to nanostructured transistor devices, and may be applied to other devices that would benefit from a S / D structure with a void. Additional manufacturing operations may be performed between various operations of the method 500, and may be omitted solely for clarity and ease of description. Additional processes may be provided before, during, and / or after the method 500; one or more of these additional processes are briefly described herein. Furthermore, not all operations may be required to perform the disclosure provided herein. Additionally, some operations may be performed simultaneously or in conjunction with Figure 5 In some embodiments, one or more other operations may be performed in addition to or in place of the operations currently described.

[0042] For the purpose of illustration, reference will be made to Figures 6 to 17An example manufacturing process for manufacturing the semiconductor device 100 is shown to describe Figure 5 The operation shown. Figures 6 to 17 1 shows a partial cross-sectional view of a semiconductor device 100 having a S / D structure with a void at various stages of its manufacture according to some embodiments. In some embodiments, Figures 6 to 17 Shown along Figure 1 A partial cross-sectional view of the semiconductor device 100 along line AA is shown at various stages of its fabrication. Figures 6 to 17 With Figures 1 to 4 Elements with the same annotations are as described above.

[0043] refer to Figure 5 , method 500 begins at operation 510 and forms a semiconductor layer stack on a substrate. Figure 6 As shown, nanostructure 122 and nanostructures 621-1, 621-2, and 621-3 (collectively referred to as "nanostructure 621") stacked on fin structure 108 may be formed on substrate 104. In some embodiments, nanostructure 122 and nanostructure 621 may be stacked in an alternating configuration. In some embodiments, nanostructures 122 and 621 may be epitaxially grown on substrate 104 and subsequently patterned to form nanostructures 122 and 621. In some embodiments, nanostructures 122 and 621 may be in the form of semiconductor layers, nanosheets, nanowires, or nanobelts. In some embodiments, nanostructures 122 and 621 may include semiconductor materials similar to or different from substrate 104. In some embodiments, fin structure 108 may include the same semiconductor material as substrate 104. In some embodiments, nanostructures 122 and 621 may include different semiconductor materials. For example, nanostructure 122 may include silicon, while nanostructure 621 may include silicon germanium.

[0044] The embodiments of the fin structure 108 and the nanostructures 122 and 621 disclosed herein may be patterned by any suitable method. For example, the fin structure and the nanostructure may be patterned using one or more photolithography processes, including a double patterning process or a multi-patterning process. The double patterning process or the multi-patterning process may combine the photolithography process with the self-alignment process to form a pattern having, for example, a smaller pitch than that obtainable using a single direct photolithography process. For example, a sacrificial layer is formed on a substrate and patterned using a photolithography process. A self-alignment process may be used to form spacers along the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fin structure and the nanostructure.

[0045] like Figure 6As shown, after forming the nanostructures 122 and 621, an STI region 106 may be formed between adjacent stacks of the nanostructures 122 and 621, a sacrificial gate structure 620 may be formed on the nanostructures 122 and the STI region 106, a gate spacer 114 may be formed on the sidewalls of the sacrificial gate structure 620, a vertical recess of the nanostructures 122 and 621 may be formed, and an internal spacer 121 may be formed. In some embodiments, the sacrificial gate structure 620 may include polysilicon. The gate spacer 114 and the internal spacer 121 may include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, low-k material, and a combination of the foregoing. In some embodiments, the vertical recess of the nanostructures 122 and 621 may expose the fin structure 108 to ensure complete removal of the bottom nanostructure 621-1 on the fin structure 108. In some embodiments, the internal spacer 121 may be formed adjacent to the end of the nanostructure 122. In some embodiments, forming the internal spacers 121 may include laterally recessing the nanostructures 621, and depositing and trimming a spacer layer. For clarity, these processes are not described in detail.

[0046] refer to Figure 5 In operation 520, an S / D structure is deposited, the S / D structure being on the substrate and in contact with the semiconductor layer stack. The S / D structure may include a void below a top surface of the S / D structure. For example, Figures 7 to 9 As shown, the S / D structure 110 may be epitaxially grown on the fin structure 108 and the substrate 104. The S / D structure 110 may include a void 111 below the top surface of the S / D structure 110. The S / D structure 110 may be used as an S / D region of the transistors 102A to 102C. In some embodiments, the S / D structure 110 may have any geometric shape, such as a polygon, a cone, a rhombus, an ellipse, and a circle. In some embodiments, the S / D structure 110 may include an epitaxially grown semiconductor material, such as silicon (e.g., the same material as the substrate 104). In some embodiments, the S / D structure 110 may include an epitaxially grown semiconductor material (e.g., silicon germanium) different from the material of the substrate 104, and stress may be applied to the channel region below the gate structure 120.

[0047] In some embodiments, the S / D structure 110 may be epitaxially grown by the following processes: (i) chemical vapor deposition (CVD), such as low pressure CVD (LPCVD), atomic layer CVD (ALCVD), ultra-high vacuum CVD (UHVCVD), reduced pressure CVD (RPCVD), and other suitable CVD; (ii) molecular beam epitaxy (MBE) process; (iii) any suitable epitaxial process; or (iv) a combination of the foregoing. In some embodiments, the S / D structure 110 may be grown by an epitaxial deposition / local etching process, which may repeat the epitaxial deposition / local etching process multiple times. Such a repeated deposition / local etching process may be referred to as a cyclic deposition etching (CDE) process. The CDE process may reduce epitaxial defects formed during growth and may control the profile of the S / D structure 110. In some embodiments, the S / D structure 110 may be in-situ doped using n-type or p-type dopants during the epitaxial growth process.

[0048] In some embodiments, the S / D structure 110 may include silicon and may be in-situ doped with n-type dopants (e.g., phosphorus and arsenic) during the epitaxial growth process. In some embodiments, the S / D structure 110 may include silicon, silicon germanium, germanium, or III-V materials (e.g., indium antimonide, gallium antimonide, or indium gallium antimonide), and may be in-situ doped with p-type dopants (e.g., boron, indium, and gallium) during the epitaxial growth process. In some embodiments, the S / D structure 110 may include one or more epitaxial layers, wherein each epitaxial layer may have a different composition and / or a different dopant concentration.

[0049] In some embodiments, during the epitaxial growth process of the S / D structure 110, a cleaning gas such as hydrogen chloride can remove the epitaxial structure grown on the dielectric layer (e.g., the gate spacer 114 and the internal spacer 121). In some embodiments, the flow rate of the cleaning gas can be in a range from about 50 sccm to about 200 sccm. If the flow rate is less than about 50 sccm, the epitaxial structure may grow on both the semiconductor material (e.g., the fin structure 108 and the nanostructure 122) and the dielectric layer (e.g., the gate spacer 114 and the internal spacer 121). If the flow rate is greater than about 200 sccm, the epitaxial structure may grow on the semiconductor material (e.g., the fin structure 108), but not on the dielectric layer (e.g., the gate spacer 114 and the internal spacer 121). In some embodiments, the flow rate of the cleaning gas can be controlled to adjust the position of the gap 111, such as at the center or edge of the S / D structure 110.

[0050] In some embodiments, the deposition pressure and / or deposition temperature of the S / D structure 110 may be controlled to adjust the growth rate of the S / D structure 110, and thus adjust the size of the void 111. In some embodiments, the deposition pressure may be in a range from about 100 torr to about 300 torr. In some embodiments, the deposition temperature may be in a range from about 550° C. to about 750° C. If the deposition pressure is less than about 100 torr or the deposition temperature is less than about 550° C., the growth rate of the S / D structure 110 may be too slow, so that the void 111 may not be formed in the S / D structure 110. If the deposition pressure is greater than about 300 torr or the deposition temperature is greater than about 750° C., the growth rate of the S / D structure 110 may be too fast, so that the void 111 may be too large, and the resistance of the S / D structure 110 may increase.

[0051] In some embodiments, Figure 7 As shown, the S / D structure 110 may first be epitaxially grown on the top surface of the fin structure 108 and the end of the nanostructure 122. In some embodiments, as shown in FIG. Figure 8 As shown, the epitaxial growth of the S / D structure 110 may continue on the ends of the fin structure 108 and the nanostructure 122. In some embodiments, the S / D structure 110 on the top nanostructure 122-3 may have a higher growth rate than the S / D structure 110 on the bottom nanostructure 122-1 and the inner spacer 121. In some embodiments, as Fig. 9 As shown, the S / D structures 110 grown on the top nanostructure 122 - 3 may merge, and voids 111 may be formed inside the S / D structures 110 below the top surface of the S / D structures 110 .

[0052] In some embodiments, the void 111 may not contact the nanostructure 122, the fin structure 108, or the internal spacer 121. In some embodiments, the void 111 may have a horizontal dimension 111w (e.g., width) in a range from about 2 nm to about 20 nm along the X-axis. In some embodiments, the void 111 may have a vertical dimension 111h (e.g., height) in a range from about 2 nm to about 50 nm along the Z-axis. In some embodiments, a first ratio of the horizontal dimension 111w to the width 110w of the S / D structure 110 may be in a range from about 0.1 to about 0.8. In some embodiments, a second ratio of the vertical dimension 111h to the height 110h of the S / D structure 110 may be in a range from about 0.05 to about 0.8. If the horizontal dimension 111w is less than about 2 nm, the vertical dimension 111h is less than about 2 nm, the first ratio is less than about 0.1, or the second ratio is less than about 0.05, the parasitic capacitance of the S / D structure 110 may not be reduced, and the device performance of the semiconductor device 100 may not be improved. If the horizontal dimension 111 w is greater than about 20 nm, the vertical dimension 111 h is greater than about 50 nm, the first ratio is greater than about 0.8, or the second ratio is greater than about 0.8, the resistance of the S / D structure 110 may increase and the device performance of the semiconductor device 100 may be reduced.

[0053] In some embodiments, the S / D structure may include Fig.10 As shown in FIG. 1 , two gaps 111 - 1 and 111 - 2 are arranged in the vertical direction along the Z axis, or as shown in FIG. Fig.11 The two gaps 111-1 and 111-2 are arranged in the horizontal direction along the X-axis. In some embodiments, the flow rate of the cleaning gas, the deposition pressure and the deposition temperature during the growth of the S / D structure 110 can be adjusted to form Fig.10 and Fig.11 In some embodiments, the growth conditions can be adjusted so that Fig.10 and Fig.11 The S / D structure 110 in Fig. 9 The S / D structure 110 in the inner spacer 121 has a slower growth rate. Therefore, the voids 111-1 and 111-2 can be formed in the S / D structure 110 instead of one void 111. In some embodiments, the S / D structure grown on the inner spacer 121 can be removed by a cleaning gas during the growth of the S / D structure 110. Therefore, the voids 111-1 and 111-2 can be formed adjacent to the inner spacer 121, such as Fig.11 In some embodiments, Fig.10 As shown, the gaps 111-1 and 111-2 may be surrounded by the S / D structure 110. In some embodiments, as shown in FIG. Fig.10As shown, the voids 111-1 and / or 111-2 may be in contact with the internal spacer 121 and / or the nanostructure 122 and may be partially surrounded by the internal spacer 121 and / or the nanostructure 122. In some embodiments, Fig.10 and Fig.11 Each of the gaps 111-1 and 111-2 in the embodiment may have a horizontal dimension (eg, width) along the X-axis in a range from about 2 nm to about 20 nm. In some embodiments, Fig.10 and Fig.11 Each of the voids 111-1 and 111-2 in the S / D structure 110 may have a vertical dimension (e.g., height) along the Z-axis in a range from about 2 nm to about 50 nm. In some embodiments, a first ratio of the horizontal dimension to the width 110w of the S / D structure 110 may be in a range from about 0.1 to about 0.8. In some embodiments, a second ratio of the vertical dimension to the height 110h of the S / D structure 110 may be in a range from about 0.05 to about 0.8.

[0054] In some embodiments, Fig.12 and Fig.13 As shown, a dielectric layer 109 may be formed on the fin structure 108 before growing the S / D structure 110. The S / D structure 110 may be epitaxially grown on the dielectric layer 109 and between adjacent stacks of the nanostructures 122. In some embodiments, the dielectric layer 109 may be formed on the fin structure 108 using a directional deposition method. In some embodiments, the dielectric layer 109 may have a thickness 109t in a range from about 1 nm to about 15 nm. In some embodiments, the top surface of the dielectric layer 109 may be lower than the bottom surface of the bottom nanostructure 122-1 to avoid blocking the contact between the nanostructure 122 and the S / D structure 110. In some embodiments, the dielectric layer 109 may reduce the leakage current of the semiconductor device 100.

[0055] In some embodiments, by adjusting the flow rate of the cleaning gas, the deposition pressure, and the deposition temperature during the growth of the S / D structure 110, a structure such as Fig.12 The gap 111 shown in FIG. 110 may be formed as shown in FIG. Fig.13 The gap 111 shown is in contact with the dielectric layer 109. In some embodiments, as Fig.12 As shown, the gap 111 may be surrounded by the S / D structure 110. In some embodiments, as shown in FIG. Fig.13 As shown, the void 111 may be in contact with the dielectric layer 109 and the S / D structure 110, and be surrounded by the dielectric layer 109 and the S / D structure 110. In some embodiments, Fig.12 and Fig.13The voids 111 in the may have a horizontal dimension 111w (eg, width) along the X-axis in a range from about 2 nm to about 20 nm. In some embodiments, Fig.12 and Fig.13 The void 111 in the S / D structure 110 may have a vertical dimension 111h (e.g., height) along the Z-axis in a range from about 2 nm to about 50 nm. In some embodiments, a first ratio of the horizontal dimension 111w to the width 110w of the S / D structure 110 may be in a range from about 0.1 to about 0.8. In some embodiments, a second ratio of the vertical dimension 111h to the height 110h of the S / D structure 110 may be in a range from about 0.05 to about 0.8.

[0056] In some embodiments, the S / D structure may be formed on the dielectric layer 109 and include: Fig.14 The two gaps 111-1 and 111-2 are arranged in the vertical direction along the Z axis as shown, or Fig.15 The two gaps 111-1 and 111-2 are arranged in the horizontal direction along the X-axis. In some embodiments, the flow rate of the cleaning gas, the deposition pressure and the deposition temperature during the growth of the S / D structure 110 can be adjusted to form Fig.14 and Fig.15 In some embodiments, as shown in FIG. Fig.14 As shown, the gaps 111-1 and 111-2 may be surrounded by the S / D structure 110 and the dielectric layer 109. In some embodiments, as shown in FIG. Fig.15 As shown, the voids 111-1 and / or 111-2 may be in contact with the internal spacer 121 and / or the nanostructure 122 and may be partially surrounded by the internal spacer 121 and / or the nanostructure 122. In some embodiments, Fig.14 and Fig.15 Each of the gaps 111-1 and 111-2 in the embodiment may have a horizontal dimension (eg, width) along the X-axis in a range from about 2 nm to about 20 nm. In some embodiments, Fig.14 and Fig.15 Each of the voids 111-1 and 111-2 in the S / D structure 110 may have a vertical dimension (e.g., height) along the Z-axis in a range from about 2 nm to about 50 nm. In some embodiments, a first ratio of the horizontal dimension to the width 110w of the S / D structure 110 may be in a range from about 0.1 to about 0.8. In some embodiments, a second ratio of the vertical dimension to the height 110h of the S / D structure 110 may be in a range from about 0.05 to about 0.8.

[0057] In some embodiments, Fig.16 and Fig.17As shown, the first S / D structure 110-1 may be formed on the fin structure 108, the dielectric layer 113 may be formed on the first S / D structure 110-1, and the second S / D structure 110-2 may be formed on the dielectric layer 113. In some embodiments, the first S / D structure 110-1 may be in contact with the bottom nanostructure 122-1, the dielectric layer 113 may be in contact with the middle nanostructure 122-2, and the second S / D structure 110-2 may be in contact with the top nanostructure 122-3. In some embodiments, the first S / D structure 110-1 may include a first type dopant. For example, the first S / D structure 110-1 may include a p-type dopant and may be used as a p-type S / D region of a bottom nanostructure transistor formed using the bottom nanostructure 122-1. In some embodiments, the second S / D structure 110-2 may include a second type dopant complementary to the first type dopant. For example, the second S / D structure 110-2 may include an n-type dopant and may be used as an n-type S / D region of a top nanostructure transistor formed using the top nanostructure 122-3. Fig.16 and Fig.17 The semiconductor device 100 in FIG. 1 may be referred to as a complementary FET (CFET) device.

[0058] In some embodiments, Fig.16 As shown, the void 111 may be formed in the second S / D structure 110-2 and surrounded by the second S / D structure 110-2 and the dielectric layer 113. In some embodiments, as shown in FIG. Fig.17 As shown, the void 111-1 may be formed in the first S / D structure 110-1, and the void 111-2 may be formed in the second S / D structure 110-2. The void 111-1 may be surrounded by the first S / D structure 110-1, and the void 111-2 may be surrounded by the second S / D structure 110-2. In some embodiments, the flow rate of the cleaning gas, the deposition pressure, and the deposition temperature during the growth of the S / D structures 110-1 and 110-2 may be adjusted to form Fig.16 and Fig.17 In some embodiments, Fig.16 and Fig.17 Each of the gaps 111, 111-1, and 111-2 in the embodiment may have a horizontal dimension (eg, width) along the X-axis in a range from about 2 nm to about 20 nm. In some embodiments, Fig.16 and Fig.17Each of the gaps 111, 111-1, and 111-2 in the S / D structures 110-1 and 110-2 may have a vertical dimension (e.g., height) along the Z-axis in a range from about 2 nm to about 50 nm. In some embodiments, a first ratio of the horizontal dimension to the width of the S / D structures 110-1 and 110-2 may be in a range from about 0.1 to about 0.8. In some embodiments, a second ratio of the vertical dimension to the height of the S / D structures 110-1 and 110-2 may be in a range from about 0.05 to about 0.8. Although Figures 9 to 17 One or two voids 111 in the S / D structure 110 are shown, but the S / D structure 110 may have any number of voids 111 .

[0059] refer to Figure 5 In operation 530, a gate structure is formed around the semiconductor layer stack. Figures 1 to 4 As shown, the gate structure 120 may replace the sacrificial gate structure 620 and may be formed to surround the nanostructure 122. Replacing the sacrificial gate structure 620 may include removing the sacrificial gate structure 620, removing the nanostructure 621 to form the n-type and p-type channel structures, and depositing the gate structure 120 surrounding the nanostructure 122. In some embodiments, as Figures 1 to 4 As shown, the gate structure 120 may include a gate dielectric layer 124 and a gate electrode 112. In some embodiments, the gate electrode 112 may include one or more work function metal layers and a metal filler. In some embodiments, the work function metal layer may include a single metal layer or a metal layer stack. The metal layer stack may include work function metals having work function values ​​that are equal to or different from each other. In some embodiments, the metal filler may include titanium, tantalum, aluminum, cobalt, tungsten, nickel, ruthenium, or other suitable conductive materials.

[0060] In some embodiments, after forming the gate structure 120, a Figures 1 to 4 In some embodiments, after forming the S / D contact structure 130, an interconnect structure, a metal line, a metal via, an ILD layer, and other suitable processes may be performed to form the S / D contact structure 130. Figures 1 to 4 The semiconductor device 100 is shown. For the sake of clarity, these processes are not described in detail.

[0061] Various embodiments in the present disclosure provide methods for forming a S / D structure with a void in a semiconductor device 100. In some embodiments, the semiconductor device 100 may include a stack of nanostructures 122 on a substrate 104. The gate structure 120 may surround the nanostructure 122. The S / D structure 110 may be formed on the substrate 104 and in contact with the nanostructure 122. The S / D structure 110 may include one or more voids 111 below the top surface of the S / D structure 110. In some embodiments, a first ratio of a horizontal dimension 111w of the void 111 to a width 110w of the S / D structure 110 may be in a range from about 0.1 to about 0.8, and a second ratio of a vertical dimension 111h of the void 111 to a height 110h of the S / D structure 110 may be in a range from about 0.05 to about 0.8. With the void 111 in the S / D structure 110, the parasitic capacitance of the S / D structure 110 may be reduced, and the device performance of the semiconductor device 100 may be improved.

[0062] In some embodiments, a semiconductor device includes: a semiconductor layer stack on a substrate, a gate structure surrounding the semiconductor layer stack, and a source / drain (S / D) structure on the substrate and in contact with the semiconductor layer stack. The S / D structure includes a gap below a top surface of the S / D structure.

[0063] In some embodiments, a semiconductor device includes: a first semiconductor layer stack and a second semiconductor layer stack on a substrate, a first gate structure surrounding the first semiconductor layer stack, a second gate structure surrounding the second semiconductor layer stack, and a source / drain (S / D) structure between the first semiconductor layer stack and the second semiconductor layer stack. The S / D structure includes a gap below a top surface of the S / D structure.

[0064] In some embodiments, a method includes: forming a semiconductor layer stack on a substrate; depositing a source / drain (S / D) structure on the substrate and in contact with the semiconductor layer stack; and forming a gate structure around the semiconductor layer stack. The S / D structure includes a void below a top surface of the S / D structure.

[0065] It should be understood that the detailed description section (rather than the abstract section of the present disclosure) is intended to be used to interpret the claims. The abstract section of the present disclosure may set forth one or more embodiments, rather than all possible embodiments of the present disclosure contemplated by the inventor(s), and is therefore not intended to limit the appended claims in any way.

[0066] The foregoing disclosure summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also appreciate that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

[0067] Example 1 is a semiconductor device comprising: a semiconductor layer stack on a substrate; a gate structure surrounding the semiconductor layer stack; and a source / drain (S / D) structure on the substrate and in contact with the semiconductor layer stack, wherein the S / D structure comprises a gap below a top surface of the S / D structure.

[0068] Example 2 is the semiconductor device of Example 1, wherein a ratio of a horizontal dimension of the void to a width of the S / D structure is in a range from about 0.1 to about 0.8.

[0069] Example 3 is the semiconductor device of Example 1, wherein a ratio of a vertical dimension of the void to a height of the S / D structure is in a range from about 0.05 to about 0.8.

[0070] Example 4 is the semiconductor device of Example 1, wherein the S / D structure includes an additional void separated from the void.

[0071] Example 5 is the semiconductor device of Example 1, wherein the void is above a top surface of the substrate.

[0072] Example 6 is the semiconductor device of Example 1, further comprising: an internal spacer between the S / D structure and the gate structure, wherein the gap is partially surrounded by the internal spacer.

[0073] Example 7 is the semiconductor device of Example 1, further comprising: a dielectric layer between the substrate and the S / D structure, wherein the void is above the dielectric layer and surrounded by the S / D structure.

[0074] Example 8 is the semiconductor device of Example 1, further comprising: a dielectric layer between the substrate and the S / D structure, wherein the gap is partially surrounded by the dielectric layer and the S / D structure.

[0075] Example 9 is the semiconductor device described in Example 1, further comprising: a dielectric layer on the S / D structure and an additional S / D structure on the dielectric layer, wherein the additional S / D structure includes an additional gap.

[0076] Example 10 is the semiconductor device described in Example 1, further comprising: a contact structure on the S / D structure, wherein the distance between the contact structure and the void is in the range from about 4 nm to about 20 nm.

[0077] Example 11 is a semiconductor device, comprising: a first semiconductor layer stack and a second semiconductor layer stack on a substrate; a first gate structure surrounding the first semiconductor layer stack; a second gate structure surrounding the second semiconductor layer stack; and a source / drain (S / D) structure between the first semiconductor layer stack and the second semiconductor layer stack, wherein the S / D structure includes a void below the top surface of the S / D structure.

[0078] Example 12 is the semiconductor device described in Example 11, wherein a first ratio of a horizontal dimension of the void to a width of the S / D structure is in the range from about 0.1 to about 0.8, and a second ratio of a vertical dimension of the void to a height of the S / D structure is in the range from about 0.05 to about 0.8.

[0079] Example 13 is the semiconductor device described in Example 11, wherein the void is adjacent to the first semiconductor layer stack, and the S / D structure includes an additional void adjacent to the second semiconductor layer stack.

[0080] Example 14 is the semiconductor device described in Example 11, further comprising: a dielectric layer between the substrate and the S / D structure; and an additional void in the S / D structure, wherein the void is adjacent to the dielectric layer, and the additional void is above the void.

[0081] Example 15 is the semiconductor device described in Example 11, further comprising: a dielectric layer on the S / D structure; and an additional S / D structure on the dielectric layer and including an additional void, wherein the dielectric layer and the additional S / D structure are located between the first semiconductor layer stack and the second semiconductor layer stack.

[0082] Example 16 is a method of forming a semiconductor device, comprising: forming a semiconductor layer stack on a substrate; depositing a source / drain (S / D) structure on the substrate and in contact with the semiconductor layer stack, wherein the S / D structure includes a void below the top surface of the S / D structure; and forming a gate structure surrounding the semiconductor layer stack.

[0083] Example 17 is the method described in Example 16, wherein depositing the S / D structure includes: forming an additional void in the S / D structure separated from the void.

[0084] Example 18 is the method of Example 16, further comprising: forming an internal spacer between the S / D structure and the gate structure, wherein the gap is partially surrounded by the internal spacer.

[0085] Example 19 is the method of Example 16, further comprising: forming a dielectric layer on the substrate before depositing the S / D structure, wherein the void is formed above the dielectric layer.

[0086] Example 20 is the method of Example 16, further comprising: forming a dielectric layer on the S / D structure; and forming an additional S / D structure on the dielectric layer, wherein the additional S / D structure includes an additional gap.

Claims

1. A semiconductor device, comprising: A semiconductor layer stack, on a substrate; A gate structure, stacked around the semiconductor layer; as well as A source / drain (S / D) structure is on the substrate and in contact with the semiconductor layer stack, wherein the S / D structure includes a void below a top surface of the S / D structure.

2. The semiconductor device according to claim 1, wherein A ratio of a horizontal dimension of the void to a width of the S / D structure ranges from 0.1 to 0.

8.

3. The semiconductor device according to claim 1, wherein A ratio of a vertical dimension of the void to a height of the S / D structure ranges from 0.05 to 0.

8.

4. The semiconductor device according to claim 1, wherein: The S / D structure includes an additional void separated from the void.

5. The semiconductor device according to claim 1, wherein The void is above a top surface of the substrate.

6. The semiconductor device according to claim 1, further comprising: An inner spacer is between the S / D structure and the gate structure, wherein the gap is partially surrounded by the inner spacer.

7. The semiconductor device according to claim 1, further comprising: A dielectric layer is between the substrate and the S / D structure, wherein the void is above the dielectric layer and surrounded by the S / D structure.

8. The semiconductor device according to claim 1, further comprising: A dielectric layer is between the substrate and the S / D structure, wherein the void is partially surrounded by the dielectric layer and the S / D structure.

9. A semiconductor device comprising: a first semiconductor layer stack and a second semiconductor layer stack on a substrate; A first gate structure, stacked around the first semiconductor layer; a second gate structure stacked around the second semiconductor layer; as well as A source / drain (S / D) structure is between the first semiconductor layer stack and the second semiconductor layer stack, wherein the S / D structure includes a void below a top surface of the S / D structure.

10. A method of forming a semiconductor device, comprising: forming a semiconductor layer stack on a substrate; depositing a source / drain (S / D) structure on the substrate and in contact with the semiconductor layer stack, wherein the S / D structure includes a void below a top surface of the S / D structure; as well as A gate structure is formed around the semiconductor layer stack.

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