Fin-type channel and plane channel mixed silicon carbide MOSFET and preparation method thereof

Abstract

The invention discloses a fin-type channel and plane channel hybrid silicon carbide MOSFET and a preparation method thereof. The device comprises a silicon carbide substrate; the N-type drift region is formed on the silicon carbide substrate; the channel layer is formed on the N-type drift region, the channel layer comprises a plane channel and a fin-type channel, and the fin-type channel is located on the plane channel; the bottom P-type base region is formed in two side regions of the upper part of the plane channel and keeps a certain distance from the fin-type channel; the bottom N + region is formed at the upper part of the bottom P-type base region; the top P-type base region is formed on the fin-type channel; the top N + region is formed on the top P-type base region; the gate dielectric layers are formed on the two sides of the fin-type channel and cover the top N + region, the top P-type base region, the side wall of the fin-type channel and the surface of the plane channel; the polysilicon gate is formed on the gate dielectric layer; the oxide layer covers the polysilicon gate; and the source ohmic contact is in contact with the surface of the bottom N + region and the surface of the top N + region. The current channel density of the device is effectively improved, and the on-resistance is reduced.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuit device structure design, and in particular relates to a fin-type channel and planar channel hybrid silicon carbide MOSFET and a preparation method thereof. Background Art

[0002] SiC metal oxide semiconductor field effect transistor (SiC MOSFET) is one of the most promising commercial power semiconductor devices. As the third generation wide bandgap semiconductor material, silicon carbide is a compound composed of silicon atoms and carbon atoms. Its breakdown field strength is 10 times that of Si, and its bandgap width is 3 times that of Si. It also has good stability under high temperature, high pressure, and strong radiation conditions. Compared with Si MOSFET, SiC MOSFET has advantages such as low on-resistance, fast switching speed, high breakdown electric field, and good stability. Therefore, it is considered to be a power device material that exceeds the limits of Si. At present, the penetration rate of SiC MOSFET has increased in new energy vehicles, energy, communications and other fields, and the market size of silicon carbide devices is expected to continue to increase.

[0003] The power loss of SiC MOSFET devices is very important in industrial applications. At present, the conductive channels of a cell of planar silicon carbide devices and trench silicon carbide devices are often no more than two, and the current channel density is small. In particular, the electron mobility of silicon carbide devices is much lower than that of traditional silicon devices. These lead to an increase in the on-resistance of traditional silicon carbide devices, thereby increasing losses. One of the current solutions is to increase the current channel density of the device, such as VC-Fin-SiC and LC-Fin-SiC.

[0004] One challenge facing SiC MOSFET is gate oxide breakdown. Under the same forward conduction capability, SiC wide bandgap power devices have a higher critical breakdown electric field than Si devices, which causes the gate oxide layer to face greater electric field stress in the blocking state. For this reason, the P-well is introduced to reduce the electric field strength at the gate oxide to meet its reliability requirements, but it will introduce a JFET region, resulting in JFET resistance. Therefore, while protecting the gate oxide, how to reduce the impact of the P-well is also a research direction of SiC MOSFET. Summary of the invention

[0005] The present invention discloses a fin-channel and planar-channel hybrid silicon carbide MOSFET, comprising: a silicon carbide substrate; an N-type drift region formed on the silicon carbide substrate; a channel layer formed on the N-type drift region, the channel layer comprising a planar channel and a fin-type channel, and the fin-type channel is located on the planar channel; a bottom P-type base region formed on both sides of the upper part of the planar channel and maintaining a certain distance from the fin-type channel; a bottom N-type base region formed on ... +The top P-type base region is formed on the fin channel. + The gate dielectric layer is formed on both sides of the fin channel, covering the top N + The top P-type base region and the sidewall and planar channel surface of the fin channel; the polysilicon gate is formed on the gate dielectric layer; the oxide layer covers the polysilicon gate; the source ohmic contact is connected to the bottom N + N on the surface and top of the zone + The surface of the area is in contact.

[0006] In the fin-channel and planar-channel hybrid silicon carbide MOSFET of the present invention, preferably, the thickness of the N-type drift region is 5 μm to 50 μm, and the doping concentration is 1×10 15 cm -3 ~1×10 17 cm -3 .

[0007] In the fin-channel and planar-channel hybrid silicon carbide MOSFET of the present invention, preferably, the doping concentration of the channel layer is 5×10 16 cm -3 ~1×10 18 cm -3 .

[0008] In the fin-channel and planar-channel hybrid silicon carbide MOSFET of the present invention, preferably, the thickness of the top P-type base region is 0.5 μm to 5 μm, and the doping concentration is 5×10 16 ~1×10 18 cm -3 ; The top N + The thickness of the region is 0.2μm to 5μm, and the doping concentration is 1×10 19 cm -3 ~1×10 20 cm -3 .

[0009] In the fin-channel and planar-channel hybrid silicon carbide MOSFET of the present invention, preferably, the thickness of the bottom P-type base region is 0.8 μm to 5 μm, and the doping concentration is 5×10 16 ~1×10 19 cm -3 ; The bottom N + The thickness of the region is 0.2μm to 1μm, and the doping concentration is 1×10 19 cm -3 ~1×10 20 cm -3 .

[0010] The present invention also discloses a method for preparing a fin-channel and planar-channel hybrid silicon carbide MOSFET, comprising the following steps: epitaxially growing an N-type drift region, an initial channel layer, and a top P-type base region on a silicon carbide substrate; performing ion implantation to form a top N-type substrate on the top of the top P-type base region; + Area; Photolithography defines the fin channel area, and then etching removes the top N + The fin-type channel and the planar channel are formed by etching the top P-type base region, the top P-type base region and the initial channel layer, and the fin-type channel and the planar channel are formed by etching the top P-type base region and the initial channel layer, and the fin-type channel and the planar channel are formed by etching the top P-type base region and the initial channel layer, and the fin-type channel and the planar channel are formed by etching the top P-type base region and the planar channel. The fin-type channel and the planar channel are formed by etching the top P-type base region and the planar channel. The fin-type channel and the planar channel are formed by etching the top P-type base region and the planar channel. The fin-type channel and the planar channel are formed by etching the top P-type base region and the planar channel. The fin-type channel and the planar channel are formed by etching the top P-type base region and the planar channel. The planar ... + The implanted ions are activated by annealing at high temperature; an oxide layer is isotropically deposited to protect the polysilicon gate, and then the oxide layer in other areas is etched away by photolithography to expose the bottom N + Area and top N + region as the source metal contact region; depositing a high work function metal to form a source ohmic contact, and then polishing the top of the device to form a single cell structure.

[0011] In the method for preparing a fin-channel and planar-channel hybrid silicon carbide MOSFET of the present invention, preferably, the thickness of the N-type drift region is 5 μm to 50 μm, and the doping concentration is 1×10 15 cm -3 ~1×10 17 cm -3 .

[0012] In the method for preparing a fin-channel and planar-channel hybrid silicon carbide MOSFET of the present invention, preferably, the doping concentration of the channel layer is 5×10 16 cm -3 ~1×10 18 cm -3 .

[0013] In the method for preparing a fin-channel and planar-channel hybrid silicon carbide MOSFET of the present invention, preferably, the thickness of the top P-type base region is 0.5 μm to 5 μm, and the doping concentration is 5×10 16 ~1×10 18 cm -3 ; The top N + The thickness of the region is 0.2μm to 5μm, and the doping concentration is 1×10 19 cm -3~1×10 20 cm -3 .

[0014] In the method for preparing a fin-channel and planar-channel hybrid silicon carbide MOSFET of the present invention, preferably, the thickness of the bottom P-type base region is 0.8 μm to 5 μm, and the doping concentration is 5×10 16 ~1×10 19 cm -3 ; The bottom N + The thickness of the region is 0.2μm to 1μm, and the doping concentration is 1×10 19 cm -3 ~1×10 20 cm -3 .

[0015] Beneficial effects:

[0016] The device designed by this patent uses a structure combining fin-type channels and planar channels, which doubles the MOS structure of the device. Compared with traditional trench-type devices, this design has double the current path. When the device is working normally, the gate controls the conduction of four channels, effectively reducing the on-resistance. The fin-type trench channel reduces the impact of the charge storage effect, and effectively utilizes the P-type base area at the bottom, reducing the electric field strength at the gate oxide while reducing the reverse transfer capacitance. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a flow chart of the method for preparing fin channel and planar channel hybrid silicon carbide MOSFET.

[0018] Figure 2 to Figure 12 It is a structural schematic diagram of each stage of the preparation method of fin channel and planar channel hybrid silicon carbide MOSFET. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. The described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0020] In the description of the present invention, it should be noted that the terms "upper", "lower", "vertical", "horizontal", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0021] In addition, many specific details of the present invention are described below, such as the structure, materials, dimensions, processing technology and techniques of the device, so that the present invention can be more clearly understood. However, as can be understood by those skilled in the art, the present invention can be implemented without following these specific details. Unless otherwise specified below, the various parts of the device can be made of materials known to those skilled in the art, or can be made of materials with similar functions developed in the future.

[0022] Figure 1 It is a method for preparing a hybrid fin channel and planar channel silicon carbide MOSFET. Figure 1 As shown, the method for preparing fin channel and planar channel silicon carbide MOSFET includes the following steps:

[0023] Step S1, in the 80 μm to 300 μm thick, doping concentration of 1×10 19 cm -3 ~1×10 20 cm -3 The epitaxial layer is 5 μm to 50 μm thick and has a doping concentration of 1×10 15 cm -3 ~1×10 17 cm -3 The N-drift region 102 has a thickness of 1 μm to 10 μm and a doping concentration of 5×10 16 cm -3 ~1×10 18 cm -3 The initial channel layer 103 (N-JFET region) is 0.5 μm to 5 μm thick and has a doping concentration of 5×10 16 ~1×10 18 cm -3 The top P-type base region (P-base) 104 of the embodiment of the present invention is shown in FIG. Figure 2 As shown. Ion implantation is performed to form a 0.2 μm to 5 μm thick layer with a doping concentration of 1×10 19 cm -3 ~1×10 20 cm -3 Top N+ Region 105, the resulting structure is as Figure 3 shown.

[0024] Step S2, define the fin channel area by photolithography, and then etch away the top N + The top P-type base region 104 and the initial channel layer 103 are stopped in the initial channel layer 103, and only the central region is retained to form a fin channel and a planar channel. The resulting structure is as shown Figure 4 As shown. Then, the bottom P-type base region is defined by photolithography, and ion implantation is performed to form 0.8μm to 5μm thick and 5×10 doping concentration on both sides of the fin channel on the upper part of the planar channel. 16 ~1×10 19 cm -3 The bottom P-type base regions 106, 107 are spaced apart from the fin-type channel, preferably with a spacing of 0.2 μm. The resulting structure is as follows Figure 5 As shown in Figure 2, the top P-type base region and the bottom P-type base region strengthen the shielding of the coupling between the gate and the drain and reduce the gate area above the JFET region. The device has lower reverse transfer capacitance and gate-drain charge (Qgd), which improves the FOM value of the device.

[0025] Step S3, thermally oxidize the surface of the above structure to form a gate oxide layer 108 with a thickness of 40nm to 60nm. The resulting structure is as follows: Figure 6 Then, a polysilicon layer 109 with a thickness of 0.5 μm to 1 μm is anisotropically deposited on the gate oxide layer 108, and the resulting structure is as shown in FIG. Figure 7 Then, the polysilicon layer 109 on the plane is isotropically etched away, the etching depth is, for example, 0.5 μm to 2 μm, so that the surface of the gate oxide layer 108 is exposed, and sidewall polysilicon gates 109 are formed on both sides of the fin-type channel. The resulting structure is as shown in FIG. Figure 8 shown.

[0026] Step S4, ion implantation is performed to form a 0.2 μm to 1 μm thick doping concentration of 1×10 19 cm -3 ~1×10 20 cm -3 Bottom N + Areas 110, 111, and then annealing at high temperature to activate all implanted ions, the resulting structure is as follows Fig. 9 As shown. By introducing N + region to form a MOS structure, and the current channel is controlled by the same gate, so that under the same cell size, the device can not only reduce the electric field strength at the oxide layer, but also have four current channels, thereby reducing the on-resistance of the device.

[0027] Step S5, isotropically depositing an oxide layer 112 with a thickness of 0.2 μm to 1 μm to protect the polysilicon gate 109, and the resulting structure is as follows: Fig.10 As shown. Then, the oxide layer 112 in other areas is etched away by photolithography to expose the bottom N + Area 110, 111 and top N + Region 105 is used as the source metal contact region, and the resulting structure is as follows Fig.11 shown.

[0028] Step S6, depositing a high work function metal to form a source ohmic contact 113, and then chemically vapor polishing the top of the device to form a single cell structure. The resulting structure is as shown in FIG. Fig.12 shown.

[0029] like Fig.12 As shown, the fin-channel and planar-channel hybrid silicon carbide MOSFET includes a silicon carbide substrate 101; an N-type drift region 102 formed on the substrate 101; a channel layer formed on the N-type drift region 102, the channel layer includes a planar channel and a fin-type channel, and the fin-type channel is located on the planar channel; a bottom P-type base region 106, 107, formed on both sides of the upper part of the planar channel, and maintaining a certain distance from the fin-type channel; a bottom N + Regions 110, 111 are formed on the top of the bottom P-type base regions 106, 107; the top P-type base region 104 is formed on the fin channel; the top N + Region 105 is formed on the top P-type base region 104; gate dielectric layer 108 is formed on both sides of the fin channel, covering the top N + The top P-type base region 104 and the sidewalls of the fin channel cover the planar channel surface and extend to cover a portion of the bottom P-type base region 106, 107 surface and a portion of the bottom N + The surface of regions 110 and 111; the polysilicon gate 109 is formed on the gate dielectric layer 108; the oxide layer 112 covers the polysilicon gate 109; the source ohmic contact 113 is connected to the bottom N + Area 110, 111 surface and top N + The surfaces of region 105 are in contact.

[0030] The silicon carbide device is an N-type MOSFET, consisting of a vertical fin channel and a horizontal plane channel. When the device is turned on, the gate voltage exceeds the channel threshold voltage, and the current flows from the drain to the source through four paths, thereby achieving extremely low on-resistance. When the device is blocked, the gate voltage is lower than the channel threshold voltage, the current channel is closed, and the device withstands high voltage through the bottom P-type base region to protect the device structure and gate oxide layer. By controlling the gate voltage to control the high-speed on and off of the device under high voltage, power conversion and circuit control are achieved.

[0031] The fin-type channel and planar channel hybrid silicon carbide MOSFET has double the current path compared to the traditional trench device design. When the device is working normally, the gate controls the four channels to conduct, effectively reducing the on-resistance. The fin-type trench channel reduces the impact of the charge storage effect, and effectively utilizes the bottom P-type base area to reduce the electric field strength at the gate oxide while reducing the reverse transfer capacitance.

[0032] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A fin channel and planar channel hybrid silicon carbide MOSFET, characterized in that: include: Silicon carbide substrate; An N-type drift region is formed on the silicon carbide substrate; A channel layer is formed on the N-type drift region, the channel layer includes a planar channel and a fin-type channel, and the fin-type channel is located on the planar channel; The bottom P-type base region is formed on both sides of the upper part of the planar channel and keeps a distance from the fin channel; Bottom N + region, formed on the upper portion of the bottom P-type base region; A top P-type base region formed on the fin-type channel; Top N + region, formed on the top P-type base region; The gate dielectric layer is formed on both sides of the fin channel and covers the top N + region, the top P-type base region and the sidewalls and planar channel surface of the fin channel; A polysilicon gate is formed on the gate dielectric layer; an oxide layer covering the polysilicon gate; The source ohmic contact is connected to the bottom N + Area surface and top N + The surface of the area is in contact.

2. The fin-channel and planar-channel hybrid silicon carbide MOSFET according to claim 1, characterized in that: The thickness of the N-type drift region is 5 μm to 50 μm, and the doping concentration is 1×10 15 cm -3 ~1×10 17 cm -3 .

3. The fin channel and planar channel hybrid silicon carbide MOSFET according to claim 1, characterized in that: The doping concentration of the channel layer is 5×10 16 cm -3 ~1×10 18 cm -3 .

4. The fin-channel and planar-channel hybrid silicon carbide MOSFET according to claim 1, characterized in that: The thickness of the top P-type base region is 0.5 μm to 5 μm, and the doping concentration is 5×10 16 ~1×10 18 cm -3 ; The top N + The thickness of the region is 0.2μm to 5μm, and the doping concentration is 1×10 19 cm -3 ~1×10 20 cm -3 .

5. The fin-channel and planar-channel hybrid silicon carbide MOSFET according to claim 1, characterized in that: The thickness of the bottom P-type base region is 0.8 μm to 5 μm, and the doping concentration is 5×10 16 ~1×10 19 cm -3 ; The bottom N + The thickness of the region is 0.2μm to 1μm, and the doping concentration is 1×10 19 cm -3 ~1×10 20 cm -3 .

6. A method for preparing a fin-channel and planar-channel hybrid silicon carbide MOSFET, characterized in that: The following steps are involved: epitaxially growing an N-type drift region, an initial channel layer and a top P-type base region on a silicon carbide substrate; Ion implantation is performed to form a top N type base region on the top of the top P type base region. + district; The fin channel area is defined by photolithography, and then the top N + region, the top P-type base region and the initial channel layer, stop in the initial channel layer, and only retain the central region to form a fin channel and a planar channel; Then, the bottom P-type base region is defined by photolithography, and ion implantation is performed to form the bottom P-type base region on both sides of the fin channel on the upper part of the planar channel, and keep a certain distance from the fin channel; A gate dielectric layer is formed on the surface of the structure; a polysilicon layer is then anisotropically deposited on the gate dielectric layer, and then the polysilicon layer on the plane is isotropically etched to expose the surface of the gate dielectric layer, and a polysilicon gate is formed on both sides of the fin channel; Ion implantation is performed to form bottom N-type base regions on both sides of the bottom P-type base region. + area, and then annealing at high temperature to activate the implanted ions; An oxide layer is deposited isotropically to protect the polysilicon gate, and then the oxide layer in other areas is etched away by photolithography to expose the bottom N + Area and top N + Region, serving as source metal contact region; A high work function metal is deposited to form an ohmic contact to the source, and then the top of the device is polished to form a single cell structure.

7. The method for preparing a fin-channel and planar-channel hybrid silicon carbide MOSFET according to claim 6, characterized in that: The thickness of the N-type drift region is 5 μm to 50 μm, and the doping concentration is 1×10 15 cm -3 ~1×10 17 cm -3 .

8. The method for preparing a fin-channel and planar-channel hybrid silicon carbide MOSFET according to claim 6, characterized in that: The doping concentration of the channel layer is 5×10 16 cm -3 ~1×10 18 cm -3 .

9. The method for preparing a fin-channel and planar-channel hybrid silicon carbide MOSFET according to claim 6, characterized in that: The thickness of the top P-type base region is 0.5 μm to 5 μm, and the doping concentration is 5×10 16 ~1×10 18 cm -3 ; The top N + The thickness of the region is 0.2μm to 5μm, and the doping concentration is 1×10 19 cm -3 ~1×10 20 cm -3 .

10. The method for preparing a fin-channel and planar-channel hybrid silicon carbide MOSFET according to claim 6, characterized in that: The thickness of the bottom P-type base region is 0.8 μm to 5 μm, and the doping concentration is 5×10 16 ~1×10 19 cm -3 ; The bottom N + The thickness of the region is 0.2μm to 1μm, and the doping concentration is 1×10 19 cm -3 ~1×10 20 cm -3 .

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