Semiconductor structure and manufacturing method thereof

By designing an electric field-changing structure composed of an oxide layer and a high dielectric layer embedded in the drift region in a high-voltage LDMOS device, the problem of hot carrier effect in a high-voltage working environment is solved, and the reliability and service life of the device are improved.

CN120035176APending Publication Date: 2025-05-23GTA SEMICON CO LTD
View PDF 0 Cites 0 Cited by

Patent Information

Application Number
CN202510233482.3
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-02-27
Publication Date
2025-05-23

AI Technical Summary

Technical Problem

High-voltage LDMOS devices are prone to hot carrier effects in high-voltage working environments, resulting in reduced reliability and reduced safe working area range.

Method used

A semiconductor structure is designed, including a substrate, a gate structure and an electric field changing structure embedded in the drift region, which consists of an oxide layer and a high dielectric layer stacked in sequence from the inside to the outside.

Benefits of technology

By reducing the peak electric field near the leakage end and reducing collision ionization, the hot carrier effect is effectively suppressed, the safe working area range is expanded, the performance reliability of the device is improved, and the service life is extended.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN120035176A_ABST
    Figure CN120035176A_ABST
Patent Text Reader

Abstract

The invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a gate structure, and an electric field changing structure. A drift region and a well region which is located on one side of the drift region in the direction parallel to the substrate are arranged in one side of the substrate; the gate structure is located on one side, with the drift region and the well region, of the substrate; one side, close to the substrate, of the gate structure is bordered with the drift region and the well region; the electric field changing structure is embedded in a trench on one side, close to the gate structure, of the drift region; the electric field changing structure is bordered with the gate structure; wherein the electric field changing structure comprises an oxide layer and a high dielectric layer which are sequentially stacked from inside to outside; the high dielectric layer covers the bottom and the side wall of the groove, and the oxide layer covers the high dielectric layer and is filled in the groove. According to the invention, the hot carrier effect in a high-voltage working environment can be effectively suppressed through simple process steps, so that the range of a safe working area is ensured, the performance reliability of the device is improved, and the service life of the device is prolonged.
Need to check novelty before this filing date? Find Prior Art

Claims

1. A semiconductor structure, characterized in that: include: A substrate; a drift region is provided inside one side of the substrate and a well region is located on one side of the drift region in a direction parallel to the substrate; A gate structure is located on a side of the substrate having the drift region and the well region; a side of the gate structure close to the substrate borders both the drift region and the well region; An electric field changing structure is embedded in a trench on one side of the drift region close to the gate structure; the electric field changing structure borders the gate structure; wherein the electric field changing structure includes an oxide layer and a high dielectric layer stacked in sequence from inside to outside; the high dielectric layer covers the bottom and sidewalls of the trench, and the oxide layer covers the high dielectric layer and fills the trench.

2. The semiconductor structure according to claim 1, characterized in that: Also includes: a source region, located inside a side of the well region close to the gate structure, and located on a side of the gate structure away from the electric field changing structure in a direction parallel to the substrate; The drain region is located inside a side of the drift region close to the gate structure and is located on a side of the electric field changing structure away from the gate structure in a direction parallel to the substrate; wherein the drain region borders the electric field changing structure close to a side wall of the electric field changing structure in a direction parallel to the substrate.

3. The semiconductor structure according to claim 2, characterized in that: The doping type of the substrate is the first doping type, the doping type of the drift region is the second doping type, the doping type of the well region is the first doping type, and the doping types of the source region and the drain region are the second doping type.

4. The semiconductor structure according to claim 1, characterized in that: A size of the drift region in a direction perpendicular to the substrate is larger than a size of the well region in a direction perpendicular to the substrate.

5. The semiconductor structure according to claim 1, characterized in that: The gate structure includes a gate dielectric layer and a gate conductive layer stacked in sequence from bottom to top in a direction perpendicular to the substrate; wherein, The gate dielectric layer is located on a side of the substrate having the drift region and the well region; a side of the gate dielectric layer close to the substrate borders the drift region, the well region and the electric field changing structure; The gate conductive layer is located on a side of the gate dielectric layer facing away from the substrate.

6. The semiconductor structure according to claim 1, characterized in that The material of the high dielectric layer includes silicon nitride or silicon oxynitride.

7. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; forming a drift region inside one side of the substrate and a well region located on one side of the drift region in a direction parallel to the substrate; forming a trench on a side of the drift region away from the substrate; forming an electric field changing structure in the trench; wherein the electric field changing structure comprises an oxide layer and a high dielectric layer stacked in sequence from inside to outside; A gate structure is formed on a side of the substrate having the drift region and the well region; wherein a side of the gate structure close to the substrate borders the drift region, the well region and the electric field changing structure.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that: The forming of the electric field changing structure in the groove comprises: forming the high dielectric layer covering the bottom and sidewalls of the trench; The oxide layer is formed to cover the high dielectric layer and fill the trench.

9. The method for manufacturing a semiconductor structure according to claim 7, characterized in that: After forming a drift region inside one side of the substrate and a well region located on one side of the drift region in a direction parallel to the substrate, the manufacturing method further includes: A source region is formed inside the well region on a side close to the gate structure; the source region is located on a side of the gate structure away from the electric field changing structure in a direction parallel to the substrate; A drain region is formed inside the drift region on a side close to the gate structure; the drain region is located on a side of the electric field changing structure away from the gate structure in a direction parallel to the substrate; the drain region is close to a side wall of the electric field changing structure in a direction parallel to the substrate and borders the electric field changing structure.

10. The method for manufacturing a semiconductor structure according to claim 7, characterized in that: The gate structure is formed on a side of the substrate having the drift region and the well region, comprising: A gate dielectric layer is formed on a side of the substrate having the drift region and the well region; a side of the gate dielectric layer close to the substrate borders the drift region, the well region and the electric field changing structure; A gate conductive layer is formed on a side of the gate dielectric layer facing away from the substrate.