ESD device of LDMOSFET structure, manufacturing method and chip

Abstract

The invention relates to the technical field of semiconductors, and provides an ESD device of an LDMOSFET structure, a manufacturing method and a chip. The device comprises a substrate, a body region, a drift region, a source region, a drain region and a gate structure, the body region is formed on the upper surface of the drift region, and the gate structure is formed in the body region; the source region is connected with the source metal layer, and the drain region is connected with the drain metal layer; the gate structure comprises a gate oxide layer, a polycrystalline silicon gate and a polycrystalline silicon resistor, and the polycrystalline silicon gate and the polycrystalline silicon resistor are connected with the body region through the gate oxide layer; the polycrystalline silicon resistor is connected with the source electrode metal layer, and the body region is connected with the source electrode metal layer; the polycrystalline silicon grid electrode is connected with the drain electrode metal layer through the isolation oxidation layer, and the polycrystalline silicon grid electrode, the isolation oxidation layer and the drain electrode metal layer form a capacitor structure. The high-voltage ESD device is equivalent to an RC type ESD protection circuit, a resistor and a capacitor do not need to be additionally arranged outside an MOS device, the area of the device is reduced, and the high-voltage protection capacity of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an ESD device with an LDMOSFET structure and a manufacturing method and a chip. Background Art

[0002] ESD (Electrostatic Discharge) refers to the charge transfer caused by objects with different electrostatic potentials approaching or directly contacting each other. When the static charge accumulated in the external environment of the IC (integrated circuit) chip or inside the IC chip flows into or out through the chip pins, the instantaneous ESD current will damage the thick gate oxide and metal wires of the internal devices of the chip, thereby causing device failure. With the continuous improvement of the process technology of very large-scale integrated circuits, complementary metal oxide semiconductor (CMOS) integrated circuits have entered the ultra-deep submicron stage, the size of MOS devices has been continuously reduced, and the harm of electrostatic discharge (ESD) to integrated circuits has become more and more significant, requiring ESD protection design for integrated circuits.

[0003] The prior art uses ESD circuits to protect integrated circuits from electrostatic discharge. Figure 1 It is an RC type ESD protection circuit using gate coupling technology. By constantly adjusting the size of capacitor Cn and resistor Rn, a suitable voltage can be coupled to the gate of NMOS device Mn1 under high ESD stress, thereby reducing the turn-on voltage of NMOS and achieving electrostatic protection. For NMOS and PMOS, if the bias voltage coupled to the gate is high, it will cause more channel current and higher electric field, making the thin gate oxide layer easy to be damaged, and the robustness of its ESD protection will decrease rapidly. However, in power management chips in the power field, the voltage can reach several thousand volts or even tens of thousands of volts when static electricity is released. This ESD circuit is difficult to achieve high-voltage electrostatic protection. In addition, the ESD circuit is connected to the capacitor and resistor outside the NMOS or PMOS device. The ESD circuit occupies a large area, which is not conducive to the miniaturization and integration of the chip. Summary of the invention

[0004] In order to solve the above technical problems, the present invention provides an ESD device with an LDMOSFET structure and a manufacturing method thereof.

[0005] On one hand, the present invention provides an ESD device of LDMOSFET structure, comprising: a substrate, a body region, a drift region, a source region, a drain region and a gate structure, wherein the drift region is formed on the surface of the substrate, the body region is formed on the upper surface of the drift region, the source region is formed on the upper surface of the body region, the drain region is formed on the lower surface of the drift region, and the gate structure is formed in the body region;

[0006] The source region is connected to a source metal layer, and the source metal layer is grounded;

[0007] The drain region is connected to a drain metal layer, and the drain metal layer serves as an input terminal;

[0008] The gate structure includes a gate oxide layer, a polysilicon gate and a polysilicon resistor, and the polysilicon gate and the polysilicon resistor are connected to the body region through the gate oxide layer;

[0009] The polysilicon resistor is connected to the source metal layer, and the body region is connected to the source metal layer;

[0010] The polysilicon gate is connected to the drain metal layer through an isolation oxide layer, and the polysilicon gate, the isolation oxide layer and the drain metal layer form a capacitor structure.

[0011] In the embodiment of the present invention, the polysilicon gate and the polysilicon resistor are stacked laterally, and the gate oxide layer is vertically arranged along the side ends of the polysilicon gate and the polysilicon resistor.

[0012] In the embodiment of the present invention, the material of the polysilicon gate is heavily doped polysilicon, and the doping concentration of ions in the heavily doped polysilicon is 1×10 20 cm -3 ~1×10 21 cm -3 ;

[0013] The material of the polysilicon resistor is lightly doped polysilicon, and the doping concentration of ions in the lightly doped polysilicon is 1×10 16 cm -3 ~1×10 18 cm -3 .

[0014] In the embodiment of the present invention, the polysilicon resistor is connected to the source metal layer through the first contact terminal.

[0015] In the embodiment of the present invention, the body region is connected to the source metal layer through the second contact terminal.

[0016] In an embodiment of the present invention, the substrate is an SOI substrate, and the SOI substrate includes a substrate silicon layer, an insulating layer and an active silicon layer;

[0017] The drift region is formed on the upper surface of the active silicon layer;

[0018] The drain region is formed by the active silicon layer.

[0019] In an embodiment of the present invention, the drain metal layer is formed on the lower surface of the active silicon layer.

[0020] In an embodiment of the present invention, the drain metal layer includes a metal contact terminal, the metal contact terminal is connected to the isolation oxide layer, and the metal contact terminal, the isolation oxide layer and the polysilicon gate constitute a capacitor structure.

[0021] The present invention also provides a method for manufacturing the ESD device of the LDMOSFET structure, comprising:

[0022] Performing epitaxy twice on the surface of an SOI substrate to form an N-type epitaxial layer and a P-type epitaxial layer, wherein the SOI substrate comprises a substrate silicon layer, an insulating layer and an N-type active silicon layer;

[0023] Etching the N-type epitaxial layer, the P-type epitaxial layer and the SOI substrate until the insulating layer of the SOI substrate is exposed to form a trench;

[0024] Filling the trench with oxide, etching the oxide filled in the trench to expose the P-type epitaxial layer on the sidewall of the trench;

[0025] The P-type epitaxial layer on the sidewall of the trench is oxidized to form a gate oxide layer connected to the P-type epitaxial layer on the sidewall of the trench, and the remaining N-type epitaxial layer is used as an N-type drift region, and the remaining P-type epitaxial layer is used as a P-type body region;

[0026] Depositing polysilicon in the trench with the gate oxide layer to form a polysilicon gate and a polysilicon resistor;

[0027] Ion implantation is performed on the surface of the P-type body region to form a source region;

[0028] The substrate silicon layer and the insulating layer of the SOI substrate are removed to expose the oxide filled in the trench, and the remaining N-type active silicon layer is used as the drain region;

[0029] Etching the oxide in the trench to form a contact hole, and the remaining oxide in the trench serves as an isolation oxide layer;

[0030] Metal is deposited in the contact hole of the trench and on the surface of the trench to form a drain metal layer, and a source metal layer is formed at the same time.

[0031] In an embodiment of the present invention, epitaxy is performed twice on the surface of an SOI substrate to form an N-type epitaxial layer and a P-type epitaxial layer, including:

[0032] Epitaxially growing N-type silicon on the surface of the N-type active silicon layer of the SOI substrate to form an N-type epitaxial layer;

[0033] P-type silicon is epitaxially grown on the surface of the N-type epitaxial layer to form a P-type epitaxial layer.

[0034] In an embodiment of the present invention, polysilicon is deposited in a trench having a gate oxide layer to form a polysilicon gate and a polysilicon resistor, including:

[0035] Polysilicon with a first doping concentration is deposited at the bottom of the trench to form a polysilicon gate. The first doping concentration is 1×10 20 cm -3 ~1×10 21 cm -3 ;

[0036] Polysilicon with a second doping concentration is deposited on the surface of the polysilicon gate in the trench to form a polysilicon resistor. The second doping concentration is 1×10 16 cm -3 ~1×10 18 cm -3 .

[0037] In an embodiment of the present invention, ion implantation is performed on the surface of the P-type body region to form a source region, including:

[0038] Performing N-type ion implantation on the surface of the P-type body region and the surface of the polysilicon resistor to form a source region and a first contact terminal;

[0039] P-type ion implantation is performed on the surface of the P-type body region to form a second contact terminal.

[0040] In an embodiment of the present invention, forming a source metal layer includes:

[0041] Depositing silicon dioxide on the body region where the active region, the first contact terminal and the second contact terminal are formed to form an oxide layer;

[0042] Etching the oxide layer to form a contact hole communicating with the source region, the first contact terminal, and the second contact terminal;

[0043] Metal is deposited on the surface of the oxide layer and in the contact hole to form a source metal layer.

[0044] The present invention also provides a chip, which includes the ESD device with the LDMOSFET structure.

[0045] The present invention designs an ESD device based on an LDMOSFET structure, utilizes the high voltage resistance capability of the LDMOSFET device, adds a polysilicon resistor and a capacitor structure consisting of a polysilicon gate, an isolation oxide layer and a drain metal layer to the LDMOSFET structure, and forms a high voltage ESD device equivalent to an RC type ESD protection circuit. There is no need to add resistors and capacitors outside the MOS device, thus reducing the area of ​​the ESD device and improving the high voltage protection capability of the ESD device.

[0046] Other features and advantages of the technical solution of the present invention will be described in detail in the specific implementation section below. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0048] Figure 1 It is an existing gate-coupled RC type ESD protection circuit;

[0049] Figure 2 It is a structural schematic diagram of an ESD device with an LDMOSFET structure provided by an embodiment of the present invention;

[0050] Figure 3 is a flow chart of a method for manufacturing an ESD device of an LDMOSFET structure provided by an embodiment of the present invention;

[0051] Figure 4a It is a schematic structural diagram of an N-type epitaxial layer and a P-type epitaxial layer formed in the manufacturing method provided in an embodiment of the present invention;

[0052] Figure 4b is a schematic structural diagram of a groove formed in a manufacturing method provided in an embodiment of the present invention;

[0053] Figure 4c is a schematic diagram of a structure formed by filling a groove in a manufacturing method provided by an embodiment of the present invention;

[0054] Figure 4d is a schematic diagram of a structure formed after etching the filled trench in the manufacturing method provided by an embodiment of the present invention;

[0055] Figure 4e is a schematic structural diagram of a gate oxide layer formed in a manufacturing method provided in an embodiment of the present invention;

[0056] Figure 4f is a schematic structural diagram of a polysilicon gate and a polysilicon resistor formed in a manufacturing method provided in an embodiment of the present invention;

[0057] Figure 4g is a schematic structural diagram of a source region formed in a manufacturing method provided in an embodiment of the present invention;

[0058] Figure 4h is a schematic structural diagram of a drain region formed in a manufacturing method provided in an embodiment of the present invention;

[0059] Figure 4i is a schematic structural diagram of a back contact hole formed in a manufacturing method provided in an embodiment of the present invention;

[0060] Figure 4j It is a schematic structural diagram of a drain metal layer and a source metal layer formed in the manufacturing method provided in an embodiment of the present invention.

[0061] Description of Reference Numerals

[0062] 101-substrate silicon layer, 102-insulating layer, 103-active silicon layer, 104-oxide layer,

[0063] 11-drift region, 12-body region, 13-gate oxide layer, 14-polysilicon gate,

[0064] 15-polysilicon resistor, 16-isolation oxide layer, 17-first contact terminal, 18-second contact terminal,

[0065] 19 - source region, 20 - source metal layer, 21 - drain region, 22 - drain metal layer, 23 - metal contact terminal. DETAILED DESCRIPTION

[0066] In order to make the technical solutions and advantages of the embodiments of the present invention more clearly understood, the exemplary embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0067] In the description of the present invention, it should be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "side", "bottom", "surface", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. The terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0068] In the present invention, unless otherwise clearly specified and limited, the terms "connected", "connected", "connected" and the like should be understood in a broad sense, for example, it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0069] Figure 2 Schematic diagram of the structure of an ESD device with LDMOSFET structure provided by an embodiment of the present invention. Figure 2 As shown, the ESD device of LDMOSFET structure provided in this embodiment includes: a substrate, a body region 12, a drift region 11, a source region 19, a drain region 21 and a gate structure, wherein the drift region 11 is formed on the surface of the substrate, the body region 12 is formed on the upper surface of the drift region 11, the source region 19 is formed on the upper surface of the body region 12, the drain region 21 is formed on the lower surface of the drift region 11, and the gate structure is formed in the body region 12. The source region 19 is connected to the source metal layer 20, and the source metal layer 20 is grounded; the drain region 21 is connected to the drain metal layer 22, and the drain metal layer 22 serves as an input terminal. The gate structure includes a gate oxide layer 13, a polysilicon gate 14 and a polysilicon resistor 15, wherein the polysilicon gate 14 and the polysilicon resistor 15 are connected to the body region 12 through the gate oxide layer 13, the polysilicon resistor 15 is connected to the source metal layer 20, and the body region 12 is connected to the source metal layer 20. The polysilicon gate 14 is connected to the drain metal layer 22 through the isolation oxide layer 16. The polysilicon gate 14 and the drain metal layer 22 serve as two plates of the capacitor respectively, and the isolation oxide layer 16 serves as a dielectric layer between the plates. The polysilicon gate 14, the isolation oxide layer 16 and the drain metal layer 22 constitute a capacitor structure.

[0070] In this embodiment, the polysilicon gate 14 and the polysilicon resistor 15 are stacked horizontally, and the gate oxide layer 13 is vertically arranged along the side ends of the polysilicon gate 14 and the polysilicon resistor 15, and the gate oxide layer 13 is connected to the side walls of the polysilicon gate 14 and the polysilicon resistor 15. The material of the polysilicon gate 14 is heavily doped polysilicon, and the doping concentration of ions in the heavily doped polysilicon is 1×10 20 cm -3 ~1×10 21 cm -3 The material of the polysilicon resistor 15 is lightly doped polysilicon, and the doping concentration of ions in the lightly doped polysilicon is 1×10 16 cm -3 ~1×10 18 cm -3 .

[0071] In this embodiment, the polysilicon resistor 15 is connected to the source metal layer 20 through the first contact terminal 17, and forms an ohmic contact with the source metal layer 20. The body region 12 is connected to the source metal layer 20 through the second contact terminal 18. The first contact terminal 17 and the two ends adjacent to the source region 19 are covered with an oxide layer 104, and the first contact terminal 17 is connected to the source metal layer 20 through a metal contact hole between the oxide layers 104 on both sides.

[0072] In an optional embodiment, the substrate is a SOI (Silicon On Insulator) substrate, the SOI substrate includes a substrate silicon layer 101, an insulating layer 102 and an active silicon layer 103, the drift region 11 is formed on the upper surface of the active silicon layer 103, and the active silicon layer 103 constitutes the drain region 21 of the device. The drain metal layer 22 is formed on the lower surface of the active silicon layer 103. The drain metal layer 22 includes a metal contact terminal 23, the metal contact terminal 23 is connected to the isolation oxide layer 16, the metal contact terminal 23 serves as the lower plate of the capacitor, the polysilicon gate 14 serves as the upper plate of the capacitor, and the polysilicon gate 14, the isolation oxide layer 16 and the metal contact terminal 23 constitute a capacitor structure.

[0073] The present invention designs an ESD device based on an LDMOSFET structure, utilizes the high voltage resistance capability of the LDMOSFET device, adds a polysilicon resistor and a capacitor structure consisting of a polysilicon gate, an isolation oxide layer and a drain metal layer to the LDMOSFET structure, and forms a high voltage ESD device equivalent to an RC type ESD protection circuit. There is no need to add resistors and capacitors outside the MOS device, thus reducing the area of ​​the ESD device and improving the high voltage protection capability of the ESD device.

[0074] The embodiment of the present invention also provides a method for manufacturing the ESD device with the LDMOSFET structure. The method adopts an SOI substrate, and the SOI substrate includes a substrate silicon layer, an insulating layer, and an N-type active silicon layer.

[0075] like Figure 3 As shown, the method comprises the following steps:

[0076] S301, performing epitaxy twice on the surface of the SOI substrate to form an N-type epitaxial layer and a P-type epitaxial layer;

[0077] S302, etching the N-type epitaxial layer, the P-type epitaxial layer and the SOI substrate until the insulating layer of the SOI substrate is exposed to form a trench;

[0078] S303, filling the trench with oxide, and etching the oxide filled in the trench to expose the P-type epitaxial layer on the sidewall of the trench;

[0079] S304, performing oxidation treatment on the P-type epitaxial layer on the sidewall of the trench to form a gate oxide layer connected to the P-type epitaxial layer on the sidewall of the trench, and the remaining N-type epitaxial layer is used as an N-type drift region, and the remaining P-type epitaxial layer is used as a P-type body region;

[0080] S305, depositing polysilicon in the trench with the gate oxide layer to form a polysilicon gate and a polysilicon resistor;

[0081] S306, performing ion implantation on the surface of the P-type body region to form a source region;

[0082] S307, removing the substrate silicon layer and the insulating layer of the SOI substrate to expose the oxide filled in the trench, and the remaining N-type active silicon layer is used as a drain region;

[0083] S308, etching the oxide in the trench to form a contact hole, and the remaining oxide in the trench serves as an isolation oxide layer;

[0084] S309, depositing metal in the contact hole of the trench and on the surface of the trench to form a drain metal layer, and at the same time forming a source metal layer.

[0085] In a specific embodiment, in the above step S301, the SOI substrate includes a substrate silicon layer 101, an insulating layer 102 and an N-type active silicon layer 103, N-type silicon is epitaxially grown on the surface of the N-type active silicon layer 103 of the SOI substrate to form an N-type epitaxial layer (corresponding to the N-type drift region 11), and P-type silicon is epitaxially grown on the surface of the N-type epitaxial layer to form a P-type epitaxial layer (corresponding to the P-type body region 12), forming the following: Figure 4a The N-type epitaxial layer is used to form an N-type drift region 11, and the P-type epitaxial layer is used to form a P-type body region 12.

[0086] In a specific embodiment, in the above step S302, a thin layer of silicon dioxide SiO is thermally oxidized on the surface of the P-type epitaxial layer. 2 Then, photoresist is applied, photolithography is performed, and the thin silicon dioxide on the surface and the P-type epitaxial layer 12, the N-type epitaxial layer 11, and the N-type active silicon layer 103 below are dry-etched until the insulating layer 102 of the SOI substrate is exposed, forming a Figure 4b Grooves shown.

[0087] In a specific embodiment, in the above step S303, the photoresist is removed, and silicon dioxide SiO is filled in the groove by chemical vapor deposition (CVD) method. 2 , CMP polishes the excess SiO 2 Since the insulating layer 102 of the SOI substrate is silicon dioxide SiO 2 At this time, SiO 2 The SiO filled in the trench 2 Together they form Figure 4c The oxide layer 104 is shown. Then, photoresist is applied, photolithography is performed, and the SiO2 in the groove is dry-etched. 2 , etching depth to the thickness of the P-type epitaxial layer 12, completely exposing the P-type epitaxial layer on the sidewall of the trench, and then removing the photoresist to form a Figure 4d The structure shown.

[0088] In a specific embodiment, in the above step S304, the P-type epitaxial layer on the sidewall of the trench is thermally oxidized to form a vertical gate oxide layer 13 on the sidewall of the trench, wherein the remaining N-type epitaxial layer serves as the N-type drift region 11, and the remaining P-type epitaxial layer serves as the P-type body region 12, forming a gate oxide layer 13 having a gate structure 14 and a gate structure 15 having a gate structure 16. Figure 4e The structure shown.

[0089] In a specific embodiment, in the above step S305, a low pressure chemical vapor deposition (LPCVD) method is used to deposit polysilicon with a first doping concentration at the bottom of the trench with the gate oxide layer 13 to form a polysilicon gate 14, and a polysilicon with a second doping concentration is deposited on the surface of the polysilicon gate 14 to form a polysilicon resistor 15. The first doping concentration is 1×10 20 cm -3 ~1×10 21 cm -3 , the second doping concentration is 1×10 16 cm -3 ~1×10 18 cm -3 Then, CMP smoothes the excess polysilicon on the surface to form Figure 4f The structure shown.

[0090] In a specific embodiment, in the above step S306, the SiO 2 , respectively, photolithography, forming an ion implantation window on the surface of the P-type body region 12, respectively performing N-type heavily doped ion implantation and P-type heavily doped ion implantation, then removing the photoresist, and performing annealing treatment to form Figure 4g The N+ region and P+ region shown. The N+ region on the surface of the P-type body region 12 is used as the source region 19, the N+ region on the surface of the polysilicon resistor 15 is used as the first contact terminal 17 for the ohmic contact between the polysilicon resistor 15 and the subsequent source metal layer, and the P+ region on the surface of the P-type body region 12 is used as the second contact terminal 18 for the connection between the P-type body region 12 and the subsequent source metal layer.

[0091] In a specific embodiment, in the above step S307, a layer of silicon dioxide SiO2 having a thickness of 1000 Å is deposited on the P-type body region 12 forming the active region N+, the first contact terminal N+ and the second contact terminal P+ by using a chemical vapor deposition (CVD) method. 2 , forming an oxide layer 104 above the source region. Etching the oxide layer 104 above the source region forms a front contact hole, which is connected to the source region N+, the first contact terminal N+, and the second contact terminal P+. Then, the substrate silicon layer 101 and the insulating layer 102 on the back of the SOI substrate are removed to expose the SiO2 filled in the trench. 2 The remaining N-type active silicon layer 103 is used as the drain region 21 to form a Figure 4hThe structure shown.

[0092] In a specific embodiment, in the above step S308, the SiO 2 Perform photolithography and dry etch the SiO in the groove 2 , forming a contact hole on the back side, and the remaining SiO 2 As the isolation oxide layer 16, a Figure 4i The structure shown.

[0093] In a specific embodiment, in the above step S309, metal is deposited in the contact hole on the back side and on the lower surface of the trench to form a drain metal layer 22, and metal is deposited in the contact hole on the front side to form a source metal layer 20, so as to form Figure 4j In this structure, the metal filled in the contact hole serves as the metal contact terminal 23, and the polysilicon gate 14, the isolation oxide layer 16 and the metal contact terminal 23 form a capacitor structure to form an ESD device of LDMOSFET structure.

[0094] An embodiment of the present invention further provides a chip, which includes the ESD device with the above-mentioned LDMOSFET structure, and electrostatic protection for integrated circuits in the chip is achieved through the ESD device.

[0095] The optional embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the technical concept of the embodiments of the present invention, a variety of simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all belong to the protection scope of the embodiments of the present invention. It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction, and as long as the combination does not violate the concept of the embodiments of the present invention, it should also be regarded as the content disclosed in the embodiments of the present invention.

Claims

1. An ESD device with an LDMOSFET structure, comprising: A substrate, a body region, a drift region, a source region, a drain region and a gate structure, wherein the drift region is formed on the surface of the substrate, the body region is formed on the upper surface of the drift region, the source region is formed on the upper surface of the body region, the drain region is formed on the lower surface of the drift region, and the gate structure is formed in the body region; The source region is connected to a source metal layer, and the source metal layer is grounded; The drain region is connected to a drain metal layer, and the drain metal layer serves as an input terminal; The gate structure includes a gate oxide layer, a polysilicon gate and a polysilicon resistor, and the polysilicon gate and the polysilicon resistor are connected to the body region through the gate oxide layer; The polysilicon resistor is connected to the source metal layer, and the body region is connected to the source metal layer; The polysilicon gate is connected to the drain metal layer through an isolation oxide layer, and the polysilicon gate, the isolation oxide layer and the drain metal layer form a capacitor structure.

2. The ESD device of the LDMOSFET structure according to claim 1, characterized in that: The polysilicon gate and the polysilicon resistor are stacked laterally, and the gate oxide layer is vertically arranged along the side ends of the polysilicon gate and the polysilicon resistor.

3. The ESD device of the LDMOSFET structure according to claim 1, characterized in that: The material of the polysilicon gate is heavily doped polysilicon, and the doping concentration of ions in the heavily doped polysilicon is 1×10 20 cm -3 ~1×10 21 cm -3 ; The material of the polysilicon resistor is lightly doped polysilicon, and the doping concentration of ions in the lightly doped polysilicon is 1×10 16 cm -3 ~1×10 18 cm -3 .

4. The ESD device of the LDMOSFET structure according to claim 1, characterized in that: The polysilicon resistor is connected to the source metal layer through a first contact terminal.

5. The ESD device of the LDMOSFET structure according to claim 1, characterized in that: The body region is connected to the source metal layer through a second contact terminal.

6. The ESD device of the LDMOSFET structure according to claim 1, characterized in that: The substrate is an SOI substrate, which includes a substrate silicon layer, an insulating layer and an active silicon layer; The drift region is formed on the upper surface of the active silicon layer; The drain region is formed by the active silicon layer.

7. The ESD device of the LDMOSFET structure according to claim 6, characterized in that: The drain metal layer is formed on the lower surface of the active silicon layer.

8. The ESD device of the LDMOSFET structure according to claim 7, characterized in that: The drain metal layer includes a metal contact terminal, the metal contact terminal is connected to the isolation oxide layer, and the metal contact terminal, the isolation oxide layer and the polysilicon gate constitute a capacitor structure.

9. A method for manufacturing an ESD device of LDMOSFET structure, characterized in that: include: Performing epitaxy twice on the surface of an SOI substrate to form an N-type epitaxial layer and a P-type epitaxial layer, wherein the SOI substrate comprises a substrate silicon layer, an insulating layer and an N-type active silicon layer; Etching the N-type epitaxial layer, the P-type epitaxial layer and the SOI substrate until the insulating layer of the SOI substrate is exposed to form a trench; Filling the trench with oxide, and etching the oxide filled in the trench to expose the P-type epitaxial layer on the side wall of the trench; The P-type epitaxial layer on the sidewall of the trench is oxidized to form a gate oxide layer connected to the P-type epitaxial layer on the sidewall of the trench, and the remaining N-type epitaxial layer is used as an N-type drift region, and the remaining P-type epitaxial layer is used as a P-type body region; Depositing polysilicon in the trench with the gate oxide layer to form a polysilicon gate and a polysilicon resistor; Ion implantation is performed on the surface of the P-type body region to form a source region; The substrate silicon layer and the insulating layer of the SOI substrate are removed to expose the oxide filled in the trench, and the remaining N-type active silicon layer is used as the drain region; Etching the oxide in the trench to form a contact hole, and the remaining oxide in the trench serves as an isolation oxide layer; Metal is deposited in the contact hole of the trench and on the surface of the trench to form a drain metal layer, and a source metal layer is formed at the same time.

10. The method for manufacturing an ESD device with an LDMOSFET structure according to claim 9, characterized in that: Performing epitaxy twice on the surface of the SOI substrate to form an N-type epitaxial layer and a P-type epitaxial layer, including: Epitaxially growing N-type silicon on the surface of the N-type active silicon layer of the SOI substrate to form an N-type epitaxial layer; P-type silicon is epitaxially grown on the surface of the N-type epitaxial layer to form a P-type epitaxial layer.

11. The method for manufacturing an ESD device with an LDMOSFET structure according to claim 9, characterized in that: Polysilicon is deposited in the trench with the gate oxide layer to form a polysilicon gate and a polysilicon resistor, including: Polysilicon with a first doping concentration is deposited at the bottom of the trench to form a polysilicon gate. The first doping concentration is 1×10 20 cm -3 ~1×10 21 cm -3 ; Polysilicon with a second doping concentration is deposited on the surface of the polysilicon gate in the trench to form a polysilicon resistor. The second doping concentration is 1×10 16 cm -3 ~1×10 18 cm -3 .

12. The method for manufacturing an ESD device with an LDMOSFET structure according to claim 9, characterized in that: Ion implantation is performed on the surface of the P-type body region to form a source region, including: Performing N-type ion implantation on the surface of the P-type body region and the surface of the polysilicon resistor to form a source region and a first contact terminal; P-type ion implantation is performed on the surface of the P-type body region to form a second contact terminal.

13. The method for manufacturing an ESD device with an LDMOSFET structure according to claim 12, characterized in that: Forming a source metal layer, including: Depositing silicon dioxide on the body region where the active region, the first contact terminal and the second contact terminal are formed to form an oxide layer; Etching the oxide layer to form a contact hole communicating with the source region, the first contact terminal, and the second contact terminal; Metal is deposited on the surface of the oxide layer and in the contact hole to form a source metal layer.

14. A chip, characterized in that: The chip comprises an ESD device with an LDMOSFET structure as claimed in any one of claims 1 to 8.

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