ESD device of LDMOSFET structure, manufacturing method and chip

Abstract

The invention relates to the technical field of semiconductors, and provides an ESD device of an LDMOSFET structure, a manufacturing method and a chip. The device comprises a substrate, a body region, a drift region, a source region, a drain region and a gate structure, the gate structure is formed above the body region and the drift region, and the gate structure comprises a polycrystalline silicon gate, an insulating dielectric layer and a polycrystalline silicon resistor which are sequentially stacked from bottom to top; the source region is connected with the source metal layer, and the drain region is connected with the drain metal layer; the polycrystalline silicon resistor is connected with the source electrode metal layer through a first contact end, and the body region is connected with the source electrode metal layer through a second contact end; a silicon nitride side wall is arranged on the side face of the polycrystalline silicon grid electrode, the silicon nitride side wall is connected with the drain electrode metal layer, and the polycrystalline silicon grid electrode, the silicon nitride side wall and the drain electrode metal layer form a capacitor structure. The polycrystalline silicon resistor and the capacitor structure are connected in parallel to form a high-voltage ESD device equivalent to an RC type ESD protection circuit, the area of the device is reduced, and the high-voltage protection capability of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an ESD device with an LDMOSFET structure and a manufacturing method and a chip. Background Art

[0002] ESD (Electrostatic Discharge) refers to the charge transfer caused by objects with different electrostatic potentials approaching or directly contacting each other. When the static charge accumulated in the external environment of the IC (integrated circuit) chip or inside the IC chip flows into or out through the chip pins, the instantaneous ESD current will damage the thick gate oxide and metal wires of the internal devices of the chip, thereby causing device failure. With the continuous improvement of the process technology of very large-scale integrated circuits, complementary metal oxide semiconductor (CMOS) integrated circuits have entered the ultra-deep submicron stage, the size of MOS devices has been continuously reduced, and the harm of electrostatic discharge (ESD) to integrated circuits has become more and more significant, requiring ESD protection design for integrated circuits.

[0003] The prior art uses ESD circuits to protect integrated circuits from electrostatic discharge. Figure 1 It is an RC type ESD protection circuit using gate coupling technology. By constantly adjusting the size of capacitor Cn and resistor Rn, a suitable voltage can be coupled to the gate of NMOS device Mn1 under high ESD stress, thereby reducing the turn-on voltage of NMOS and achieving electrostatic protection. For NMOS and PMOS, if the bias voltage coupled to the gate is high, it will cause more channel current and higher electric field, making the thin gate oxide layer easy to be damaged, and the robustness of its ESD protection will decrease rapidly. However, in power management chips in the power field, the voltage can reach several thousand volts or even tens of thousands of volts when static electricity is released. This ESD circuit is difficult to achieve high-voltage electrostatic protection. In addition, the ESD circuit is connected to the capacitor and resistor outside the NMOS or PMOS device. The ESD circuit occupies a large area, which is not conducive to the miniaturization and integration of the chip. Summary of the invention

[0004] In order to solve the above technical problems, the present invention provides an ESD device with an LDMOSFET structure and a manufacturing method thereof.

[0005] On one hand, the present invention provides an ESD device of LDMOSFET structure, comprising: a substrate, a body region, a drift region, a source region, a drain region and a gate structure, wherein the body region and the drift region are formed in the substrate, the source region is formed on the surface of the body region, the drain region is formed on the surface of the drift region, and the gate structure is formed above the body region and the drift region;

[0006] The gate structure includes a polysilicon gate, an insulating dielectric layer and a polysilicon resistor stacked in sequence from bottom to top;

[0007] The source region is connected to the source metal layer, and the drain region is connected to the drain metal layer;

[0008] The polysilicon resistor is connected to the source metal layer via a first contact terminal, and the body region is connected to the source metal layer via a second contact terminal;

[0009] A silicon nitride sidewall is disposed on the side of the polysilicon gate, the silicon nitride sidewall is connected to the drain metal layer, and the polysilicon gate, the silicon nitride sidewall and the drain metal layer form a capacitor structure.

[0010] In an embodiment of the present invention, the gate structure further includes a gate oxide layer, and the gate oxide layer is connected to the lower surface of the polysilicon gate.

[0011] In the embodiment of the present invention, the upper surface of the polysilicon gate is connected to the lower surface of the insulating dielectric layer, and the upper surface of the insulating dielectric layer is connected to the lower surface of the polysilicon resistor;

[0012] The sidewall of the polysilicon gate, the sidewall of the insulating dielectric layer and the sidewall of the polysilicon resistor are all connected to the silicon nitride sidewall.

[0013] In the embodiment of the present invention, the material of the polysilicon gate is heavily doped polysilicon, and the doping concentration of ions in the heavily doped polysilicon is 1×10 20 cm -3 ~1×10 21 cm -3 ;

[0014] The material of the polysilicon resistor is lightly doped polysilicon, and the doping concentration of ions in the lightly doped polysilicon is 1×10 16 cm -3 ~1×10 18 cm -3 ;

[0015] The material of the insulating dielectric layer is undoped polysilicon or silicon dioxide.

[0016] In an embodiment of the present invention, the first contact terminal is located on the surface of the polysilicon resistor, and the polysilicon resistor is connected to the source metal layer through the first contact terminal to form an ohmic contact with the source metal layer;

[0017] The second contact terminal is located on the surface of the body region, and the body region is connected to the source metal layer through the second contact terminal.

[0018] In the embodiment of the present invention, it also includes an N-type well region and a P-type well region, and the N-type well region is located below the body region and the drift region;

[0019] An N+ contact terminal is arranged on the surface of the N-type well region, and a power supply voltage is connected through the N+ contact terminal;

[0020] A P+ contact terminal is arranged on the surface of the P-type well region, and is connected to the ground through the P+ contact terminal.

[0021] In an embodiment of the present invention, a field plate structure is further included. The field plate structure includes a shallow trench isolation region. The shallow trench isolation region is formed in the drift region.

[0022] The present invention also provides a method for manufacturing the ESD device of the LDMOSFET structure, comprising:

[0023] forming a body region and a drift region in a substrate;

[0024] A gate oxide layer is formed above the body region and the drift region, and a polysilicon gate, an insulating dielectric layer and a polysilicon resistor are sequentially formed on the surface of the gate oxide layer;

[0025] A source region is formed on the surface of the body region, a drain region is formed on the surface of the drift region, a first contact terminal is formed on the surface of the polysilicon resistor, and a second contact terminal is formed on the surface of the body region;

[0026] forming a silicon nitride sidewall on the side of the polysilicon gate;

[0027] An isolation oxide layer is formed above the body region, the drift region and the polysilicon resistor, and the isolation oxide layer is etched to form a plurality of contact holes, wherein the plurality of contact holes are respectively connected to the source region, the drain region, the first contact terminal and the second contact terminal;

[0028] Metal is deposited in the contact hole to form a drain metal layer and a source metal layer.

[0029] In an embodiment of the present invention, a body region and a drift region are formed in a substrate, including:

[0030] P-type ion implantation and N-type ion implantation are performed on the surface of the substrate respectively, and high-temperature driving is performed to form a P-type body region and an N-type drift region.

[0031] In an embodiment of the present invention, a polysilicon gate, an insulating dielectric layer and a polysilicon resistor are sequentially formed on the surface of a gate oxide layer, including:

[0032] Polysilicon with a first doping concentration is deposited on the surface of the gate oxide layer to form a polysilicon gate. The first doping concentration is 1×10 20 cm -3 ~1×10 21 cm -3 ;

[0033] Depositing undoped polysilicon on the surface of the polysilicon gate to form an insulating dielectric layer;

[0034] Polysilicon with a second doping concentration is deposited on the surface of the insulating dielectric layer to form a polysilicon resistor. The second doping concentration is 1×10 16 cm -3 ~1×10 18 cm -3 .

[0035] In the embodiment of the present invention, a source region is formed on the surface of the body region, a drain region is formed on the surface of the drift region, a first contact terminal is formed on the surface of the polysilicon resistor, and a second contact terminal is formed on the surface of the body region, including:

[0036] Performing photolithography on the surface of the body region, the surface of the drift region and the surface of the polysilicon resistor respectively to form ion implantation windows, and implanting N-type ions into the ion implantation windows to form a source region, a drain region and a first contact terminal;

[0037] P-type ions are implanted into the ion implantation window of the body region to form a second contact terminal.

[0038] In an embodiment of the present invention, a silicon nitride sidewall is formed on a side of a polysilicon gate, comprising:

[0039] Silicon nitride is deposited on the side walls of the polysilicon gate, the insulating dielectric layer and the polysilicon resistor, and then etched to form silicon nitride sidewalls.

[0040] In an embodiment of the present invention, depositing metal in the contact hole to form a drain metal layer and a source metal layer includes:

[0041] Using a physical vapor deposition process, metal is deposited in the contact hole to form a metal layer;

[0042] The metal layer is etched to form a drain metal layer and a source metal layer, and the body region, the source region and the polysilicon resistor are interconnected through the source metal layer.

[0043] In an embodiment of the present invention, the method for manufacturing the ESD device with the LDMOSFET structure further includes:

[0044] When forming the P-type body region and the N-type drift region, the N-type well region and the P-type well region are formed simultaneously;

[0045] A shallow trench isolation region is formed on the surface of the N-type drift region and the surface of the N-type well region.

[0046] The present invention also provides a chip, which includes the ESD device with the LDMOSFET structure.

[0047] The present invention designs an ESD device based on an LDMOSFET structure, utilizes the ability of the LDMOSFET device to resist high voltage, adds a polysilicon resistor and a capacitor structure composed of a polysilicon gate, a silicon nitride sidewall and a drain metal layer to the LDMOSFET structure, and forms a high-voltage ESD device equivalent to an RC-type ESD protection circuit, without adding resistors and capacitors outside the MOS device, reducing the area of ​​the ESD device and improving the high-voltage protection capability of the ESD device. In addition, the polysilicon resistor and the polysilicon gate are stacked to reduce the area occupied by the RC-type gate structure, further reducing the device area.

[0048] Other features and advantages of the technical solution of the present invention will be described in detail in the specific implementation section below. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0050] Figure 1 It is an existing gate-coupled RC type ESD protection circuit;

[0051] Figure 2 It is a structural schematic diagram of an ESD device with an LDMOSFET structure provided by an embodiment of the present invention;

[0052] Figure 3 is a flow chart of a method for manufacturing an ESD device of an LDMOSFET structure provided by an embodiment of the present invention;

[0053] Figure 4a is a schematic structural diagram of a body region and a drift region formed in a manufacturing method provided in an embodiment of the present invention;

[0054] Figure 4b is a schematic structural diagram of a shallow trench isolation region formed in a manufacturing method provided in an embodiment of the present invention;

[0055] Figure 4c is a schematic diagram of a gate structure formed in a manufacturing method provided in an embodiment of the present invention;

[0056] Figure 4d It is a schematic structural diagram of a source region, a drain region and a contact terminal formed by ion implantation in a manufacturing method provided in an embodiment of the present invention;

[0057] Figure 4e is a schematic structural diagram of a silicon nitride sidewall formed in a manufacturing method provided in an embodiment of the present invention;

[0058] Figure 4fis a schematic structural diagram of an isolation oxide layer formed in a manufacturing method provided in an embodiment of the present invention;

[0059] Figure 4g It is a schematic structural diagram of a source metal layer and a drain metal layer formed in the manufacturing method provided in an embodiment of the present invention.

[0060] Description of Reference Numerals

[0061] 10-substrate, 11-body region, 12-drift region, 13-well region, 14-shallow trench isolation region,

[0062] 15-gate oxide layer, 16-polysilicon gate, 17-insulating dielectric layer, 18-polysilicon resistor,

[0063] 19 - silicon nitride sidewall, 20 - first contact terminal, 21 - second contact terminal, 22 - source region, 23 - drain region, 24 - isolation oxide layer, 25 - source metal layer, 26 - drain metal layer. DETAILED DESCRIPTION

[0064] In order to make the technical solutions and advantages of the embodiments of the present invention more clearly understood, the exemplary embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0065] In the description of the present invention, it should be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "side", "bottom", "surface", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. The terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0066] In the present invention, unless otherwise clearly specified and limited, the terms "connected", "connected", "connected" and the like should be understood in a broad sense, for example, it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0067] Figure 2 Schematic diagram of the structure of an ESD device with LDMOSFET structure provided by an embodiment of the present invention. Figure 2 As shown, the ESD device of the LDMOSFET structure provided in this embodiment includes: a substrate 10, a body region 11, a drift region 12, a source region 22, a drain region 23 and a gate structure, wherein the body region 11 and the drift region 12 are formed in the substrate 10, the source region 22 is formed on the surface of the body region 11, the drain region 23 is formed on the surface of the drift region 12, and the gate structure is formed above the body region 11 and the drift region 12. The gate structure includes a polysilicon gate 16, an insulating dielectric layer 17 and a polysilicon resistor 18 stacked in sequence from bottom to top. The source region 22 is connected to a source metal layer 25, and the source metal layer 25 is grounded. The drain region 23 is connected to a drain metal layer 26, and the drain metal layer 26 serves as an input terminal. The polysilicon resistor 18 is connected to the source metal layer 25 through a first contact terminal 20, and the body region 11 is connected to the source metal layer 25 through a second contact terminal 21. A silicon nitride sidewall 19 is provided on the side of the polysilicon gate 16, and the silicon nitride sidewall 19 is connected to the drain metal layer 26. The polysilicon gate 16 is connected to the drain metal layer 26 through the silicon nitride sidewall 19. The polysilicon gate 16 and the drain metal layer 26 serve as two plates of the capacitor respectively, and the silicon nitride sidewall 19 serves as a dielectric layer between the plates. The polysilicon gate 16, the silicon nitride sidewall 19 and the drain metal layer 26 constitute a capacitor structure.

[0068] In this embodiment, the gate structure further includes a gate oxide layer 15, and the gate oxide layer 15 is connected to the lower surface of the polysilicon gate 16. The upper surface of the polysilicon gate 16 is connected to the lower surface of the insulating dielectric layer 17, and the upper surface of the insulating dielectric layer 17 is connected to the lower surface of the polysilicon resistor 18. The sidewalls of the polysilicon gate 16, the sidewalls of the insulating dielectric layer 17, and the sidewalls of the polysilicon resistor 18 are all connected to the silicon nitride sidewall 19. The material of the polysilicon gate 16 is heavily doped polysilicon, and the doping concentration of ions in the heavily doped polysilicon is 1×10 20 cm -3 ~1×10 21 cm -3 The material of the polysilicon resistor 18 is lightly doped polysilicon, and the doping concentration of ions in the lightly doped polysilicon is 1×10 16 cm -3 ~1×10 18 cm -3The material of the insulating dielectric layer 17 is undoped polysilicon or silicon dioxide.

[0069] In this embodiment, the first contact terminal 20 is located on the surface of the polysilicon resistor 18, the first contact terminal 20 is connected to the source metal layer 25, the polysilicon resistor 18 is connected to the source metal layer 25 through the first contact terminal 20, and forms an ohmic contact with the source metal layer 25. The second contact terminal 21 is located on the surface of the body region 11, the second contact terminal 21 is connected to the source metal layer 25, and the body region 11 is connected to the source metal layer 25 through the second contact terminal 21. An isolation oxide layer 24 is formed on the surface of the polysilicon resistor 18, a part of the surface of the drain region 23, and a part of the surface of the second contact terminal 21, and the source metal layer 25 is isolated from the drain metal layer 26 by the isolation oxide layer 24.

[0070] In a specific embodiment, the silicon nitride sidewall 19 can be formed only on the right side of the polysilicon gate 16, or only on the right side of the polysilicon gate 16, the insulating dielectric layer 17 and the polysilicon resistor 18, and the silicon nitride sidewall 19 on the left side is not necessary.

[0071] In an optional embodiment, the ESD device of the LDMOSFET structure further includes a well region 13. An N-type well region 13 may be formed below the P-type body region 11 and the N-type drift region 12, and an additional P-type well region 13 may be provided. An N+ contact terminal is provided on the surface of the N-type well region 13 on the left, and a power supply voltage (VDD) is connected through the N+ contact terminal. A P+ contact terminal is provided on the surface of the P-type well region 13 on the right, and a ground (Ground) is connected through the P+ contact terminal.

[0072] In an optional embodiment, the ESD device of the LDMOSFET structure further includes a field plate structure, which includes an STI (shallow trench isolation) shallow trench isolation region 14, and the shallow trench isolation region 14 is formed on the surface of the N-type drift region 12 and the surface of the N-type well region 13. The field plate structure can increase the breakdown voltage of the ESD device and improve the high-voltage protection capability of the ESD device.

[0073] The present invention designs an ESD device based on an LDMOSFET structure, utilizes the ability of the LDMOSFET device to resist high voltage, adds a polysilicon resistor and a capacitor structure composed of a polysilicon gate, a silicon nitride sidewall and a drain metal layer to the LDMOSFET structure, and connects the polysilicon resistor and the capacitor structure in parallel to form a high-voltage ESD device equivalent to an RC-type ESD protection circuit, without adding resistors and capacitors outside the MOS device, reducing the area of ​​the ESD device and improving the high-voltage protection capability of the ESD device. In addition, the polysilicon resistor and the polysilicon gate are stacked to reduce the area occupied by the RC-type gate structure, further reducing the device area.

[0074] The embodiment of the present invention also provides a method for manufacturing the ESD device of the LDMOSFET structure. Figure 3 As shown, the method comprises the following steps:

[0075] S301, forming a body region and a drift region in a substrate;

[0076] S302, forming a gate oxide layer above the body region and the drift region, and sequentially forming a polysilicon gate, an insulating dielectric layer and a polysilicon resistor on the surface of the gate oxide layer;

[0077] S303, forming a source region on the surface of the body region, forming a drain region on the surface of the drift region, forming a first contact terminal on the surface of the polysilicon resistor, and forming a second contact terminal on the surface of the body region;

[0078] S304, forming a silicon nitride sidewall on the side of the polysilicon gate;

[0079] S305, forming an isolation oxide layer on the body region, the drift region and the polysilicon resistor, and etching the isolation oxide layer to form a plurality of contact holes;

[0080] S306, depositing metal in the contact hole to form a drain metal layer and a source metal layer.

[0081] In a specific embodiment, in the above step S301, a P-type silicon substrate is selected, and a thin oxide layer is formed on the surface of the P-type silicon substrate. P-type ion implantation and N-type ion implantation are performed on the surface of the P-type silicon substrate 10, and high temperature driving is performed to form Figure 4a The P-type body region 11 and the N-type drift region 12 are shown.

[0082] In an optional embodiment, when forming the P-type body region 11 and the N-type drift region 12, the N-type well region 13 below the P-type body region 11 and the N-type drift region 12, and the P-type well region 13 on the right are formed at the same time. Then, according to the standard STI (shallow trench isolation, shallow trench isolation) process, a shallow trench isolation region 14 is formed on the surface of the N-type drift region 12 and the surface of the N-type well region 13, forming a Figure 4b The structure shown.

[0083] In a specific embodiment, in the above step S302, a gate oxide layer 15 is formed above the P-type body region 11 and the N-type drift region 12, and then a low pressure chemical vapor deposition (LPCVD) method is used to deposit polysilicon with a first doping concentration on the surface of the gate oxide layer 15 to form a polysilicon gate 16. The first doping concentration is 1×10 20 cm -3 ~1×10 21 cm -3Next, undoped polysilicon is deposited on the surface of the polysilicon gate 16, or silicon dioxide (SiO 2 ), forming an insulating dielectric layer 17; then, polysilicon with a second doping concentration is deposited on the surface of the insulating dielectric layer 17 to form a polysilicon resistor 18, wherein the second doping concentration is 1×10 16 cm -3 ~1×10 18 cm -3 , forming Figure 4c The structure shown.

[0084] In a specific embodiment, in the above step S303, photolithography is performed on the surface of the P-type body region 11, the surface of the N-type drift region 12, and the surface of the polysilicon resistor 18 to form an ion implantation window, N-type ions are implanted in the ion implantation window, and annealing is performed to form a source region N+ on the surface of the P-type body region 11, a drain region N+ on the surface of the N-type drift region 12, and a contact terminal N+ on the surface of the polysilicon resistor 18; P-type ions are implanted in the ion implantation window of the P-type body region 11 to form a contact terminal P+ on the surface of the P-type body region 11, and the like is formed. Figure 4d The structure shown.

[0085] In a specific embodiment, in the above step S304, a low pressure chemical vapor deposition (LPCVD) method is used. Figure 4d Silicon nitride (SiN) is deposited on the surface of the structure shown in the figure, and then the silicon nitride is dry-etched to retain the silicon nitride on the sidewalls of the polysilicon gate 16, the insulating dielectric layer 17 and the polysilicon resistor 18, forming a structure as shown in FIG. Figure 4e The silicon nitride spacer 19 is shown.

[0086] In a specific embodiment, the contact terminal N+ on the surface of the polysilicon resistor 18 formed in the above step S303 is used as the first contact terminal 20, and the contact terminal P+ on the surface of the P-type body region 11 is used as the second contact terminal 21. In step S305, silicon dioxide (SiO2) is deposited on the P-type body region 11, the N-type drift region 12 and the polysilicon resistor 18. 2 ), forming an isolation oxide layer 24, and etching the isolation oxide layer 24 to form a plurality of contact holes, wherein the plurality of contact holes are respectively connected to the source region 22, the drain region 23, the first contact terminal 20 and the second contact terminal 21, forming a Figure 4f The structure shown.

[0087] In a specific embodiment, in the above step S306, a physical vapor deposition (PVD) process is used to deposit metal in the contact hole to form a metal layer, and the metal layer is etched to form a source metal layer 25 and a drain metal layer 26. The body region 11, the source region 22 and the polysilicon resistor 18 are interconnected through the source metal layer 25 to form a Figure 4g The structure shown in FIG. 1 is used to obtain an ESD device with an LDMOSFET structure.

[0088] An embodiment of the present invention further provides a chip, which includes the ESD device with the above-mentioned LDMOSFET structure, and electrostatic protection for integrated circuits in the chip is achieved through the ESD device.

[0089] The optional embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the technical concept of the embodiments of the present invention, a variety of simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all belong to the protection scope of the embodiments of the present invention. It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction, and as long as the combination does not violate the concept of the embodiments of the present invention, it should also be regarded as the content disclosed in the embodiments of the present invention.

Claims

1. An ESD device with an LDMOSFET structure, comprising: A substrate, a body region, a drift region, a source region, a drain region and a gate structure, wherein the body region and the drift region are formed in the substrate, the source region is formed on the surface of the body region, the drain region is formed on the surface of the drift region, and the gate structure is formed above the body region and the drift region; The gate structure includes a polysilicon gate, an insulating dielectric layer and a polysilicon resistor stacked in sequence from bottom to top; The source region is connected to the source metal layer, and the drain region is connected to the drain metal layer; The polysilicon resistor is connected to the source metal layer via a first contact terminal, and the body region is connected to the source metal layer via a second contact terminal; A silicon nitride sidewall is disposed on the side of the polysilicon gate, the silicon nitride sidewall is connected to the drain metal layer, and the polysilicon gate, the silicon nitride sidewall and the drain metal layer form a capacitor structure.

2. The ESD device of the LDMOSFET structure according to claim 1, characterized in that: The gate structure further includes a gate oxide layer, and the gate oxide layer is connected to the lower surface of the polysilicon gate.

3. The ESD device of the LDMOSFET structure according to claim 2, characterized in that: The upper surface of the polysilicon gate is connected to the lower surface of the insulating dielectric layer, and the upper surface of the insulating dielectric layer is connected to the lower surface of the polysilicon resistor; The sidewall of the polysilicon gate, the sidewall of the insulating dielectric layer and the sidewall of the polysilicon resistor are all connected to the silicon nitride sidewall.

4. The ESD device of the LDMOSFET structure according to claim 1, characterized in that: The material of the polysilicon gate is heavily doped polysilicon, and the doping concentration of ions in the heavily doped polysilicon is 1×10 20 cm -3 ~1×10 21 cm -3 ; The material of the polysilicon resistor is lightly doped polysilicon, and the doping concentration of ions in the lightly doped polysilicon is 1×10 16 cm -3 ~1×10 18 cm -3 ; The material of the insulating dielectric layer is undoped polysilicon or silicon dioxide.

5. The ESD device of the LDMOSFET structure according to claim 1, characterized in that: The first contact terminal is located on the surface of the polysilicon resistor, and the polysilicon resistor is connected to the source metal layer through the first contact terminal to form an ohmic contact with the source metal layer; The second contact terminal is located on the surface of the body region, and the body region is connected to the source metal layer through the second contact terminal.

6. The ESD device of the LDMOSFET structure according to claim 1, characterized in that: It also includes an N-type well region and a P-type well region, wherein the N-type well region is located below the body region and the drift region; An N+ contact terminal is arranged on the surface of the N-type well region, and a power supply voltage is connected through the N+ contact terminal; A P+ contact terminal is arranged on the surface of the P-type well region, and is connected to the ground through the P+ contact terminal.

7. The ESD device of the LDMOSFET structure according to claim 1, characterized in that: A field plate structure is also included. The field plate structure includes a shallow trench isolation region formed in the drift region.

8. A method for manufacturing an ESD device of LDMOSFET structure, characterized in that: include: forming a body region and a drift region in a substrate; A gate oxide layer is formed above the body region and the drift region, and a polysilicon gate, an insulating dielectric layer and a polysilicon resistor are sequentially formed on the surface of the gate oxide layer; A source region is formed on the surface of the body region, a drain region is formed on the surface of the drift region, a first contact terminal is formed on the surface of the polysilicon resistor, and a second contact terminal is formed on the surface of the body region; forming a silicon nitride sidewall on the side of the polysilicon gate; An isolation oxide layer is formed above the body region, the drift region and the polysilicon resistor, and the isolation oxide layer is etched to form a plurality of contact holes, wherein the plurality of contact holes are respectively connected to the source region, the drain region, the first contact terminal and the second contact terminal; Metal is deposited in the contact hole to form a drain metal layer and a source metal layer.

9. The method for manufacturing an ESD device of LDMOSFET structure according to claim 8, characterized in that: A body region and a drift region are formed in the substrate, including: P-type ion implantation and N-type ion implantation are performed on the surface of the substrate respectively, and high-temperature driving is performed to form a P-type body region and an N-type drift region.

10. The method for manufacturing an ESD device with an LDMOSFET structure according to claim 8, characterized in that: A polysilicon gate, an insulating dielectric layer and a polysilicon resistor are sequentially formed on the surface of the gate oxide layer, including: Polysilicon with a first doping concentration is deposited on the surface of the gate oxide layer to form a polysilicon gate. The first doping concentration is 1×10 20 cm -3 ~1×10 21 cm -3 ; Depositing undoped polysilicon on the surface of the polysilicon gate to form an insulating dielectric layer; Polysilicon with a second doping concentration is deposited on the surface of the insulating dielectric layer to form a polysilicon resistor. The second doping concentration is 1×10 16 cm -3 ~1×10 18 cm -3 .

11. The method for manufacturing an ESD device with an LDMOSFET structure according to claim 8, characterized in that: A source region is formed on the surface of the body region, a drain region is formed on the surface of the drift region, a first contact terminal is formed on the surface of the polysilicon resistor, and a second contact terminal is formed on the surface of the body region, including: Performing photolithography on the surface of the body region, the surface of the drift region and the surface of the polysilicon resistor respectively to form ion implantation windows, and implanting N-type ions into the ion implantation windows to form a source region, a drain region and a first contact terminal; P-type ions are implanted into the ion implantation window of the body region to form a second contact terminal.

12. The method for manufacturing an ESD device with an LDMOSFET structure according to claim 8, characterized in that: A silicon nitride sidewall is formed on the side of the polysilicon gate, comprising: Silicon nitride is deposited on the side walls of the polysilicon gate, the insulating dielectric layer and the polysilicon resistor, and then etched to form silicon nitride sidewalls.

13. The method for manufacturing an ESD device with an LDMOSFET structure according to claim 8, characterized in that: Depositing metal in the contact hole to form a drain metal layer and a source metal layer, including: Using physical vapor deposition process, metal is deposited in the contact hole to form a metal layer; The metal layer is etched to form a drain metal layer and a source metal layer, and the body region, the source region and the polysilicon resistor are interconnected through the source metal layer.

14. The method for manufacturing an ESD device with an LDMOSFET structure according to claim 9, characterized in that: The method further comprises: When forming the P-type body region and the N-type drift region, the N-type well region and the P-type well region are formed simultaneously; A shallow trench isolation region is formed on the surface of the N-type drift region and the surface of the N-type well region.

15. A chip, characterized in that: The chip comprises an ESD device with an LDMOSFET structure as claimed in any one of claims 1 to 7.

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