ESD device of LDMOSFET structure, manufacturing method and chip

Abstract

The invention relates to the technical field of semiconductors, and provides an ESD device of an LDMOSFET structure, a manufacturing method and a chip. The device comprises a substrate, a body region, a drift region, a source region, a drain region and a gate structure, the body region and the drift region are formed in the substrate, the source region is connected with a source metal layer, the drain region is connected with a drain metal layer, and the gate structure comprises a gate oxide layer, a polycrystalline silicon gate, a polycrystalline silicon resistor and a metal silicide layer. The polycrystalline silicon gate and the polycrystalline silicon resistor are formed on the surface of the gate oxide layer, the metal silicide layer is formed on the surface of the polycrystalline silicon gate, and the polycrystalline silicon gate and the polycrystalline silicon resistor form a conductive channel through the metal silicide layer; a silicon nitride side wall is arranged at the side end of the polycrystalline silicon grid electrode and connected with the drain electrode metal layer, and the polycrystalline silicon grid electrode, the silicon nitride side wall and the drain electrode metal layer form a capacitor structure. The ESD protection circuit is a high-voltage ESD device equivalent to an RC type ESD protection circuit, and the area of the ESD device is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an ESD device with an LDMOSFET structure and a manufacturing method and a chip. Background Art

[0002] ESD (Electrostatic Discharge) refers to the charge transfer caused by objects with different electrostatic potentials approaching or directly contacting each other. When the static charge accumulated in the external environment of the IC (integrated circuit) chip or inside the IC chip flows into or out through the chip pins, the instantaneous ESD current will damage the thick gate oxide and metal wires of the internal devices of the chip, thereby causing device failure. With the continuous improvement of the process technology of very large-scale integrated circuits, complementary metal oxide semiconductor (CMOS) integrated circuits have entered the ultra-deep submicron stage, the size of MOS devices has been continuously reduced, and the harm of electrostatic discharge (ESD) to integrated circuits has become more and more significant, requiring ESD protection design for integrated circuits.

[0003] The prior art uses ESD circuits to protect integrated circuits from electrostatic discharge. Figure 1 It is an RC type ESD protection circuit using gate coupling technology. By constantly adjusting the size of capacitor Cn and resistor Rn, a suitable voltage can be coupled to the gate of NMOS device Mn1 under high ESD stress, thereby reducing the turn-on voltage of NMOS and achieving electrostatic protection. For NMOS and PMOS, if the bias voltage coupled to the gate is high, it will cause more channel current and higher electric field, making the thin gate oxide layer easy to be damaged, and the robustness of its ESD protection will decrease rapidly. However, in power management chips in the power field, the voltage can reach several thousand volts or even tens of thousands of volts when static electricity is released. This ESD circuit is difficult to achieve high-voltage electrostatic protection. In addition, the ESD circuit is connected to the capacitor and resistor outside the NMOS or PMOS device. The ESD circuit occupies a large area, which is not conducive to the miniaturization and integration of the chip. Summary of the invention

[0004] In order to solve the above technical problems, the present invention provides an ESD device with an LDMOSFET structure and a manufacturing method thereof.

[0005] On one hand, the present invention provides an ESD device of LDMOSFET structure, comprising: a substrate, a body region, a drift region, a source region, a drain region and a gate structure, wherein the body region and the drift region are formed in the substrate, the source region is formed on the surface of the body region, the drain region is formed on the surface of the drift region, and the gate structure is formed above the body region and the drift region;

[0006] The source region is connected to the source metal layer, and the drain region is connected to the drain metal layer;

[0007] The gate structure comprises: a gate oxide layer, a polysilicon gate, a polysilicon resistor and a metal silicide layer, wherein the polysilicon gate and the polysilicon resistor are formed on the surface of the gate oxide layer, the metal silicide layer is formed on the surface of the polysilicon gate, the polysilicon resistor is connected to the source metal layer, and the polysilicon gate forms a conductive channel with the polysilicon resistor through the metal silicide layer;

[0008] A silicon nitride sidewall is disposed at the side end of the polysilicon gate, the silicon nitride sidewall is connected to the drain metal layer, and the polysilicon gate, the silicon nitride sidewall and the drain metal layer form a capacitor structure.

[0009] In the embodiment of the present invention, one side end of the polysilicon resistor is connected to a first contact end, the first contact end is connected to the source metal layer, and the polysilicon resistor is connected to the source metal layer through the first contact end.

[0010] In the embodiment of the present invention, the other side of the polysilicon resistor is connected to the polysilicon gate and the metal silicide layer.

[0011] In the embodiment of the present invention, a second contact terminal is formed on the surface of the body region, and the second contact terminal is connected to the source metal layer.

[0012] In the embodiment of the present invention, the source metal layer is grounded, and the drain metal layer serves as an input terminal.

[0013] In the embodiment of the present invention, the material of the polysilicon gate is heavily doped polysilicon, and the doping concentration of ions in the heavily doped polysilicon is 1×10 20 cm -3 ~1×10 21 cm -3 ;

[0014] The material of the polysilicon resistor is lightly doped polysilicon, and the doping concentration of ions in the lightly doped polysilicon is 1×10 16 cm -3 ~1×10 18 cm -3 .

[0015] In an embodiment of the present invention, the ESD device further includes: a well region, wherein the well region is formed below the body region and the drift region.

[0016] In an embodiment of the present invention, the ESD device further includes a field plate structure, the field plate structure includes a shallow trench isolation region, and the shallow trench isolation region is formed in the drift region.

[0017] The present invention also provides a method for manufacturing the ESD device of the LDMOSFET structure, comprising:

[0018] forming a body region and a drift region in a substrate;

[0019] A source region is formed on the surface of the body region, and a drain region is formed on the surface of the drift region;

[0020] forming a gate oxide layer above the body region and the drift region, and forming a polysilicon gate and a polysilicon resistor on the surface of the gate oxide layer;

[0021] forming a silicon nitride sidewall at a side end of the polysilicon gate;

[0022] forming a metal silicide layer on the surface of the polysilicon gate, wherein the metal silicide layer is connected to the polysilicon resistor;

[0023] A source metal layer connected to the source region and a drain metal layer connected to the drain region are formed.

[0024] In an embodiment of the present invention, a body region and a drift region are formed in a substrate, including: performing P-type ion implantation and N-type ion implantation on the surface of the substrate respectively, and performing high-temperature driving to form a P-type body region and an N-type drift region.

[0025] In an embodiment of the present invention, a polysilicon gate and a polysilicon resistor are formed on the surface of a gate oxide layer, comprising: depositing a first doped polysilicon on the surface of the gate oxide layer to form a polysilicon layer, wherein the first doping concentration is 1×10 16 cm -3 ~1×10 18 cm -3 ;

[0026] Part of the polysilicon layer is doped twice. The polysilicon doped twice is used as the polysilicon gate, and the polysilicon that is not doped twice is used as the polysilicon resistor. The concentration of the secondary doping is 1×10 20 cm -3 ~1×10 21 cm -3 .

[0027] In an embodiment of the present invention, a portion of the polysilicon layer is secondary doped, including: secondary doping the polysilicon at both ends of the polysilicon layer, wherein the secondary doped polysilicon at one end serves as a polysilicon gate, and the secondary doped polysilicon at the other end serves as a first contact end of the polysilicon resistor.

[0028] In an embodiment of the present invention, a silicon nitride sidewall is formed on the side of a polysilicon gate, including: depositing silicon nitride on a substrate having a polysilicon gate and a polysilicon resistor, and etching to retain the silicon nitride on the side of the polysilicon gate to form a silicon nitride sidewall.

[0029] In an embodiment of the present invention, forming a metal silicide layer on a surface of a polysilicon gate includes:

[0030] forming silicon dioxide as a barrier layer on the substrate of the polysilicon gate and the polysilicon resistor;

[0031] Depositing metal on the surface of the barrier layer and performing heat treatment to form metal silicide;

[0032] The unreacted metal on the surface of the barrier layer is removed to form a metal silicide layer.

[0033] In an embodiment of the present invention, forming a source metal layer connected to a source region and a drain metal layer connected to a drain region includes:

[0034] forming an isolation oxide layer on the body region, the drift region, the polysilicon gate and the polysilicon resistor, and etching the isolation oxide layer to form a plurality of contact holes;

[0035] Depositing metal in the contact hole to form a metal layer;

[0036] The metal layer is etched to form a source metal layer connected to the source region and a drain metal layer connected to the drain region.

[0037] The present invention also provides a chip, which includes the ESD device with the LDMOSFET structure.

[0038] The present invention designs an ESD device based on an LDMOSFET structure, utilizes the high-voltage resistance capability of the LDMOSFET device, adds a polysilicon resistor and a capacitor structure consisting of a polysilicon gate, a silicon nitride sidewall and a drain metal layer to the LDMOSFET structure, and connects the polysilicon resistor in series with the capacitor structure through a metal silicide layer to form a high-voltage ESD device equivalent to an RC-type ESD protection circuit, thereby eliminating the need to add resistors and capacitors outside a MOS device and reducing the area of ​​the ESD device; and reduces the on-resistance between the polysilicon resistor and the polysilicon gate through the metal silicide layer to increase the on-effect and further improve the high-voltage protection capability of the ESD device.

[0039] Other features and advantages of the technical solution of the present invention will be described in detail in the specific implementation section below. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0041] Figure 1 It is an existing gate-coupled RC type ESD protection circuit;

[0042] Figure 2It is a structural schematic diagram of an ESD device with an LDMOSFET structure provided by an embodiment of the present invention;

[0043] Figure 3 is a flow chart of a method for manufacturing an ESD device of an LDMOSFET structure provided by an embodiment of the present invention;

[0044] Figure 4a is a schematic structural diagram of a body region and a drift region formed in a manufacturing method provided in an embodiment of the present invention;

[0045] Figure 4b is a schematic structural diagram of a shallow trench isolation region formed in a manufacturing method provided in an embodiment of the present invention;

[0046] Figure 4c is a schematic diagram of a source region, a drain region and a contact terminal formed in a manufacturing method provided in an embodiment of the present invention;

[0047] Figure 4d is a schematic structural diagram of a polysilicon resistor formed in a manufacturing method provided in an embodiment of the present invention;

[0048] Figure 4e is a schematic structural diagram of a polysilicon gate formed in a manufacturing method provided in an embodiment of the present invention;

[0049] Figure 4f is a schematic structural diagram of a silicon nitride sidewall formed in a manufacturing method provided in an embodiment of the present invention;

[0050] Figure 4g is a schematic structural diagram of a metal silicide layer formed in a manufacturing method provided in an embodiment of the present invention;

[0051] Figure 4h is a schematic structural diagram of an isolation oxide layer formed in a manufacturing method provided in an embodiment of the present invention;

[0052] Figure 4i It is a schematic structural diagram of a source metal layer and a drain metal layer formed in the manufacturing method provided in an embodiment of the present invention.

[0053] Description of Reference Numerals

[0054] 10-substrate, 11-body region, 12-drift region, 13-well region, 14-shallow trench isolation region,

[0055] 15-gate oxide layer, 16-polysilicon gate, 17-polysilicon resistor, 18-silicon nitride sidewall,

[0056] 19 - metal silicide layer, 20 - source region, 21 - drain region, 22 - first contact terminal, 23 - second contact terminal, 24 - isolation oxide layer, 25 - source metal layer, 26 - drain metal layer. DETAILED DESCRIPTION

[0057] In order to make the technical solutions and advantages of the embodiments of the present invention more clearly understood, the exemplary embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0058] In the description of the present invention, it should be understood that the terms "center", "upper", "lower", "front", "back", "left", "right", "side", "bottom", "surface", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. The terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0059] In the present invention, unless otherwise clearly specified and limited, the terms "connected", "connected", "connected" and the like should be understood in a broad sense, for example, it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0060] Figure 2 Schematic diagram of the structure of an ESD device with LDMOSFET structure provided by an embodiment of the present invention. Figure 2As shown, the ESD device of LDMOSFET structure provided in this embodiment includes: substrate 10, body region 11, drift region 12, source region 20, drain region 21 and gate structure, the body region 11 and drift region 12 are formed in substrate 10, the source region 20 is formed on the surface of body region 11, the drain region 21 is formed on the surface of drift region 12, and the gate structure is formed above body region 11 and drift region 12. Source region 20 is connected to source metal layer 25, and drain region 21 is connected to drain metal layer 26. The gate structure includes gate oxide layer 15, polysilicon gate 16, polysilicon resistor 17 and metal silicide layer 19, the polysilicon gate 16 and polysilicon resistor 17 are formed on the surface of gate oxide layer 15, the metal silicide layer 19 is formed on the surface of polysilicon gate 16, the polysilicon gate 16 forms a conductive channel with polysilicon resistor 17 through metal silicide layer 19, and polysilicon resistor 17 is connected to source metal layer 25. A silicon nitride sidewall 18 is provided at the side end of the polysilicon gate 16, and the silicon nitride sidewall 18 is connected to the drain metal layer 26. The polysilicon gate 16 and the drain metal layer 26 serve as two plates of the capacitor respectively, and the silicon nitride sidewall 18 serves as a dielectric layer between the two plates. The polysilicon gate 16, the silicon nitride sidewall 18 and the drain metal layer 26 constitute a capacitor structure. When the source metal layer 25 is grounded and the drain metal layer 26 serves as an input terminal, the above-mentioned LDMOSFET structure is equivalent to an RC-type ESD protection circuit.

[0061] In this embodiment, one side end of the polysilicon resistor 17 is connected to the first contact end 22, and the first contact end 22 is connected to the source metal layer 25. The polysilicon resistor 17 is connected to the source metal layer 25 through the first contact end 22, thereby forming an ohmic contact with the source metal layer 25. The other side end of the polysilicon resistor 17 is connected to the polysilicon gate 16 and the metal silicide layer 19. When the polysilicon resistor 17 is connected in series with the capacitor structure, since the resistance between the polysilicon gate 16 and the polysilicon resistor 17 is large, a large on-resistance will be formed inside the device. Therefore, a metal silicide layer 19 is added to one side end of the polysilicon resistor 17, and the polysilicon gate 16 forms a conductive channel with the polysilicon resistor 17 through the metal silicide layer 19. The resistance between the polysilicon resistor 17 and the polysilicon gate 16 is reduced through the metal silicide layer 19, thereby increasing the conduction effect.

[0062] In this embodiment, the material of the polysilicon gate 16 is heavily doped polysilicon, and the doping concentration of ions in the heavily doped polysilicon is 1×10 20 cm -3 ~1×10 21 cm -3 The material of the polysilicon resistor 17 is lightly doped polysilicon, and the doping concentration of ions in the lightly doped polysilicon is 1×10 16 cm -3 ~1×10 18 cm -3.

[0063] In this embodiment, a second contact terminal 23 is formed on the surface of the body region 11, and the second contact terminal 23 is connected to the source metal layer 25. The body region 11 is connected to the source metal layer 25 through the second contact terminal 23. A well region 13 is formed below the body region 11 and the drift region 12, and an N+ contact terminal is arranged on the surface of the well region 13, and the well region 13 is connected to the drain metal layer 26 through the N+ contact terminal. An isolation oxide layer 24 is formed on the surface of the metal silicide layer 19, a part of the surface of the drain region 21, and a part of the surface of the second contact terminal 23, and the source metal layer 25 is isolated from the drain metal layer 26 through the isolation oxide layer 24.

[0064] In an optional embodiment, the ESD device of the LDMOSFET structure further includes a field plate structure, wherein the field plate structure includes an STI (shallow trench isolation) shallow trench isolation region 14 formed on the surface of the drift region 12 and the surface of the well region 13. The field plate structure can increase the breakdown voltage of the ESD device and improve the high voltage protection capability of the ESD device.

[0065] The present invention designs an ESD device based on an LDMOSFET structure, utilizes the high-voltage resistance capability of the LDMOSFET device, adds a polysilicon resistor and a capacitor structure consisting of a polysilicon gate, a silicon nitride sidewall and a drain metal layer to the LDMOSFET structure, and connects the polysilicon resistor in series with the capacitor structure through a metal silicide layer to form a high-voltage ESD device equivalent to an RC-type ESD protection circuit, thereby eliminating the need to add resistors and capacitors outside a MOS device and reducing the area of ​​the ESD device; and reduces the on-resistance between the polysilicon resistor and the polysilicon gate through the metal silicide layer to increase the on-effect and further improve the high-voltage protection capability of the ESD device.

[0066] The embodiment of the present invention also provides a method for manufacturing the ESD device of the LDMOSFET structure. Figure 3 As shown, the method comprises the following steps:

[0067] S301, forming a body region and a drift region in a substrate;

[0068] S302, forming a source region on the surface of the body region, and forming a drain region on the surface of the drift region;

[0069] S303, forming a gate oxide layer above the body region and the drift region, and forming a polysilicon gate and a polysilicon resistor on the surface of the gate oxide layer;

[0070] S304, forming a silicon nitride sidewall at a side end of the polysilicon gate;

[0071] S305, forming a metal silicide layer on the surface of the polysilicon gate, wherein the metal silicide layer is connected to the polysilicon resistor;

[0072] S306, forming a source metal layer connected to the source region and a drain metal layer connected to the drain region.

[0073] In a specific embodiment, in the above step S301, a P-type silicon substrate 10 is selected, and P-type ion implantation and N-type ion implantation are respectively performed on the surface of the P-type silicon substrate 10, and high-temperature advancement is performed to form a Figure 4a The P-type body region 11 and the N-type drift region 12 are shown.

[0074] In an optional embodiment, when forming the P-type body region 11 and the N-type drift region 12, the N-type well region 13 is formed at the same time. Then, according to the standard STI (shallow trench isolation) process, a shallow trench isolation region 14 is formed on the surface of the N-type drift region 12 and the surface of the N-type well region 13, forming a Figure 4b The structure shown.

[0075] In a specific embodiment, in the above step S302, photolithography is performed on the surface of the P-type body region 11 and the surface of the N-type drift region 12 to form an ion implantation window, N-type ions are implanted in the ion implantation window, and annealing is performed to form an N+ source region 20 and an N+ drain region 21, and an N+ contact terminal of the N-type well region 13 is formed at the same time; P-type ions are implanted in the ion implantation window of the P-type body region 11 to form a P+ contact terminal (i.e., a second contact terminal 23) on the surface of the P-type body region 11, and the like is formed. Figure 4c The structure shown.

[0076] In a specific embodiment, in the above step S303, a gate oxide layer 15 is formed on the P-type body region 11 and the N-type drift region 12, and then a first doped polysilicon is deposited on the surface of the gate oxide layer 15 by a low pressure chemical vapor deposition (LPCVD) method to form a polysilicon layer. The first doping concentration is 1×10 16 cm -3 ~1×10 18 cm -3 At this time, the doping concentration of the polysilicon layer is low and the resistance is large, and the polysilicon resistor 17 is formed as follows Figure 4d Next, a portion of the polysilicon layer is doped twice, and the polysilicon doped twice is used as the polysilicon gate 16, and the polysilicon not doped twice is used as the polysilicon resistor 17. The concentration of the doping twice is 1×10 20 cm -3 ~1×10 21 cm -3Specifically, the polysilicon at both ends of the polysilicon layer can be doped twice, wherein the polysilicon at one end is used as the polysilicon gate 16, and the polysilicon at the other end is used as the first contact end 22 of the polysilicon resistor 17, forming Figure 4e This step uses only one polysilicon photolithography process to form a polysilicon resistor and a polysilicon gate (the prior art usually requires two photolithography processes). The polysilicon gate also serves as a plate of the capacitor, the process is simple, and the gate occupies a small area.

[0077] In a specific embodiment, in the above step S304, silicon nitride is deposited on the substrate having the polysilicon gate 16 and the polysilicon resistor 17, and then etched to retain the silicon nitride on the side of the polysilicon gate 16, so as to form Figure 4f The silicon nitride sidewall 18 is shown. Specifically, silicon nitride can be formed only on the right side of the polysilicon gate 16. In the conventional manufacturing process, silicon nitride is formed on both sides of the gate structure, that is, there is silicon nitride on the left side of the first contact end 22 of the polysilicon resistor 17. The silicon nitride on the left side can also be retained, which will not affect the ohmic contact between the polysilicon resistor 17 and the source metal layer 25.

[0078] In a specific embodiment, in the above step S305, a thin layer of silicon dioxide (SiO2) is formed on the substrate 10 having the polysilicon gate 16 and the polysilicon resistor 17. 2 ) as a barrier layer for the silicide region, and dry-etching the silicon dioxide to open the silicide region; depositing metal (such as Ti, Co, Ni, etc.) on the surface of the barrier layer, and performing rapid thermal processing (RTP) to form metal silicide, and then wet etching to remove the unreacted metal on the surface of the barrier layer to form a Figure 4g The metal silicide layer 19 is shown.

[0079] In a specific embodiment, in the above step S306, an isolation oxide layer 24 is formed on the body region 11, the drift region 12, the metal silicide layer 19 and the polysilicon resistor 17, and the isolation oxide layer 24 is etched to form a plurality of contact holes, such as Figure 4h shown.

[0080] Next, a physical vapor deposition (PVD) process is used to deposit metal in the contact hole to form a metal layer, and the metal layer is etched to form a Figure 4i The source metal layer 25 and the drain metal layer 26 are shown to obtain an ESD device with an LDMOSFET structure.

[0081] An embodiment of the present invention further provides a chip, which includes the ESD device with the above-mentioned LDMOSFET structure, and electrostatic protection for integrated circuits in the chip is achieved through the ESD device.

[0082] The optional embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the technical concept of the embodiments of the present invention, a variety of simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all belong to the protection scope of the embodiments of the present invention. It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction, and as long as the combination does not violate the concept of the embodiments of the present invention, it should also be regarded as the content disclosed in the embodiments of the present invention.

Claims

1. An ESD device with an LDMOSFET structure, comprising: A substrate, a body region, a drift region, a source region, a drain region and a gate structure, wherein the body region and the drift region are formed in the substrate, the source region is formed on the surface of the body region, the drain region is formed on the surface of the drift region, and the gate structure is formed above the body region and the drift region; The source region is connected to the source metal layer, and the drain region is connected to the drain metal layer; The gate structure comprises: a gate oxide layer, a polysilicon gate, a polysilicon resistor and a metal silicide layer, wherein the polysilicon gate and the polysilicon resistor are formed on the surface of the gate oxide layer, the metal silicide layer is formed on the surface of the polysilicon gate, the polysilicon resistor is connected to the source metal layer, and the polysilicon gate forms a conductive channel with the polysilicon resistor through the metal silicide layer; A silicon nitride sidewall is disposed at the side end of the polysilicon gate, the silicon nitride sidewall is connected to the drain metal layer, and the polysilicon gate, the silicon nitride sidewall and the drain metal layer form a capacitor structure.

2. The ESD device of the LDMOSFET structure according to claim 1, characterized in that: One side end of the polysilicon resistor is connected to a first contact end, the first contact end is connected to the source metal layer, and the polysilicon resistor is connected to the source metal layer through the first contact end.

3. The ESD device of the LDMOSFET structure according to claim 2, characterized in that: The other side of the polysilicon resistor is connected to the polysilicon gate and the metal silicide layer.

4. The ESD device of the LDMOSFET structure according to claim 1, characterized in that: A second contact terminal is formed on the surface of the body region, and the second contact terminal is connected to the source metal layer.

5. The ESD device of the LDMOSFET structure according to claim 1, characterized in that: The source metal layer is grounded, and the drain metal layer serves as an input terminal.

6. The ESD device of the LDMOSFET structure according to claim 1, characterized in that: The material of the polysilicon gate is heavily doped polysilicon, and the doping concentration of ions in the heavily doped polysilicon is 1×10 20 cm -3 ~1×10 21 cm -3 ; The material of the polysilicon resistor is lightly doped polysilicon, and the doping concentration of ions in the lightly doped polysilicon is 1×10 16 cm -3 ~1×10 18 cm -3 .

7. The ESD device of the LDMOSFET structure according to claim 1, characterized in that: Also includes: A well region is formed below the body region and the drift region.

8. The ESD device of LDMOSFET structure according to claim 1, characterized in that: A field plate structure is also included. The field plate structure includes a shallow trench isolation region formed in the drift region.

9. A method for manufacturing an ESD device of LDMOSFET structure, characterized in that: include: forming a body region and a drift region in a substrate; A source region is formed on the surface of the body region, and a drain region is formed on the surface of the drift region; forming a gate oxide layer above the body region and the drift region, and forming a polysilicon gate and a polysilicon resistor on the surface of the gate oxide layer; forming a silicon nitride sidewall at a side end of the polysilicon gate; forming a metal silicide layer on the surface of the polysilicon gate, wherein the metal silicide layer is connected to the polysilicon resistor; A source metal layer connected to the source region and a drain metal layer connected to the drain region are formed.

10. The method for manufacturing an ESD device with an LDMOSFET structure according to claim 9, characterized in that: A body region and a drift region are formed in the substrate, including: P-type ion implantation and N-type ion implantation are performed on the surface of the substrate respectively, and high-temperature driving is performed to form a P-type body region and an N-type drift region.

11. The method for manufacturing an ESD device with an LDMOSFET structure according to claim 9, characterized in that: A polysilicon gate and a polysilicon resistor are formed on the surface of the gate oxide layer, including: A first doped polysilicon is deposited on the surface of the gate oxide layer to form a polysilicon layer. The first doping concentration is 1×10 16 cm -3 ~1×10 18 cm -3 ; Part of the polysilicon layer is doped twice. The polysilicon doped twice is used as the polysilicon gate, and the polysilicon that is not doped twice is used as the polysilicon resistor. The concentration of the secondary doping is 1×10 20 cm -3 ~1×10 21 cm -3 .

12. The method for manufacturing an ESD device with an LDMOSFET structure according to claim 11, characterized in that: Secondary doping of part of the polysilicon layer includes: The polysilicon at both ends of the polysilicon layer is doped twice, wherein the secondarily doped polysilicon at one end serves as a polysilicon gate, and the secondarily doped polysilicon at the other end serves as a first contact end of a polysilicon resistor.

13. The method for manufacturing an ESD device with an LDMOSFET structure according to claim 9, characterized in that: A silicon nitride sidewall is formed at a side end of a polysilicon gate, comprising: Silicon nitride is deposited on a substrate having a polysilicon gate and a polysilicon resistor, and then etched to retain the silicon nitride on the side end of the polysilicon gate to form a silicon nitride sidewall.

14. The method for manufacturing an ESD device with an LDMOSFET structure according to claim 9, characterized in that: A metal silicide layer is formed on the surface of the polysilicon gate, comprising: forming silicon dioxide as a barrier layer on the substrate of the polysilicon gate and the polysilicon resistor; Depositing metal on the surface of the barrier layer and performing heat treatment to form metal silicide; The unreacted metal on the surface of the barrier layer is removed to form a metal silicide layer.

15. The method for manufacturing an ESD device with an LDMOSFET structure according to claim 9, characterized in that: Forming a source metal layer connected to the source region and a drain metal layer connected to the drain region, comprising: forming an isolation oxide layer on the body region, the drift region, the polysilicon gate and the polysilicon resistor, and etching the isolation oxide layer to form a plurality of contact holes; Depositing metal in the contact hole to form a metal layer; The metal layer is etched to form a source metal layer connected to the source region and a drain metal layer connected to the drain region.

16. A chip, characterized in that: The chip comprises an ESD device with an LDMOSFET structure as claimed in any one of claims 1 to 8.

Images