GaN-based power transistor structure of mixed grid

Abstract

The invention provides a GaN-based power transistor structure of a mixed grid electrode, which comprises a laminated structure, and the laminated structure comprises a substrate; the GaN buffer layer is arranged on the substrate; the Al (In, Ga) GaN barrier layer is arranged on one side, far away from the substrate, of the GaN buffer layer; the source electrode structure is arranged at the first end of the laminated structure; the drain electrode structure is arranged at the second end of the laminated structure relative to the source electrode structure; the gate structure is arranged on the laminated structure and located between the first end and the second end, and the gate structure comprises a p-(In, Al) GaN epitaxial layer arranged on the laminated structure, a p-(In, Al) GaN epitaxial layer arranged on the p-(In, Al) GaN epitaxial layer, and a p-(In, Al) GaN epitaxial layer arranged on the p-(In, Al) GaN epitaxial layer; the doping layer is arranged on one side, far away from the laminated structure, of the p-(In, Al) GaN epitaxial layer; the first gate metal layer is arranged on the side, away from the laminated structure, of the doped layer, the doped layer comprises at least one p-type doped region and a plurality of n-type doped regions, and the at least one p-type doped region is located between the n-type doped regions.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a GaN-based power transistor structure with a hybrid gate. Background Art

[0002] GaN-based power electronic devices have high breakdown field, good mobility, high carrier density and good thermal conductivity, and are rapidly being commercialized for power switching applications. The current mainstream commercial enhancement mode (normally off) GaN-based transistor products are based on p-(Al)GaN gates, but there are trade-offs between reliability, stability and gate leakage. Transistors with ohmic contact gates have high threshold stability, but large gate leakage, which increases power consumption; using Schottky contact gates can suppress gate leakage, but there are gate reliability issues, that is, the Schottky gate interface is easily damaged at high gate voltages, so the gate voltage operating range is narrow, which is not conducive to suppressing gate ringing and misleading conduction in high-frequency power switching applications; using pn junction gates has a reliable gate and an extremely wide gate voltage operating range, while further reducing gate leakage, but it also exacerbates the threshold instability caused by the floating p-(Al)GaN gate region, which deteriorates the dynamic performance of the power transistor and reduces the power conversion efficiency of the transistor.

[0003] Therefore, it is currently extremely necessary to achieve good gate reliability under the premise of low gate leakage to obtain a larger gate drive swing required for safe operation, as well as a more stable threshold to achieve good dynamic performance.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to those skilled in the art. Summary of the invention

[0005] 1. Technical issues to be resolved

[0006] In view of the fact that several existing GaN-based enhancement-mode power electronic devices based on p-(Al)GaN gates have the problem that gate reliability, threshold stability and gate leakage are difficult to be optimized simultaneously, the present invention discloses a GaN-based power transistor structure with a hybrid gate. On the basis of a high-reliability pn junction gate structure, a small p-type region is introduced to electrically connect the gate metal and the p-(In, Al)GaN inside to form a dynamic leakage path, which can improve the threshold stability without increasing the gate leakage. The invention can simultaneously achieve a reliable gate, a stable threshold and low gate leakage, and is of great value to the development of commercial enhancement-mode GaN-based power electronics.

[0007] (II) Technical solution

[0008] One aspect of the present invention discloses a hybrid gate GaN-based power transistor structure, comprising: a stacked structure, wherein the stacked structure comprises: a substrate; a GaN buffer layer disposed on the substrate; and an Al(In, Ga)GaN barrier layer disposed on a side of the GaN buffer layer away from the substrate; a source structure disposed at a first end of the stacked structure; and a drain structure disposed at a second end of the stacked structure relative to the source structure; and a gate structure disposed on the stacked structure and located between the first end and the second end, wherein the gate structure comprises: a p-(In, Al)GaN epitaxial layer disposed on the stacked structure; a doped layer disposed on a side of the p-(In, Al)GaN epitaxial layer away from the stacked structure; and a first gate metal layer disposed on a side of the doped layer away from the stacked structure, wherein the doped layer comprises at least one p-type doped region and a plurality of n-type doped regions, and the at least one p-type doped region is located between the plurality of n-type doped regions.

[0009] According to some embodiments of the present invention, the at least one p-type doping region is surrounded by the plurality of n-type doping regions.

[0010] According to some embodiments of the present invention, the p-type doped region includes m p-type doped sub-regions, wherein m is equal to 1; or, the p-type doped region includes m p-type doped sub-regions, and the m p-type doped sub-regions are spaced apart from each other along a first direction, wherein m is a positive integer greater than or equal to 2; or, the p-type doped region includes m p-type doped sub-regions, and the m p-type doped sub-regions are spaced apart from each other along both the first direction and the second direction, wherein m is a positive integer greater than or equal to 4.

[0011] According to some embodiments of the present invention, an orthographic projection of each of the p-type doped sub-regions on the substrate has a first width in a first direction, and the first width is 5-1000 nm.

[0012] According to some embodiments of the present invention, the orthographic projection of the p-type doped region on the substrate is located within the orthographic projection of the first gate metal layer on the substrate, and an ohmic contact is formed between the first gate metal layer and the p-type doped region; and the orthographic projection of the n-type doped region on the substrate partially overlaps with the orthographic projection of the first gate metal layer on the substrate, and a Schottky contact is formed between the n-type doped region and the first gate metal layer.

[0013] According to some embodiments of the present invention, the orthographic projection of each of the m p-type doped sub-regions on the substrate is a strip; or, the orthographic projection of each of the m p-type doped sub-regions on the substrate is a rectangle; or, the orthographic projection of each of the m p-type doped sub-regions on the substrate is a circle.

[0014] According to some embodiments of the present invention, the hybrid gate GaN-based power transistor structure also includes a second gate metal layer, which is arranged on a side of the first gate metal layer away from the substrate, or the second gate metal layer is arranged between the doping layer and the first gate metal layer; the second gate metal layer is electrically connected to the first gate metal layer; and an ohmic contact is formed between the second gate metal layer and the n-type doped region.

[0015] According to some embodiments of the present invention, the main material of the doping layer includes: a combination of one or more of (In, Al) GaN, polysilicon, NiO, and diamond; and / or the thickness of the doping layer is 5 to 500 nm; and / or the doping concentration of the p-type doping region is 10 17 -10 21 cm -3 ; and / or, the doping concentration of the n-type doping region is 10 17 -10 21 cm -3 .

[0016] According to some embodiments of the present invention, the thickness of the p-(In, Al)GaN epitaxial layer is 10 to 500 nm; and / or the doping concentration of the p-(In, Al)GaN epitaxial layer is 10 17 -10 21 cm -3 .

[0017] According to some embodiments of the present invention, the doping in the p-(In, Al)GaN epitaxial layer may be uniformly doped; and / or, the doping in the p-(In, Al)GaN epitaxial layer may be gradually doped from top to bottom.

[0018] According to some embodiments of the present invention, the orthographic projection of the p-type doped region on the substrate coincides with the orthographic projection of the first gate metal layer on the substrate, and an ohmic contact is formed between the first gate metal layer and the p-type doped region; and the hybrid gate GaN-based power transistor structure also includes: a second gate metal layer, the second gate metal layer is located on a side of the first gate metal layer away from the substrate, wherein the second gate metal layer is electrically connected to the first gate metal layer; and an ohmic contact is formed between the second gate metal layer and the n-type doped region.

[0019] According to some embodiments of the present invention, the orthographic projection of the first gate metal layer on the substrate has a second width in the first direction, the orthographic projection of the p-(In, Al)GaN epitaxial layer on the substrate has a third width in the first direction, and the second width is less than or equal to the third width.

[0020] According to some embodiments of the present invention, the work function of the first gate metal layer is in the range of 5.0 to 6.5 eV; and / or the work function of the second gate metal layer is in the range of 4.0 to 5.5 eV.

[0021] Another aspect of the present invention discloses a hybrid gate GaN-based power transistor structure, comprising: a stacked structure, wherein the stacked structure comprises: a substrate; a GaN buffer layer disposed on the substrate; and an Al(In, Ga)GaN barrier layer disposed on a side of the GaN buffer layer away from the substrate; a source structure disposed at a first end of the stacked structure; and a drain structure disposed at a second end of the stacked structure relative to the source structure; and a gate structure disposed on the stacked structure and located between the first end and the second end, wherein the gate structure comprises: a p-(In, Al)GaN epitaxial layer disposed on the stacked structure; a doped layer disposed on a side of the p-(In, Al)GaN epitaxial layer away from the stacked structure; and a first gate metal layer disposed on a side of the doped layer away from the stacked structure, wherein the doped layer comprises at least one via and a plurality of n-type doped regions, the at least one via being located between the plurality of n-type doped regions; and the first gate metal layer forms an ohmic contact with the p-(In, Al)GaN epitaxial layer through the at least one via.

[0022] (III) Beneficial effects

[0023] One aspect of the present invention discloses a hybrid gate GaN-based power transistor structure, comprising: a stacked structure, wherein the stacked structure comprises: a substrate; a GaN buffer layer disposed on the substrate; and an Al(In, Ga)GaN barrier layer disposed on a side of the GaN buffer layer away from the substrate; a source structure disposed at a first end of the stacked structure; and a drain structure disposed at a second end of the stacked structure relative to the source structure; and a gate structure disposed on the stacked structure and located between the first end and the second end, wherein the gate structure comprises: a p-(In, Al)GaN epitaxial layer disposed on the stacked structure; a doped layer disposed on a side of the p-(In, Al)GaN epitaxial layer away from the stacked structure; and a first gate metal layer disposed on a side of the doped layer away from the stacked structure, wherein the doped layer comprises at least one p-type doped region and a plurality of n-type doped regions, and the at least one p-type doped region is located between the plurality of n-type doped regions. By arranging a doping layer on the p-(In, Al)GaN gate, wherein the doping layer includes at least one p-type doping region and multiple n-type doping regions, and the at least one p-type doping region is located between the multiple n-type doping regions, a p-type dynamic leakage path can be introduced on the basis of a high-voltage and high-reliability pn junction gate, thereby improving device stability and its dynamic characteristics, while keeping gate leakage at a low level. The beneficial effects of the present invention are as follows:

[0024] 1. High gate reliability is achieved by using reverse biased pn junction gate, which realizes larger gate swing and working life;

[0025] 2. Introduce a p-type region, which serves as a p-type dynamic leakage path connecting the gate metal and the p-(In, Al)GaN epitaxial layer. This path is in an open state at a lower gate voltage, providing a charge leakage path to achieve higher threshold stability; at a higher gate voltage, this path is pinched off by the extension of the depletion regions on both sides, reducing the gate leakage current;

[0026] 3. The gate reliability, stability and leakage characteristics of hybrid-gate GaN-based power transistors are simultaneously optimized, which is of great significance to the future development of GaN power transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above contents and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0028] Figure 1 is a schematic structural diagram of a hybrid gate GaN-based power transistor structure provided according to an embodiment of the present invention;

[0029] Figure 2is a schematic structural diagram of a hybrid gate GaN-based power transistor structure provided according to some other embodiments of the present invention;

[0030] Figure 3A , Figure 3B , Figure 3C and Figure 3D They are respectively schematic top plan views of doped layers in a GaN-based power transistor structure with a hybrid gate provided according to some embodiments of the present invention;

[0031] Figure 4 is a schematic structural diagram of a hybrid gate GaN-based power transistor structure provided according to some embodiments of the present invention;

[0032] Figure 5 is a schematic structural diagram of a hybrid gate GaN-based power transistor structure provided according to some other embodiments of the present invention;

[0033] Figure 6 is a schematic structural diagram of a hybrid gate GaN-based power transistor structure provided according to some embodiments of the present invention;

[0034] Figure 7 is a schematic structural diagram of a hybrid gate GaN-based power transistor structure provided according to some embodiments of the present invention;

[0035] Figure 8 is a schematic structural diagram of a hybrid gate GaN-based power transistor structure provided according to some embodiments of the present invention;

[0036] Fig. 9 is a schematic structural diagram of a hybrid gate GaN-based power transistor structure provided according to some other embodiments of the present invention;

[0037] Fig.10 It is a structural schematic diagram of a hybrid gate GaN-based power transistor structure provided according to some embodiments of the present invention.

[0038] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present invention, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] It should be noted that in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. Thus, the size and relative size of each element are not necessarily limited to the size and relative size shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0041] Unless otherwise defined, the technical terms or scientific terms used in the present invention shall have the usual meanings understood by those of ordinary skill in the art. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. The words "include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0042] In this document, unless otherwise specified, directional terms such as "upper", "lower", "left", "right", "inner", "outer", etc. are used to indicate the orientation or positional relationship based on the drawings, and are only for the convenience of describing the present invention, and do not indicate or imply that the device, element or component referred to must have a specific orientation, be constructed or operate in a specific orientation. It should be understood that when the absolute position of the described object changes, the relative positional relationship they represent may also change accordingly. Therefore, these directional terms should not be understood as limiting the present invention.

[0043] At least some embodiments of the present invention provide a GaN-based p-(In, Al)GaN gate enhancement-mode power transistor structure with a hybrid gate. On the basis of a high-reliability pn junction gate structure, a small p-type region is introduced to electrically connect the metal and the p-(In, Al)GaN inside to form a dynamic leakage path, which can improve the threshold stability without increasing the gate leakage. The invention can simultaneously achieve a reliable gate, a stable threshold, and low gate leakage, which can greatly improve the stability of enhancement-mode GaN-based power electronics and expand the application scenarios of enhancement-mode GaN-based power electronics.

[0044] Figure 1 It is a structural schematic diagram of a hybrid gate GaN-based power transistor structure provided according to an embodiment of the present invention.

[0045] Exemplarily, in some embodiments of the present invention, referring to FIG. 1, a GaN-based power transistor structure with a hybrid gate includes: a stacked structure 1, wherein the stacked structure 1 includes: a substrate 11; a GaN buffer layer 12 disposed on the substrate 11; and an Al(In, Ga)GaN barrier layer 13 disposed on a side of the GaN buffer layer 12 away from the substrate 11; a source structure 2 disposed at a first end S1 of the stacked structure 1; and a drain structure 3 disposed at a second end S2 of the stacked structure 1 relative to the source structure 2; and a gate structure 4 disposed on the stacked structure 1. , and is located between the first end S1 and the second end S2, wherein the gate structure 4 includes: a p-(In, Al)GaN epitaxial layer 41 disposed on the stacked structure 1; a doping layer 42 disposed on the side of the p-(In, Al)GaN epitaxial layer 41 away from the stacked structure 1; and a first gate metal layer 43 disposed on the side of the doping layer 42 away from the stacked structure 1, wherein the doping layer 42 includes at least one p-type doping region 421 and a plurality of n-type doping regions 422, and the at least one p-type doping region 421 is located between the plurality of n-type doping regions 422. The plurality of n-type doping regions 422 in the doping layer 42 form a pn junction with the p-(In, Al)GaN epitaxial layer 41, and can share the gate electric field in reverse bias under a positive gate voltage, thereby ensuring that the transistor has the characteristics of high reliability and low leakage. Furthermore, by introducing a small p-type region to electrically connect the first gate metal layer 43 and the inside of the p-(In, Al)GaN epitaxial layer 41 to form a dynamic leakage path, the charge accumulated inside the p-(In, Al)GaN epitaxial layer 41 when the transistor switch is working can be balanced to reach a stable threshold, thereby improving the threshold stability of the transistor.

[0046] Figure 2 It is a schematic structural diagram of a hybrid gate GaN-based power transistor structure provided according to some other embodiments of the present invention.

[0047] For example, refer to Figure 2The doping layer 42 may include a plurality of p-type doping sub-regions 4211 and a plurality of n-type doping regions 422, wherein the plurality of p-type doping sub-regions 4211 are arranged at intervals between the plurality of n-type doping regions 422, that is, each of the plurality of p-type doping sub-regions 4211 is surrounded by a plurality of n-type doping regions 422, and the plurality of p-type doping sub-regions 4211 may contact a first gate metal layer 43 located on a side of the doping layer 42 away from the substrate, and the plurality of p-type doping sub-regions 4211 may be electrically connected to a p-(In, Al)GaN layer located on a side of the doping layer 42 close to the substrate, thereby forming a plurality of electrical connection paths between the first gate metal layer 43 and the p-(In, Al)GaN epitaxial layer 41, which may more efficiently leak the charges accumulated inside the p-(In, Al)GaN epitaxial layer 41 when the transistor switch is working, and reach a stable threshold more quickly, thereby improving the threshold stability of the transistor.

[0048] Figure 3A , Figure 3B , Figure 3C and Figure 3D They are respectively schematic top plan views of doped layers in a hybrid gate GaN-based power transistor structure provided according to some embodiments of the present invention.

[0049] Exemplarily, in some embodiments of the present invention, in combination with reference Figure 3A , Figure 3B , Figure 3C and Figure 3D , the at least one p-type doping region 421 is surrounded by the plurality of n-type doping regions 422 .

[0050] Preferably, the p-type doping region 421 may include m p-type doping sub-regions 4211, where m is equal to 1. Figure 3A The p-type doping region may include a single p-type doping sub-region 4211. The orthographic projection of the single p-type doping sub-region 4211 on the substrate 11 may be in a strip shape.

[0051] Preferably, the p-type doping region 421 may include m p-type doping sub-regions 4211, and the m p-type doping sub-regions 4211 are arranged in a spaced relationship from each other along the first direction X, wherein m is a positive integer greater than or equal to 2. Figure 3B The p-type doping region 421 may include a plurality of p-type doping sub-regions 4211, and the orthographic projection of each of the plurality of p-type doping sub-regions 4211 on the substrate 11 may be in the shape of a strip. In other words, the doping layer 42 may include a plurality of p-type doping sub-regions 4211 distributed in strips.

[0052] It should be noted that the widths of the positive projections of multiple p-type doped sub-regions 4211 on the substrate in the first direction X can be the same as each other, or can be different from each other; or, the lengths of the multiple p-type doped sub-regions 4211 in the second direction Y can be the same as each other, or can be different from each other.

[0053] Preferably, the p-type doped region 421 includes m p-type doped sub-regions 4211, and the m p-type doped sub-regions 4211 can be spaced apart from each other along both the first direction X and the second direction Y, where m is a positive integer greater than or equal to 4. For example, referring to Figure 3C and Figure 3D , the m p-type doped sub-regions 4211 can be distributed in the doped layer 42 in an array.

[0054] Preferably, the positive projection of each of the m p-type doped sub-regions on the substrate is a rectangle; or, the positive projection of each of the m p-type doped sub-regions on the substrate is a circle.

[0055] It should be noted that the positive projection of each of the m p-type doped sub-regions on the substrate can also be various shapes such as a polygon, an ellipse, etc., and the present invention does not make special limitations thereto.

[0056] Exemplarily, in some embodiments of the present invention, with reference to Figure 1 , Figure 3A and Figure 3B , the positive projection of each p-type doped sub-region 4211 on the substrate has a first width d1 in the first direction X, and the first width d1 is 5 to 1000 nm.

[0057] By setting the width of each p-type doped sub-region 4211 to be relatively narrow, at a lower gate voltage, the depletion region 100 of the pn junction formed by the multiple n-type doped regions 422 and the p-(In, Al)GaN epitaxial layer 41 does not pinch off the channel of the p-type doped sub-region 4211. Therefore, the p-type doped sub-region 4211 can serve as a channel for electrical connection between the first gate metal layer 43 and the p-(In, Al)GaN epitaxial layer 41, providing a charge leakage path to balance the charge accumulated inside the p-(In, Al)GaN epitaxial layer 41 during transistor switching, so as to achieve a stable threshold; at a higher gate voltage, since the width of each p-type doped sub-region 4211 is relatively narrow and each p-type doped sub-region 4211 is surrounded by the n-type doped region 422, when the pn junction formed by the n-type doped region 422 and the p-(In, Al)GaN epitaxial layer 41 is reverse-biased, the depletion region 100 can extend laterally along the first direction X to pinch off the channel of the p-type doped sub-region 4211, thereby disconnecting the channel for electrical connection between the first gate metal layer 43 and the p-(In, Al)GaN epitaxial layer 41, thereby reducing the gate leakage of the transistor.

[0058] Preferably, refer to Figure 1 , the orthographic projection of the p-type doping region 421 on the substrate falls between the orthographic projections of the first gate metal layer 43 on the substrate, and an ohmic contact is formed between the first gate metal layer 43 and the p-type doping region 421. By such a design, it can be ensured that when the gate voltage of the gate structure is low, the p-type doping region 421 serves as a channel directly connecting the top first gate metal layer 43 and the lower p-(In, Al)GaN epitaxial layer 41, providing a leakage path to balance the charges accumulated inside the p-(In, Al)GaN epitaxial layer 41 when the transistor switch is working, thereby improving the stability of the transistor gate state, thereby improving the stability of the transistor threshold, and ensuring the normal operation of the transistor. The orthographic projection of the n-type doped region 422 on the substrate partially overlaps with the orthographic projection of the first gate metal layer 43 on the substrate, wherein a Schottky contact is formed between the n-type doped region 422 and the first gate metal layer 43, wherein the first gate metal layer 43 serves as a gate conductive metal, and the n-type doped region 422 forms a pn junction with the lower p-(In, Al)GaN epitaxial layer 41, and a reverse-biased pn junction can be used to achieve high gate reliability, thereby achieving a larger gate swing and a longer service life.

[0059] By setting a doping layer 42, wherein an n-type doping region 422 forms a pn junction with the p-(In, Al)GaN epitaxial layer 41, when the gate structure 4 is at a positive gate voltage, the pn junction formed by the n-type doping region 422 and the lower p-(In, Al)GaN epitaxial layer 41 can reversely share the gate electric field, thereby ensuring that the gate of the GaN-based power transistor has a highly reliable characteristic. At the same time, since the first width d1 of the p-type doped sub-region 4211 in the first direction X is narrow and each of the p-type doped sub-regions 4211 is surrounded by the n-type doped region 422, when the gate voltage of the gate structure is low, the p-type doped sub-region 4211 serves as a channel directly connecting the top first gate metal layer 43 and the lower p-(In, Al)GaN epitaxial layer 41, and can provide a leakage path to balance the charge accumulated inside the p-(In, Al)GaN epitaxial layer 41 when the transistor switch is working, thereby improving the stability of the transistor gate state, and then improving the stability of the transistor threshold, ensuring the normal operation of the transistor; when the gate voltage of the gate structure is high, the depletion region 100 of the reverse biased pn junction extends along the first direction X, and can pinch off the channel of the p-type doped sub-region 4211, thereby reducing gate leakage.

[0060] By arranging a doping layer 42 on the side of the p-(In, Al)GaN epitaxial layer 41 away from the stacked structure 1 to form a hybrid gate, the high withstand voltage and high reliability of the pn junction gate can be combined with the p-type dynamic leakage path, thereby overcoming the defect of threshold instability caused by the floating pn junction gate, improving the dynamic characteristics of the transistor gate, and keeping the gate leakage at a low level.

[0061] Figure 4 is a schematic structural diagram of a hybrid gate GaN-based power transistor structure provided according to some embodiments of the present invention; Figure 5 It is a schematic structural diagram of a hybrid gate GaN-based power transistor structure provided according to some other embodiments of the present invention.

[0062] Exemplarily, in some embodiments of the present invention, in combination with reference Figure 4 and Figure 5 The hybrid gate GaN-based power transistor structure further includes a second gate metal layer 44, which can be arranged on a side of the first gate metal layer 43 away from the substrate 11, or the second gate metal layer 44 can be arranged between the doping layer 42 and the first gate metal layer 43. The second gate metal layer 44 is electrically connected to the first gate metal layer 43; and an ohmic contact is formed between the second gate metal layer 44 and the n-type doping region 422. The ohmic contact between the second gate metal layer 44 and the n-type doping region 422 can short-circuit the parasitic Schottky diode formed between the first gate metal layer 43 and the n-type doping region 422, ensuring that all excess gate voltage is applied to the reverse biased pn junction, thereby facilitating the lateral depletion region of the reverse biased pn junction to limit the gate leakage flowing through the p-type doping region 421, thereby reducing the gate leakage of the transistor.

[0063] Preferably, the main material of the doping layer includes: a combination of one or more of (In, Al)GaN, polysilicon, NiO, and diamond; and / or the thickness of the doping layer is 5 to 500 nm; and / or the doping concentration of the p-type doping region is 10 17 -10 21 cm -3 ; and / or, the doping concentration of the n-type doping region is 10 17 -10 21 cm -3 .

[0064] Preferably, the thickness of the p-(In, Al)GaN epitaxial layer is 10 to 500 nm; and / or the doping concentration of the p-(In, Al)GaN epitaxial layer is 10 17 -10 21 cm -3 .

[0065] Preferably, the doping in the p-(In, Al)GaN epitaxial layer is uniform doping; or, the doping in the p-(In, Al)GaN epitaxial layer is graded doping from top to bottom.

[0066] Figure 6 It is a structural schematic diagram of a hybrid gate GaN-based power transistor structure provided according to some embodiments of the present invention.

[0067] Exemplarily, in some embodiments of the present invention, referring to Figure 6 , the orthographic projection of the p-type doping region 421 on the substrate 11 coincides with the orthographic projection of the first gate metal layer 43 on the substrate, and an ohmic contact is formed between the first gate metal layer 43 and the p-type doping region 421; and the GaN-based power transistor structure of the hybrid gate further includes: a second gate metal layer 44, the second gate metal layer 44 is located on the side of the first gate metal layer 43 away from the substrate 11, wherein the second gate metal layer 44 is electrically connected to the first gate metal layer 43; and an ohmic contact is formed between the second gate metal layer 44 and the n-type doping region 422. By such a design, the formation of a parasitic Schottky diode between the first gate metal layer 43 and the n-type doping region 422 can be avoided, ensuring that all excess gate voltage is applied to the reverse biased pn junction, thereby facilitating the lateral depletion region of the reverse biased pn junction to limit the gate leakage flowing through the p-type doping region 421, thereby reducing the gate leakage of the transistor.

[0068] Preferably, refer to Figure 1 The orthographic projection of the first gate metal layer 43 on the substrate 11 has a second width d2 in the first direction X, and the orthographic projection of the p-(In, Al)GaN epitaxial layer 41 on the substrate 11 has a third width d3 in the first direction X, and the second width d2 is less than or equal to the third width d3. The first width d1 is less than or equal to the second width d2

[0069] Preferably, the work function of the first gate metal layer 43 is in the range of 5.0 to 6.5 eV. The first gate metal layer 43 may be a single metal layer or a metal stack with a high work function. For example, the first gate metal layer 43 may include a combination of one or more of Pt, Ni, Au, and Pd, so as to form an ohmic contact with the p-type doped region 421.

[0070] Preferably, the work function of the second gate metal layer 44 is in the range of 4.0 to 5.5 eV. The second gate metal layer 44 may be a single metal layer or a metal stack with a low work function. For example, the second gate metal layer 44 may include a combination of one or more of Ti, Al, and Cr, so as to form an ohmic contact with the n-type doping region 422.

[0071] Figure 7 It is a structural schematic diagram of a hybrid gate GaN-based power transistor structure provided according to some embodiments of the present invention.

[0072] Exemplarily, in some embodiments of the present invention, referring to Figure 7 The GaN-based power transistor structure of the hybrid gate includes: a stacked structure 1, wherein the stacked structure 1 includes: a substrate 11; a GaN buffer layer 12 arranged on the substrate 11; and an Al(In, Ga)GaN barrier layer 13 arranged on the side of the GaN buffer layer 12 away from the substrate; a source structure 2, arranged at a first end S1 of the stacked structure 1; and a drain structure 3, arranged at a second end S2 of the stacked structure 1 relative to the source structure 2; and a gate structure 4, arranged on the stacked structure 1 and located between the first end S1 and the second end S2, wherein the gate structure 4 includes The invention comprises: a p-(In, Al)GaN epitaxial layer 41 disposed on the stacked structure 1; a doping layer 42 disposed on the side of the p-(In, Al)GaN epitaxial layer 41 away from the stacked structure 1; and a first gate metal layer 43 disposed on the side of the doping layer 42 away from the stacked structure 1, wherein the doping layer 42 comprises at least one via hole VH and a plurality of n-type doping regions 422, and the at least one via hole VH is located between the plurality of n-type doping regions 422; and the first gate metal layer 43 forms an ohmic contact with the p-(In, Al)GaN epitaxial layer 41 through the at least one via hole VH. By such a design, the first gate metal layer 43 and the inside of the p-(In, Al)GaN epitaxial layer 41 can be electrically connected to form a dynamic leakage path, which can balance the charge accumulated inside the p-(In, Al)GaN epitaxial layer 41 when the transistor switch is working, and reach a stable threshold, thereby improving the threshold stability of the transistor. In addition, integrating the dynamic leakage path with the gate conductive metal can simplify the process steps and reduce costs.

[0073] Preferably, refer to Figure 7The orthographic projection of the via hole VH on the substrate 11 has a fourth width d4 in the first direction X, wherein the fourth width d4 is 5 to 1000 nm. The first gate metal layer 43 includes a main body 431 and a connecting portion 432. The connecting portion 432 is located in the via hole VH, and the first gate metal layer 43 is electrically connected to the inside of the p-(In, Al)GaN epitaxial layer 41 through the connecting portion 432.

[0074] Since the connection portion 432 of the first gate metal layer is located in the via hole VH, the width of the orthographic projection of the via hole VH on the substrate 11 in the first direction X can be limited by designing the width of the orthographic projection of the connection portion 432 of the first gate metal layer on the substrate 11 in the first direction X.

[0075] By setting the width of the positive projection of the connecting portion 432 of the first gate metal layer on the substrate 11 in the first direction X to be relatively narrow, under a relatively low gate voltage, the depletion region 100 of the pn junction formed by the plurality of n-type doping regions 422 and the p-(In, Al)GaN epitaxial layer 41 does not pinch off the connecting portion 432 of the first gate metal layer, so that the connecting portion 432 of the first gate metal layer can serve as a channel for electrical connection between the first gate metal layer 43 and the p-(In, Al)GaN epitaxial layer 41, providing a charge path to balance the p-(In, Al)GaN epitaxial layer 41 when the transistor is switched. 41, the charge accumulated inside reaches a stable threshold; under a higher gate voltage, since the width of the connecting portion 432 of the first gate metal layer is narrow and each connecting portion 432 of the first gate metal layer is surrounded by the n-type doping region 422, the depletion region 100 of the pn junction formed by the n-type doping region 422 and the p-(In, Al)GaN epitaxial layer 41 when reverse biased can extend laterally along the first direction X to pinch off the connecting portion 432 of the first gate metal layer, thereby disconnecting the channel of electrical connection between the first gate metal layer 43 and the p-(In, Al)GaN epitaxial layer 41, and reducing gate leakage.

[0076] Figure 8 is a schematic structural diagram of a hybrid gate GaN-based power transistor structure provided according to some embodiments of the present invention; Fig. 9 It is a schematic structural diagram of a hybrid gate GaN-based power transistor structure provided according to some other embodiments of the present invention.

[0077] Exemplarily, in some embodiments of the present invention, in combination with reference Figure 8 and Fig. 9The GaN-based power transistor structure of the hybrid gate further includes a second gate metal layer 44, which can be arranged on a side of the first gate metal layer 43 away from the substrate 11, or the second gate metal layer 44 can be arranged between the doping layer 42 and the first gate metal layer 43. The second gate metal layer 44 is electrically connected to the first gate metal layer 43; and an ohmic contact is formed between the second gate metal layer 44 and the n-type doping region 422. The ohmic contact between the second gate metal layer 44 and the n-type doping region 422 can short-circuit the parasitic Schottky diode formed between the first gate metal layer 43 and the n-type doping region 422, ensuring that all excess gate voltage is applied to the reverse biased pn junction, thereby facilitating the lateral depletion region of the reverse biased pn junction to limit the gate leakage flowing through the first gate metal layer connection portion 432, thereby reducing the gate leakage of the transistor.

[0078] Fig.10 It is a structural schematic diagram of a hybrid gate GaN-based power transistor structure provided according to some embodiments of the present invention.

[0079] Exemplarily, in some embodiments of the present invention, referring to Fig.10 , the orthographic projection of the main part 431 of the first gate metal layer on the substrate 11 coincides with the orthographic projection of the connection part 432 of the first gate metal layer on the substrate; and the GaN-based power transistor structure of the hybrid gate further includes: a second gate metal layer 44, the second gate metal layer 44 is located on the side of the first gate metal layer 43 away from the substrate 11, wherein the second gate metal layer 44 is electrically connected to the first gate metal layer 43; and an ohmic contact is formed between the second gate metal layer 44 and the n-type doping region 422. By designing in this way, it is possible to avoid the formation of a parasitic Schottky diode between the first gate metal layer 43 and the n-type doping region 422, ensuring that all excess gate voltage is applied to the reverse biased pn junction, thereby facilitating the lateral depletion region of the reverse biased pn junction to limit the gate leakage flowing through the connection part 432 of the first gate metal layer, thereby reducing the gate leakage of the transistor. In addition, the integrated design of the dynamic leakage path and the gate conductive metal can also simplify the process steps and reduce costs.

[0080] Although some embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined by the claims and their equivalents.

Claims

1. A hybrid gate GaN-based power transistor structure, It is characterized in that include: A laminated structure, wherein the laminated structure comprises: substrate; A GaN buffer layer disposed on the substrate; and An Al(In, Ga)GaN barrier layer disposed on a side of the GaN buffer layer away from the substrate; A source structure disposed at a first end of the stacked structure; and a drain structure, disposed at a second end of the stacked structure relative to the source structure; and A gate structure is disposed on the stacked structure and located between the first end and the second end, wherein the gate structure comprises: A p-(Tn, Al)GaN epitaxial layer disposed on the stacked structure; a doping layer disposed on a side of the p-(In, Al)GaN epitaxial layer away from the stacked structure; and a first gate metal layer disposed on a side of the doping layer away from the stacked structure, The doping layer includes at least one p-type doping region and a plurality of n-type doping regions, and the at least one p-type doping region is located between the plurality of n-type doping regions.

2. The hybrid gate GaN-based power transistor structure according to claim 1, in, The at least one p-type doping region is surrounded by the plurality of n-type doping regions.

3. The hybrid gate GaN-based power transistor structure according to claim 2, in, The p-type doped region includes m p-type doped sub-regions, wherein m is equal to 1; or, The p-type doping region includes m p-type doping sub-regions, and the m p-type doping sub-regions are arranged in a spaced relationship from each other along a first direction, wherein m is a positive integer greater than or equal to 2; or The p-type doping region includes m p-type doping sub-regions, and the m p-type doping sub-regions are arranged to be spaced apart from each other along the first direction and the second direction, wherein m is a positive integer greater than or equal to 4.

4. The hybrid gate GaN-based power transistor structure according to claim 3, in, The orthographic projection of each of the p-type doped sub-regions on the substrate has a first width in the first direction, and the first width is 5-1000 nm.

5. The hybrid gate GaN-based power transistor structure according to claim 2, in, The orthographic projection of the p-type doping region on the substrate is located within the orthographic projection of the first gate metal layer on the substrate, and an ohmic contact is formed between the first gate metal layer and the p-type doping region; as well as The orthographic projection of the n-type doping region on the substrate partially overlaps with the orthographic projection of the first gate metal layer on the substrate, and a Schottky contact is formed between the n-type doping region and the first gate metal layer.

6. The hybrid gate GaN-based power transistor structure according to claim 3, in, The orthographic projection of each of the m p-type doped sub-regions on the substrate is a strip; or, The orthographic projection of each of the m p-type doped sub-regions on the substrate is a rectangle; or, The orthographic projection of each of the m p-type doped sub-regions on the substrate is a circle.

7. The hybrid gate GaN-based power transistor structure according to claim 5, in, The hybrid gate GaN-based power transistor structure further includes a second gate metal layer, which is disposed on a side of the first gate metal layer away from the substrate, or the second gate metal layer is disposed between the doped layer and the first gate metal layer; The second gate metal layer is electrically connected to the first gate metal layer; and An ohmic contact is formed between the second gate metal layer and the n-type doping region.

8. The hybrid gate GaN-based power transistor structure according to claim 2, in, The main material of the doping layer includes: a combination of one or more of (In, Al)GaN, polysilicon, NiO, and diamond; and / or, The thickness of the doping layer is 5 to 500 nm; and / or, The doping concentration of the p-type doping region is 10 17 -10 21 cm -3 and / or, The doping concentration of the n-type doping region is 10 17 -10 21 cm -3 .

9. The hybrid gate GaN-based power transistor structure according to claim 2, in, The thickness of the p-(In, Al)GaN epitaxial layer is 10 to 500 nm; and / or, The doping concentration of the p-(In, Al)GaN epitaxial layer is 10 17 -10 21 cm -3 .

10. The hybrid gate GaN-based power transistor structure according to claim 2, in, The doping in the p-(In, Al)GaN epitaxial layer is uniformly doped; or, The doping in the p-(In, Al)GaN epitaxial layer is graded from top to bottom.

11. The hybrid gate GaN-based power transistor structure according to claim 2, in, The orthographic projection of the p-type doped region on the substrate coincides with the orthographic projection of the first gate metal layer on the substrate, and an ohmic contact is formed between the first gate metal layer and the p-type doped region; as well as The hybrid gate GaN-based power transistor structure also includes: a second gate metal layer, which is located on a side of the first gate metal layer away from the substrate, wherein the second gate metal layer is electrically connected to the first gate metal layer; and an ohmic contact is formed between the second gate metal layer and the n-type doped region.

12. The hybrid gate GaN-based power transistor structure according to any one of claims 1 to 11, in, The orthographic projection of the first gate metal layer on the substrate has a second width in the first direction, the orthographic projection of the p-(In, Al)GaN epitaxial layer on the substrate has a third width in the first direction, and the second width is less than or equal to the third width.

13. The hybrid gate GaN-based power transistor structure according to claim 12, in, The work function range of the first gate metal layer is 5.0 to 6.5 eV; and / or, The work function of the second gate metal layer ranges from 4.0 to 5.5 eV.

14. A hybrid gate GaN-based power transistor structure, It is characterized in that include: A laminated structure, wherein the laminated structure comprises: substrate; A GaN buffer layer disposed on the substrate; and An Al(In, Ga)GaN barrier layer disposed on a side of the GaN buffer layer away from the substrate; A source structure disposed at a first end of the stacked structure; and a drain structure, disposed at a second end of the stacked structure opposite to the source structure; and A gate structure is disposed on the stacked structure and is located between the first end and the second end, wherein: The gate structure comprises: A p-(In, Al)GaN epitaxial layer disposed on the stacked structure; A doping layer disposed on a side of the p-(In, Al)GaN epitaxial layer away from the stacked structure; and a first gate metal layer disposed on a side of the doping layer away from the stacked structure, wherein the doping layer comprises at least one via hole and a plurality of n-type doping regions, and the at least one via hole is located between the plurality of n-type doping regions; and The first gate metal layer forms an ohmic contact with the p-(In, Al)GaN epitaxial layer through the at least one via hole.

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