NMOS (N-channel metal oxide semiconductor) device structure and forming method thereof

Abstract

The invention discloses an NMOS device structure and a forming method thereof, the device comprises an SOI substrate, the SOI substrate comprises a top silicon layer, a source region, a drain region and a body contact region are distributed in the top silicon layer, the source region and the drain region are arranged along a first direction, the body contact region is at least located on the source region and one side of the top silicon layer between the source region and the drain region along a second direction, and the first direction is perpendicular to the second direction; the first isolation structure is at least located between the top silicon layer between the source region and the drain region and the body contact region and penetrates through the top silicon layer, the first isolation structure and the gate structure are partially overlapped, the two ends of the first isolation structure in the first direction are a first isolation end and a second isolation end respectively, and the first isolation end is located between the source region and the drain region; the second isolation end is flush with or exceeds the boundary of the body contact area in the first direction; the gate structure is located on the surface of the top silicon layer, the source region and the drain region are located on the two sides of the gate structure respectively, and the first isolation structure and the gate structure are partially overlapped. The stray capacitance is reduced, and the floating body effect suppression effect is good.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to an NMOS device structure and a forming method thereof. Background Art

[0002] Compared with bulk silicon devices, PD-SOI devices (partially depleted SOI devices) made on SOI substrates are widely used in RF, MEMS and other fields due to their superior performance such as good device isolation, no latch-up effect, and reduced coupling effect between active and passive devices and the substrate.

[0003] However, the Kinke effect caused by the floating body effect of PD-SOI devices is harmful in analog circuits. In order to suppress the floating body effect, the body is usually connected to a fixed potential to control the change of body potential. This method is called body contact.

[0004] like Figure 1 and Figure 2 As shown, in the conventional T-type gate structure, P+ is ion-implanted downward from the top part of the T-type gate 10 to form a P+ implantation region 20, and the P+ implantation region 20 is connected to the P-type body region 30 below the T-type gate 10. When the MOS device is working, the hole carriers accumulated in the P-type body region 30 are discharged through the P+ implantation region 20, thereby achieving the purpose of reducing the body region potential. However, there is a large parasitic capacitance and parasitic resistance between the additional T-type gate extension region and the lower oxide layer and the top silicon layer, which causes device performance delay and circuit performance degradation. Summary of the invention

[0005] The technical problem solved by the present invention is to provide an NMOS device structure and a method for forming the same, so as to reduce parasitic capacitance and parasitic resistance and achieve good floating body effect suppression effect.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides an NMOS device structure, comprising: an SOI substrate, the SOI substrate comprising a top silicon layer, a source region, a drain region and a body contact region are distributed in the top silicon layer, the source region and the drain region are arranged along a first direction, the body contact region is at least located on one side of the source region and the top silicon layer between the source region and the drain region along a second direction, and the first direction is perpendicular to the second direction; a first isolation structure, located between the top silicon layer between the source region and the drain region and the body contact region, and penetrates the top silicon layer, the two ends of the first isolation structure along the first direction are respectively a first isolation end and a second isolation end, the first isolation end is closer to the source region than the second isolation end, and the first isolation end is located between the source region and the drain region, and the second isolation end is flush with or exceeds the boundary of the body contact region in the first direction; a gate structure, located on the surface of the top silicon layer, the source region and the drain region are respectively located on both sides of the gate structure, and the first isolation structure partially overlaps with the gate structure.

[0007] Optionally, the body contact region is also located on one side of the drain region along the second direction.

[0008] Optionally, the gate structure is a straight-line structure extending along the second direction, and one end of the gate structure extends to a surface of the first isolation structure.

[0009] Optionally, the gate structure includes a first partial gate and a second partial gate which are connected and form an "L"-shaped structure, the source region and the drain region are located on both sides of the first partial gate, the second partial gate is located on the surface of the first isolation structure, and on the surfaces of the drain region and the body contact region on both sides of the first isolation structure along the second direction, the second partial gate includes adjacent first and second regions, the first region is located on the surface of the drain region, and the doping ion type of the first region is the same as the doping ion type of the drain region, the second region is located on the surface of the body contact region, and the doping ion type of the second region is the same as the doping ion type of the body contact region.

[0010] Optionally, the source region is in contact with the body contact region; the NMOS device structure further includes: a silicide blocking layer located on the surfaces of the source region and the body contact region, and the silicide blocking layer covers the surface where the source region and the body contact region are connected.

[0011] Optionally, the gate structure includes a first partial gate and a third partial gate which are connected and form an "L"-shaped structure, the source region and the drain region are located on both sides of the first partial gate, the third partial gate is located on the surface of the first isolation structure, the source region and the body contact region, the third partial gate includes adjacent third and fourth regions, the third region is located on the surface of the source region, the doping ion type of the third region is the same as the doping ion type of the source region, the fourth region is located on the surface of the body contact region, and the doping ion type of the fourth region is the same as the doping ion type of the body contact region.

[0012] Optionally, the source region and the body contact region are spaced apart.

[0013] Optionally, it further includes: a second isolation structure, wherein the second isolation structure is located in the top silicon layer and penetrates the top silicon layer, and the second isolation structure surrounds the source region, the drain region and the body contact region.

[0014] Optionally, surfaces of the gate structure, the source region, the drain region and the body contact region have a metal silicide film.

[0015] Correspondingly, the technical solution of the present invention also provides a method for forming the above-mentioned NMOS device structure, including: providing an SOI substrate; based on a mask, forming a plurality of isolation openings in the top silicon layer of the SOI substrate, the bottom of the isolation openings exposing the surface of the buried oxide layer of the SOI substrate; filling materials in the plurality of isolation openings to form a first isolation structure and a shallow trench isolation structure other than the first isolation structure, the first isolation structure and the shallow trench isolation structure other than the first isolation structure penetrate the top silicon layer and contact the buried oxide layer; after forming the first isolation structure and the shallow trench isolation structure other than the first isolation structure, forming a source region, a drain region and a body contact region in the top silicon layer, respectively, the source region and the drain region are arranged along a first direction, the body contact region is at least located in the source region, and the The first direction is perpendicular to the second direction; after the source region, the drain region and the body contact region are formed, a gate structure is formed on the surface of the top silicon layer, and the source region and the drain region are respectively located on both sides of the gate structure; wherein the first isolation structure is also at least located between the top silicon layer between the source region and the drain region and the body contact region, and the first isolation structure partially overlaps with the gate structure, and the two ends of the first isolation structure along the first direction are respectively a first isolation end and a second isolation end, the first isolation end is closer to the source region than the second isolation end, and the first isolation end is located between the source region and the drain region, and the second isolation end is flush with or exceeds the boundary of the body contact region in the first direction.

[0016] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0017] In the NMOS device structure and its formation method provided by the technical solution of the present invention, since the first isolation structure penetrates the top silicon layer and partially overlaps with the gate structure, the first isolation structure is not the top silicon layer below the portion of the gate structure overlapping with the first isolation structure, thereby reducing the parasitic capacitance generated by the gate structure and the top silicon layer. In addition, since the first isolation structure is at least located between the top silicon layer and the body contact region between the source region and the drain region, and the first isolation end is located between the source region and the drain region, and the second isolation end is flush with or exceeds the boundary of the body contact region in the first direction, the first isolation structure completely isolates the contact or coupling between the drain region and the body contact region, reduces the width of the depletion layer generated between the body contact region and the source and drain, and reduces the resistance between the two, thereby ensuring the extraction efficiency of the body contact region, so that the floating body effect suppression effect of the NMOS device is good. In summary, the parasitic capacitance is reduced, the shutdown performance of the device at high frequencies is improved, and the RF performance is improved. In addition, the extraction efficiency of the body contact region is high, and the floating body effect suppression effect of the NMOS device is good. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of the structure of a PD-SOI device;

[0019] Figure 2 yes Figure 1 Schematic diagram of the cross-sectional structure along the A1-A2 direction;

[0020] Figure 3 is a schematic top view of the NMOS device structure in the first embodiment of the present invention;

[0021] Figure 4 yes Figure 3 A schematic diagram of the cross-sectional structure along the A3-A4 direction;

[0022] Figure 5 is a schematic top view of the NMOS device structure in the second embodiment of the present invention;

[0023] Figure 6 yes Figure 5 Schematic diagram of the cross-sectional structure along the B1-B2 direction;

[0024] Figure 7 is a schematic top view of an NMOS device structure in a third embodiment of the present invention;

[0025] Figure 8 yes Figure 7 A schematic diagram of the cross-sectional structure along the A3-A4 direction;

[0026] Fig. 9is a schematic top view of an NMOS device structure in another embodiment of the present invention;

[0027] Fig.10 is a schematic top view of an NMOS device structure in a fourth embodiment of the present invention;

[0028] Fig.11 yes Fig.10 A schematic diagram of the cross-sectional structure along the A3-A4 direction;

[0029] Fig.12 is a schematic top view of an NMOS device structure in a fifth embodiment of the present invention;

[0030] Fig.13 yes Fig.12 Schematic diagram of the cross-sectional structure along the B1-B2 direction;

[0031] Fig.14 is a schematic top view of an NMOS device structure in a fifth embodiment of the present invention;

[0032] Fig.15 yes Fig.14 Schematic diagram of the cross-sectional structure along the B1-B2 direction.

[0033] Description of reference numerals:

[0034] 10-T-type gate; 20-P+ injection region; 30-P-type body region;

[0035] 100-SOI substrate; 101-bottom silicon layer; 102-buried oxide layer; 103-top silicon layer; 110, 210, 310-gate structure; 211, 311-first partial gate; 212-second partial gate; 313-third partial gate; 120, 220, 320-first isolation structure; 121, 321-first isolation terminal; 122, 222, 322-second isolation terminal; 130-second isolation structure; 140-metal silicide film; 150, 151-conductive structure; 160-silicide blocking layer; I-first region; II-second region; III-third region; IV-fourth region; S-source region; D-drain region; B-body contact region. DETAILED DESCRIPTION

[0036] As described in the background art, in the existing PD-SOI device structure, there is a large parasitic capacitance and parasitic resistance between the body contact and the bottom silicon of the SOI substrate, which causes circuit device delay and reduces RF performance.

[0037] In order to solve the above technical problems, the technical solution of the present invention provides an NMOS device structure and a method for forming the same. A first isolation structure is set up, and the first isolation structure penetrates the top silicon layer and partially overlaps with the gate structure. The first isolation structure isolates the drain region and the body contact region. The length of the first isolation structure along the first direction is less than the length of the body contact region along the first direction, thereby achieving isolation between the parasitic device and the main device to reduce the parasitic resistance, and achieving reduction of the parasitic capacitance, and having a good floating body effect suppression effect.

[0038] In order to make the above-mentioned purposes, features and beneficial effects of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. In addition, directional terms such as above, below, up, down, upward, downward, left, right, etc. are used relative to the exemplary embodiments as they are shown in the figures, with the upward or upper direction toward the top of the corresponding figure, and the downward or lower direction toward the bottom of the corresponding figure.

[0040] [First embodiment]

[0041] Please refer to Figure 3 and Figure 4 The NMOS device structure includes: an SOI substrate 100 , a gate structure 110 and a first isolation structure 120 .

[0042] It should be noted that Figure 3 For ease of understanding, the position of the first isolation structure 120 below the gate structure 110 is indicated by a dotted line.

[0043] The SOI substrate 100 includes a bottom silicon layer 101 , a buried oxide layer 102 , and a top silicon layer 103 which are stacked in sequence.

[0044] The source region S, drain region D, and body contact region B are distributed within the top silicon layer 103.

[0045] The doping ion types of the source region S and drain region D are opposite to that of the body contact region B.

[0046] In this embodiment, both the source region S and drain region D are N-type heavily doped regions, and the body contact region B is a P-type heavily doped region.

[0047] It should be noted that Figure 1 、 Figure 3 、 Figure 5 、 Figure 7 、 Fig. 9 、 Fig.10 、 Fig.12 and Fig.14 In

[0048] ,

[0049] the N+ region (N-type heavily doped region) is represented by a blue dashed line, and the P+ region (P-type heavily doped region) is represented by a red dashed line, so as to facilitate the understanding of the above embodiments.

[0050] The source region S and drain region D are arranged along the first direction X, and the body contact region B is at least located on one side of the top silicon layer 103 between the source region S and between the source region S and drain region D along the second direction Y. Wherein, the first direction X and the second direction Y are perpendicular to each other.

[0051] In one embodiment, a diode is formed between the body contact region B and the source region to attract the holes generated by the floating body region, thereby realizing pick up.

[0052] In this embodiment, the layer thickness of the top silicon layer 103 is greater than the depth of the depletion layer. Correspondingly, the body contact region B attracts the holes generated by the floating body region through the top silicon layer 103 under the source region S to realize pick up, and has a higher pick up efficiency.

[0053] The gate structure 110 is located on the surface of the top silicon layer 103, and the source region S and drain region D are respectively located on both sides of the gate structure 110.

[0054] Specifically, the gate structure 110 includes: a gate dielectric layer (not shown) located on the surface of the top silicon layer 103, and a gate electrode located on the surface of the gate dielectric layer.

[0055] The material of the gate electrode includes N-type heavily doped polysilicon.

[0056] The first isolation structure 120 is located between the top silicon layer 103 and the body contact region B between the source region S and the drain region D and penetrates the top silicon layer 103 . In the direction from the gate structure 110 to the SOI substrate 100 , the first isolation structure 120 partially overlaps with the gate structure 110 .

[0057] The two ends of the first isolation structure 120 along the first direction X are respectively a first isolation end 121 and a second isolation end 122. The first isolation end 121 is closer to the source region S than the second isolation end 122, and the first isolation end 121 is located between the source region S and the drain region D. The second isolation end 122 is flush with the boundary of the body contact region B in the first direction X.

[0058] Since the first isolation structure 120 penetrates the top silicon layer 103 and partially overlaps with the gate structure 110, the first isolation structure 120 rather than the top silicon layer 103 is located below the portion of the gate structure 110 overlapping with the first isolation structure 120. Therefore, the parasitic capacitance generated between the gate structure 110 and the top silicon layer 103 is reduced.

[0059] In addition, since the first isolation structure 120 is at least located between the top silicon layer 103 and the body contact region B between the source region S and the drain region D, and the first isolation end 121 is located between the source region S and the drain region D, and the second isolation end 122 is flush with the boundary of the body contact region B in the first direction X, therefore, on the one hand, the first isolation structure 120 completely isolates the contact or coupling between the drain region D and the body contact region B, reduces the width of the depletion layer generated between the body contact region B and the source and drain, and reduces the resistance from the N+ region to the P+ region. On the other hand, the first isolation structure 120 does not overlap with the source region S in the first direction X, and provides sufficient channels for the extraction of holes between the source region S and the body contact region B, thereby ensuring the extraction efficiency of the body contact region B and achieving good suppression of the floating body effect of the NMOS device.

[0060] In summary, the parasitic capacitance is reduced, the turn-off performance of the device at high frequencies is improved, the RF performance is enhanced, and the lead-out efficiency of the body contact region B is high, and the floating body effect suppression effect of the NMOS device is good.

[0061] Moreover, since the first isolation structure 120 penetrates the top silicon layer 103, the first isolation structure 120 is not connected to other STI structures (shallow trench isolation structures, such as Figure 4The depth of the second isolation structure 130) shown in the figure is the same, so that during the formation process of the NMOS device structure, the first isolation structure 120 can be formed with other shallow trench isolation structures using the same photomask (PhotoMask) without the need for an additional photomask, so that the process of the first isolation structure 120 is simple and the manufacturing cost is low.

[0062] It should be understood that although the first isolation end 121 is located between the source region S and the drain region D, in order to ensure that the first isolation structure 120 partially overlaps with the gate structure 110, the distance between the first isolation end 121 and the source region S in the first direction X is greater than or equal to zero, but the distance between the first isolation end 121 and the drain region D in the first direction X is greater than zero.

[0063] In the present embodiment, the first isolation end 121 extends to the boundary of the source region S. Therefore, the parasitic capacitance generated between the gate structure 110 and the top silicon layer 103 is minimized.

[0064] In other embodiments, the first isolation terminal may also be located at any other position between the boundary of the source region S and the boundary of the drain region D.

[0065] The first isolation structure 120 is a dielectric material.

[0066] Furthermore, the gate structure 110 is a straight-line structure extending along the second direction Y, and one end of the gate structure 110 extends to the surface of the first isolation structure 120. Therefore, on the one hand, a partially overlapping structure between the gate structure 110 and the first isolation structure 120 can be achieved, and on the other hand, there is no additional T-shaped extension, so that compared with the traditional T-shaped gate structure contact, the parasitic capacitance can be greatly reduced and the floating body effect can be improved.

[0067] Furthermore, the source region S is in contact with the body contact region B, thereby facilitating improvement of device integration.

[0068] Furthermore, the surfaces of the gate structure 110, the source region S, the drain region D, and the body contact region B are all provided with a metal silicide film 140, and mutually independent conductive structures are formed on the gate structure 110, the source region S, the drain region D, and the body contact region B, respectively, and the bottom of the conductive structure contacts the metal silicide film 140. Thus, the resistance between the gate structure 110, the source region S, the drain region D, and the body contact region B and the conductive structure is further reduced, and the device performance is improved.

[0069] Among the mutually independent conductive structures, each conductive structure 150 is located at the gate structure 110 , the source region S and the drain region D respectively, and the conductive structure 151 is located on the body contact region B.

[0070] The material of the metal silicide film 140 is, for example, nickel silicide (NiSi) or other materials such as CoSi.

[0071] It should be noted that, for ease of understanding and explanation, Figure 3 The metal silicide film 140 is not shown.

[0072] In this embodiment, the NMOS device structure further includes: a second isolation structure 130 .

[0073] The second isolation structure 130 is located in the top silicon layer 103 and penetrates the top silicon layer 103. The second isolation structure 130 surrounds the source region S, the drain region D and the body contact region B, thereby isolating the device surrounded by the second isolation structure 130 from other devices. In other words, the second isolation structure 130 is used for isolation between devices.

[0074] The material of the second isolation structure 130 is a dielectric material.

[0075] Accordingly, an embodiment of the present invention provides a method for forming an NMOS device structure to form Figure 3 and Figure 4 The NMOS device structure in the illustrated embodiment may include:

[0076] An SOI substrate 100 is provided.

[0077] Based on a photomask, a plurality of isolation openings (not shown) penetrating the top silicon layer 103 are formed in the top silicon layer 103 of the SOI substrate 100 , and the bottoms of the isolation openings expose a portion of the buried oxide layer 102 surface of the SOI substrate 100 .

[0078] Materials are filled in the isolation openings to form a first isolation structure 120 and a shallow trench isolation structure (not shown) outside the first isolation structure 120 , so that the first isolation structure 120 and the shallow trench isolation structure outside the first isolation structure 120 penetrate the top silicon layer 103 and contact the buried oxide layer 102 .

[0079] After forming the first isolation structure 120 and the shallow trench isolation structure outside the first isolation structure 120 , a source region S, a drain region D and a body contact region B are respectively formed in the top silicon layer 103 .

[0080] After forming the source region S, the drain region D and the body contact region B, a gate structure 110 is formed on the surface of the SOI substrate 100 . The source region S and the drain region D are respectively located on two sides of the gate structure 110 .

[0081] It should be noted that for the specific description of each feature in the embodiment of the present formation method, please refer to the detailed explanation and description of each feature in the aforementioned NMOS device structure embodiment, which will not be repeated here.

[0082] In one embodiment, after the gate structure 110 is formed, a metal silicide film 140 is formed on the surfaces of the gate structure 110 , the source region S, the drain region D and the body contact region B.

[0083] In one embodiment, after the gate structure 110 is formed, a plurality of conductive structures respectively located at the gate structure 110 , the source region S, and the drain region D are further formed.

[0084] In one embodiment, the conductive structure may be formed on the metal silicide film 140 , that is, the conductive structure is respectively connected to the gate structure 110 , the source region S, the drain region D and the body contact region B through the metal silicide film 140 .

[0085] In one of the embodiments, after forming the source region S, the drain region D and the body contact region B, a second isolation structure 130 is formed in and through the top silicon layer 103. The second isolation structure 130 surrounds the source region S, the drain region D and the body contact region B, thereby isolating the device surrounded by the second isolation structure 130 from other devices.

[0086] [Second embodiment]

[0087] This embodiment is a modified embodiment of the first embodiment. Please refer to Figure 5 and Figure 6 The difference between this embodiment and the first embodiment is that the NMOS device structure further includes: a silicide blocking layer 160 (SAB).

[0088] The silicide blocking layer 160 is located on the surface of the source region S and the body contact region B, and the silicide blocking layer 160 covers the surface where the source region S and the body contact region B are connected.

[0089] The silicide barrier layer 160 makes the surface where the source region S and the body contact region B meet become a high impedance region, which is beneficial for the hole carriers generated by the device to be led out from the lightly doped silicon layer under the silicide, further improving the Pickup efficiency of the body contact region B.

[0090] In the present embodiment, the depth of the source region S below the silicide blocking layer 160 is consistent with the depth of the source region S not covered by the silicide blocking layer 160 .

[0091] In other embodiments, when the silicide blocking layer 160 is formed before the source region S and the body contact region B, it can also block the injected ions so that the depths of the source region S and the body contact region B below the silicide blocking layer 160 are smaller, and accordingly, the depth of the source region S below the silicide blocking layer 160 is smaller than the depth of the source region S not covered by the silicide blocking layer 160. Thus, the Pickup efficiency of the body contact region B is further improved.

[0092] The material of the silicide blocking layer 160 includes, but is not limited to, silicon oxide or silicon nitride.

[0093] Accordingly, an embodiment of the present invention provides a method for forming an NMOS device structure to form Figure 5 and Figure 6 The NMOS device structure in the illustrated embodiment is different from the above-mentioned embodiment of the method for forming the NMOS device structure in that a silicide blocking layer 160 is further formed on the surface of the source region S and the body contact region B.

[0094] In this embodiment, the silicide blocking layer 160 is formed after the source region S and the body contact region B are formed.

[0095] In other embodiments, the silicide blocking layer 160 is formed after the first isolation structure 120 is formed and before the source region S and the body contact region B are formed.

[0096] [Third embodiment]

[0097] This embodiment is a modified embodiment of the second embodiment. Please refer to Figure 7 and Figure 8 The difference between this embodiment and the second embodiment is that in this embodiment, the gate structure 110 and the first isolation structure 120 in the second embodiment are replaced by a gate structure 210 and a first isolation structure 220 .

[0098] It should be noted that, for ease of understanding, Figure 7 The portion of the gate structure 210 above the first isolation structure 220 is not shown.

[0099] The difference between the first isolation structure 220 and the first isolation structure 120 is that the second isolation end 222 of the first isolation structure 220 exceeds the boundary between the body contact region B and the drain region D in the first direction X. Thus, the isolation between the body contact region B and the drain region D is further ensured.

[0100] In this embodiment, the gate structure 210 includes a first partial gate 211 and a second partial gate 212 .

[0101] The first partial gate 211 and the second partial gate 212 are connected to form an “L”-shaped structure.

[0102] The source region S and the drain region D are located at both sides of the first partial gate 211 .

[0103] The second partial gate 212 is located on a surface of the first isolation structure 220 and surfaces of the drain region D and the body contact region B at both sides of the first isolation structure 220 along the second direction Y.

[0104] The second partial gate 212 includes adjacent first and second regions I and II.

[0105] The first region I is located on the surface of the drain region D on one side of the first isolation structure 220 along the second direction Y, and the doping ion type of the first region I is the same as the doping ion type of the drain region D. Further, the first region I is heavily N-type doped.

[0106] The second region II is located on the surface of the body contact region B on the other side of the first isolation structure 220 along the second direction Y, and the doping ion type of the second region II is the same as the doping ion type of the body contact region B. Further, the second region II is heavily P-type doped.

[0107] Specifically, the gate structure 210 includes: a gate dielectric layer (not shown) located on the surface of the top silicon layer 103, and a gate electrode located on the surface of the gate dielectric layer. The material of the gate electrode includes polysilicon, and the gate electrode of the first region I is heavily doped with N type, and the gate electrode of the second region II is heavily doped with P type.

[0108] In another embodiment, the silicide blocking layer 160 (eg, Fig. 9 ).

[0109] [Fourth embodiment]

[0110] This embodiment is a modified embodiment of the first embodiment. Please refer to Fig.10 and Fig.11 The difference between this embodiment and the first embodiment is that in this embodiment, the gate structure 110 and the first isolation structure 120 in the second embodiment are replaced by a gate structure 310 and a first isolation structure 320 .

[0111] It should be noted that, for ease of understanding, Fig.10 The portion of the gate structure 310 above the first isolation structure 320 is not shown.

[0112] The difference between the first isolation structure 320 and the first isolation structure 120 is that the first isolation end 321 of the first isolation structure 320 is located in the middle area between the source region S and the drain region D.

[0113] In addition, the second isolation end 322 of the first isolation structure 320 exceeds the boundary between the body contact region B and the drain region D in the first direction X. Thus, the isolation between the body contact region B and the drain region D is further ensured.

[0114] In this embodiment, the gate structure 310 includes a first partial gate 311 and a third partial gate 313 .

[0115] The first partial gate 311 and the third partial gate 313 are connected to form an “L”-shaped structure.

[0116] The source region S and the drain region D are located at both sides of the first partial gate 311 .

[0117] The third partial gate 313 is located on the surface of the source region S and the body contact region B of the first isolation structure 320 .

[0118] The third partial gate 313 includes adjacent third and fourth regions III and IV.

[0119] The third region III is located on the surface of the source region S, and the doping ion type of the third region III is the same as the doping ion type of the source region S. Furthermore, the third region III is heavily N-type doped.

[0120] The fourth region IV is located on the surface of the body contact region B, and the doping ion type of the fourth region IV is the same as the doping ion type of the body contact region B. Furthermore, the fourth region IV is heavily doped with P type.

[0121] Specifically, the gate structure 310 includes: a gate dielectric layer (not shown) located on the surface of the top silicon layer 103, and a gate electrode located on the surface of the gate dielectric layer. The material of the gate electrode includes polysilicon, and the gate electrode of the third region III is heavily doped with N type, and the gate electrode of the fourth region IV is heavily doped with P type.

[0122] [Fifth embodiment]

[0123] This embodiment is a modified embodiment of the first embodiment. Please refer to Fig.12 and Fig.13 The difference between this embodiment and the first embodiment is that in this embodiment, the source region S and the body contact region B are spaced apart.

[0124] By creating a gap between the source region S and the body contact region B, the width of the depletion layer between the two is further reduced, thereby further reducing the resistance from the N+ region to the P+ region, thereby further improving the extraction efficiency (Pick up efficiency) of the body contact region B and enhancing the floating body effect suppression effect of the NMOS device.

[0125] [Sixth embodiment]

[0126] This embodiment is a variation of the fifth embodiment. Fig.14 and Fig.15 The difference between this embodiment and the fifth embodiment is that in this embodiment, the gate structure 110 and the first isolation structure 120 in the fifth embodiment are replaced by a gate structure 310 and a first isolation structure 320 .

[0127] It should be noted that, for ease of understanding, Fig.14 The position of the body contact region B below the gate structure 310 is shown by a dotted line.

[0128] For detailed description of the gate structure 310 and the first isolation structure 320 , please refer to the related explanations and illustrations in the aforementioned fourth embodiment, which will not be repeated here.

[0129] In other embodiments, the gate structure 210 may be used to replace the gate structure 110 in the fifth embodiment. Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. An NMOS device structure, characterized in that: include: An SOI substrate, the SOI substrate comprising a top silicon layer, a source region, a drain region and a body contact region distributed in the top silicon layer, the source region and the drain region being arranged along a first direction, the body contact region being at least located on one side of the source region and the top silicon layer between the source region and the drain region along a second direction, the first direction being perpendicular to the second direction; a first isolation structure, located between the top silicon layer between the source region and the drain region and the body contact region, and penetrating the top silicon layer, wherein two ends of the first isolation structure along the first direction are respectively a first isolation end and a second isolation end, wherein the first isolation end is closer to the source region than the second isolation end, and the first isolation end is located between the source region and the drain region, and the second isolation end is flush with or exceeds a boundary of the body contact region in the first direction; The gate structure is located on the surface of the top silicon layer, the source region and the drain region are respectively located on both sides of the gate structure, and the first isolation structure partially overlaps with the gate structure.

2. The NMOS device structure according to claim 1, characterized in that: The body contact region is also located at one side of the drain region along the second direction.

3. The NMOS device structure according to claim 1, characterized in that: The gate structure is a straight-line structure extending along the second direction, and one end of the gate structure extends to the surface of the first isolation structure.

4. The NMOS device structure according to claim 1, characterized in that: The gate structure includes a first partial gate and a second partial gate that are connected and form an "L"-shaped structure, the source region and the drain region are located on both sides of the first partial gate, the second partial gate is located on the surface of the first isolation structure, and on the surfaces of the drain region and the body contact region on both sides of the first isolation structure along the second direction, the second partial gate includes adjacent first and second regions, the first region is located on the surface of the drain region, the doping ion type of the first region is the same as the doping ion type of the drain region, the second region is located on the surface of the body contact region, and the doping ion type of the second region is the same as the doping ion type of the body contact region.

5. The NMOS device structure according to any one of claims 3 or 4, characterized in that: The source region is in contact with the body contact region; the NMOS device structure further includes: a silicide barrier layer located on the surfaces of the source region and the body contact region, and the silicide barrier layer covers the surface where the source region and the body contact region are connected.

6. The NMOS device structure according to claim 1, characterized in that: The gate structure includes a first partial gate and a third partial gate which are connected and form an "L"-shaped structure, the source region and the drain region are located on both sides of the first partial gate, the third partial gate is located on the surface of the first isolation structure, the source region and the body contact region, the third partial gate includes adjacent third and fourth regions, the third region is located on the surface of the source region, the doping ion type of the third region is the same as the doping ion type of the source region, the fourth region is located on the surface of the body contact region, and the doping ion type of the fourth region is the same as the doping ion type of the body contact region.

7. The NMOS device structure according to claim 1, characterized in that: The source region is spaced apart from the body contact region.

8. The NMOS device structure according to claim 1, characterized in that: Also includes: A second isolation structure is disposed in the top silicon layer and penetrates the top silicon layer, and the second isolation structure surrounds the source region, the drain region and the body contact region.

9. The NMOS device structure according to claim 1, characterized in that: The surfaces of the gate structure, the source region, the drain region and the body contact region have metal silicide films.

10. A method for forming an NMOS device structure, characterized in that: include: Providing an SOI substrate; Based on a photomask, a plurality of isolation openings are formed in the top silicon layer of the SOI substrate, wherein the bottoms of the isolation openings expose the surface of the buried oxide layer of the SOI substrate; Filling a material in the plurality of isolation openings to form a first isolation structure and a shallow trench isolation structure outside the first isolation structure, wherein the first isolation structure and the shallow trench isolation structure outside the first isolation structure penetrate the top silicon layer and contact the buried oxide layer; After forming a first isolation structure and a shallow trench isolation structure other than the first isolation structure, a source region, a drain region and a body contact region are respectively formed in the top silicon layer, wherein the source region and the drain region are arranged along a first direction, and the body contact region is at least located on one side of the top silicon layer between the source region and the drain region along a second direction, wherein the first direction is perpendicular to the second direction; After forming the source region, the drain region and the body contact region, forming a gate structure on the surface of the top silicon layer, wherein the source region and the drain region are respectively located on two sides of the gate structure; Among them, the first isolation structure is also at least located between the top silicon layer between the source region and the drain region and the body contact region, and the first isolation structure partially overlaps with the gate structure, and the two ends of the first isolation structure along the first direction are respectively a first isolation end and a second isolation end, the first isolation end is closer to the source region than the second isolation end, and the first isolation end is located between the source region and the drain region, and the second isolation end is flush with or exceeds the boundary of the body contact region in the first direction.

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