Silicon carbide VDMOS insulation high UIS characteristic terminal and preparation method thereof

Abstract

The invention provides a silicon carbide VDMOS insulation high UIS characteristic terminal and a preparation method thereof, and the method comprises the steps: carrying out the epitaxial growth on a silicon carbide substrate, and forming a drift layer; forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and performing ion implantation to form a P-type region; re-forming a barrier layer, etching the barrier layer to form a through hole, and performing ion implantation to form a P + well region; re-forming a barrier layer, etching the barrier layer to form a through hole, and performing ion implantation to form a P + region; re-forming a barrier layer, etching the barrier layer to form a through hole, etching the P + well region and the P-type region to form a groove, and depositing an insulating medium to form an insulating medium region; re-forming a barrier layer, etching the barrier layer to form a through hole, and depositing to form an insulating layer; and re-forming a barrier layer, etching the barrier layer to form a through hole, depositing metal, forming a source metal layer, and removing the barrier layer, thereby improving the UIS performance of the terminal.

Description

Technical Field

[0001] The invention relates to a silicon carbide VDMOS insulation high UIS characteristic terminal and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices and is widely used in electric vehicles, aerospace, power conversion and other fields. Based on the device structure design, the edge of the repeated cell has electric field concentration in the lateral direction due to the lateral distribution of the electric field, resulting in breakdown at the edge of the device. The traditional cell uses the same doping concentration field limiting ring structure to suppress the electric field concentration. Since the doping concentration and spacing distribution of the field limiting ring are equal, the electric field strength distribution gradually decreases, and there are still high and low differences in the electric field distribution. The risk of breakdown in the area close to the P+ well area is still high. In addition, since the device works under the condition of unclamped inductive load, there is a situation where the drain is subjected to high voltage after the device is turned off, that is, the UIS characteristic of the device, and the terminal structure has a weak point in the device UIS characteristic. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a silicon carbide VDMOS insulation high UIS characteristic terminal and a preparation method to improve the UIS performance of the terminal.

[0004] In a first aspect, the present invention provides a method for preparing a silicon carbide VDMOS insulated high UIS characteristic terminal, comprising the following steps: Step 1: epitaxially growing on a silicon carbide substrate to form a drift layer; Step 2, forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions to form a P-type region; Step 3, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implantation to form a P+ well region; Step 4, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implantation to form a P+ region; Step 5, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the P+ well region and the P-type region to form a groove, and depositing an insulating medium to form an insulating medium region; Step 6, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form an insulating layer; Step 7: remove the barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer, and remove the barrier layer.

[0005] In a second aspect, the present invention provides a silicon carbide VDMOS insulation high-UIS characteristic terminal, and the silicon carbide VDMOS is prepared by using the preparation method of the silicon carbide VDMOS insulation high-UIS characteristic terminal described in the first aspect.

[0006] The advantages of the present invention are as follows: 1. In the present invention, an insulating dielectric region wrapped by a P-type region is arranged on the terminal structure beside the P+ well region of the device, truncating the edge region of the P+ well region to avoid the reduction of the breakdown voltage caused by the electric field concentration on the side of the P+ well region near the terminal; there is a P-type region connected to the lower part of the P+ well region near the terminal to buffer the electric field concentration below it, thereby reducing the electric field strength and improving the terminal breakdown voltage of the device. 2. In the present invention, the electric fields of the insulating dielectric region and the P-type region extend into the drift layer of the device, so that the terminal electric field distribution extends into the device body, avoiding the breakdown effect on the terminal structure of the device. 3. The P-type region and the P+ region outside the insulating dielectric region of the present invention can ensure that when the drain of the device bears voltage, the electric field is first distributed horizontally and then vertically, improving the breakdown voltage at the edge of the terminal. 4. The insulating dielectric structure of the present invention includes an insulating dielectric region and an insulating layer. Since the breakdown field strength of the insulating dielectric structure is greater, the breakdown voltage of the device terminal is stronger; the insulating dielectric structure and the horizontal and vertical combined breakdown voltage structure outside the terminal can improve the breakdown voltage of the device, thereby improving the UIS characteristic of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention will be further described below with reference to the accompanying drawings in conjunction with embodiments.

[0008] Figure 1 It is a schematic diagram of a silicon carbide VDMOS insulation high-UIS characteristic terminal of the present invention.

[0009] Figure 2 It is a process cross-section of a silicon carbide VDMOS insulation high-UIS characteristic terminal of the present invention Figure 1 。

[0010] Figure 3 It is a process cross-section of a silicon carbide VDMOS insulation high-UIS characteristic terminal of the present invention Figure 2 。

[0011] Figure 4 It is a process cross-section of a silicon carbide VDMOS insulation high-UIS characteristic terminal of the present invention Figure 3 。

[0012] Figure 5 It is a process cross-section of a silicon carbide VDMOS insulation high-UIS characteristic terminal of the present invention Figure 4 。

[0013] Figure 6 A cross-sectional view of the process of manufacturing a silicon carbide VDMOS insulated high UIS characteristic terminal according to the present invention Figure 5 .

[0014] Figure 7 A cross-sectional view of the process of manufacturing a silicon carbide VDMOS insulated high UIS characteristic terminal according to the present invention Figure 6 .

[0015] Figure 8 A cross-sectional view of the process of manufacturing a silicon carbide VDMOS insulated high UIS characteristic terminal according to the present invention Figure 7 .

[0016] Fig. 9 A cross-sectional view of the process of manufacturing a silicon carbide VDMOS insulated high UIS characteristic terminal according to the present invention Figure 8 . DETAILED DESCRIPTION

[0017] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0019] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0020] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0021] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0022] like Figures 1 to 9 As shown, the embodiment of the present application provides a method for preparing a silicon carbide VDMOS insulated high UIS characteristic terminal, comprising the following steps: Step 1: epitaxially growing on a silicon carbide substrate 1 to form a drift layer 2; Step 2, forming a barrier layer 6 on the drift layer 2, etching the barrier layer 6 to form a through hole, and implanting ions to form a P-type region 22; Step 3, removing the barrier layer 6, re-forming the barrier layer 6, etching the barrier layer 6 to form a through hole, and ion implantation to form a P+ well region 21; Step 4, removing the barrier layer 6, re-forming the barrier layer 6, etching the barrier layer 6 to form a through hole, and ion implantation to form a P+ region 24; Step 5, removing the barrier layer 6, re-forming the barrier layer 6, etching the barrier layer 6 to form a through hole, etching the P+ well region 21 and the P-type region 22 to form a groove 25, and depositing an insulating medium to form an insulating medium region 23; Step 6, removing the barrier layer 6, re-forming the barrier layer 6, etching the barrier layer 6 to form a through hole, and depositing to form an insulating layer 3; Step 7: remove the barrier layer 6, re-form the barrier layer 6, etch the barrier layer 6 to form a through hole, deposit metal to form a source metal layer 4, and remove the barrier layer 6.

[0023] In this embodiment, preferably, a thickness w1 of the P-type region 22 located on the left side of the insulating dielectric region 23 is smaller than a thickness w2 of the P-type region 22 located on the right side of the insulating dielectric region 23 .

[0024] In this embodiment, preferably, the doping concentration of the P-type region 22 is less than the doping concentration of the P+ well region 21 .

[0025] In this embodiment, preferably, the doping concentration of the P-type region 22 is less than the doping concentration of the P+ region 24 .

[0026] In this embodiment, preferably, a thickness w2 of the P-type region 22 located on the right side of the insulating dielectric region 23 is equal to a thickness w3 of the drift layer 2 located on the right side of the P-type region 22 .

[0027] like Figure 1 As shown, the high UIS characteristic terminal obtained by the above manufacturing method includes: Silicon carbide substrate 1; A drift layer 2, wherein the drift layer 2 is disposed on the upper side of the silicon carbide substrate 1, and a P+ well region 21, a P-type region 22, an insulating dielectric region 23 and a P+ region 24 are disposed on the drift layer 2; the lower portion of the insulating dielectric region 23 is disposed in the P-type region 22; the right side surface of the P+ well region 21 is connected to the left side surface of the insulating dielectric region 23, and the lower side surface of the P+ well region 21 is respectively connected to the drift layer 2 and the P-type region 22; the left side surface of the P+ region 24 is connected to the right side surface of the insulating dielectric region 23, and the lower side surface of the P+ region 24 is respectively connected to the drift layer 2 and the P-type region 22; An insulating layer 3, wherein the lower side of the insulating layer 3 is connected to the upper side of the insulating medium region 23 and the upper side of the P+ region 24; A source metal layer 4 connected to the upper side of the P+ well region 21 and the upper side of the insulating layer 3; The drain metal layer 5 is connected to the lower side of the silicon carbide substrate 1 .

[0028] In another embodiment of the present invention, the doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm -3 , the doping concentration of the N-type drift layer 2 is 5-9e16cm -3 , the doping concentration of the P-type region 22 is 0.8-5e17cm -3 , the doping concentration of the P+ well region 21 is 5-8e18cm -3 , the doping concentration of the P+ region 24 is 1-5e18cm -3The material of the insulating layer 3 may be silicon dioxide, the material of the insulating dielectric region 23 may be one of SiN and diamond, and the material of the source metal layer 4 may be one of Al, Cu, and Ni or an alloy of several metals; The doping concentrations of the N-type silicon carbide substrate 1, the N-type drift layer 2, and the P+ well region 21 are considered in the traditional design structure of the planar gate silicon carbide VDMOS device. The doping concentration of the P-type region 22 is to achieve the purpose of spreading the electric field distribution of the P+ well region 21 downward after the insulating dielectric region 23 laterally shares the main electric field, thereby reducing the electric field strength and improving the device reliability. The width d0 of the P+ well region 21 in the cell structure of the device is 3 μm, and the insulating dielectric region 23 in the terminal structure etches a portion of the P+ well region 21, and the width w0 of the portion is 500 nm; the width w1 of the P-type region 22 close to the P+ well region 21 is 500 nm, the width d1 of the insulating dielectric region 23 is 5 μm, the width w2 of the P-type region 22 close to the P+ region 24 is 1 μm, the width w2+w3 of the P+ region 24 is 2 μm, the width w3 of the N-type drift layer 2 on the right side of the P-type region 22 is 1 μm, and the thickness of the insulating dielectric region 23 is 5-10 μm. According to the design and adjustment of the device terminal withstand voltage capability, the thickness of the P-type region 22 located at the bottom of the insulating dielectric region 23 is 500 nm; In this embodiment, an insulating dielectric region 23 wrapped by a P-type region 22 is provided on the terminal structure next to the P+ well region 21 of the device, so as to cut off the edge area of ​​the P+ well region 21, thereby avoiding the electric field concentration on the side of the P+ well region 21 near the terminal, which leads to a decrease in the withstand voltage capability; a P-type region 22 is provided below the P+ well region 21 near the terminal, and the electric field below it is concentrated for buffering, thereby reducing the electric field strength and improving the withstand voltage capability of the device at the terminal; In this embodiment, the electric field of the insulating dielectric region 23 and the P-type region 22 is extended into the device drift layer 2, so that the terminal electric field distribution extends into the device body, thereby avoiding the breakdown effect on the terminal structure of the device; The P-type region 22 and the P+ region 24 outside the insulating dielectric region 23 of this embodiment can ensure that when the device drain is subjected to voltage, the electric field is first distributed horizontally and then vertically, thereby improving the voltage resistance at the edge of the terminal; The insulating dielectric structure of this embodiment includes an insulating dielectric region 23 and an insulating layer 3. Since the breakdown field strength of the insulating dielectric structure is greater, the voltage resistance of the device terminal is stronger; the insulating dielectric structure and the horizontal and vertical voltage-resistant structure combined with the terminal outer side can improve the voltage resistance of the device, thereby improving the UIS characteristics of the device.

[0029] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a silicon carbide VDMOS insulated high UIS characteristic terminal, characterized in that: The steps include: Step 1: epitaxially growing on a silicon carbide substrate to form a drift layer; Step 2, forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions to form a P-type region; Step 3, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implantation to form a P+ well region; Step 4, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and ion implantation to form a P+ region; Step 5, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the P+ well region and the P-type region to form a groove, and depositing an insulating medium to form an insulating medium region; Step 6, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and depositing to form an insulating layer; Step 7: remove the barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit metal to form a source metal layer, and remove the barrier layer.

2. The method for preparing a silicon carbide VDMOS insulated high UIS characteristic terminal according to claim 1, characterized in that: The thickness of the P-type region located on the left side of the insulating dielectric region is smaller than the thickness of the P-type region located on the right side of the insulating dielectric region.

3. The method for preparing a silicon carbide VDMOS insulated high UIS characteristic terminal according to claim 1, characterized in that: The doping concentration of the P-type region is less than the doping concentration of the P+ well region.

4. The method for preparing a silicon carbide VDMOS insulated high UIS characteristic terminal according to claim 1, characterized in that: The doping concentration of the P-type region is lower than the doping concentration of the P+ region.

5. The method for preparing a silicon carbide VDMOS insulated high UIS characteristic terminal according to claim 1, characterized in that: The thickness of the P-type region located on the right side of the insulating dielectric region is equal to the thickness of the drift layer located on the right side of the P-type region.

6. A silicon carbide VDMOS insulated high UIS characteristic terminal, characterized in that: The terminal is prepared by the preparation method described in any one of claims 1 to 5.

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