Silicon carbide VDMOS device shallow slot insulation terminal structure and preparation method thereof

Abstract

The invention provides a silicon carbide VDMOS device shallow slot insulation terminal structure and a preparation method, and the method comprises the steps: carrying out the epitaxial growth on a silicon carbide substrate, and forming a drift layer; a barrier layer is formed, etching and ion implantation are carried out, and a first left P + doped region and a second left P + doped region are formed; a barrier layer is formed again, etching and ion implantation are carried out, and a P + well region and a cut-off ring contact region are formed; a barrier layer is formed again, etching and deposition are carried out, and a second right P + doping region and a first right P + doping region are formed through thermal diffusion; forming a barrier layer again, etching and depositing to form a second insulating medium region and a first insulating medium region; forming a barrier layer again, etching and depositing metal, and forming a source metal layer and a cut-off ring metal layer; and the barrier layer is re-formed, the barrier layer is etched to form the through hole, the insulating layer is deposited and formed, and the barrier layer is removed, so that the terminal structure width is saved while the voltage endurance capability of the terminal is ensured.

Description

Technical Field

[0001] The invention relates to a shallow trench insulation terminal structure of a silicon carbide VDMOS device and a preparation method thereof. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices, and is widely used in electric vehicles, aerospace, power conversion and other fields. Based on the device structure design, the edge of the repeated cell has electric field concentration in the lateral direction due to the lateral distribution of the electric field, resulting in breakdown at the edge of the device. Traditional cells use the same doping concentration field limiting ring structure to suppress electric field concentration. Since the field limiting ring doping concentration and spacing distribution are equal, the electric field strength distribution gradually decreases, and there are still high and low differences in the electric field distribution. The risk of breakdown in the area close to the P+ well area is still high, and more field limiting rings are required to achieve the withstand voltage of the device terminal, which requires sacrificing area in exchange for withstand voltage. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a shallow trench insulation terminal structure and a preparation method for a silicon carbide VDMOS device. The shallow trench insulation terminal is adopted to avoid the problem of the difficulty of realizing the deep trench terminal process, and at the same time, the terminal withstand voltage within 1200V is achieved, and the withstand voltage capacity of the terminal per unit width is improved, that is, the terminal withstand voltage capacity is ensured while saving the terminal structure width.

[0004] In a first aspect, the present invention provides a method for preparing a shallow trench insulation terminal structure of a silicon carbide VDMOS device, comprising the following steps: Step 1: epitaxially growing on a silicon carbide substrate to form a drift layer; Step 2, forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions to form a first left P+ doping region; Step 3, removing the barrier layer, re-forming a barrier layer on the N-type drift layer, etching the barrier layer to form a through hole, and ion implantation to form a second left P+ doping region; Step 4, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and implanting ions to form a P+ well region and a cutoff ring contact region; Step 5, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing, and forming a second right P+ doping region by thermal diffusion, wherein the second P+ doping region includes a second left P+ doping region and a second right P+ doping region; Step 6, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing, and forming a first right P+ doping region by thermal diffusion, wherein the first P+ doping region includes a first left P+ doping region and a first right P+ doping region; Step 7, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the second P+ doped region to form a second trench, and depositing to form a second insulating dielectric region; Step 8, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the first P+ doped region to form a first trench, and depositing to form a first insulating dielectric region; Step 9, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, forming a source metal layer and a stop ring metal layer; Step 10: remove the barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit to form an insulating layer, and remove the barrier layer.

[0005] In a second aspect, the present invention provides a shallow trench insulation terminal structure of a silicon carbide VDMOS device, wherein the silicon carbide VDMOS is prepared by the method for preparing a shallow trench insulation terminal structure of a silicon carbide VDMOS device described in the first aspect.

[0006] The advantages of the present invention are: 1. The present invention provides a first insulating dielectric region wrapped by a first P+ doping region in a terminal structure next to a P+ well region of a device, thereby effectively cutting off the electric field at the edge of the P+ well region, thereby suppressing the electric field intensity in the terminal region; 2. The present invention provides a second insulating dielectric region wrapped by a second P+ doped region to achieve secondary cutoff and gradual suppression of strong electric fields. The double-layer structure can meet the device requirements within 1200V. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0008] Figure 1 The schematic diagram of the shallow trench insulation terminal structure of a silicon carbide VDMOS device of the present invention.

[0009] Figure 2 A cross-sectional view of the process of a shallow trench insulation terminal structure of a silicon carbide VDMOS device of the present invention Figure 1 .

[0010] Figure 3 A cross-sectional view of the process of a shallow trench insulation terminal structure of a silicon carbide VDMOS device of the present invention Figure 2 .

[0011] Figure 4 A cross-sectional view of the process of a shallow trench insulation terminal structure of a silicon carbide VDMOS device of the present invention Figure 3 .

[0012] Figure 5 A cross-sectional view of the process of a shallow trench insulation terminal structure of a silicon carbide VDMOS device of the present invention Figure 4 .

[0013] Figure 6 A cross-sectional view of the process of a shallow trench insulation terminal structure of a silicon carbide VDMOS device of the present invention Figure 5 .

[0014] Figure 7 A cross-sectional view of the process of a shallow trench insulation terminal structure of a silicon carbide VDMOS device of the present invention Figure 6 .

[0015] Figure 8 A cross-sectional view of the process of a shallow trench insulation terminal structure of a silicon carbide VDMOS device of the present invention Figure 7 .

[0016] Fig. 9 A cross-sectional view of the process of a shallow trench insulation terminal structure of a silicon carbide VDMOS device of the present invention Figure 8 .

[0017] Fig.10 A cross-sectional view of the process of a shallow trench insulation terminal structure of a silicon carbide VDMOS device of the present invention Figure 9 .

[0018] Fig.11 A cross-sectional view of the process of a shallow trench insulation terminal structure of a silicon carbide VDMOS device of the present invention Figure 10 .

[0019] Fig.12 A cross-sectional view of the process of a shallow trench insulation terminal structure of a silicon carbide VDMOS device of the present invention Figure 10 one.

[0020] Fig.13 A cross-sectional view of the process of a shallow trench insulation terminal structure of a silicon carbide VDMOS device of the present invention Figure 10 two. DETAILED DESCRIPTION

[0021] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0023] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0024] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0025] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0026] like Figures 1 to 13 As shown, the embodiment of the present application provides a method for preparing a shallow trench insulation terminal structure of a silicon carbide VDMOS device, comprising the following steps: Step 1: epitaxially growing on a silicon carbide substrate 1 to form a drift layer 2; Step 2, forming a barrier layer 7 on the drift layer 2, etching the barrier layer 7 to form a through hole, and implanting ions to form a first left P+ doping region 231; Step 3, removing the barrier layer 7, re-forming the barrier layer 7 on the N-type drift layer 2, etching the barrier layer 7 to form a through hole, and ion implantation to form a second left P+ doping region 2521; Step 4, removing the barrier layer 7, re-forming the barrier layer 7, etching the barrier layer 7 to form a through hole, and implanting ions to form a P+ well region 21 and a stop ring contact region 24; Step 5, removing the barrier layer 7, reforming the barrier layer 7, etching the barrier layer 7 to form a through hole, depositing a high P-type doped silicon carbide material, and forming a second right P+ doping region 2522 by thermal diffusion, wherein the second P+ doping region 252 includes a second left P+ doping region 2521 and a second right P+ doping region 2522; since thermal diffusion requires a concentration gradient, it will not affect the doping concentration of the second left P+ doping region 2521 formed in the previous process step; Step 6, removing the barrier layer 7, reforming the barrier layer 7, etching the barrier layer 7 to form a through hole, depositing a high P-type doped silicon carbide material, and forming a first right P+ doping region 232 by thermal diffusion, wherein the first P+ doping region 23 includes a first left P+ doping region 231 and a first right P+ doping region 232; Step 7, removing the barrier layer 7, re-forming the barrier layer 7, etching the barrier layer 7 to form a through hole, etching the second P+ doped region 252 to form a second trench 2523, and depositing to form a second insulating dielectric region 251; Step 8, removing the barrier layer 7, re-forming the barrier layer 7, etching the barrier layer 7 to form a through hole, etching the first P+ doped region 23 to form a first trench 233, and depositing to form a first insulating dielectric region 22; Step 9, removing the barrier layer 7, re-forming the barrier layer 7, etching the barrier layer 7 to form a through hole, depositing metal, forming a source metal layer 5 and a stop ring metal layer 4; Step 10: remove the barrier layer 7, re-form the barrier layer 7, etch the barrier layer 7 to form a through hole, deposit to form an insulating layer 3, and remove the barrier layer 7.

[0027] In this embodiment, preferably, at least one field limiting ring 25 is provided in the drift layer 2, each of the field limiting rings 25 includes a second insulating dielectric region 251 and a second P+ doping region 252, the second insulating dielectric region 251 is provided in the second P+ doping region 252, and the second P+ doping region 252 is located between the first P+ doping region 23 and the cut-off ring contact region 24; the lower side of the insulating layer 3 is connected to the upper side of the second insulating dielectric region 251 and the upper side of the second P+ doping region 252.

[0028] In this embodiment, preferably, the depth of the first insulating dielectric region 22 is less than the depth of the second insulating dielectric region 251 ; the depth of the first P+ doping region 23 is less than the depth of the second P+ doping region 252 .

[0029] In this embodiment, preferably, the width of the second P+ doping region 252 located on the left side of the second insulating dielectric region 251 is smaller than the width of the second P+ doping region 252 located on the right side of the second insulating dielectric region 251 .

[0030] In this embodiment, preferably, the width of the first P+ doping region 23 located on the left side of the first insulating dielectric region 22 is smaller than the width of the first P+ doping region 23 located on the right side of the first insulating dielectric region 22 .

[0031] like Figure 1 As shown, the terminal structure obtained by the above manufacturing method includes: Silicon carbide substrate 1, A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1; a P+ well region 21, a first insulating dielectric region 22, a first P+ doping region 23 and a cut-off ring contact region 24 are provided on the drift layer 2; one side of the P+ well region 21 is connected to one side of the first insulating dielectric region 22, the lower side of the P+ well region 21 is connected to the first P+ doping region 23, the first insulating dielectric region 22 is provided in the first P+ doping region 23, and the cut-off ring contact region 24 is located on one side of the first P+ doping region 23; An insulating layer 3, wherein the lower side of the insulating layer 3 is connected to the upper side of the first insulating medium region 22, the upper side of the first P+ doped region 23 and the upper side of the drift layer 2; A stop ring metal layer 4, wherein the lower side of the stop ring metal layer 4 is connected to the upper side of the stop ring contact area 24; A source metal layer 5, wherein the lower side of the source metal layer 5 is connected to the P+ well region 21; A drain metal layer 6 connected to the lower side of the silicon carbide substrate 1 .

[0032] In another embodiment of the present invention, the terminal structure is applied to the terminal of the planar gate silicon carbide VDMOS device. The terminal structure on one side of the device is used as an example for explanation. The terminal structure on the other side is a mirror image of the structure of the present embodiment. The doping concentration of the N-type silicon carbide substrate 1 is 2-8e18cm -3 , the doping concentration of the N-type drift layer 2 is 5-9e16cm -3 The doping concentrations of the first P+ doping region 23 and the second P+ doping region 252 are both 1-5e18cm -3 , the doping concentration of the P+ well region 21 is 5-8e18cm -3The doping concentration of the stop ring contact region 24 is 5-8e18cm -3 , the material of the insulating layer 3 may be silicon dioxide, and the material of the first insulating dielectric region 22 and the second insulating dielectric region 251 may be one of SiN and diamond; The doping concentrations of the N-type silicon carbide substrate 1, the N-type drift layer 2, and the P+ well region 21 are based on the traditional design structure of the planar gate silicon carbide VDMOS device. The doping concentrations of the first P+ doping region 23 and the second P+ doping region 252 are to achieve the purpose of spreading the electric field distribution of the P+ well region 21 downward after the first insulating dielectric region 22 and the second insulating dielectric region 251 share the main electric field laterally, thereby reducing the electric field strength and improving the device reliability. The width d1 of the first P+ doping region 23 located on the right side of the first insulating dielectric region 22 in the terminal structure is 1 μm, and the width w of the first insulating dielectric region 22 is 1 μm; the width w1 of the first P+ doping region 23 located on the left side of the first insulating dielectric region 22 is 300 nm, and the maximum depth of the first P+ doping region 23 is 1.3 μm; the width d2 of the second P+ doping region 252 located on the right side of the second insulating dielectric region 251 in the terminal structure is 1.5 μm, the width w of the second insulating dielectric region 251 is 1 μm, the width w2 of the second P+ doping region 252 located on the left side of the second insulating dielectric region 251 is 200 nm, the maximum depth of the second P+ doping region 252 is 1.7 μm, and the minimum spacing between the first insulating dielectric region 22 and the second insulating dielectric region 251 is 2 μm; the thickness of the insulating layer 3, the source metal layer 5, and the stop ring metal layer 4 are all 300 nm, and the thickness of the insulating layer 3 is to ensure that after the electric field is staged, the device is not affected by the top interconnection structure of the device when the device withstands voltage; By setting a first insulating dielectric region 22 wrapped by a first P+ doped region 23 in the terminal structure next to the device P+ well region 21, the electric field at the edge of the P+ well region 21 is effectively cut off; the electric field strength in the terminal region is suppressed; a second insulating dielectric region 251 wrapped by a second P+ doped region 252 is set to achieve secondary cutoff and gradual suppression of the strong electric field. The double-layer structure can meet the device requirements within 1200V.

[0033] The device terminal structure is scalable. When the device withstands higher voltage, more structures can be designed according to the electric field distribution, but the terminal structure parameters need to be optimized according to the electric field distribution.

[0034] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a shallow trench insulation terminal structure of a silicon carbide VDMOS device, characterized in that: The steps include: Step 1: epitaxially growing on a silicon carbide substrate to form a drift layer; Step 2, forming a barrier layer above the drift layer, etching the barrier layer to form a through hole, and implanting ions to form a first left P+ doping region; Step 3, removing the barrier layer, re-forming a barrier layer on the N-type drift layer, etching the barrier layer to form a through hole, and ion implantation to form a second left P+ doping region; Step 4, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and implanting ions to form a P+ well region and a cutoff ring contact region; Step 5, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing, and forming a second right P+ doping region by thermal diffusion, wherein the second P+ doping region includes a second left P+ doping region and a second right P+ doping region; Step 6, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing, and forming a first right P+ doping region by thermal diffusion, wherein the first P+ doping region includes a first left P+ doping region and a first right P+ doping region; Step 7, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the second P+ doped region to form a second trench, and depositing to form a second insulating dielectric region; Step 8, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the first P+ doped region to form a first trench, and depositing to form a first insulating dielectric region; Step 9, removing the barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, depositing metal, forming a source metal layer and a stop ring metal layer; Step 10: remove the barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, deposit to form an insulating layer, and remove the barrier layer.

2. The method for preparing a shallow trench insulation termination structure of a silicon carbide VDMOS device according to claim 1, characterized in that: The second insulating dielectric region is disposed in the second P+ doping region, and the second P+ doping region is located between the first P+ doping region and the cutoff ring contact region; the lower side of the insulating layer is connected to the upper side of the second insulating dielectric region and the upper side of the second P+ doping region.

3. The method for preparing a shallow trench insulation termination structure of a silicon carbide VDMOS device according to claim 1, characterized in that: The depth of the first insulating dielectric region is less than the depth of the second insulating dielectric region; the depth of the first P+ doping region is less than the depth of the second P+ doping region.

4. The method for preparing a shallow trench insulation termination structure of a silicon carbide VDMOS device according to claim 1, characterized in that: The width of the second P+ doping region located on the left side of the second insulating dielectric region is smaller than the width of the second P+ doping region located on the right side of the second insulating dielectric region.

5. The method for preparing a shallow trench insulation termination structure of a silicon carbide VDMOS device according to claim 1, characterized in that: The width of the first P+ doping region located on the left side of the first insulating dielectric region is smaller than the width of the first P+ doping region located on the right side of the first insulating dielectric region.

6. A shallow trench insulation termination structure for a silicon carbide VDMOS device, characterized in that: The terminal structure is prepared by the preparation method described in any one of claims 1 to 5.

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