Bidirectional silicon controlled rectifier chip with transverse structure and manufacturing method of bidirectional silicon controlled rectifier chip

Abstract

The invention discloses a bidirectional silicon controlled rectifier chip with a transverse structure and a manufacturing method of the bidirectional silicon controlled rectifier chip. The bidirectional silicon controlled rectifier chip comprises an N-type silicon substrate, a P-type short base region group is arranged at the upper end of the N-type silicon substrate, a P-type field ring group is arranged on the outer side of the P-type short base region group, and an N + type emitter region group is arranged on the inner side of the P-type short base region group; the bidirectional silicon controlled rectifier of a transverse structure is adopted, a punch-through ring structure is not needed, the production efficiency can be greatly improved, the blocking voltage of 1000 V can be achieved by only needing the depth of the first P-type field ring and the depth of the second P-type field ring to be 35-40 microns, electric leakage is lower, the first N + type emitter region, the second N + type emitter region and the third N + type emitter region enable current density distribution to be more uniform, and the reliability of the device is improved. Compared with the prior art, higher di / dt can be borne, temperature rise is lower, the distance between the first P-type short base region and the second P-type short base region is far, the distance between the first P-type short base region and the second P-type short base region is larger than 250 micrometers, parasitic capacitance is small, and dv / dt is high.

Description

Technical Field

[0001] The invention relates to the field of electronic technology, in particular to a bidirectional thyristor chip with a lateral structure and a manufacturing method thereof. Background Art

[0002] Planar bidirectional thyristors are all vertical structures. The bidirectional thyristors are injected with N+ type emitter regions on the back and gate areas, which can be equivalent to a combination of two anti-parallel connected unidirectional thyristors, dividing the thyristor into two areas, each occupying half the area, to achieve bidirectional conduction.

[0003] Deficiencies of existing technology: At present, the formation of the p+ type through-ring structure requires a long time of diffusion and has low efficiency. In addition, the planar thyristor does not have a passivation groove structure. In order to achieve an 800V blocking voltage, it is necessary to add a field ring structure on both sides of the front p-type short base region to reduce the electric field strength at the edge of the curved junction. The depth of the field ring is generally 60~80um, which also requires a long time of diffusion. Summary of the invention

[0004] The object of the present invention is to provide a bidirectional thyristor chip with a lateral structure and a manufacturing method thereof, so as to solve the problems raised in the above background technology.

[0005] To achieve the above-mentioned purpose, the present invention provides the following technical solution: a bidirectional thyristor chip with a lateral structure, comprising an N-type silicon substrate, a P-type short base region group is arranged on the upper end of the N-type silicon substrate, a P-type field ring group is arranged on the outer side of the P-type short base region group, and an N+ type emitter region group is arranged on the inner side of the P-type short base region group.

[0006] Preferably, the P-type short base region group includes a first P-type short base region and a second P-type short base region, and the first P-type short base region and the second P-type short base region are respectively arranged on both sides of the upper end of the N-type silicon substrate.

[0007] Preferably, the P-type field ring group includes a first P-type field ring and a second P-type field ring, the first P-type field ring is arranged outside the first P-type short base region, and the second P-type field ring is arranged outside the second P-type short base region.

[0008] Preferably, the N+ type emitter region group includes a first N+ type emitter region, a second N+ type emitter region and a third N+ type emitter region, the first N+ type emitter region is arranged on the inner side of the upper end of the first P type short base region, the second N+ type emitter region is arranged on the upper end of the second P type short base region and close to the side of the first P type short base region, and the third N+ type emitter region is arranged on the upper end of the second P type short base region and away from the side of the first P type short base region.

[0009] Preferably, a T1 electrode is disposed on the upper end surface of the first N+ type emitter region, a T2 electrode is disposed on the second N+ type emitter region, and a gate electrode is disposed on the upper end surface of the third N+ type emitter region.

[0010] Preferably, an N+ type cutoff ring is arranged on the upper end surface of the N-type silicon substrate around the outside of the first P-type short base region and the second P-type short base region; and the N-type silicon substrate is provided with a surface passivation layer.

[0011] The present invention also provides a method for manufacturing a bidirectional thyristor chip with a lateral structure, and the manufacturing method specifically comprises the following steps: S1, prepare resistivity of 80~100Ω·cm, thickness of 275~285μm, <111> The N-type silicon substrate of the crystal orientation; S2, growing an oxide film, the thickness of which is greater than 1.2 μm; S3, diffusion-pushing the first P-type field ring and the second P-type field ring; S4, diffusion-pushing the first P-type short base region and the second P-type short base region; S5, diffusion and push junction of the first N+ type emitter region, the second N+ type emitter region, the third N+ type emitter region and the N+ type cutoff ring; S6, using BOE buffered etching solution to completely remove the oxide layers on the front and back sides of the N-type silicon substrate; S7, depositing a SIPOS film and a silicon nitride film on the front of the N-type silicon substrate respectively by an LPCVD device, and depositing a TEOS film by a PECVD device, wherein the thicknesses of the SIPOS film, the silicon nitride film and the TEOS film are 0.6 μm, 0.1 μm and 1 μm respectively; and uniformly coating the photoresist on the front of the N-type silicon substrate by a coating machine, opening a lead window after pre-baking, exposure, post-baking, development and hardening processes, etching the TEOS film in the window by a BOE buffered etching solution, etching the silicon nitride film and the SIPOS film in the window by a dry etching device, and removing the glue, cleaning and drying; S8. A layer of metal aluminum film is evaporated on the front side of the N-type silicon substrate by high vacuum electron beam evaporation equipment, and the thickness of the metal aluminum film is 3~5μm; photoresist is evenly coated on the front side of the metal aluminum film by a coating machine, and a reverse etching window is opened after pre-baking, exposure, post-baking, development and hardening processes, and the metal aluminum film in the window is removed by metal etching liquid. The metals left after degumming, cleaning and drying are respectively the gate electrode, the T1 electrode and the T2 electrode.

[0012] Preferably, the step S3 specifically includes the following steps: a1. Evenly coating the photoresist on the front side of the N-type silicon substrate by a coating machine, opening the first P-type field ring and the second P-type field ring windows after pre-baking, exposure, post-baking, development and hardening processes, etching away the silicon dioxide film in the first P-type field ring and the second P-type field ring windows by BOE buffer etching solution, and performing coating removal, cleaning and drying; a2. Inject boron ions into the surface layer of the N-type silicon substrate in the first P-type field ring and the second P-type field ring window by an ion implanter, with an implantation energy of 30-50 keV and an implantation dose of 1.5E14-2E14 / cm 2 , the injection angle is 7°; a3. Place the N-type silicon substrate in a diffusion furnace, introduce protective gas, and diffuse and push the junction at high temperature.

[0013] Preferably, the step S4 specifically includes the following steps: b1. Evenly coating the photoresist on the front side of the N-type silicon substrate by a coating machine, opening the first P-type short base region and the second P-type short base region windows after pre-baking, exposure, post-baking, development and hardening processes, etching away the silicon dioxide film in the first P-type short base region and the second P-type short base region windows by a BOE buffered etching solution, and performing coating removal, cleaning and spin drying; b2. Inject boron ions into the surface layer of the N-type silicon substrate in the first P-type short base region and the second P-type short base region window by an ion implanter, with an implantation energy of 50-80 keV and an implantation dose of 2.5E14-3.5E14 / cm 2 , the injection angle is 7°; b3. Place the N-type silicon substrate in a diffusion furnace, introduce protective gas, and diffuse the junction at high temperature. The final junction depth of the first P-type short base region and the second P-type short base region is 15-20 μm, and the final junction depth of the field ring is 35-40 μm.

[0014] Preferably, the step S5 specifically includes the following steps: c1. Evenly coating the photoresist on the front of the N-type silicon substrate by a coating machine, opening the first N+ type emitter region, the second N+ type emitter region, the third N+ type emitter region and the N+ type cutoff ring window after pre-baking, exposure, post-baking, development and hardening processes, etching the silicon dioxide film in the window by BOE buffered etching solution, and performing debonding, cleaning and drying; c2. Phosphorus ions are implanted into the first N+ type emitter region, the second N+ type emitter region, the third N+ type emitter region and the surface layer of the N- type silicon substrate in the N+ type cutoff ring window by an ion implanter, with an implantation energy of 50-80 keV and an implantation dose of 1.5E15-3E15 / cm 2, the injection angle is 7°; c3. Place the N-type silicon substrate in a diffusion furnace, introduce protective gas, diffuse and push the junction at high temperature, and finally achieve a junction depth of 5-10 μm.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The present invention discloses a bidirectional thyristor chip with a lateral structure and a manufacturing method thereof. The bidirectional thyristor with a lateral structure is adopted, and a through-ring structure is not required, so that production efficiency can be greatly improved. The depth of the first P-type field ring and the second P-type field ring only needs to be 35-40 μm to achieve a blocking voltage of 1000 V, and the leakage current is lower. The first N+ type emitter region, the second N+ type emitter region and the third N+ type emitter region make the current density distribution more uniform, and can withstand a higher di / dt, with a lower temperature rise. The first P-type short base region and the second P-type short base region are far apart, the distance between the first P-type short base region and the second P-type short base region is greater than 250 μm, the parasitic capacitance is small, and the dv / dt is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a specific schematic diagram of the overall structure of the present invention; Figure 2 It is a cross-sectional schematic diagram of the present invention; Figure 3 It is a schematic diagram of the forward and reverse blocking voltages of the present invention; Figure 4 It is a schematic diagram of the conduction of three quadrants of the present invention; In the figure: 110, N-type silicon substrate; 121, first P-type short base region; 122, second P-type short base region; 131, first P-type field ring; 132, second P-type field ring; 141, first N+ type emitter region; 142, second N+ type emitter region; 143, third N+ type emitter region; 151, T1 electrode; 152, T2 electrode; 153, gate electrode; 160, N+ type cutoff ring; 170, surface passivation layer. DETAILED DESCRIPTION

[0017] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0018] In the description of the present invention, it is necessary to understand that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicating orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0019] In the description of this patent, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "setting" should be understood in a broad sense, for example, it can be fixed connection, setting, or detachable connection, setting, or integrated connection, setting. For ordinary technicians in this field, the specific meanings of the above terms in this patent can be understood according to specific circumstances.

[0020] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "several" is two or more, unless otherwise clearly and specifically defined.

[0021] Example See also Figure 1-4As shown, the present invention provides a technical solution of a bidirectional thyristor chip with a lateral structure: comprising an N-type silicon substrate 110, a P-type short base region group is arranged at the upper end of the N-type silicon substrate 110, a P-type field ring group is arranged outside the P-type short base region group, an N+ type emitter region group is arranged inside the P-type short base region group, the P-type short base region group comprises a first P-type short base region 121 and a second P-type short base region 122, the first P-type short base region 121 and the second P-type short base region 122 are respectively arranged on both sides of the upper end of the N-type silicon substrate 110, the P-type field ring group comprises a first P-type field ring 131 and a second P-type field ring 132. The first P-type field ring 131 is arranged outside the first P-type short base region 121, the second P-type field ring 132 is arranged outside the second P-type short base region 122, the N+ type emitter region group includes a first N+ type emitter region 141, a second N+ type emitter region 142 and a third N+ type emitter region 143, the first N+ type emitter region 141 is arranged inside the upper end of the first P-type short base region 121, the second N+ type emitter region 142 is arranged at the upper end of the second P-type short base region 122 and close to the side of the first P-type short base region 121, and the third N+ type emitter region 143 is arranged inside the second P-type short base region 121. A T1 electrode 151 is arranged on the upper end of the first N+ type emitter region 141 and away from the side of the first P type short base region 122, a T2 electrode 152 is arranged on the second N+ type emitter region 142, a gate electrode 153 is arranged on the upper end of the third N+ type emitter region 143, an N+ type cut-off ring 160 is arranged on the upper end of the N- type silicon substrate 110 around the outside of the first P type short base region 121 and the second P type short base region 122, and a surface passivation layer 170 is arranged on the N- type silicon substrate 110; the overall structure does not need a through-ring structure, which can greatly improve production efficiency , and the depth of the first P-type field ring 131 and the second P-type field ring 132 only needs to be 35~40μm to achieve a blocking voltage of 1000V, and the leakage is lower. The first N+ type emitter region 141, the second N+ type emitter region 142 and the third N+ type emitter region 143 make the current density distribution more uniform, can withstand higher di / dt, and have lower temperature rise. The first P-type short base region 121 and the second P-type short base region 122 are far apart, and the distance between the first P-type short base region 121 and the second P-type short base region 122 is greater than 250μm, the parasitic capacitance is small, and the dv / dt is high.

[0022] Furthermore, the bidirectional conduction is divided into three cases. Case 1: T1 electrode 151 is connected to the positive, T2 electrode 152 is connected to the negative, the main current flows from T1 electrode 151 to T2 electrode 152, the gate electrode 153 is connected to the positive, T2 electrode 152 is connected to the negative, and the trigger current flows from gate electrode 153 to T2 electrode 152. At this time, the first quadrant is turned on; Case 2: T1 electrode 151 is connected to the positive, T2 electrode 152 is connected to the negative, and the main current flows from T1 electrode 151 to T2 electrode Case three: T1 electrode 151 is connected to negative, T2 electrode 152 is connected to positive, the main current flows from T2 electrode 152 to T1 electrode 151, the gate electrode 153 is connected to negative, T2 electrode 152 is connected to positive, the trigger current flows from T2 electrode 152 to gate electrode 153, and the third quadrant is turned on.

[0023] The present invention provides a method for manufacturing a bidirectional thyristor chip with a lateral structure, and the manufacturing method specifically comprises the following steps: S1, prepare resistivity of 80~100Ω·cm, thickness of 275~285μm, <111> The N-type silicon substrate 110 of crystal orientation; S2, growing an oxide film, the thickness of which is greater than 1.2 μm; S3, diffusion and push junction of the first P-type field ring 131 and the second P-type field ring 132; a1. Use a coating machine to evenly coat the photoresist on the front side of the N-type silicon substrate 110, and after pre-baking, exposure, post-baking, development and hardening processes, open the first P-type field ring 131 and the second P-type field ring 132 windows, use BOE buffered etching solution to etch away the silicon dioxide film in the first P-type field ring 131 and the second P-type field ring 132 windows, and then perform debonding, cleaning and spin drying; a2. Boron ions are implanted into the surface of the N-type silicon substrate 110 in the windows of the first P-type field ring 131 and the second P-type field ring 132 by an ion implanter, with an implantation energy of 30-50 keV and an implantation dose of 1.5E14-2E14 / cm 2 , the injection angle is 7°; a3. Place the N-type silicon substrate 110 in a diffusion furnace, introduce protective gas, and diffuse and push the junction at high temperature; S4, diffusion and push junction between the first P-type short base region 121 and the second P-type short base region 122; b1. Use a coating machine to evenly coat the photoresist on the front of the N-type silicon substrate 110, and after pre-baking, exposure, post-baking, development and hardening processes, open the first P-type short base region 121 and the second P-type short base region 122 windows, and use BOE buffered etching solution to etch away the silicon dioxide film in the first P-type short base region 121 and the second P-type short base region 122 windows, and then perform debonding, cleaning and spin drying; b2. Boron ions are implanted into the surface of the N-type silicon substrate 110 in the windows of the first P-type short base region 121 and the second P-type short base region 122 by an ion implanter, with an implantation energy of 50-80 keV and an implantation dose of 2.5E14-3.5E14 / cm 2 , the injection angle is 7°; b3. Place the N-type silicon substrate 110 in a diffusion furnace, introduce protective gas, and diffuse the junction at high temperature. The final junction depth of the first P-type short base region 121 and the second P-type short base region 122 is 15-20 μm, and the final junction depth of the first P-type field ring 131 and the second P-type field ring 132 is 35-40 μm. S5, diffusion and push junction of the first N+ type emitter region 141, the second N+ type emitter region 142, the third N+ type emitter region 143 and the N+ type cutoff ring 160; c1. Use a coating machine to evenly coat the photoresist on the front of the N-type silicon substrate 110, and after pre-baking, exposure, post-baking, development and hardening processes, open the first N+ type emitter region 141, the second N+ type emitter region 142, the third N+ type emitter region 143 and the N+ type cutoff ring 160 window, use BOE buffered etching solution to etch away the silicon dioxide film in the window, and then perform debonding, cleaning and drying; c2. Phosphorus ions are implanted into the surface of the N-type silicon substrate 110 in the first N+ type emitter region 141, the second N+ type emitter region 142, the third N+ type emitter region 143 and the N+ type cutoff ring 160 window by an ion implanter, with an implantation energy of 50-80 keV and an implantation dose of 1.5E15-3E15 / cm 2 , the injection angle is 7°; c3. Place the N-type silicon substrate 110 in a diffusion furnace, introduce protective gas, and diffuse and push the junction at high temperature, with a final junction depth of 5-10 μm; S6, using BOE buffered etching solution to completely remove the oxide layers on the front and back sides of the N-type silicon substrate 110; S7, depositing a SIPOS film and a silicon nitride film on the front of the N-type silicon substrate 110 by an LPCVD device, and depositing a TEOS film by a PECVD device, wherein the thicknesses of the SIPOS film, the silicon nitride film and the TEOS film are 0.6 μm, 0.1 μm and 1 μm respectively; and uniformly coating the photoresist on the front of the N-type silicon substrate 110 by a coating machine, opening a lead window after pre-baking, exposure, post-baking, development and hardening processes, etching the TEOS film in the window by a BOE buffered etching solution, etching the silicon nitride film and the SIPOS film in the window by a dry etching device, and removing the glue, cleaning and drying; S8. A layer of metal aluminum film is deposited on the front side of the N-type silicon substrate 110 by high vacuum electron beam evaporation equipment, and the thickness of the metal aluminum film is 3~5μm; photoresist is evenly coated on the front side of the metal aluminum film by a coating machine, and a reverse etching window is opened after pre-baking, exposure, post-baking, development and hardening processes, and the metal aluminum film in the window is removed by metal etching liquid. After degumming, cleaning and drying, the metals left are respectively the gate electrode 153, T1 electrode 151 and T2 electrode 152.

[0024] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments. The above embodiments and descriptions are only preferred examples of the present invention and are not intended to limit the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A lateral bidirectional thyristor chip, comprising an N-type silicon substrate (110), characterized in that: A P-type short base region group is arranged at the upper end of the N-type silicon substrate (110), a P-type field ring group is arranged outside the P-type short base region group, and an N+ type emitter region group is arranged inside the P-type short base region group.

2. A bidirectional thyristor chip with a lateral structure according to claim 1, characterized in that: The P-type short base region group comprises a first P-type short base region (121) and a second P-type short base region (122), wherein the first P-type short base region (121) and the second P-type short base region (122) are respectively arranged on both sides of the upper end of the N-type silicon substrate (110).

3. The bidirectional thyristor chip with a lateral structure according to claim 2, characterized in that: The P-type field ring group comprises a first P-type field ring (131) and a second P-type field ring (132); the first P-type field ring (131) is arranged outside the first P-type short base region (121); and the second P-type field ring (132) is arranged outside the second P-type short base region (122).

4. The bidirectional thyristor chip with a lateral structure according to claim 2, characterized in that: The N+ type emitter region group comprises a first N+ type emitter region (141), a second N+ type emitter region (142) and a third N+ type emitter region (143); the first N+ type emitter region (141) is arranged on the inner side of the upper end of the first P type short base region (121); the second N+ type emitter region (142) is arranged on the upper end of the second P type short base region (122) and close to a side of the first P type short base region (121); and the third N+ type emitter region (143) is arranged on the upper end of the second P type short base region (122) and away from a side of the first P type short base region (121).

5. The bidirectional thyristor chip with a lateral structure according to claim 4, characterized in that: A T1 electrode (151) is arranged on the upper end surface of the first N+ type emitter region (141), a T2 electrode (152) is arranged on the second N+ type emitter region (142), and a gate electrode (153) is arranged on the upper end surface of the third N+ type emitter region (143).

6. The bidirectional thyristor chip with a lateral structure according to claim 2, characterized in that: An N+ type cut-off ring (160) is arranged on the upper end surface of the N-type silicon substrate (110) around the first P-type short base region (121) and the second P-type short base region (122); and the N-type silicon substrate (110) is provided with a surface passivation layer (170).

7. The method for manufacturing a bidirectional thyristor chip with a lateral structure according to any one of claims 1 to 6, characterized in that: The manufacturing method specifically comprises the following steps: S1, prepare resistivity of 80~100Ω·cm, thickness of 275~285μm, <111> The N-type silicon substrate (110) of the crystal orientation; S2, growing an oxide film, the thickness of which is greater than 1.2 μm; S3, diffusion-pushing the first P-type field ring (131) and the second P-type field ring (132); S4, diffusion-pushing the first P-type short base region (121) and the second P-type short base region (122); S5, diffusion-pushing the first N+ type emitter region (141), the second N+ type emitter region (142), the third N+ type emitter region (143) and the N+ type cutoff ring (160); S6, using a BOE buffered etching solution to completely remove the oxide layers on the front and back sides of the N-type silicon substrate (110); S7, depositing a SIPOS film and a silicon nitride film on the front surface of the N-type silicon substrate (110) by LPCVD equipment, and depositing a TEOS film by PECVD equipment, wherein the thicknesses of the SIPOS film, the silicon nitride film, and the TEOS film are 0.6 μm, 0.1 μm, and 1 μm, respectively; and uniformly coating the photoresist on the front surface of the N-type silicon substrate (110) by a coating machine, opening a lead window after pre-baking, exposure, post-baking, development, and hardening processes, etching away the TEOS film in the window by BOE buffered etching solution, and etching away the silicon nitride film and SIPOS film in the window by dry etching equipment, and then removing the photoresist, washing, and drying; S8. A layer of metal aluminum film is deposited on the front side of the N-type silicon substrate (110) by high vacuum electron beam evaporation equipment, and the thickness of the metal aluminum film is 3-5 μm; a photoresist is evenly coated on the front side of the metal aluminum film by a coating machine, and a reverse etching window is opened after pre-baking, exposure, post-baking, development and hardening processes, and the metal aluminum film in the window is removed by metal etching liquid. After debonding, cleaning and drying, the metals left are the gate electrode (153), the T1 electrode (151) and the T2 electrode (152).

8. The method for manufacturing a bidirectional thyristor chip with a lateral structure according to claim 7, characterized in that: The step S3 specifically comprises the following steps: a1. Using a coating machine to evenly coat photoresist on the front surface of the N-type silicon substrate (110), opening the first P-type field ring (131) and the second P-type field ring (132) windows after pre-baking, exposure, post-baking, development and hardening processes, etching away the silicon dioxide film in the first P-type field ring (131) and the second P-type field ring (132) windows using a BOE buffered etching solution, and performing debonding, cleaning and spin drying; a2. Boron ions are implanted into the surface layer of the N-type silicon substrate (110) in the windows of the first P-type field ring (131) and the second P-type field ring (132) by an ion implanter, with an implantation energy of 30-50 keV and an implantation dose of 1.5E14-2E14 / cm 2 , the injection angle is 7°; a3. Placing the N-type silicon substrate (110) in a diffusion furnace, introducing protective gas, and performing diffusion and bonding at high temperature.

9. The method for manufacturing a bidirectional thyristor chip with a lateral structure according to claim 7, characterized in that: The step S4 specifically comprises the following steps: b1. uniformly coating the photoresist on the front side of the N-type silicon substrate (110) by means of a coating machine, opening the first P-type short base region (121) and the second P-type short base region (122) windows after pre-baking, exposure, post-baking, development and hardening processes, etching away the silicon dioxide film in the first P-type short base region (121) and the second P-type short base region (122) windows by means of a BOE buffered etching solution, and performing coating removal, cleaning and spin drying; b2. Injecting boron ions into the surface layer of the N-type silicon substrate (110) in the windows of the first P-type short base region (121) and the second P-type short base region (122) by an ion implanter, with an implantation energy of 50-80 keV and an implantation dose of 2.5E14-3.5E14 / cm 2 , the injection angle is 7°; b3. Placing the N-type silicon substrate (110) in a diffusion furnace, introducing a protective gas, and diffusing and pushing the junction at a high temperature, wherein the final junction depth of the first P-type short base region (121) and the second P-type short base region (122) is 15-20 μm, and the final junction depth of the field ring is 35-40 μm.

10. The method for manufacturing a bidirectional thyristor chip with a lateral structure according to claim 7, characterized in that: The step S5 specifically comprises the following steps: c1. Using a coating machine to evenly coat photoresist on the front side of the N-type silicon substrate (110), and after pre-baking, exposure, post-baking, development and hardening processes, the first N+ type emitter region (141), the second N+ type emitter region (142), the third N+ type emitter region (143) and the N+ type cutoff ring (160) window are opened, and the silicon dioxide film in the window is etched away using a BOE buffered etching solution, and then the coating is removed, cleaned and dried; c2. Phosphorus ions are implanted into the first N+ type emitter region (141), the second N+ type emitter region (142), the third N+ type emitter region (143) and the surface layer of the N-type silicon substrate (110) in the window of the N+ type cutoff ring (160) by an ion implanter, with an implantation energy of 50-80 keV and an implantation dose of 1.5E15-3E15 / cm 2 , the injection angle is 7°; c3. Placing the N-type silicon substrate (110) in a diffusion furnace, introducing protective gas, and diffusing and pushing the junction at high temperature, with a final junction depth of 5-10 μm.

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