Thin film transistor, method of manufacturing same, and display device including same

Abstract

Disclosed are a thin film transistor, a method of manufacturing the same, and a display device including the same. The thin film transistor includes: a base substrate; the buffer layer is arranged on the base substrate, and the upper surface of the buffer layer is provided with grooves; an active layer on the buffer layer; a gate spaced apart from the active layer and at least partially overlapping the active layer in a plan view, the active layer including a channel region overlapping the gate in the plan view, a source region connected to one side of the channel region, and a drain region connected to the other side of the channel region, the trenches including a first trench having the source region therein and a second trench having the drain region therein, the channel region includes: a first channel region; a second channel region on one side of the first channel region, in contact with the source region and in the first trench; and a third channel region on the other side of the first channel region, in contact with the drain region and in the second trench, a shortest distance between an upper surface of the base substrate and the second and third channel regions being shorter than a shortest distance between the upper surface of the base substrate and the first channel region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to Korean Patent Application No. 10-2023-0162292, filed on November 21, 2023, which is hereby incorporated by reference into this application as if fully set forth herein. Technical Field

[0003] The present invention relates to a thin film transistor and a method for manufacturing the same, and a display device including the thin film transistor. Background Art

[0004] Transistors are widely used as switching devices or driving devices in the field of electronic devices. In particular, thin film transistors are widely used as switching devices of display devices such as liquid crystal display devices or organic light emitting devices because they can be manufactured on glass substrates or plastic substrates.

[0005] Based on the material constituting the active layer, thin film transistors can be divided into amorphous silicon thin film transistors using amorphous silicon as an active layer, polycrystalline silicon thin film transistors using polycrystalline silicon as an active layer, and oxide semiconductor thin film transistors using oxide semiconductors as an active layer.

[0006] Since amorphous silicon can be deposited in a shorter time to form an active layer, amorphous silicon thin film transistors (a-SiTFTs) have the advantages of short manufacturing process time and low production cost, but have the disadvantage of being limited when used in active matrix organic light-emitting devices (AMOLEDs) due to lower mobility, poor current driving capability, and varying threshold voltage.

[0007] After depositing amorphous silicon, a polycrystalline silicon thin film transistor (poly-Si TFT) is manufactured by crystallizing the amorphous silicon. Since a process of crystallizing amorphous silicon is required in the process of manufacturing a polycrystalline silicon thin film transistor, the manufacturing cost increases with the increase in the number of processes, and since the crystallization process is performed at a high process temperature, it is difficult to apply the polycrystalline silicon thin film transistor to a large area device. In addition, due to its polycrystalline characteristics, it is difficult to ensure the consistency of the polycrystalline silicon thin film transistor.

[0008] In an oxide semiconductor thin film transistor (TFT), since the oxide constituting the active layer can be formed at a relatively low temperature, has a high mobility, and has a large resistance change according to the oxygen content, it is easy to obtain the desired physical properties. In addition, due to the properties of the oxide, since the oxide semiconductor is transparent, it is also conducive to realizing a transparent display.

[0009] In an oxide semiconductor, when doping for conductivity occurs, a conductive region is unnecessarily formed by doping. Therefore, it may be difficult to optimize the threshold voltage (Vth) of a thin film transistor within the same process.

[0010] Therefore, research on technology for controlling the depth of conductive penetration is continuing. Summary of the invention

[0011] An embodiment of the present invention is to provide a thin film transistor including a trench in order to maintain an effective channel length and control or prevent conductive diffusion.

[0012] An embodiment of the present invention is to provide a thin film transistor including a trench so as to prevent or suppress a threshold voltage Vth from shifting in a negative (-) direction even when a channel region has a short channel.

[0013] Another embodiment of the present invention is to provide a display device including such a thin film transistor.

[0014] Another embodiment of the present invention is to provide a method for manufacturing such a thin film transistor.

[0015] In addition to the above-mentioned objects of the present invention, additional objects and features of the present invention will be clearly understood by those skilled in the art from the following description of the present invention.

[0016] According to one aspect of the present invention, the above and other objects can be achieved by providing a thin film transistor, the thin film transistor comprising: a base substrate; a buffer layer, the buffer layer is arranged on the base substrate, the upper surface of the buffer layer has a groove; an active layer on the buffer layer; and a gate, the gate is separated from the active layer and at least partially overlaps with the active layer in a plan view, wherein the active layer comprises: a channel region overlapping with the gate in a plan view; a source region connected to one side of the channel region in a plan view; and a drain region connected to the other side of the channel region in a plan view, wherein the groove comprises a first groove having the source region therein and a second groove having a drain region therein. a second trench in the drain region, wherein the channel region comprises: a first channel region; a second channel region, the second channel region is on one side of the first channel region, in contact with the source region and in the first trench; and a third channel region, the third channel region is on the other side of the first channel region, in contact with the drain region and in the second trench, wherein the shortest distance between the upper surface of the base substrate and the second channel region is shorter than the shortest distance between the upper surface of the base substrate and the first channel region, wherein the shortest distance between the upper surface of the base substrate and the third channel region is shorter than the shortest distance between the upper surface of the base substrate and the first channel region.

[0017] The first trench and the second trench may be spaced apart from each other.

[0018] The channel region, the source region, and the drain region may be integrally formed, and the active layer may have a constant thickness.

[0019] Each of the first groove and the second groove may include: a first surface, the first surface is parallel to the upper surface of the base substrate; a second surface, the second surface is connected to one side of the first surface and is inclined at a predetermined angle relative to the first surface; and a third surface, the third surface is connected to the other side of the first surface and is inclined at a predetermined angle relative to the first surface, the active layer may be arranged on the second surface and the third surface, and at least a portion of the second surface may overlap with the gate.

[0020] The entire second surface may overlap the gate in a region overlapping the active layer.

[0021] A gate insulating layer may be provided between the active layer and the gate. The gate insulating layer may include a first gate insulating layer on the active layer and a second gate insulating layer on the first gate insulating layer. The first gate insulating layer may be provided on the channel region of the active layer and the groove.

[0022] The thickness of the first gate insulating layer may be greater than the thickness of the second gate insulating layer.

[0023] The source region may include: a first source region, the first source region overlaps with the first gate insulation layer and the second gate insulation layer; and a second source region, the second source region overlaps with the second gate insulation layer and does not overlap with the first gate insulation layer, and the drain region may include: a first drain region, the first drain region overlaps with the first gate insulation layer and the second gate insulation layer; and a second drain region, the second drain region overlaps with the second gate insulation layer and does not overlap with the first gate insulation layer.

[0024] The first source region and the first drain region may contact the first gate insulating layer, and the second source region and the second drain region may contact the second gate insulating layer.

[0025] A gate insulating layer disposed between the active layer and the gate may be further included, and the gate insulating layer may cover the channel region and expose the source region and the drain region.

[0026] The second source region may have a higher dopant concentration than the first source region, and the second drain region may have a higher dopant concentration than the first drain region.

[0027] In a plan view, the first source region and the first drain region may have a length of 0.7 μm to 1.0 μm in a length direction of the channel region.

[0028] The groove has a height ratio of 0.15 to 0.65, wherein the height ratio refers to a value obtained by dividing the height of the groove by the width of the groove, the width may be the longest length in the length direction of the channel region in a plan view, and the height may be the difference between the maximum distance and the minimum distance between the upper surface of the buffer layer and the upper surface of the base substrate in a direction perpendicular to the length direction of the channel region.

[0029] Each of the second surface and the third surface may have a taper angle of 30 to 45 degrees with respect to the first surface.

[0030] Another configuration of the present invention provides a display device including the thin film transistor.

[0031] Another embodiment of the present invention provides a method for manufacturing a thin film transistor, comprising: forming a first insulating material on a base substrate, and patterning the first insulating material to form a buffer layer including a groove; forming an active layer on the buffer layer; forming a second insulating material on the active layer and forming a first gate insulating layer by patterning the second insulating material; forming a second gate insulating layer on the first gate insulating layer; and forming a gate on the second gate insulating layer, wherein at least a portion of the groove overlaps with the gate in a plan view.

[0032] After the step of forming the gate, the step of doping the active layer with a dopant may be further included. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other objects, features and other advantages of the present invention will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0034] Figure 1 is a plan view of a thin film transistor according to an embodiment of the present invention.

[0035] Figure 2 is along Figure 1 A cross-sectional view taken along line II'.

[0036] Figure 3 is a cross-sectional view of a thin film transistor according to another embodiment of the present invention.

[0037] Figure 4 is a cross-sectional view of a thin film transistor according to another embodiment of the present invention.

[0038] Figures 5A to 5G is a process diagram illustrating a process of manufacturing a thin film transistor according to an embodiment of the present invention.

[0039] Figure 6 is a schematic diagram of a display device according to an embodiment of the present invention.

[0040] Figure 7 yes Figure 6 Circuit diagram of any pixel.

[0041] Figure 8 yes Figure 7 A floor plan of pixels.

[0042] Fig. 9 is along Figure 8 A cross-sectional view taken along line II-II'. DETAILED DESCRIPTION

[0043] The advantages and features of the present invention and the methods for implementing the same will be explained by the following embodiments described with reference to the accompanying drawings. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided to make the present disclosure thorough and complete and to fully convey the scope of the present invention to those of ordinary skill in the art. In addition, the present invention is limited only by the scope of the claims.

[0044] The shapes, sizes, proportions, angles and quantities disclosed in the drawings used to describe the embodiments of the present invention are merely examples, and therefore, the present invention is not limited to the illustrative details. Similar reference numerals refer to similar elements throughout the specification. In the following description, when it is determined that a detailed description of a related known function or structure would unnecessarily obscure the focus of the present invention, this detailed description will be omitted.

[0045] Where “including,” “having,” and “comprising” are used in the present invention, other parts may be added unless “only” is used. Terms in the singular form may include plural forms unless otherwise specified.

[0046] In interpreting the elements, the elements are interpreted as including a margin of error even though this is not explicitly described.

[0047] When describing a positional relationship, for example, when the positional relationship between two parts is described as "on", "over", "below", or "after", one or more other parts may be set between the two parts unless "just" or "directly" is used.

[0048] Spatially relative terms such as "under," "below," "lower," "above," and "above" may be used herein to simply describe the relationship of one or more elements as shown to another or more elements. It will be understood that these terms are intended to cover different orientations of the devices in addition to the orientations depicted in the figures. For example, if the devices shown in the figures are reversed, a device described as being disposed "under" or "below" another device may be disposed "above" the other device. Thus, the exemplary term "under or below" may include the orientations of "under or below" as well as "above." Similarly, the exemplary term "above" or "upper" may include the orientations of "above" as well as "under or below."

[0049] When describing a time relationship, for example, when a time sequence is described as "after", "subsequently", "next", "before", discontinuous situations may be included unless "directly" or "directly" is used.

[0050] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish an element from other elements. For example, without departing from the scope of the present invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0051] It should be understood that the term "at least one" includes all combinations related to any one item. For example, "at least one of the first element, the second element, and the third element" may include: all combinations of two or more elements selected from the first element, the second element, and the third element; and each element of the first element, the second element, and the third element.

[0052] The features of the various embodiments of the present invention may be combined or combined with each other in part or in whole, and may be technically interoperable and driven with each other in various ways, as can be fully understood by those skilled in the art. The embodiments of the present invention may be implemented independently of each other, or may be implemented together in a mutually dependent relationship.

[0053] When adding reference numerals to elements of each figure for describing an embodiment of the present invention, the same elements may have the same symbols as may be shown in other figures.

[0054] In the embodiments of the present invention, the source and the drain are distinguished for the convenience of description, and the source and the drain are interchangeable. The source may be the drain, and vice versa. In addition, the source in any embodiment may be the drain in another embodiment, and the drain in any embodiment may be the source in another embodiment.

[0055] In some embodiments of the present invention, for ease of description, the source region and the source are distinguished, and the drain region and the drain are distinguished, but the embodiments of the present invention are not limited thereto. The source region may be the source, and the drain region may be the drain. In addition, the source region may be the drain, and the drain region may be the source.

[0056] Figure 1 is a plan view of a thin film transistor 100 according to an embodiment of the present invention. Figure 2 is along Figure 1 A cross-sectional view taken along line II'. Figure 3 is a cross-sectional view of a thin film transistor 200 according to another embodiment of the present invention. Figure 4 is a cross-sectional view of a thin film transistor 300 according to another embodiment of the present invention.

[0057] Specifically, refer to Figure 1 and 2, may include a buffer layer 120 on a base substrate 110 , an active layer 130 on the buffer layer 120 , and a gate 150 spaced apart from the active layer 130 and at least partially overlapping the active layer 130 .

[0058] According to an embodiment of the present invention, the thin film transistor 100 may further include a base substrate 110. Figure 1 and 2 , the buffer layer 120 is disposed on the base substrate 110 .

[0059] According to an embodiment of the present invention, the thin film transistor 100 may further include a gate insulating layer 140. Figure 1 and 2 , the gate insulating layer 140 is disposed on the active layer 130. Specifically, the gate insulating layer 140 is disposed between the active layer 130 and the gate 150.

[0060] According to an embodiment of the present invention, other layers of the thin film transistor 100 may be additionally disposed on the gate electrode 150. Specifically, the thin film transistor 100 may further include an interlayer insulating layer 160. Figure 2 , the interlayer insulating layer 160 is disposed on the gate 150. Specifically, the gate 150 is disposed between the gate insulating layer 140 and the interlayer insulating layer 160.

[0061] According to an embodiment of the present invention, the thin film transistor 100 may further include a source electrode 171 and a drain electrode 172. Figure 1 and 2 , a source electrode 171 and a drain electrode 172 are disposed on the interlayer insulating layer 160 .

[0062] Hereinafter, components of the thin film transistor 100 according to an embodiment of the present invention will be described in more detail.

[0063] Glass or plastic can be used for the base substrate 110. Transparent plastic having flexible properties, such as polyimide, can be used as the plastic.

[0064] When polyimide is used as the base substrate 110, heat-resistant polyimide capable of withstanding high temperatures may be used in consideration of performing a high-temperature deposition process on the base substrate 110. In this case, in order to form a thin film transistor, processes such as deposition, etching, etc. may be performed in a state where the polyimide substrate is disposed on a carrier substrate made of a high-durable material such as glass.

[0065] Reference Figure 1 and 2 , the buffer layer 120 may be disposed on the base substrate 110 .

[0066] The buffer layer 120 is formed on the base substrate 110 and may be formed of an inorganic material or an organic material. For example, the buffer layer 120 may include silicon oxide (SiOx), aluminum oxide (Al 2 O 3 ) and other insulating oxides.

[0067] The buffer layer 120 protects the active layer 130 by blocking impurities such as moisture and oxygen introduced from the base substrate 110 , serves to planarize an upper portion of the base substrate 110 , and may be formed as a single layer or a multi-layer.

[0068] According to an embodiment of the present invention, the buffer layer 120 may include a groove 125. Specifically, the groove 125 refers to a region in the buffer layer 120 that is partially etched.

[0069] Reference Figure 1 and 2 , the active layer 130 may be disposed on the buffer layer 120 .

[0070] The active layer 130 may include a channel region 130 n , a source region 130 a , and a drain region 130 b .

[0071] The channel region 130n overlaps the gate electrode 150. The channel region 130n serves as a channel of the thin film transistor 100.

[0072] Specifically, the active layer 130 may include: a channel region 130n overlapping the gate 150 in a plan view; a source region 130a not overlapping the gate 150 in a plan view and connected to one side of the channel region 130n; and a drain region 130b not overlapping the gate 150 in a plan view and connected to the other side of the channel region 130n.

[0073] According to an embodiment of the present invention, the source region 130 a and the drain region 130 b are spaced apart from each other with the channel region 130 n interposed therebetween.

[0074] According to the configuration of the present invention, the active layer 130 may be formed of a semiconductor material. The active layer 130 may include an oxide semiconductor material.

[0075] The oxide semiconductor material may include at least one of an IZO (InZnO)-based oxide semiconductor material, an IGO (InGaO)-based oxide semiconductor material, an ITO (InSnO)-based oxide semiconductor material, an IGZO (InGaZnO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, a GZTO (GaZnSnO)-based oxide semiconductor material, a GZO (GaZnO)-based oxide semiconductor material, an ITZO (InSnZnO)-based oxide semiconductor material, and a FIZO (FeInZnO)-based oxide semiconductor material. However, the embodiments of the present invention are not limited thereto, and the active layer 130 may be made of other oxide semiconductor materials known in the art.

[0076] The source region 130a and the drain region 130b may be formed by selectively conducting the active layer 130 made of a semiconductor material. According to an embodiment of the present invention, "giving conductivity to a specific portion of the active layer 130 so that it can be used as a conductor" is referred to as selective conduction. Through this selective conduction, the portion given conductivity is made into a conductor, and the portion not given conductivity is not made into a conductor.

[0077] Figure 1 and 2 The source region 130 a and the drain region 130 b shown are portions rendered conductive by selective conductivity.

[0078] According to an embodiment of the present invention, selective conductivity can be achieved by doping with a dopant. In addition, selective conductivity can be achieved by plasma treatment.

[0079] For example, the active layer 130 may be selectively conductive by dopant doping or dopant implantation using the gate 150 or a photoresist as a mask. The dopant may include, for example, at least one of boron (B), phosphorus (P), fluorine (F), and hydrogen (H).

[0080] When the active layer 130 is selectively conductive by doping with a dopant, a region of the active layer 130 doped with a dopant is selectively conductive to become a source region 130a or a drain region 130b. A region of the active layer 130 not doped with a dopant is not conductive and may become a channel region 130n.

[0081] Alternatively, the active layer 130 may be selectively made conductive by applying plasma treatment to the process of patterning the gate insulating layer 140. For example, plasma may be used in the process of patterning the gate insulating layer 140, and a portion of the active layer 130 in contact with the plasma may be selectively made conductive to become a source region 130a or a drain region 130b of the active layer 130. A portion of the active layer 130 that is protected by the gate insulating layer 140 and does not contact the plasma may not be made conductive and may be a channel region 130n.

[0082] However, for selective conductivity, when doping is performed using a dopant, the following problems may occur: the conductive region diffuses, and the conductive region is unnecessarily formed by doping. As a result, the threshold voltage (Vth) of the thin film transistor may shift in the negative (-) direction, and the problem of device degradation may occur.

[0083] In order to prevent the above problem, the buffer layer 120 including the trench 125 may be formed, and the active layer 130 may be formed on the trench 125 . Figure 1 and Figure 2 A structure in which the active layer 130 is formed on the buffer layer 120 and the trench 125 is illustrated. Specifically, at least a portion of the trench 125 according to the embodiment of the present invention may overlap with the gate 150. Specifically, the trench 125 according to the embodiment of the present invention includes a first trench 126 overlapping with the source region 130a and a second trench 127 overlapping with the drain region 130b. In this case, the first trench 126 and the second trench 127 are provided to be separated from each other.

[0084] When the active layer 130 is formed on the trench 125 having the constant inclined surface, the active layer 130 may also have the constant inclined surface. Specifically, when at least a portion of the trench 125 overlaps the gate 150 and the channel region 130n of the active layer 130 has the constant inclined surface, the conductive diffusion toward the inclined channel region 130n can be controlled or prevented, thereby further protecting the channel region 130n, thereby controlling or preventing the conductive diffusion while maintaining the effective channel length.

[0085] As a result, even if the channel region 130n has a short channel, the threshold voltage (Vth) can be prevented or suppressed from shifting in the negative (-) direction, and device degradation can be prevented or suppressed.

[0086] According to an embodiment of the present invention, when viewed in a plan view, at least a portion of the trench 125 may overlap with any one of the source region 130a and the drain region 130b. More specifically, the trench 125 includes a first trench 126 overlapping with the source region 130a and a second trench 127 overlapping with the drain region 130b.

[0087] In general, when the conduction is performed with respect to the source region 130a and the drain region 130b, the conduction diffusion from the interface between the channel region 130n and the conduction portion toward the channel region 130n may be greatly advanced. If the conduction diffusion is greatly advanced toward the channel region 130n, the threshold voltage (Vth) of the thin film transistor 100 may move in the negative (-) direction, thereby deteriorating the driving stability of the thin film transistor 100.

[0088] However, according to an embodiment of the present invention, when the first trench 126 overlaps with the source region 130a, the second trench 127 overlaps with the drain region 130b, and the first trench 126 and the second trench 127 overlap with the gate 150, the first trench 126 and the second trench 127 are respectively disposed at the boundary between the channel region 130n and the source region 130a and at the boundary between the channel region 130n and the drain region 130b. Therefore, the channel region 130n of the active layer 130 disposed on the first trench 126 and the second trench 127 and having a predetermined inclined surface is disposed in a region adjacent to the boundary between the channel region 130n and the source region 130a and the boundary between the channel region 130n and the drain region 130b, thereby controlling or preventing the diffusion of conduction.

[0089] According to an embodiment of the present invention, the channel region 130n may include a first channel region 130n1, a second channel region 130n2, and a third channel region 130n3.

[0090] Specifically, the channel region 130n includes: a first channel region 130n1 serving as an effective channel; a second channel region 130n2 disposed on one side of the first channel region 130n1, in contact with the source region 130a and disposed in the first trench 126; and a third channel region 130n3 disposed on the other side of the first channel region 130n1, in contact with the drain region 130b and disposed in the second trench 127.

[0091] exist Figure 2 , an arrangement structure of the first channel region 130n1, the second channel region 130n2, and the third channel region 130n3 is illustrated.

[0092] According to an embodiment of the present invention, the shortest distance between the upper surface of the base substrate 110 and the second and third channel regions 130n2 and 130n3 may be shorter than the shortest distance between the upper surface of the base substrate 110 and the first channel region 130n1. Specifically, the thickness of the buffer layer 120 overlapping the second and third channel regions 130n2 and 130n3 may be smaller than the thickness of the buffer layer overlapping the first channel region 130n1.

[0093] When the shortest distance between the upper surface of the base substrate 110 and the second channel region 130n2 and the third channel region 130n3 is shorter than the shortest distance between the upper surface of the base substrate 110 and the first channel region 130n1, the second channel region 130n2 and the third channel region 130n3 have a predetermined inclined surface relative to the first channel region 130n1, and the conductive diffusion toward the inclined channel region 130n can be controlled or prevented, thereby further protecting the channel region 130n, so that the conductive diffusion can be controlled or prevented while maintaining the effective channel length.

[0094] According to an embodiment of the present invention, each of the first groove 126 and the second groove 127 has: a first surface 126a, 127a parallel to the upper surface of the base substrate 110; a second surface 126b, 127b connected to one side of the first surface 126a, 127a and inclined at a predetermined angle relative to the first surface 126a, 127a; and a third surface 126c, 127c connected to the other side of the first surface 126a, 127a and inclined at a predetermined angle relative to the first surface 126a, 127a.

[0095] Specifically, refer to Figure 2 The active layer 130 is disposed on the first surfaces 126a, 127a, the second surfaces 126b, 127b and the third surfaces 126c, 127c of the first and second trenches 126 and 127, and the first surfaces 126a, 127 of the first and second trenches 126 and 127 are disposed between the second surfaces 126b, 127b and the third surfaces 126c, 127c.

[0096] According to an embodiment of the present invention, at least a portion of the second surfaces 126 b , 127 b of the first trench 126 and the second trench 127 may overlap with the gate 150 .

[0097] exist Figure 2 , a configuration is illustrated in which at least a portion of the second surfaces 126b and 127b of the first trench 126 and the second trench 127 overlaps with the gate 150. However, the embodiments of the present invention are not limited thereto, and a portion of the second surfaces 126b and 127b of the first trench 126 and the second trench 127 may overlap with the gate 150 (see Figure 4 ), the entire second surfaces 126b and 127b of the first trench 126 and the second trench 127 may overlap with the gate 150 in the region overlapping with the active layer 130 (see Figure 2 and Figure 3 ).

[0098] When at least a portion of the second surfaces 126b and 127b of the first trench 126 and the second trench 127 overlap with the gate 150, the active layer 130 disposed on the second surfaces 126b and 127b also overlaps with the gate 150, and more specifically, the inclined surface of the active layer 130 may overlap with the gate 150. That is, the conductive diffusion toward the inclined channel region 130n may be controlled or prevented, thereby further protecting the channel region 130n, thereby controlling or preventing the conductive diffusion while maintaining the effective channel length.

[0099] Preferably, the entire second surfaces 126b and 127b of the first trench 126 and the second trench 127 may overlap with the gate 150. Even if the entire second surfaces 126b and 127b of the first trench 126 and the second trench 127 overlap with the gate 150, the conductive diffusion toward the inclined channel region 130n may be controlled or prevented, thereby further protecting the channel region 130n, thereby controlling or preventing the conductive diffusion while maintaining the effective channel length.

[0100] According to an embodiment of the present invention, the thickness of the buffer layer 120 overlapping the first surfaces 126a, 127a of the first and second grooves 126 and 127 may be less than the thickness of the buffer layer 120 overlapping the second surfaces 126b, 127b and the third surfaces 126c, 127c of the first and second grooves 126 and 127.

[0101] Despite Figure 1 and 2 , the active layer 130 is formed of a single layer, but the configuration of the present invention is not limited thereto. The active layer 130 may have a single layer structure or a multi-layer structure.

[0102] According to an embodiment of the present invention, the channel region 130n, the source region 130a, and the drain region 130b of the active layer 130 may be integrally formed, and the active layer 130 may have a constant thickness. Specifically, the active layer 130 may have substantially the same thickness.

[0103] The gate insulating layer 140 is disposed on the active layer 130. The gate insulating layer 140 protects the channel region 130n. Specifically, the gate insulating layer 140 is disposed between the active layer 130 and the gate 150.

[0104] The gate insulating layer 140 has insulating properties. The gate insulating layer 140 may include, for example, at least one of silicon oxide, silicon nitride, and metal-based oxide. The gate insulating layer 140 may have a single-layer structure or a multi-layer structure.

[0105] According to an embodiment of the present invention, the gate insulating layer 140 may include a first gate insulating layer 141 and a second gate insulating layer 142 .

[0106] Specifically, the gate insulating layer 140 includes a first gate insulating layer 141 on the active layer 130 and a second gate insulating layer 142 on the first gate insulating layer 141. In this case, the first gate insulating layer 141 may be disposed on the channel region 130n and the trench 125 of the active layer 130. Specifically, the first gate insulating layer 141 may be disposed in the channel region 130n, the first trench 126, and the second trench 127 of the active layer 130n.

[0107] According to an embodiment of the present invention, the thickness of the first gate insulating layer 141 may be greater than the thickness of the second gate insulating layer 142 .

[0108] According to an embodiment of the present invention, the first gate insulating layer 141 may be disposed on the channel region 130 n of the active layer 130 and the trench 125 , and the second gate insulating layer 142 may be disposed over the entire surfaces of the active layer 130 and the buffer layer 120 .

[0109] exist Figure 2 , a configuration in which the first source region 130a1 and the first drain region 130b1 are in contact with the first gate insulating layer 141 is illustrated, and a configuration in which the second source region 130a2 and the second drain region 130b2 are in contact with the second gate insulating layer 142 is illustrated.

[0110] Specifically, the source region 130 a includes: a first source region 130 a 1 overlapping the first gate insulating layer 141 and the second gate insulating layer 142 ; and a second source region 130 a 2 overlapping the second gate insulating layer 142 and not overlapping the first gate insulating layer 141 .

[0111] In addition, the drain region 130 b includes a first drain region 130 b 1 overlapping the first gate insulating layer 141 and the second gate insulating layer 142 , and a second drain region 130 b 2 overlapping the second gate insulating layer 142 and not overlapping the first gate insulating layer 141 .

[0112] That is, the area adjacent to the channel region 130n and arranged on the groove 125 in the source region 130a and the drain region 130b overlaps with the first gate insulating layer 141 and the second gate insulating layer 142, and the area separated from the channel region 130n and not arranged on the groove 125 does not overlap with the first gate insulating layer 141, but only overlaps with the second gate insulating layer 142.

[0113] When the area set on the trench 125 in the source region 130a and the drain region 130b overlaps with the first gate insulating layer 141 and the second gate insulating layer 142, and the area not set on the trench 125 in the source region 130a and the drain region 130b does not overlap with the first gate insulating layer 141 but only overlaps with the second gate insulating layer 142, the thickness of the gate insulating layer 140 set on the first source region 130a1 and the first drain region 130b1 becomes greater than the thickness of the gate insulating layer 140 set on the second source region 130a2 and the second drain region 130b2, so that during doping for selective conductivity, the second source region 130a2 may have a higher dopant concentration than the first source region 130a1, and the second drain region 130b2 may have a higher dopant concentration than the first drain region 130b1. As a result, the dopant concentration in the region adjacent to the channel region 130n is lower, and conductive diffusion toward the channel region 130n may be controlled or prevented, thereby further protecting the channel region 130n, thereby controlling or preventing conductive diffusion while maintaining an effective channel length.

[0114] However, the embodiments of the present invention are not limited thereto, and even in a structure in which the gate insulating layer 140 covers the channel region 130n and exposes the source region 130a and the drain region 130b, at least a portion of the trench 125 overlaps the gate 150, and the active layer 130 is formed on the trench 125, the conductive diffusion toward the inclined channel region 130n can be controlled or prevented, thereby further protecting the channel region 130n, thereby controlling or preventing the conductive diffusion while maintaining the effective channel length (see Figure 4 ).

[0115] although Figure 4 A structure in which the gate insulating layer 140 is provided with the first gate insulating layer 141 and the second gate insulating layer 142 is shown, but the embodiments of the present invention are not limited thereto, and the gate insulating layer 140 may be formed of a single layer.

[0116] According to an embodiment of the present invention, the first source region 130a1 and the first drain region 130b1 may have a length L of 0.7 μm to 1.0 μm in the longitudinal direction of the channel region 130n. In this case, the longitudinal direction of the channel region 130n refers to a direction parallel to a direction connecting the source region 130a and the drain region 130b by the shortest distance in a plan view.

[0117] When the first source region 130a1 and the first drain region 130b1 have a length L greater than 1.0 μm in the length direction of the channel region 130n, the region where the trench 125 is provided is excessively ensured, resulting in that the conductive region in the first source region 130a1 and the first drain region 130b1 may be excessively reduced. As a result, the current characteristics of the device may be deteriorated.

[0118] On the other hand, when the first source region 130a1 and the first drain region 130b1 have a length L less than 0.7 μm in the length direction of the channel region 130n, a region where the trench 125 can be provided cannot be sufficiently ensured, thereby making it difficult to suppress or prevent conductive diffusion in the device.

[0119] In addition, according to an embodiment of the present invention, the groove 125 may have a height ratio (H / W) of 0.15 to 0.65. In this case, the height ratio (H / W) refers to a value obtained by dividing the height H of the groove 125 by the width W of the groove 125. More specifically, the width W of the groove 125 refers to the longest length in the length direction of the channel region 130n in a plan view, and the height H of the groove 125 refers to the difference between the maximum distance and the minimum distance between the upper surface of the buffer layer 120 and the upper surface of the base substrate 110 in a direction perpendicular to the length direction of the channel region 130n. More specifically, the height H of the groove 125 refers to the depth of the groove 125.

[0120] Considering the step coverage of the upper deposited film of the trench 125 , that is, the effect of preventing conductive diffusion and the step coverage, the trench 125 needs to have a height ratio (H / W) of 0.15 to 0.65.

[0121] On the other hand, when the trench 125 has a height ratio (H / W) greater than 0.65, the thickness of the active layer 130 deposited on the second surfaces 126b, 127b and the third surfaces 126c, 127c of the first and second trenches 126 and 127 is reduced, resulting in uneven device characteristics.

[0122] In addition, when the trench 125 has a height ratio (H / W) less than 0.15, the second surfaces 126b, 127b and the third surfaces 126c, 127c of the first trench 126 and the second trench 127 may not be sufficiently protected. Specifically, since the inclined area of ​​the channel region 130n is not sufficiently ensured, the conductive diffusion toward the channel region 130n is not controlled or prevented.

[0123] In addition, according to an embodiment of the present invention, the second surfaces 126 b and 127 b and the third surfaces 126 c and 127 of the first and second grooves 126 and 127 may have a tapered angle θ of 30 to 45 degrees relative to the first surfaces 126 a and 127 a .

[0124] Specifically, when the first surfaces 126a, 127a of the first and second trenches 126 and 127 are parallel to the base substrate 110 and the taper angle is 0 degrees, the second and third surfaces 126b, 127b, 126c, 127c of the first and second trenches 126 and 127 may have a taper angle of 30 to 45 degrees.

[0125] When the second surfaces 126 b , 127 b and the third surfaces 126 c , 127 c of the first and second trenches 126 and 127 have a taper angle of 30 to 45 degrees, the active layer 130 may be formed on the trench 125 to have a uniform thickness.

[0126] On the other hand, when the taper angles of the second surfaces 126b, 127b and the third surfaces 126c, 127c of the first groove 126 and the second groove 127 exceed the range of 30 degrees to 45 degrees, the thickness of the active layer 130 deposited on the second surfaces 126b, 127b and the third surfaces 126c, 127c of the first groove 126 and the second groove 127 is reduced, resulting in disconnection.

[0127] The gate 150 is disposed on the gate insulating layer 140. The gate 150 overlaps the channel region 130n of the active layer 130.

[0128] The gate 150 may include at least one of an aluminum-based metal such as aluminum (Al) or an aluminum alloy, a silver-based metal such as silver (Ag) or a silver alloy, a copper-based metal such as copper (Cu) or a copper alloy, a molybdenum-based metal such as molybdenum (Mo) or a molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate 150 may have a multilayer structure including at least two conductive layers having different physical properties, respectively. For example, the gate 150 may include at least one of molybdenum (Mo) and titanium (Ti).

[0129] According to an embodiment of the present invention, the gate insulating layer 140 may be patterned by etching using the gate 150 as a mask, and in this process, the active layer 130 may be selectively conductive to form the source region 130a and the drain region 130b. Specifically, according to an embodiment of the present invention, the region of the active layer 130 overlapping with the gate 150 is not conductive to become the channel region 130n having semiconductor characteristics, and the region not overlapping with the gate 150 may be conductive to become the source region 130a and the drain region 130b.

[0130] Reference Figure 2 , an interlayer insulating layer 160 may be disposed on the gate electrode 150. The interlayer insulating layer 160 may be made of an organic or inorganic insulating material. The interlayer insulating layer 160 may be formed of a composite layer of an organic layer and an inorganic layer.

[0131] According to an embodiment of the present invention, the thin film transistor 100 may include a source electrode 171 and a drain electrode 172 disposed on the interlayer insulating layer 160. The positions of the source electrode 171 and the drain electrode 172 may be exchanged with each other. However, the embodiment of the present invention is not limited thereto, and the source region 130a and the drain region 130b may be used as a source electrode and a drain electrode, respectively.

[0132] Reference Figure 1 and 2 Each of the source electrode 171 and the drain electrode 172 may be connected to the active layer 130 via a contact hole. Specifically, the source electrode 171 may contact the source region 130a via the contact hole. The drain electrode 172 may be separated from the source electrode 171 and contact the drain region 130b via the contact hole.

[0133] Although not shown in the drawings, a light blocking layer may be disposed on the base substrate 110. Specifically, the light blocking layer may be disposed between the base substrate 110 and the active layer 130. The light blocking layer may overlap the channel region 130n. The light blocking layer protects the channel region 130n by blocking light incident from the outside.

[0134] The light blocking layer may be formed of a material having light blocking properties. The light blocking layer may include at least one of aluminum-based metals such as aluminum (Al) or aluminum alloys, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), titanium (Ti), and iron (Fe). According to an embodiment of the present invention, the light blocking layer may have electrical conductivity.

[0135] The light blocking layer may be omitted. Figure 1 , 2 3 , but a buffer layer may be additionally disposed between the base substrate 110 and the light blocking layer. The light blocking layer may be electrically connected to one of the source electrode 171 and the drain electrode 172.

[0136] Hereinafter, a method of manufacturing the thin film transistor 100 according to an embodiment of the present invention will be described.

[0137] According to an embodiment of the present invention, a method for manufacturing a thin film transistor 100 may include: forming a first insulating material 121 on a base substrate 110; patterning the first insulating material 121 to form a buffer layer 120 including a groove 125; forming an active layer 130 on the buffer layer 120; forming a second insulating material 141a on the active layer 130; forming a first gate insulating layer 141 by patterning the second insulating material 141a; forming a second gate insulating layer 142 on the first gate insulating layer 141; and forming a gate 150 on the second gate insulating layer 142.

[0138] Figures 5A to 5G 1 is a process diagram illustrating a method of manufacturing the thin film transistor 100 according to an embodiment of the present invention. Figures 5A to 5G Corresponding to the Figure 1 A cross-sectional view taken along line II'.

[0139] Reference Figure 5A , a first insulating material 121 is formed on the base substrate 110. Specifically, the first insulating material 121 is disposed on the entire surface of the base substrate 110.

[0140] Reference Figure 5B , a buffer layer 120 including a trench 125 is formed by patterning the first insulating material 121 .

[0141] Reference Figure 5C , the active layer 130 is formed on the buffer layer 120 .

[0142] Reference Figure 5D , the second insulating material 141a is formed on the active layer 130. Specifically, the second insulating material 141a is formed on the entire surface of the active layer 130 and on the buffer layer 120 on which the active layer 130 is not disposed.

[0143] Reference Figure 5E , the second insulating material 141a is patterned to form a first gate insulating layer 141. In this case, the first insulating layer 141 may overlap a portion of the active layer 130 and may not overlap another portion of the active layer 130.

[0144] Reference Fig. 5F , a second gate insulating layer 142 is formed on the first gate insulating layer 141, and a gate 150 is formed on the second gate insulating layer 142. Specifically, the second gate insulating layer 142 is disposed on the entire surface of the first gate insulating layer 141 and on the active layer 130 and the buffer layer 120 on which the first gate insulating layer 141 is not disposed.

[0145] Reference Figure 5G , an interlayer insulating layer 160 is formed on the gate 150 , and a source electrode 171 and a drain electrode 172 are respectively formed on the interlayer insulating layer 160 .

[0146] In this case, each of the source electrode 171 and the drain electrode 172 contacts at least a portion of the active layer 130 .

[0147] According to an embodiment of the present invention, after the step of forming the gate 150, the step of doping the active layer 130 with a dopant may be further included. Specifically, the dopant doped into the active layer 130 may include, for example, at least one of boron (B), phosphorus (P), fluorine (F), and hydrogen (H). In this case, the region of the active layer 130 overlapping the first gate insulating layer 141 and the second gate insulating layer 142 at the same time is classified as the first source region 130a1 and the first drain region 130b1 due to the low dopant concentration, and the region not overlapping the first gate insulating layer 141 but only overlapping the second gate insulating layer 142 is classified as the second source region 130a2 and the second drain region 130b2 due to the high dopant concentration.

[0148] The description of each configuration of the thin film transistor 100 according to the present invention is repeated above and is omitted.

[0149] Figure 6 is a schematic diagram illustrating a display device 1000 according to still another embodiment of the present invention.

[0150] like Figure 6 As shown, a display device 1000 according to still another embodiment of the present invention may include a display panel 310 , a gate driver 320 , a data driver 330 , and a controller 340 .

[0151] The display panel 310 includes gate lines GL and data lines DL, and pixels P are disposed in crossing regions of the gate lines GL and the data lines DL. An image is displayed by driving the pixels P. The gate lines GL, the data lines DL, and the pixels P may be disposed on a base substrate 110 .

[0152] The controller 340 controls the gate driver 320 and the data driver 330 .

[0153] The controller 340 outputs a gate control signal GCS for controlling the gate driver 320 and a data control signal DCS for controlling the data driver 330 by using a signal provided from an external system not shown. In addition, the controller 340 samples input image data input from the external system, rearranges the sampled data, and provides the rearranged digital image data RGB to the data driver 330.

[0154] The gate control signal GCS includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), a start signal (Vst) and a gate clock (GCLK). In addition, a control signal for controlling the shift register may be included in the gate control signal GCS.

[0155] The data control signal DCS includes a source start pulse (SSP), a source shift clock signal (SSC), a source output enable signal (SOE), and a polarity control signal (POL).

[0156] The data driver 330 supplies data voltages to the data lines DL of the display panel 310. Specifically, the data driver 330 converts the image data RGB input from the controller 340 into analog data voltages and supplies the data voltages to the data lines DL.

[0157] According to one embodiment of the present invention, the gate driver 320 may be packaged on the display panel 310. In this way, the structure in which the gate driver 320 is directly packaged on the display panel 3210 will be referred to as a gate-in-panel (GIP) structure. Specifically, in the gate-in-panel (GIP) structure, the gate driver 320 may be disposed on the base substrate 110.

[0158] The display device 1000 according to one embodiment of the present invention may include the above-described thin film transistors 100, 200, and 300. According to one embodiment of the present invention, the gate driver 320 may include the above-described thin film transistors 100, 200, and 300.

[0159] The gate driver 320 may include a shift register 350 .

[0160] The shift register 350 sequentially supplies gate pulses to the gate lines GL in one frame by using a start signal and a gate clock transmitted from the controller 340. In this case, one frame refers to a period of time during which one image is output through the display panel 310. The gate pulse has a turn-on voltage capable of turning on a switching device (thin film transistor) provided in the pixel P.

[0161] In addition, the shift register 350 provides a gate-off signal capable of turning off the switching device to the gate line GL during other periods of a frame when no gate pulse is provided. Hereinafter, the gate pulse and the gate-off signal will be collectively referred to as a scan signal SS or Scan.

[0162] The shift register 350 may include the above-described thin film transistors 100 , 200 , and 300 .

[0163] Figure 7 It is a graphic Figure 6 Circuit diagram of any pixel P.

[0164] Figure 7 The circuit diagram of FIG. 1 is an equivalent circuit diagram of a pixel P of the display device 1000 including an organic light emitting diode (OLED) as a display element 710 .

[0165] Reference Figure 7The pixel P includes a display element 710 and a pixel driving circuit PDC for driving the display element 710. Specifically, the display device 1000 according to an embodiment of the present invention may include a pixel driving circuit PDC located on a base substrate 110.

[0166] Figure 7 The pixel driving circuit PDC includes a first thin film transistor TR1 as a switching transistor and a second thin film transistor TR2 as a driving transistor. A display device 1000 according to another embodiment of the present invention may include at least one of the above-described thin film transistors 100, 200, and 300.

[0167] The first thin film transistor TR1 is connected to the gate line GL and the data line DL, and is turned on or off by a scan signal SS supplied through the gate line GL.

[0168] The data line DL provides a data voltage Vdata to the pixel driving circuit PDC, and the first thin film transistor TR1 controls application of the data voltage Vdata.

[0169] The driving power line PL supplies a driving voltage Vdd to the display element 710 , and the first thin film transistor TR1 controls the driving voltage Vdd. The driving voltage Vdd is a pixel driving voltage for driving an organic light emitting diode (OLED) as the display element 710 .

[0170] When the first thin film transistor TR1 is turned on by the scan signal SS applied from the gate driver 320 through the gate line GL, the data voltage Vdata supplied through the data line DL is supplied to the gate of the second thin film transistor TR2 connected to the display element 710. The data voltage Vdata is charged in the storage capacitor C1 formed between the gate and source of the second thin film transistor TR2.

[0171] The amount of current supplied to the organic light emitting diode (OLED) as the display element 710 through the second thin film transistor TR2 is controlled according to the data voltage Vdata, whereby the gray level of light output from the display element 710 may be controlled.

[0172] Figure 8 yes Figure 7 The pixel map, Fig. 9 is along Figure 8 A cross-sectional view taken along line II-II'.

[0173] Reference Figure 8 and 9 , the first thin film transistor TR1 and the second thin film transistor TR2 are disposed on the base substrate 110 .

[0174] The base substrate 110 may be made of glass or plastic. As the base substrate 110, plastic having a flexible property, such as polyimide (PI), may be used.

[0175] The light blocking layer 111 is disposed on the base substrate 110. The light blocking layer 111 may have a light blocking property. The light blocking layer 111 may protect the active layers A1 and A2 by blocking light incident from the outside.

[0176] The buffer layer 120 is disposed on the light blocking layer 111. The buffer layer 120 is made of an insulating material and protects the active layers A1 and A2 from moisture or oxygen introduced from the outside.

[0177] The buffer layer 120 may include a trench 125. The trench 125 refers to a region that is partially etched away in the buffer layer 120. Specifically, the trench 125 includes a first trench 126 overlapping the source region and a second trench 127 overlapping the drain region.

[0178] The first active layer A1 of the first thin film transistor TR1 and the second active layer A2 of the second thin film transistor TR2 are disposed on the buffer layer 120. Specifically, the first active layer A1 of the first thin film transistor TR1 and the second active layer A2 of the second thin film transistor TR2 are disposed on the groove 125.

[0179] The first active layer A1 and the second active layer A2 may include, for example, an oxide semiconductor material. The first active layer A1 and the second active layer A2 may be formed of an oxide semiconductor layer made of an oxide semiconductor material.

[0180] In the first thin film transistor TR1, the first active layer A1 may include a channel region, a source region, and a drain region. The channel region of the first active layer A1 overlaps the gate G1. According to another configuration of the present invention, the source region may be referred to as a source S1, and the drain region may be referred to as a drain D1.

[0181] In the second thin film transistor TR2, the second active layer A2 may include a channel region, a source region and a drain region. The channel region of the second active layer A2 overlaps the gate G2. According to another configuration of the present invention, the source region may be referred to as a source S2, and the drain region may be referred to as a drain D2.

[0182] The gate insulating layer 140 is disposed on the active layers A1 and A2. The gate insulating layer 140 covers upper surfaces of the active layers A1 and A2.

[0183] The gate insulating layer 140 includes a first gate insulating layer 141 and a second gate insulating layer 142 on the first active layer A1 of the first thin film transistor TR1 and the second active layer A2 of the second thin film transistor TR2 .

[0184] In this case, the thickness of the first gate insulating layer 141 may be greater than the thickness of the second gate insulating layer 142 .

[0185] The gate electrode G1 of the first thin film transistor TR1 and the gate electrode G2 of the second thin film transistor TR2 are disposed on the gate insulating layer 140 .

[0186] Although not shown in the drawings, the gate line GL may be disposed on the gate insulating layer 140. The gate G1 of the first thin film transistor TR1 may extend from the gate line GL or may be a part of the gate line GL.

[0187] Reference Figure 8 and 9 , a first capacitor electrode CE1 of the storage capacitor Cst is formed on the gate insulating layer 140. The first capacitor electrode CE1 may be formed of the same material as the gates G1 and G2 through the same process.

[0188] An interlayer insulating layer 160 is disposed on the gates G1 and G2 and the first capacitor electrode CE1 .

[0189] The data line DL and the driving power line PL are disposed on the interlayer insulating layer 160. Also, on the interlayer insulating layer 160, a source S1 and a drain D1 of the first thin film transistor TR1 are disposed, and a source S2 and a drain D2 of the second thin film transistor TR2 are disposed.

[0190] The source electrode S1 of the first thin film transistor TR1 may be integrally formed with the data line DL, and may have a structure extending from the data line DL.

[0191] The source electrode S1 of the first thin film transistor TR1 may contact a side surface of the active layer A1 of the first thin film transistor TR1 through the first contact hole H1.

[0192] The drain electrode D1 of the first thin film transistor TR1 contacts the other side surface of the active layer A1 of the first thin film transistor TR1 through the second contact hole H2. In addition, the drain electrode D1 of the first thin film transistor TR1 is connected to the first capacitor electrode CE1 through the third contact hole H3. As a result, the first capacitor electrode CE1 may be connected to the first thin film transistor TR1.

[0193] The drain electrode D2 of the second thin film transistor TR2 may be integrally formed with the driving power line PL, and may have a structure extending from the driving power line PL.

[0194] The drain electrode D2 of the second thin film transistor TR2 may contact the side surface of the active layer A2 of the second thin film transistor TR2 through the sixth contact hole H6.

[0195] The source electrode S2 of the second thin film transistor TR2 contacts the other side surface of the active layer A2 of the second thin film transistor TR2 via the fifth contact hole H5. In addition, the source electrode S2 of the second thin film transistor TR2 is connected to the light blocking layer 111 via the fourth contact hole H4. The same voltage as the voltage applied to the source electrode S2 of the second thin film transistor TR2 may be applied to the light blocking layer 111 overlapping the second thin film transistor TR2.

[0196] The source electrode S2 of the second thin film transistor TR2 may extend onto the interlayer insulating layer 160 to form a second capacitor electrode CE2 of the storage capacitor Cst.

[0197] According to an embodiment of the present invention, the first capacitor electrode CE1 and the second capacitor electrode CE2 may overlap to form a storage capacitor Cst.

[0198] Reference Figure 8 and 9 The planarization layer 190 is disposed on the data line DL, the driving power line PL, the source electrodes S1 and S2, the drain electrodes D1 and D2, and the second capacitor electrode CE2. The planarization layer 190 planarizes the upper portion of the first thin film transistor TR1 and the second thin film transistor TR2 and protects the first thin film transistor TR1 and the second thin film transistor TR2. The planarization layer 190 serves as a protective layer.

[0199] The first electrode 711 of the display element 710 is disposed on the planarization layer 190. The first electrode 711 of the display element 710 contacts the second capacitor electrode CE2 via the seventh contact hole H7 formed in the planarization layer 190. As a result, the first electrode 711 of the display element 710 may be connected to the source S2 of the second thin film transistor TR2.

[0200] The bank layer 750 is disposed at an edge of the first electrode 711. The bank layer 750 defines a light emitting region of the display element 710.

[0201] The organic light emitting layer 712 is provided on the first electrode 711, and the second electrode 713 is provided on the organic light emitting layer 712. Thus, the display element 710 is completed. Figure 7 The display element 710 shown is an organic light emitting diode (OLED). Therefore, the display device 1000 according to the embodiment of the present invention is an organic light emitting display device.

[0202] The pixel driving circuit PDC according to another configuration of the present invention may be formed in various structures other than the above-mentioned structure. The pixel driving circuit PDC may include, for example, three or more thin film transistors.

[0203] According to the present invention, the following advantageous effects can be obtained.

[0204] The thin film transistor according to the embodiment of the present invention includes a trench in order to maintain an effective channel length and control or prevent conductive diffusion.

[0205] The thin film transistor according to the embodiment of the present invention includes a trench so as to prevent or suppress the threshold voltage Vth from shifting in the negative (-) direction even when the channel region has a short channel.

[0206] In addition to the above effects, ordinary technicians in the field to which the present invention belongs will also clearly understand other features and advantages of the present invention based on such technology and description given above.

[0207] It will be clear to those skilled in the art that the invention described above is not limited by the above-mentioned embodiments and drawings, and various substitutions, modifications and changes can be made in the invention without departing from the spirit or scope of the invention. Therefore, the scope of the invention is defined by the appended claims, and all changes or modifications derived from the meaning, scope and equivalent concepts of the claims are intended to fall within the scope of the invention.

Claims

1. A thin film transistor, comprising: Basic substrate; A buffer layer, wherein the buffer layer is disposed on the base substrate, and an upper surface of the buffer layer has a groove; an active layer on the buffer layer; as well as a gate electrode spaced apart from the active layer and at least partially overlapping the active layer in a plan view, The active layer comprises: a channel region overlapping the gate in a plan view; A source region connected to one side of the channel region in a plan view; and a drain region connected to the other side of the channel region in a plan view, wherein the trench comprises a first trench having the source region therein and a second trench having the drain region therein, The channel region includes: a first channel region; a second channel region on one side of the first channel region, in contact with the source region, and in the first trench; and a third channel region on the other side of the first channel region, in contact with the drain region and in the second trench, wherein the shortest distance between the upper surface of the base substrate and the second channel region is shorter than the shortest distance between the upper surface of the base substrate and the first channel region, The shortest distance between the upper surface of the base substrate and the third channel region is shorter than the shortest distance between the upper surface of the base substrate and the first channel region. 2 . The thin film transistor according to claim 1 , wherein the first trench and the second trench are spaced apart from each other. 3 . The thin film transistor according to claim 1 , wherein the channel region, the source region, and the drain region of the active layer are integrally formed, and the active layer has a constant thickness.

4. The thin film transistor according to claim 1, wherein each of the first trench and the second trench comprises: a first surface, the first surface being substantially parallel to an upper surface of the base substrate; a second surface, the second surface connected to one side of the first surface, the second surface being inclined at a first angle relative to the first surface; as well as a third surface, the third surface being connected to the other side of the first surface, the third surface being inclined at a second angle relative to the first surface, wherein the active layer is on the second surface and the third surface, At least a portion of the second surface overlaps with the gate in a plan view. 5 . The thin film transistor according to claim 4 , wherein an entire second surface of each of the first trench and the second trench overlaps the gate.

6. The thin film transistor according to claim 1, further comprising a gate insulating layer between the active layer and the gate, wherein the gate insulating layer comprises a first gate insulating layer on the active layer and a second gate insulating layer on the first gate insulating layer, The first gate insulating layer is on the channel region of the active layer and the trench. 7 . The thin film transistor according to claim 6 , wherein a thickness of the first gate insulating layer is greater than a thickness of the second gate insulating layer.

8. The thin film transistor according to claim 6, wherein the source region comprises: a first source region, the first source region overlapping the first gate insulating layer and the second gate insulating layer; as well as a second source region, the second source region overlaps with the second gate insulating layer and does not overlap with the first gate insulating layer, The drain region comprises: a first drain region, the first drain region overlapping the first gate insulating layer and the second gate insulating layer; as well as A second drain region overlaps with the second gate insulating layer and does not overlap with the first gate insulating layer.

9. The thin film transistor according to claim 8, wherein the first source region and the first drain region contact the first gate insulating layer, The second source region and the second drain region contact the second gate insulating layer.

10. The thin film transistor according to claim 1, further comprising a gate insulating layer between the active layer and the gate, The gate insulating layer covers the channel region and the source region and the drain region.

11. The thin film transistor according to claim 8, wherein the second source region has a higher dopant concentration than the first source region, The second drain region has a higher dopant concentration than the first drain region. 12 . The thin film transistor according to claim 8 , wherein in a plan view, the first source region and the first drain region have a length of 0.7 μm to 1.0 μm in a length direction of the channel region.

13. The thin film transistor according to claim 1, wherein the trench has a height ratio of 0.15 to 0.65, wherein the height ratio is obtained by dividing the height of the groove by the width of the groove, wherein the width is the longest length in the length direction of the channel region in a plan view, The height is a difference between a maximum distance and a minimum distance between an upper surface of the buffer layer and an upper surface of the base substrate in a direction perpendicular to a length direction of the channel region. 14 . The thin film transistor of claim 4 , wherein each of the first angle and the second angle relative to the first surface is between 30 degrees and 45 degrees.

15. A display device comprising the thin film transistor according to claim 1.

16. A method for manufacturing a thin film transistor, comprising: forming a first insulating material on a base substrate, and patterning the first insulating material to form a buffer layer including a groove; forming an active layer on the buffer layer; forming a second insulating material on the active layer and forming a first gate insulating layer by patterning the second insulating material; forming a second gate insulating layer on the first gate insulating layer; and forming a gate on the second gate insulating layer, At least a portion of the trench overlaps with the gate in a plan view. 17 . The method for manufacturing a thin film transistor according to claim 16 , further comprising the step of doping the active layer with a dopant after the step of forming the gate electrode.

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