Manufacturing method of high-voltage device

Abstract

The invention provides a manufacturing method of a high-voltage device, and the method comprises the steps: forming a sacrificial oxide layer through thermal oxidation, and removing the sacrificial oxide layer, thereby reducing the surface height of a substrate, and enabling a device isolation structure around a high-voltage region to be thinned in the transverse direction, therefore, a subsequently formed high-voltage gate oxide layer can be ensured to be formed on the substrate surface of a high-voltage region limited by the device isolation structure in a self-aligned manner; and after the sacrificial oxide layer is removed and the side, close to the high-voltage region, of the device isolation structure is etched and opened, a barrier layer is formed to at least cover the side wall of the device isolation structure and expose the top surface of the substrate of the high-voltage region, so that in the process of forming a high-voltage gate oxide layer required by the high-voltage region through thermal oxidation, the high-voltage gate oxide layer is formed; the blocking side wall can be used for blocking oxygen molecules from transversely diffusing to an adjacent active region through the top of the thinned device isolation structure, so that the aim of improving beaks is fulfilled.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and in particular to a method for manufacturing a high-voltage device. Background Art

[0002] With the continuous miniaturization of semiconductor components and the requirements of specific application scenarios, current product designs often require different low-voltage devices and high-voltage devices to be designed on the same substrate. A high-voltage device is a device that can withstand higher voltages while ensuring that the gate is not broken down under high-voltage operation. Generally, the thickness of the high-voltage gate oxide layer of a high-voltage device is one or two orders of magnitude higher than the thickness of the gate oxide layer of a low-voltage device. For example, the thickness of the high-voltage gate oxide layer of a high-voltage device is dozens of times the thickness of the gate oxide layer of a low-voltage device.

[0003] At present, since the thickness of the high-voltage gate oxide layer is relatively thick, in the process of forming the high-voltage gate oxide layer by thermal oxidation, it will inevitably be affected by the bird's beak problem caused by the lateral diffusion of oxygen molecules in the thermal oxidation process. Summary of the invention

[0004] The object of the present invention is to provide a method for manufacturing a high voltage device, which can improve the bird's beak problem generated during the formation of a high voltage gate oxide layer.

[0005] To achieve the above object, the present invention provides a method for manufacturing a high voltage device, which comprises the following steps:

[0006] Providing a substrate having a patterned hard mask layer formed on the surface, wherein the patterned hard mask layer exposes a surface of a high voltage region of the substrate and a surface of a device isolation structure portion around the high voltage region;

[0007] Under the mask of the patterned hard mask layer, a portion of the substrate in the high voltage region is consumed by thermal oxidation to form a sacrificial oxide layer;

[0008] Removing the sacrificial oxide layer by wet etching, and etching open a side of the top of the device isolation structure close to the high voltage region, so that the top of the substrate of the high voltage region becomes lower and the top of the device isolation structure becomes thinner in the lateral direction;

[0009] Forming a blocking sidewall, wherein the blocking sidewall at least covers a sidewall on a side of the top of the device isolation structure close to the high voltage region and exposes a top surface of the substrate of the high voltage region;

[0010] Under the masking of the patterned hard mask layer and the blocking spacer, a high voltage gate oxide layer is formed on the surface of the high voltage region by thermal oxidation.

[0011] Optionally, the step of providing a substrate having a patterned hard mask layer formed on the surface thereof comprises:

[0012] forming a pad oxide layer on the substrate and forming the device isolation structure in the substrate to define the high voltage region in the substrate;

[0013] Depositing a hard mask layer on the pad oxide layer and the device isolation structure, and etching the hard mask layer to form the patterned hard mask layer;

[0014] Under the masking of the patterned hard mask layer, the pad oxide layer on the high voltage region is removed by a wet method to expose the substrate surface of the high voltage region.

[0015] Optionally, after removing the sacrificial oxide layer by wet etching and before forming the blocking spacer, a stress buffer layer is further formed, wherein the stress buffer layer at least covers the surface of the substrate in the high-voltage region.

[0016] Optionally, after the sacrificial oxide layer is removed by wet etching, the top of the device isolation structure is etched open on one side close to the high voltage region to form a groove; after the sacrificial oxide layer is removed by wet etching and before the stress buffer layer is formed, the device isolation structure in the groove is also etched to deepen the groove; the formed blocking side wall also covers the bottom of the groove, and the top surface of the blocking side wall on the bottom of the groove is lower than or flush with the top surface of the substrate of the high voltage region.

[0017] Optionally, the step of forming the blocking spacer includes:

[0018] Covering the stress buffer layer at least on the surface of the substrate exposed in the high-voltage region;

[0019] Depositing a barrier layer on the stress buffer layer and the exposed surfaces of the device isolation structure and the patterned hard mask layer;

[0020] The barrier layer on the substrate surface of the high voltage region is removed by dry etching, and at least the barrier layer on the sidewall of the top of the device isolation structure close to the high voltage region is retained to form the barrier sidewall.

[0021] Optionally, the dry etching includes plasma etching in which the etching direction is perpendicular to the surface of the substrate.

[0022] Optionally, the step of forming the blocking sidewall includes: converting a sidewall of a corresponding thickness on a side of the top of the device isolation structure close to the high voltage region into the blocking sidewall by ion doping or surface modification.

[0023] Optionally, the ions used in the ion doping method include at least one of oxygen, nitrogen and carbon, and the surface modification treatment includes plasma nitridation or annealing in a nitrogen atmosphere.

[0024] Optionally, after forming the blocking sidewall and before forming the high-voltage gate oxide layer by thermal oxidation, the stress buffer layer on the high-voltage region is wet-removed under the masking of the patterned hard mask layer and the blocking sidewall to re-expose the substrate surface of the high-voltage region.

[0025] Optionally, the stress buffer layer includes a silicon oxide layer, and the barrier layer includes a silicon nitride layer or a silicon oxynitride layer.

[0026] Optionally, when a side of the top of the device isolation structure close to the high voltage region is etched open, a top of the opened region of the device isolation structure is lower than a top of a substrate of the high voltage region.

[0027] Optionally, after forming the high-voltage gate oxide layer, the method further includes: removing the patterned hard mask layer and the blocking sidewalls together or separately by wet etching.

[0028] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0029] 1. A sacrificial oxide layer is formed by thermal oxidation and when the sacrificial oxide layer is removed, on the one hand, the surface height of the substrate is reduced, and on the other hand, the device isolation structure around the high-voltage area is thinned in the lateral direction, thereby ensuring that the subsequently formed high-voltage gate oxide layer can be self-alignedly formed on the substrate surface of the high-voltage area defined by the device isolation structure.

[0030] 2. After removing the sacrificial oxide layer and etching open one side of the device isolation structure close to the high-voltage region to form a groove on the top of one side of the device isolation structure, a blocking sidewall is formed on the sidewall of the groove or on the sidewall and bottom of the groove. In this way, in the process of thermal oxidation to form the high-voltage gate oxide layer required for the high-voltage region, the blocking sidewall can be used to block oxygen molecules from passing through the thinned top of the device isolation structure and laterally diffusing into the adjacent active area, thereby achieving the purpose of improving the bird's beak.

[0031] 3. It is suitable for small-size products. In the process of manufacturing the high-voltage gate oxide layer, it can ensure that the device isolation structure that must be lost is sufficient to meet the alignment requirements, avoid the problem of loose device isolation structure being penetrated by oxygen to form a bird's beak, and ensure that there is no adverse effect on the formation of the high-voltage gate oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0033] Figure 1It is a schematic diagram of a bird's beak produced when forming a high-voltage gate oxide layer of a high-voltage device in the prior art.

[0034] Figure 2 It is a schematic flow chart of a method for manufacturing a high voltage device according to an embodiment of the present invention.

[0035] Figures 3 to 10 yes Figure 2 A schematic diagram of the device cross-sectional structure in a method for manufacturing a high-voltage device is shown.

[0036] Fig.11 It is a schematic diagram of a device cross-sectional structure in a method for manufacturing a high-voltage device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0037] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described. It should be understood that the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make the disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. The same reference numerals represent the same elements from beginning to end. It should be understood that when an element is referred to as "connected to", "coupled" other elements, it can be directly connected to other elements, or there can be intervening elements. On the contrary, when an element is referred to as "directly connected to" other elements, there is no intervening element. When used here, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0038] Generally, the gate oxide thickness of low-voltage devices and high-voltage devices differs by dozens of times. When these two devices are manufactured on a substrate at the same height level, the difference in gate oxide thickness often leads to poor surface flatness, thus affecting subsequent processes.

[0039] Please refer to Figure 1The current mainstream technology is roughly as follows: after manufacturing an STI (shallow trench isolation) structure in the substrate SUB and forming a high-voltage area (i.e., the active area of ​​the high-voltage device) AA and a non-high-voltage area (i.e., the active area of ​​the non-high-voltage device) through processes such as well implantation, the non-high-voltage area is covered with a silicon nitride film layer SiN (not shown), a sacrificial oxide layer (not shown) is formed in the high-voltage area through thermal oxidation, and then the sacrificial oxide layer is removed to reduce the horizontal height of the top of the substrate in the high-voltage area, and then a high-voltage gate oxide layer HVGOX is formed through thermal oxidation to restore the surface flatness of the high-voltage area.

[0040] The inventor has found that Figure 1 , the above technology has the following defects in practical application:

[0041] 1. In the process of restoring the surface flatness of the high voltage region by forming a high voltage gate oxide layer HVGOX through thermal oxidation, due to the thick required thickness of HVGOX and the long process time, the oxygen molecules O 2 It not only diffuses in the vertical direction to achieve HVGOX growth, but also diffuses in the horizontal direction. Moreover, as the size of semiconductor components continues to shrink, in order to meet the minimum spacing requirements from high-voltage devices to contact holes (CT) and other structures, and considering the window (window) and other issues in the process, the top of the STI structure around the high-voltage area will be etched open near the high-voltage gate oxide layer HVGOX, which also causes the thickness of the top of the STI to become thinner in the horizontal direction, resulting in the oxygen molecule O 2 It is easier to diffuse laterally along the thinned top of the STI structure into the adjacent active area, causing the top of the active area there to be partially oxidized to form a bird's beak (such as Figure 1 ) as indicated by the dotted circle in the figure.

[0042] 2. The STI structure is usually formed by filling a shallow trench (not shown) in the substrate SUB with silicon oxide or the like through a CVD process. The texture of the STI structure is relatively loose, so in the process of restoring the surface flatness of the high-voltage region by forming a high-voltage gate oxide layer HVGOX through thermal oxidation, oxygen molecules O 2 It is easy to pass through the STI structure and diffuse laterally into the active area far away from the high-voltage gate oxide layer HVGOX to form a bird's beak. When the lateral length of these bird's beaks is long, it is easy to pass through the top surface of the adjacent active area from one side of an STI structure and connect with another STI structure, thereby causing a series of problems such as the inability to subsequently form a metal silicide on the active area, the inability of a contact hole CT subsequently formed on the active area to be connected to the metal silicide, a high RC delay of the formed contact hole CT, high power consumption of the high-voltage device, or even failure to work normally. Therefore, it is urgent to improve or reduce the bird's beak problem of high-voltage devices.

[0043] Based on this, the present invention provides a method for manufacturing a high-voltage device. After the sacrificial oxide layer (SACoxide) in the high-voltage area is removed, a blocking sidewall is formed on the sidewall of the STI structure. In the process of forming a high-voltage gate oxide layer (HVGOX) of the high-voltage device in the high-voltage area by thermal oxidation, the blocking sidewall formed on the sidewall of the STI structure is used to block oxygen molecules from lateral diffusion through the STI structure, thereby alleviating surface oxidation adjacent to the active area, thereby achieving the purpose of improving the bird's beak effect.

[0044] The technical solution proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0045] Please refer to Figure 2 An embodiment of the present invention provides a method for manufacturing a high voltage device, which comprises the following steps:

[0046] S1, providing a substrate having a patterned hard mask layer formed on the surface, wherein the patterned hard mask layer exposes a surface of a high voltage region of the substrate and a surface of a device isolation structure portion around the high voltage region;

[0047] S2, under the mask of the patterned hard mask layer, consuming a portion of the substrate in the high voltage region by thermal oxidation to form a sacrificial oxide layer;

[0048] S3, removing the sacrificial oxide layer by wet etching, and etching open a side of the top of the device isolation structure close to the high voltage region, so that the top of the base of the high voltage region becomes lower and the top of the device isolation structure becomes thinner in the lateral direction;

[0049] S4, forming a blocking spacer, wherein the blocking spacer at least covers a side wall on a side of the top of the device isolation structure close to the high voltage region;

[0050] S5, forming a high voltage gate oxide layer on the surface of the high voltage region by thermal oxidation under the masking of the patterned hard mask layer and the blocking spacer.

[0051] In step S1, refer to Figure 3 The provided substrate (SUB) 100 may be any suitable semiconductor substrate material, such as pure silicon, silicon germanium (SiGe), silicon carbide (SiC) or silicon on insulator (SOI), etc., and a patterned hard mask layer 102 is further formed on the surface of the substrate 100, and a device isolation structure is formed in the substrate 100. The specific steps include:

[0052] (1) Please refer to Figure 3A pad oxide layer (PAD OX) 101 is formed on the substrate 100 by any suitable process such as thermal oxidation, atomic layer deposition or plasma enhanced chemical vapor deposition. The pad oxide layer 101 provides a buffer for the subsequently formed patterned hard mask layer 102 and can also serve as a stop layer in the subsequent step of removing the hard mask layer.

[0053] (2) Please refer to Figure 3 , firstly, the substrate 100 is etched to form a shallow trench (not shown) by photolithography and etching processes, and a linear oxide layer (not shown) is formed on the inner surface of the shallow trench by thermal oxidation, atomic layer deposition or plasma enhanced chemical vapor deposition, and then an insulating dielectric material is deposited by chemical vapor deposition to fill the shallow trench, and further by chemical mechanical polishing or wet etching process, the excess insulating dielectric material is removed, thereby forming a shallow trench isolation structure STI filled in the shallow trench and serving as a device isolation structure, and defining a high voltage area AA (i.e., an active area of ​​a high voltage device) in the substrate 100. As an example, multiple high voltage areas AA can be defined in the substrate, such as an NMOS high voltage area and a PMOS high voltage area.

[0054] (3) Please refer to Figure 3 , silicon nitride or silicon oxynitride and other materials are deposited on the pad oxide layer 101 and the shallow trench isolation structure STI to form a hard mask layer, and the hard mask layer is further etched through photolithography and etching processes to form a patterned hard mask layer 102, which not only exposes the surface of the substrate 100 of the high-voltage area AA, but also exposes a portion of the top of the shallow trench isolation structure STI adjacent to the high-voltage area AA.

[0055] (4) Please refer to Figure 4 , under the mask of the patterned hard mask layer 102 , the pad oxide 101 layer on the high voltage area AA is wet removed to expose the surface of the substrate 100 in the high voltage area.

[0056] In addition, before forming the device isolation structure or after forming the patterned hard mask layer 102, P-type ions such as boron can be further implanted in the corresponding area of ​​the substrate 100 to form a P-well region (not shown), and N-type ions such as arsenic or phosphorus can be implanted to form an N-well region (not shown).

[0057] In step S2, please refer to Figure 5, thermal oxidation is performed under the mask of the patterned hard mask layer 101. The thermal oxidation can be achieved by a furnace tube oxidation process. In the thermal oxidation process, since the surface of the substrate 101 in the high-voltage area AA is exposed, the oxygen molecules directly contact and react with the substrate 100 in this area and consume the substrate 100 downward to form a sacrificial oxide layer 103 of the required thickness. Moreover, the performance of the shallow trench isolation structure STI is relatively good at this time, and the oxygen molecules are not easy to pass through the shallow trench isolation structure STI and reach the adjacent active area.

[0058] In step S3, please refer to Figure 6 HF acid solution, SPM (H 2 SO4、H 2 O 2 , H 2 O mixture) or SC1 (NH 4 OH, H 2 O 2 , H 2 The sacrificial oxide layer 103 is wet-etched and removed by any suitable etching solution such as a mixture of 2,4-dimethylformamide (DMSO) and 2,4-dimethylformamide (DMSO) and 2,4-dimethylformamide (DMSO) and 2,4-dimethylformamide (DMSO) ions. In this process, since the etching selectivity ratio of the shallow trench isolation structure STI to the sacrificial oxide layer 103 is not high, the etching solution will also etch the top and sidewall of the shallow trench isolation structure STI exposed by the patterned hard mask layer 103. After removing the sacrificial oxide layer 103, the top of the substrate 100 of the high voltage region AA is lowered to the required height. At this time, the top of the shallow trench isolation structure STI close to the side of the high voltage region AA is etched open, so that the top of the shallow trench isolation structure STI is thinned in the lateral direction, and the top of the region where the shallow trench isolation structure STI is etched open is lowered, which can be equal to or lower than the top of the substrate 100 of the high voltage region AA exposed again after removing the sacrificial oxide layer 103, thereby expanding the process window for forming the high voltage gate oxide layer, and meeting the requirements of the minimum spacing between the gate and the source contact plug of the high voltage device, etc., which is conducive to the subsequent self-aligned formation of the high voltage gate oxide layer and avoids affecting the reliability of the device.

[0059] In this embodiment, the top of the shallow trench isolation structure STI on one side close to the high voltage area AA is lower than the top of the substrate 100 of the re-exposed high voltage area AA, thereby forming a groove 103a of a certain depth, that is, the top of the area where the shallow trench isolation structure STI is etched open and the top of the substrate 100 of the re-exposed high voltage area AA form a step due to the height difference.

[0060] In step S4, please refer to Figure 7First, a stress buffer layer 104 is formed by any suitable process such as atomic layer deposition, plasma enhanced chemical vapor deposition, or thermal oxidation (for example, in-situ steam oxidation). When the stress buffer layer 104 is deposited by a deposition process, the stress buffer layer 104 will cover the patterned hard mask layer 102, the exposed surface of the shallow trench isolation structure STI, and the exposed surface of the substrate 100. The stress buffer layer 104 can be used as a protective layer for protecting the substrate 100 in the high-voltage area when a blocking sidewall is subsequently formed, or as a buffer layer for stress buffering. The material thereof can be any suitable material, such as silicon oxide. When the stress buffer layer 104 is formed by a thermal oxidation process, the stress buffer layer 104 only covers the exposed surface of the substrate 100 (see Fig.11 ).

[0061] In step S4, then, refer to Figures 7 and 8 , a blocking sidewall is formed by any suitable process, which covers at least the exposed sidewall of the shallow trench isolation structure STI (that is, covers the sidewall of the substrate 100 on one side of the groove 103a away from the high voltage area AA) and exposes the top of the substrate 100 in the high voltage area AA.

[0062] As an example, the step of forming a blocking spacer on the exposed sidewall of the shallow trench isolation structure STI includes:

[0063] First, please refer to Figure 7 , by any suitable process such as atomic layer deposition or plasma enhanced chemical vapor deposition, on the stress buffer layer 104 and the surface of the patterned hard mask layer 102 and the shallow trench isolation structure STI exposed by the stress buffer layer 104, any suitable film layer such as silicon nitride or silicon oxynitride is deposited to form a barrier layer 105. In this process, the stress buffer layer 104 can buffer the stress caused to the substrate 100 in the high voltage area AA during the formation of the barrier layer 105;

[0064] Next, please refer to Figure 8, by etching the barrier layer 105 through any suitable dry etching process such as plasma etching, the barrier layer 105 on the surface of the substrate 100 in the high voltage region AA can be removed, and the barrier layer 105 on the side wall of the shallow trench isolation structure STI adjacent to the high voltage region AA (i.e., the side wall of the STI exposed by the groove 103a) and the barrier layer 105 on the top of the patterned hard mask layer 102 can be retained, or the barrier layer 105 on the substrate 100 in the high voltage region AA and the patterned hard mask layer 102 can be removed, and the barrier layer 105 on the side wall of the shallow trench isolation structure STI adjacent to the high voltage region AA can be retained, so that the remaining barrier layer 105 on the exposed side wall of the shallow trench isolation structure STI forms a barrier sidewall. In this process, the stress buffer layer 104 can be used as a protective layer to prevent the substrate 100 from being damaged in the process of etching the barrier layer 105 to form a barrier sidewall.

[0065] As another example, consider combining Figure 8 , by ion doping or any suitable surface modification method, the sidewall of the top of the shallow trench isolation structure STI close to the high voltage area AA with a corresponding thickness is converted into a blocking sidewall. In the ion doping or surface modification process, the stress buffer layer 104 acts as a protective layer to prevent the substrate surface of the high voltage area AA from being adversely affected.

[0066] Optionally, the ions used in the ion doping method may include ions that can react with oxygen and consume oxygen. These ions in the blocking sidewall formed by the ion doping can react with laterally diffused oxygen molecules during the subsequent thermal oxidation process when the high-voltage gate oxide layer is formed, thereby inhibiting the lateral diffusion of oxygen molecules during the thermal oxidation process when the high-voltage gate oxide layer is formed, and preventing the oxygen molecules from passing through the top of the shallow trench isolation structure STI and reacting with the active area on the other side of the top of the shallow trench isolation structure STI to form a bird's beak structure.

[0067] Optionally, the ions used in the ion doping method may also include ions that can improve the density of the exposed top side walls of the shallow trench isolation structure STI. The blocking side walls formed by the ion doping can directly block the oxygen molecules that diffuse laterally from passing through during the thermal oxidation process when the high-voltage gate oxide layer is subsequently formed, thereby inhibiting the lateral diffusion of oxygen molecules during the thermal oxidation process when the high-voltage gate oxide layer is subsequently formed, and preventing the oxygen molecules from passing through the top of the shallow trench isolation structure STI and reacting with the active area on the other side of the top of the shallow trench isolation structure STI to form a bird's beak structure.

[0068] As an example, the ion doping method uses ions including at least one of oxygen, nitrogen, and carbon.

[0069] Optionally, the surface modification method includes plasma nitridation or annealing in a nitrogen atmosphere, thereby converting the sidewall of the corresponding thickness of the top of the shallow trench isolation structure STI close to the high-voltage area AA into a denser film layer such as silicon nitride or silicon nitride oxide to serve as a blocking sidewall. The blocking sidewall can block the lateral diffusion of oxygen molecules during the subsequent thermal oxidation process when the high-voltage gate oxide layer is formed, making it difficult for the oxygen molecules to pass through the top of the shallow trench isolation structure STI and react with the active area on the other side of the top of the shallow trench isolation structure STI to form a bird's beak structure.

[0070] In step S4, please refer to Figure 8 After forming the blocking spacer, the stress buffer layer 104 on the high voltage area AA is wet-removed under the masking of the patterned hard mask layer 102 and the blocking spacer to re-expose the surface of the substrate 100 in the high voltage area AA.

[0071] In step S5, please refer to Fig. 9 According to the thickness requirement of the high-voltage gate oxide layer of the high-voltage device, a corresponding thermal oxidation process recipe (gate oxide recipe) is set, and the surface of the exposed substrate 100 is thermally oxidized according to the process recipe, and then the high-voltage gate oxide layer HVGOX of the high-voltage region is self-alignedly grown, and the thickness of the high-voltage gate oxide layer HVGOX can meet the requirements of high-voltage device manufacturing. Further, the thickness of the high-voltage gate oxide layer HVGOX is also sufficient to restore the surface flatness between the top surface of the high-voltage region AA relative to its surrounding area. It should be understood that during the thermal oxidation process, the blocking sidewall on the top sidewall of the STI can block the lateral diffusion of oxygen molecules, thereby avoiding the formation of a bird's beak structure.

[0072] Optionally, refer to Fig.10 When the materials of the patterned hard mask layer 102 and the blocking sidewall on the top sidewall of STI are the same or similar, after the high-voltage gate oxide layer HVGOX is formed, the patterned hard mask layer 102 and the blocking sidewall are further removed together through a wet etching process; when the materials of the patterned hard mask layer 102 and the blocking sidewall on the top sidewall of STI are different, after the high-voltage gate oxide layer HVGOX is formed, different wet etching processes are further used to successively remove the blocking sidewall and the patterned hard mask layer 102 to prepare for subsequent processes.

[0073] In another embodiment of the present invention, please refer to Figure 6 and Fig.11In (B), in order to maximize the isolation effect of STI, after step S3 and before executing step S4, that is, after the sacrificial oxide layer is removed by wet etching and the top side of the STI is etched open to form the groove 103a, and before the stress buffer layer 104 is formed, the STI at the groove 103a can be etched to deepen the groove 103a of the STI or deepen and enlarge it to become a groove 103b.

[0074] Therefore, in this embodiment, the specific execution process from removing the sacrificial oxide layer to forming the blocking sidewall includes:

[0075] First, please refer to Figure 6 and Fig.11 In (A), after the above-mentioned step S3 is executed, the STI at the groove 103a is wet-etched again using an etchant with a relatively small etching ratio for the substrate and the oxide, or the STI at the groove 103a is dry-etched using a suitable dry etching process. Optionally, the etching process for forming the groove 103b can simultaneously round the top corners of the substrate 100 in the high-voltage area AA.

[0076] Next, please refer to Fig.11 In (B), the process of forming the stress buffer layer 104 in the above step S4 is performed. Exemplarily, the exposed surface layer of the substrate 100 is thermally oxidized by a thermal oxidation process such as in-situ steam oxidation to form the stress buffer layer 104.

[0077] Then, please refer to Fig.11 In (C), the barrier layer 105 formation process in the above step S4 is performed. Exemplarily, the barrier layer 105 is deposited on the surface of the stress buffer layer 104 and the exposed patterned hard mask layer 102 and the shallow trench isolation structure STI through a plasma enhanced chemical vapor deposition process. The deposited barrier layer 105 can fill the groove 103b on the top of the STI.

[0078] Then, please refer to Fig.11In (D), the barrier layer 105 is etched by any suitable dry etching process such as plasma etching to remove the barrier layer 105 on the surface of the substrate 100 in the high-voltage area AA and on the top of the patterned mask layer 102, and the barrier layer is retained on the sidewalls of the groove 103b (including the sidewalls of the shallow trench isolation structure STI and the sidewalls of the patterned mask layer 102) and on the bottom of the groove 103b, thereby forming the required barrier sidewall. In this etching process, by controlling the etching process conditions, etc., after the etching is completed, the barrier layer 105 remaining in the groove 103b can have a certain thickness that fully covers the bottom surface of the groove 103b, and the thickness can even fill the groove 103b. That is, after the etching is completed, the top of the barrier layer 105 remaining in the groove 103b is lower than or flush with the top of the substrate 100 in the high-voltage area AA. Therefore, the barrier layer 105 remaining in the groove 103b can be used as a part of the STI, so as to ensure a good isolation effect of the STI.

[0079] Afterwards, please refer to Fig.11 In (D), after forming the blocking sidewall, the wet etching process of the stress buffer layer 104 in the above-mentioned step S4 can be performed, that is, under the masking of the patterned hard mask layer 102 and the blocking sidewall, the stress buffer layer 104 on the high voltage area AA is wet-removed to re-expose the surface of the substrate 100 of the high voltage area AA, so as to prepare for the subsequent thermal oxidation process of step S5 to form the high voltage gate oxide layer HVGOX.

[0080] As an example, after the stress buffer layer 104 on the high-voltage region AA is removed by wet method, a groove 103c is still retained on the top side of the STI. On the one hand, in the horizontal direction, the isolation film layer at the groove 103c is the remaining stress buffer layer 104, the barrier layer 105 and the STI, which is equivalent to adding the barrier layer 105 and the stress buffer layer 104 film layer to the original STI structure. Since the isolation performance of the barrier layer 105 is better than the isolation performance of the original material of the STI, the isolation performance of the STI can be greatly improved, avoiding the problem of oxygen molecules diffusing laterally and passing through the STI to the active area on the other side to form a bird's beak in the process of forming the high-voltage gate oxide layer. On the other hand, in the vertical direction, controlling the depth of the groove 103c can control the height difference between it and the top surface of the substrate of the high-voltage region, thereby ensuring that the high-voltage gate oxide layer HVGOX can be formed in a self-aligned manner.

[0081] It should be understood that the above embodiments are described using the shallow trench isolation structure STI as an example, but the technical solution of the present invention is not limited to this. In other embodiments of the present invention, a local field oxygen isolation structure can also be used to replace the shallow trench isolation structure STI as a device isolation structure.

[0082] In summary, the manufacturing method of the high-voltage device of the present invention first forms a sacrificial oxide layer by thermal oxidation and then removes the sacrificial oxide layer, on the one hand, reduces the surface height of the substrate, and on the other hand, makes the device isolation structure around the high-voltage area thinner in the lateral direction, so as to ensure that the subsequently formed high-voltage gate oxide layer can be self-aligned and formed on the substrate surface of the high-voltage area defined by the device isolation structure; and after removing the sacrificial oxide layer and etching and opening the side of the device isolation structure close to the high-voltage area, a blocking sidewall is formed to at least cover the sidewall of the device isolation structure and expose the top surface of the substrate of the high-voltage area, so that in the process of thermal oxidation to form the high-voltage gate oxide layer required for the high-voltage area, the blocking sidewall can be used to block oxygen molecules from passing through the top of the thinned device isolation structure and laterally diffusing into the adjacent active area, thereby achieving the purpose of improving the bird's beak. The technical solution of the present invention is suitable for small-sized products, and can ensure that the device isolation structure that must be lost is sufficient to meet the alignment requirements in the process of manufacturing its high-voltage gate oxide layer, and can avoid the problem of loose device isolation structure being penetrated by oxygen to form a bird's beak, and can also ensure that there is no adverse effect on the formation of the high-voltage gate oxide layer.

[0083] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for manufacturing a high voltage device, It is characterized in that The following steps are involved: Providing a substrate having a patterned hard mask layer formed on the surface, wherein the patterned hard mask layer exposes a surface of a high voltage region of the substrate and a surface of a device isolation structure portion around the high voltage region; Under the mask of the patterned hard mask layer, a portion of the substrate in the high voltage region is consumed by thermal oxidation to form a sacrificial oxide layer; Removing the sacrificial oxide layer by wet etching, and etching open a side of the top of the device isolation structure close to the high voltage region, so that the top of the base of the high voltage region becomes lower and the top of the device isolation structure becomes thinner in the lateral direction; Forming a blocking sidewall, wherein the blocking sidewall at least covers a sidewall on a side of the top of the device isolation structure close to the high voltage region and exposes a top surface of the substrate of the high voltage region; Under the masking of the patterned hard mask layer and the blocking spacer, a high voltage gate oxide layer is formed on the surface of the high voltage region by thermal oxidation.

2. The manufacturing method according to claim 1, It is characterized in that The step of providing a substrate having a patterned hard mask layer formed on the surface thereof comprises: forming a pad oxide layer on the substrate and forming the device isolation structure in the substrate to define the high voltage region in the substrate; Depositing a hard mask layer on the pad oxide layer and the device isolation structure, and etching the hard mask layer to form the patterned hard mask layer; Under the masking of the patterned hard mask layer, the pad oxide layer on the high voltage region is removed by a wet method to expose the substrate surface of the high voltage region.

3. The manufacturing method according to claim 1, It is characterized in that After removing the sacrificial oxide layer by wet etching and before forming the blocking spacer, a stress buffer layer is formed, wherein the stress buffer layer at least covers the surface of the substrate in the high-voltage region.

4. The manufacturing method according to claim 3, It is characterized in that After the sacrificial oxide layer is removed by wet etching, the top of the device isolation structure close to the high voltage region is etched open to form a groove; after the sacrificial oxide layer is removed by wet etching and before the stress buffer layer is formed, the device isolation structure in the groove is also etched to deepen the groove; the formed blocking side wall also covers the bottom of the groove, and the top surface of the blocking side wall on the bottom of the groove is lower than or flush with the top surface of the substrate of the high voltage region.

5. The manufacturing method according to claim 3 or 4, It is characterized in that The steps of forming the blocking sidewalls include: Covering the stress buffer layer at least on the surface of the substrate exposed in the high-voltage region; Depositing a barrier layer on the stress buffer layer and the exposed surfaces of the device isolation structure and the patterned hard mask layer; The barrier layer on the substrate surface of the high voltage region is removed by dry etching, and at least the barrier layer on the sidewall of the top of the device isolation structure close to the high voltage region is retained to form the barrier sidewall.

6. The manufacturing method according to claim 3, It is characterized in that The step of forming the blocking sidewall includes: converting the sidewall of a corresponding thickness on the top of the device isolation structure close to the high voltage region into the blocking sidewall through ion doping or surface modification.

7. The manufacturing method according to claim 6, It is characterized in that The ions used in the ion doping method include at least one of oxygen, nitrogen and carbon, and the surface modification treatment includes plasma nitridation or annealing in a nitrogen atmosphere.

8. The manufacturing method according to claim 3, 4 or 6, It is characterized in that After forming the blocking spacer and before forming the high voltage gate oxide layer by thermal oxidation, the stress buffer layer on the high voltage region is wet-removed under the masking of the patterned hard mask layer and the blocking spacer to re-expose the substrate surface of the high voltage region.

9. The manufacturing method according to claim 3, 4 or 6, It is characterized in that The stress buffer layer includes a silicon oxide layer, and the barrier layer includes a silicon nitride layer or a silicon nitride oxide layer.

10. The manufacturing method according to any one of claims 1 to 4 or 6 to 9, It is characterized in that After forming the high-voltage gate oxide layer, the method further includes: removing the patterned hard mask layer and the blocking sidewalls together or separately by wet etching.

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