Low resistance source / drain feature

Abstract

Methods of forming low resistance source / drain features for a multi-gate device are provided. An example method includes forming a fin-shaped structure including a plurality of channel layers interleaved with a plurality of sacrificial layers; a source / drain region of the fin-shaped structure is recessed to form a source / drain recess; selectively and partially recessing sidewalls of the plurality of sacrificial layers to form internal spacer recesses; forming an inner spacer in the inner spacer recess; forming a bottom dielectric layer over the substrate; depositing a first epitaxial layer over the inner spacers and sidewalls of the plurality of channel layers; performing a heat treatment to reshape the first epitaxial layer; after performing the thermal treatment, a second epitaxial layer is deposited over the first epitaxial layer. The first epitaxial layer includes germanium, and the second epitaxial layer is free of germanium.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing, and more particularly to low resistance source / drain features. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous generation. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per unit chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down has also increased the complexity of processing and manufacturing ICs.

[0003] For example, as integrated circuit (IC) technology moves toward smaller technology nodes, multi-gate metal oxide semiconductor field effect transistors (multi-gate MOSFETs or multi-gate devices) have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short channel effects. A multi-gate device generally refers to a device having a gate structure or portion thereof disposed on more than one side of a channel region. Gate all around (GAA) transistors are examples of multi-gate devices that have become popular and promising candidates for high performance and low leakage applications. GAA transistors have a gate structure that can extend partially or completely around the channel region to provide access to the channel region on two or more sides. Since the gate structure of the GAA transistor surrounds the channel region, the GAA transistor may also be referred to as a surround gate transistor (SGT) or a multi-bridge channel (MBC) transistor.

[0004] To improve the performance of GAA transistors, efforts are being made to develop epitaxial features that reduce leakage, capacitance, and resistance. Summary of the invention

[0005] In one aspect, an embodiment of the present application provides a method comprising: forming a fin-shaped structure above a substrate, the fin-shaped structure comprising multiple channel layers interlaced with multiple sacrificial layers; recessing the source / drain region of the fin-shaped structure to form a source / drain recess, the source / drain recess exposing a portion of the substrate and the sidewalls of the multiple channel layers; selectively and partially recessing the sidewalls of the multiple sacrificial layers to form an internal spacer recess; forming an internal spacer in the internal spacer recess; forming a bottom dielectric layer to cover the exposed portion of the substrate; depositing a first epitaxial layer over the exposed sidewalls of the internal spacer and the multiple channel layers; performing a thermal treatment to reshape the first epitaxial layer; after performing the thermal treatment, depositing a second epitaxial layer over the first epitaxial layer, wherein the first epitaxial layer comprises germanium, and wherein the second epitaxial layer does not contain germanium.

[0006] In another aspect, a method is provided, comprising: forming a fin structure over a substrate, the fin structure comprising a plurality of channel layers interlaced with a plurality of sacrificial layers; recessing a source / drain region of the fin structure to form a source / drain recess exposing a portion of the substrate and sidewalls of the plurality of channel layers; selectively and partially recessing the sidewalls of the plurality of sacrificial layers to form an internal spacer recess; forming an internal spacer in the internal spacer recess; forming a bottom epitaxial layer to cover the exposed portion of the substrate; depositing a first epitaxial layer over the exposed sidewalls of the internal spacer and the plurality of channel layers; performing a thermal treatment to reshape the first epitaxial layer; and depositing a second epitaxial layer over the first epitaxial layer after performing the thermal treatment, wherein the first epitaxial layer comprises germanium, and wherein the second epitaxial layer does not contain germanium.

[0007] In yet another aspect, a semiconductor structure is provided, comprising: a base fin protruding from a substrate; a first plurality of nanostructures disposed over a first channel region of the base fin; a second plurality of nanostructures disposed over a second channel region of the base fin; and a source / drain feature disposed between and in contact with the first plurality of nanostructures and the second plurality of nanostructures, wherein the source / drain feature comprises: a bottom epitaxial layer extending into the base fin, a first epitaxial layer in direct contact with the first plurality of nanostructures, the second plurality of nanostructures and the bottom epitaxial layer, a second epitaxial layer disposed over the first epitaxial layer, and a third epitaxial layer disposed over the second epitaxial layer, wherein the first epitaxial layer and the third epitaxial layer do not contain germanium, and wherein the second epitaxial layer comprises germanium. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure may be best understood by the following specific implementations when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with standard practice in the industry, various features are not drawn to scale and are only used for illustrative purposes. In fact, the size of various features may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1 A flow chart of a method for forming a semiconductor device according to one or more aspects of the present disclosure is shown.

[0010] Figure 2-14 According to one or more aspects of the present disclosure, Figure 1 A partial cross-sectional view of a work-in-progress (WIP) structure during a manufacturing process of the method.

[0011] Fig.15 Schematically illustrates the use of one or more aspects of the present disclosure Figure 1 Different trench bottom profiles of multi-gate transistors fabricated by the method.

[0012] Fig.16 Schematically illustrates the use of one or more aspects of the present disclosure Figure 1 The method of manufacturing a multi-gate transistor has different end face profiles of the channel component.

[0013] Fig.17 A flow chart of a method for forming source / drain features of a multi-gate transistor according to one or more aspects of the present disclosure is shown.

[0014] Figure 18-21 According to one or more aspects of the present disclosure, Fig.17 A partial cross-sectional view of a WIP structure during a manufacturing process of the method.

[0015] Fig. 22 A flow chart of a method for forming source / drain features of a multi-gate transistor according to one or more aspects of the present disclosure is shown.

[0016] Figure 23-31 According to one or more aspects of the present disclosure, Fig. 22 A partial cross-sectional view of a WIP structure during a manufacturing process of the method.

[0017] Fig.32 A flow chart of a method for forming source / drain features of a multi-gate transistor according to one or more aspects of the present disclosure is shown.

[0018] Figure 33-36 According to one or more aspects of the present disclosure, Fig.32 A partial cross-sectional view of a WIP structure during a manufacturing process of the method.

[0019] Fig.37 A flow chart of a method for forming source / drain features of a multi-gate transistor according to one or more aspects of the present disclosure is shown.

[0020] Figure 38-46 According to one or more aspects of the present disclosure, Fig.37 A partial cross-sectional view of a WIP structure during a manufacturing process of the method.

[0021] Fig.47 A flow chart of a method for forming source / drain features of a multi-gate transistor according to one or more aspects of the present disclosure is shown.

[0022] Figure 48-51 According to one or more aspects of the present disclosure, Fig.47 A partial cross-sectional view of a WIP structure during a manufacturing process of the method.

[0023] Fig.52 A flow chart of a method for forming source / drain features of a multi-gate transistor according to one or more aspects of the present disclosure is shown.

[0024] Figure 53-61 According to one or more aspects of the present disclosure, Fig.52 A partial cross-sectional view of a WIP structure during a manufacturing process of the method. DETAILED DESCRIPTION

[0025] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of brevity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0026] Additionally, spatially relative terms (e.g., "below," "beneath," "lower," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature shown in a figure relative to another element(s) or feature(s). Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0027] In addition, when a number or a range of numbers is described using "about," "approximately," etc., the term is intended to encompass numbers within a reasonable range that takes into account variations that inherently occur during manufacturing as understood by those of ordinary skill in the art. For example, a number or range of numbers encompasses a reasonable range that includes the stated number (based on known manufacturing tolerances associated with manufacturing features having the property associated with the number, e.g., within + / - 10% of the stated number). For example, a material layer having a thickness of "about 5 nm" may include a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with depositing the material layer is + / - 15% known to those of ordinary skill in the art.

[0028] The present disclosure generally relates to multi-gate transistors and manufacturing methods, and more specifically, to source / drain features of GAA transistors. The channel region of the GAA transistor can be arranged in a nanowire channel member, a strip channel member, a nanosheet channel member, a nanostructure channel member, a column-shaped channel member, a post-shaped channel member, and / or other suitable channel configurations. Depending on the shape of the channel member, the GAA transistor may also be referred to as a nanowire transistor or a nanosheet transistor. Regardless of the shape, each channel member of the GAA transistor extends between and couples to two source / drain features. In some prior arts, the source / drain feature is epitaxially grown from the end face of the semiconductor layer to be manufactured into the channel member. Due to the faceted growth of the source / drain material, during the deposition of the source / drain feature, when the source / source material is prematurely merged on the unfilled space in the source / drain recess, a void may be formed. The presence of the void reduces the volume of the doped source / drain material, resulting in an increase in resistance. Furthermore, in the subsequent process of forming source / drain contacts, the voids may result in overly large / deep source / drain contact openings, leading to increased contact resistance or even electrical connection failure.

[0029] The present disclosure provides a method for forming a void-free source / drain feature. Specifically, the present disclosure provides a method for forming a void-free n-type source / drain feature. The n-type source / drain feature formed using the method of the present disclosure includes at least one germanium-containing epitaxial layer. In some existing implementations, germanium is only present in the p-type source / drain feature, and the n-type source / drain feature does not contain germanium. The method of the present disclosure heat treats at least one germanium-containing epitaxial layer to reshape it into a smooth profile that is not conducive to the formation of voids. The germanium content in at least one germanium-containing epitaxial layer allows the heat treatment to have a lower temperature range. In addition, the germanium content in at least one germanium-containing epitaxial layer allows it to be reshaped to have a smooth surface, rather than a faceted shape. The void-free source / drain feature of the present disclosure can produce reduced resistance and reduced contact resistance with the source / drain contact.

[0030] Various aspects of the present disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 1 is a flow chart illustrating a method 100 of forming a semiconductor structure from a work-in-progress (WIP) structure according to an embodiment of the present disclosure. The semiconductor structure includes source / drain features, and Fig.17 , Fig. 22 , Fig.32 , Fig.37 , Fig.47 and Fig.52 Flowcharts showing methods 300, 350, 400, 450, 500, and 550 of forming source / drain features for semiconductor structures. Methods 100, 300, 350, 400, 450, 500, and 550 are merely examples and are not intended to limit the present disclosure to what is explicitly shown in methods 100, 300, 350, 400, 450, 500, and 550. Additional steps may be provided before, during, and after methods 100, 300, 350, 400, 450, 500, or 550, and some of the steps described may be replaced, eliminated, or moved around for additional embodiments of the methods. For reasons of simplicity, not all steps are described in detail. Figure 2-14 Describing method 100, Figure 2-14 is based on Figure 1 The WIP structure of the embodiment of the method 100 in FIG. 1 is a partial cross-sectional view at different manufacturing stages. Figure 18-21 Describing method 300, Figure 18-21 is based on Fig.17 The WIP structure of the embodiment of the method 300 in FIG. 3 is a partial cross-sectional view at different manufacturing stages. Figure 23-31 Describing method 350, Figure 23-31 is based on Fig. 22 The WIP structure of the embodiment of the method 350 in FIG. 3 is a partial cross-sectional view at different manufacturing stages. Figure 33-36 Describing method 400, Figure 33-36 is based on Fig.32 The WIP structure of the embodiment of the method 400 in FIG. 4 is a partial cross-sectional view at different manufacturing stages. Figure 38-46 Describing method 450, Figure 38-46 is based on Fig.37 The WIP structure of the embodiment of the method 450 in FIG. 4 is a partial cross-sectional view at different manufacturing stages. Figure 48-51 Describing method 500, Figure 48-51 is based on Fig.47 The WIP structure of the embodiment of the method 500 in FIG. 5 is a partial cross-sectional view at different manufacturing stages. Figure 53-61 describing method 550, Figure 53-61 is based on Fig.525. A partial cross-sectional view of a WIP structure of an embodiment of method 550 in different manufacturing stages. Since the WIP structure 200 will be manufactured into a semiconductor structure or a semiconductor device, the WIP structure 200 may be referred to herein as a semiconductor structure or a semiconductor device 200 as the context requires. For illustration, Figure 2-14 , Figure 18-21 , Figure 23-31 , Figure 33-36 , Figure 38-46 , Figure 48-51 and Figure 53-61 The X, Y, and Z directions are mutually perpendicular. Throughout this disclosure, unless otherwise explicitly described, the same reference numerals represent the same features or steps. That is, the material properties of various numbered elements described in association with a method or a figure and their comparisons should apply to the same numbered elements described in association with different methods or different figures.

[0031] refer to Figure 1 and Figure 2 , the method 100 includes block 102, where a stack 204 of alternating semiconductor layers is formed over the WIP structure 200. Figure 2 As shown, the WIP structure 200 includes a substrate 202. In some embodiments, the substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. According to design requirements known in the art, the substrate 202 may include various doping configurations. In an embodiment where the semiconductor device is p-type, an n-type doping configuration (i.e., an n-type well or n-well) may be formed on the substrate 202. In some implementations, the n-type dopant for forming the n-type well may include phosphorus (P), arsenic (As), or antimony (Sb). In an embodiment where the semiconductor device is n-type, a p-type doping configuration (i.e., a p-type well or p-well) may be formed on the substrate 202. In some implementations, the p-type dopant for forming the p-type well may include boron (B) or gallium (Ga). Suitable doping may include ion implantation and / or diffusion processes of dopants. The substrate 202 may also include other semiconductors, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), germanium tin (GeSn), or diamond. Alternatively, the substrate 202 may include a compound semiconductor and / or an alloy semiconductor. Additionally, the substrate 202 may optionally include an epitaxial layer (epi layer), may be strained for performance enhancement, may include a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) structure, and / or may have other suitable enhancement features.

[0032] In some embodiments, the stack 204 on the substrate 202 includes channel layers 208 of a first semiconductor composition interleaved with sacrificial layers 206 of a second semiconductor composition. It can also be said that the sacrificial layers 206 are interleaved with the channel layers 208. The first semiconductor composition and the second semiconductor composition can be different. In some embodiments, the sacrificial layers 206 include silicon germanium (SiGe) or germanium tin (GeSn), and the channel layers 208 include silicon (Si). It is noted that, as Figure 2 As shown, four (4) layers of sacrificial layer 206 and three (3) layers of channel layer 208 are arranged alternately, which is for illustration purposes only and is not intended to limit the specific contents recited in the claims. It can be appreciated that any number of epitaxial layers can be formed in stack 204. The number of layers depends on the desired number of channel components of semiconductor device 200. In some embodiments, the number of channel layers 208 is between 2 and 10. Figure 2 In the illustrated embodiment, the stack 204 includes a bottommost sacrificial layer 206 and a topmost sacrificial layer 206. In an embodiment, the topmost sacrificial layer 206 is used to protect the topmost channel layer and may be completely consumed in subsequent processes.

[0033] The sacrificial layer 206 and the channel layer 208 in the stack 204 can be deposited using a molecular beam epitaxy (MBE) process, a vapor phase deposition (VPE) process, and / or other suitable epitaxial growth processes. As described above, in at least some examples, the sacrificial layer 206 includes an epitaxially grown silicon germanium (SiGe) layer, and the channel layer 208 includes an epitaxially grown silicon (Si) layer. In some embodiments, the sacrificial layer 206 and the channel layer 208 are substantially free of dopants (i.e., have a dopant concentration of from about 0 atoms / cm 3 To about 1×10 17 Atom / cm 3 extrinsic dopant concentration), wherein, for example, no intentional doping is performed during the epitaxial growth process of the stack 204.

[0034] refer to Figure 1 , Figure 2 and Figure 3 The method 100 includes a block 104 in which a fin structure 212 is formed from the stack 204 and the substrate 202. To pattern the stack 204, a hard mask layer 210 (eg, Figure 2) to form an etching mask. The hard mask layer 210 may be a single layer or a multilayer. For example, the hard mask layer 210 may include a pad oxide layer and a pad nitride layer disposed on the pad oxide layer. The fin structure 212 may be patterned from the stack 204 and the substrate 202 using a photolithography process and an etching process. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. As Figure 3 As shown, the etching process at box 104 forms a trench extending in a vertical direction through the stack 204 and a portion of the substrate 202. The trench defines a fin structure 212. In some implementations, a double patterning or multiple patterning process can be used to define the fin structure, for example, a pitch of the fin structure is smaller than a pitch that is otherwise obtainable using a single direct lithography process. For example, in one embodiment, a material layer is formed above a substrate and the material layer is patterned using a photolithography process. Spacers are formed along the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fin structure 212 by etching a portion of the stack 204 and the substrate 202. As shown in FIG. Figure 3 As shown, the fin structure 212 including the sacrificial layer 206 and the channel layer 208 extends vertically along the Z direction and longitudinally along the X direction. Figure 3 As shown, the fin structure 212 includes a base fin structure 212B patterned from the substrate 202. The patterned stack 204 including the sacrificial layer 206 and the channel layer 208 is disposed directly above the base fin structure 212B.

[0035] An isolation feature 214 is formed adjacent to the fin structure 212. Figure 3In some of the illustrated embodiments, the isolation feature 214 is disposed on the sidewall of the base fin structure 212B. In some embodiments, the isolation feature 214 may be formed in a trench to isolate the fin structure 212 from an adjacent fin structure. The isolation feature 214 may also be referred to as a shallow trench isolation (STI) feature 214. For example, in some embodiments, a dielectric layer is first deposited over the substrate 202 to fill the trench with the dielectric layer. In some embodiments, the dielectric layer may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, a combination thereof, and / or other suitable materials. In various examples, the dielectric layer may be deposited by a CVD process, a sub-atmospheric CVD (SACVD) process, a flowable CVD process, a spin coating process, and / or other suitable processes. The deposited dielectric material is then thinned and planarized, for example, by a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further recessed or pulled back by a dry etching process, a wet etching process, and / or a combination thereof to form Figure 3 The STI features 214 are shown. The fin structures 212 are taller than the STI features 214 after the recess, while the base fin structures 212B are embedded or buried in the isolation features 214.

[0036] refer to Figure 1 , Figure 4 and Figure 5 The method 100 includes a block 106, wherein a dummy gate stack 220 is formed over the channel region 212C of the fin structure 212. In some embodiments, a gate replacement process (or a gate-last process) is used, wherein the dummy gate stack 220 (eg, Figure 4 and Figure 5 ) is used as a placeholder to undergo various processes and will be removed and replaced by a functional gate structure. Other processes and configurations are also possible. Figure 5 In some embodiments shown, the dummy gate stack 220 is formed on the fin structure 212, and the fin structure 212 can be divided into a channel region 212C below the dummy gate stack 220 and a source / drain region 212SD not located below the dummy gate stack 220. The channel region 212C is adjacent to the source / drain region 212SD. Figure 5 As shown, along the X direction, the source / drain region 212SD is disposed between the two channel regions 212C.

[0037] The formation of the dummy gate stack 220 may include depositing some layers in the dummy gate stack 220 and patterning the layers. Figure 4, a dummy dielectric layer 216, a dummy electrode layer 218, and a gate top hard mask layer 222 can be uniformly deposited on the WIP structure 200. In some embodiments, the dummy dielectric layer 216 can be formed on the fin structure 212 using a chemical vapor deposition (CVD) process, an ALD process, an oxygen plasma oxidation process, or other suitable process. In some cases, the dummy dielectric layer 216 may include silicon oxide. Thereafter, a dummy electrode layer 218 can be deposited on the dummy dielectric layer 216 using a CVD process, an ALD process, or other suitable process. In some cases, the dummy electrode layer 218 can include polysilicon. For patterning purposes, a gate top hard mask layer 222 can be deposited on the dummy electrode layer 218 using a CVD process, an ALD process, or other suitable process. The gate top hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216 can then be patterned to form a dummy gate stack 220, such as Figure 5 As shown. For example, the patterning process may include a photolithography process (e.g., photolithography or electron beam lithography) and an etching process. The photolithography process may also include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. The photolithography process forms a patterned photoresist layer. The patterned photoresist layer is then applied as an etching mask in an etching process to pattern the gate top hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. In some embodiments, the gate top hard mask layer 222 may include a silicon oxide layer 223 and a silicon nitride layer 224 on the silicon oxide layer 223. As Figure 5 As shown, the dummy gate stack 220 is patterned such that it is disposed only over the channel region 212C and not over the source / drain regions 212SD.

[0038] refer to Figure 1 and Figure 6, the method 100 includes a frame 108, wherein a gate spacer layer 226 is deposited over the WIP structure 200 (including over the dummy gate stack 220). In some embodiments, the gate spacer layer 226 is conformally deposited over the WIP structure 200 (including over the top surface and sidewalls of the dummy gate stack 220). For the convenience of describing a layer having a substantially uniform thickness over various regions, the term "conformal" may be used herein. The gate spacer layer 226 may be a single layer or multiple layers. At least one layer of the gate spacer layer 226 may include silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or silicon nitride. The gate spacer layer 226 may be deposited over the dummy gate stack 220 using a process such as a CVD process, a sub-atmospheric CVD (SACVD) process, an ALD process, or other suitable process.

[0039] refer to Figure 1 and Figure 7 , method 100 includes block 110, in which the source / drain region 212SD of the fin structure 212 is anisotropically recessed to form a source / drain trench 228. The anisotropic etching may include dry etching or a suitable etching process that etches the source / drain region 212SD and a portion of the substrate 202 located below the source / drain region 212SD. The resulting source / source trench 228 extends vertically through the depth of the stack 204 and partially into the substrate 202. The exemplary dry etching process of block 110 may be implemented with an oxygen-containing gas, a fluorine-containing gas (e.g., CF 4 , SF 6 , CH 2 F 2 , CHF 3 , C 4 F 8 and / or C 2 F 6 ), chlorine-containing gases (e.g., Cl 2 , CHCl 3 , CCl 4 and / or BCl 3 ), bromine-containing gases (e.g., HBr and / or CHBr 3 ), iodine-containing gas, other suitable gas and / or plasma and / or a combination thereof. Figure 7 As shown, the source / drain region 212SD of the fin structure 212 is recessed to expose the sidewalls of the sacrificial layer 206 and the channel layer 208. Since the source / drain trench 228 extends below the stack 204 and into the substrate 202, the source / source trench 228 includes a lower sidewall and a bottom surface defined in the substrate 202. Fig.15 , Fig.15Shows different bottom profiles of the source / drain trenches 228 when different combinations of etchant species are selected. In a dry etching process, SF 6 and C 4 F 8 In some implementations, when the flow rate of C 4 F 8 is greater than the flow rate of SF 6 , a large tapering bottom profile (A) can be produced. When the flow rate of SF 6 is greater than the flow rate of C 4 F 8 , a small tapering bottom profile (C) can be produced. When the dry etching is allowed to continue for a longer time, a faceted bottom profile (B) can be produced.

[0040] Referring to Figure 1 , Figure 8 and Fig. 9 , method 100 includes block 112, in which an internal spacer feature 234 is formed. Although not explicitly shown, the operations at block 112 may include: selectively and partially removing the sacrificial layer 206 to form an internal spacer recess 230 (as Figure 8 shown), depositing an internal spacer material over the WIP structure 200, and etch-backing the internal spacer material to form an internal spacer feature 234 in the internal spacer recess 230 (as Fig. 9 shown). Referring to Figure 8 , the sacrificial layer 206 exposed in the source / drain trenches 228 is selectively and partially recessed to form an internal spacer recess 230, while the gate spacer layer 226, the exposed portions of the substrate 202, and the channel layer 208 are substantially not etched. In embodiments where the channel layer 208 consists primarily of silicon (Si) and the sacrificial layer 206 consists primarily of silicon germanium (SiGe), the selective recessing of the sacrificial layer 206 can be performed using a selective wet etching process or a selective dry etching process. Exemplary selective dry etching processes may include using one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. Exemplary selective wet etching processes may include APM etching (e.g., an ammonia-hydrogen peroxide-water mixture).

[0041] After forming the internal spacer recess 230, an internal spacer material is deposited over the WIP structure 200 (including over the internal spacer recess 230). The internal spacer material can include metal oxides, silicon oxides, silicon carbonitride, silicon nitride, silicon oxynitride, carbon-rich silicon carbonitride, or low-k dielectric materials. The metal oxides can include aluminum oxide, zirconium oxide, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide, or other suitable metal oxides. Although not explicitly shown, the internal spacer material can be a single layer or multiple layers. In some implementations, CVD, PECVD, SACVD, ALD, or other suitable methods can be used to deposit the internal spacer material. The internal spacer material is deposited into the internal spacer recess 230 and on the sidewalls of the channel layer 208 that are exposed in the source / drain trenches 228. Refer to Fig. 9 , and then the deposited internal spacer material is etch-back to remove the internal spacer from the sidewalls of the channel layer 208, thereby forming internal spacer features 234 in the internal spacer recess 230. At block 112, the internal spacer material can also be removed from the top surface and / or sidewalls of the gate spacer layer 226 and the gate top hard mask layer 222. As Fig. 9 shown, each internal spacer feature 234 is in direct contact with the recessed sacrificial layer 206 and is vertically (in the Z direction) disposed between two adjacent channel layers 208.

[0042] Depending on the conditions of the etch-back process for forming the internal spacer features 234, Figure 8 the end faces of each channel layer 208 exposed in the source / drain trenches 228 as shown by the dashed lines in Fig.16 can have different cross-sectional profiles. The five (5) example cross-sectional profiles provided in

[0043] Although not explicitly shown, before forming any epitaxial layers, method 100 may include a cleaning process to clean the surface of WIP structure 200. The cleaning process may include dry cleaning, wet cleaning, or a combination thereof. In some examples, wet cleaning may include using Standard Cleaner 1 (RCA SC-1, a mixture of deionized (DI) water, ammonium hydroxide, and hydrogen peroxide), Standard Cleaner 2 (RCA SC-2, a mixture of DI water, hydrochloric acid, and hydrogen peroxide), SPM (sulfuric acid peroxide mixture), and / or hydrofluoric acid for oxide removal. The dry cleaning process may include helium (He) and hydrogen (H 2 ) treatment. Hydrogen treatment can convert silicon on the surface into silane (SiH 4 ), which can be pumped out for removal.

[0044] refer to Figure 1 and Fig.10 , method 100 includes box 114, in which a source / drain feature 240 is formed over the source / drain region 212D. In some embodiments shown in the figure, the source / drain feature 240 is an n-type source / drain feature. The source / drain feature 240 includes multiple epitaxial layers and is doped with an n-type dopant, such as phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. At least one epitaxial layer of the multiple epitaxial layers in the source / drain feature 240 includes silicon (Si) and germanium (Ge). At least one epitaxial layer of the multiple epitaxial layers in the source / drain feature 240 includes silicon (Si) and does not contain germanium (Ge). It can be used Fig.17 Method 300, Fig. 22 Method 350, Fig.32 Method 400, Fig.37 Method 450, Fig.47 Method 500 or Fig.52 The method 550 in the embodiment of the present invention is used to form the source / drain features 240. It is to be understood that when the method 300 is used, Fig.10 and the subsequent Figure 11-14 The source / drain features 240 shown in FIG. 2 may be Fig.21 source / drain features 240 in; when method 350 is used, Figure 10-14 The source / drain features 240 shown in FIG. 2 may be Fig.30 or Fig.31 source / drain features 240 in; when method 400 is used, Figure 10-14 The source / drain features 240 shown in FIG. 2 may be Fig.36 source / drain features 240 in; when method 450 is adopted, Figure 10-14 The source / drain features 240 shown in FIG. 2 may be Fig.45 or Fig.46Source / drain features 240 in; when method 500 is adopted, Figure 10-14 The source / drain features 240 shown in FIG. 2 may be Fig.51 source / drain features 240 in; and when method 550 is employed, Figure 10-14 The source / drain features 240 shown in FIG. 2 may be Fig.60 or Fig.61 The source / drain features 240 in FIG. Figure 10-14 The source / drain features 240 shown in FIG. 2 are placeholders for: Fig.21 Source / drain features 240, Fig.30 or Fig.31 Source / drain features 240, Fig.36 Source / drain features 240, Fig.45 or Fig.46 Source / drain features 240, Fig.51 Source / drain features 240 in, or Fig.60 or Fig.61 The source / drain features 240 in FIG. Figure 17-61 The operations of forming source / drain features 240 according to various embodiments of the present disclosure are described in greater detail.

[0045] refer to Figure 1 and Figure 11-12 , the method 100 includes block 116, where the dummy gate stack 220 is removed. Block 116 may include depositing a contact etch stop layer (CESL) 242 and an interlayer dielectric (ILD) layer 244 (eg, Fig.11 ), and removing the dummy gate stack 220 (as shown Fig.12 ). Fig.11, a CESL 242 is deposited over the WIP structure 200 (including over the source / drain features 240). The CESL 242 may include silicon nitride or aluminum nitride. In some implementations, the CESL 242 may be deposited using CVD or ALD. An ILD layer 244 is then deposited over the CESL 242. In some embodiments, the ILD layer 244 includes a material such as tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials. The ILD layer 244 may be deposited using CVD, FCVD, spin coating, or a suitable deposition technique. After the ILD layer 244 is deposited, the WIP structure 200 may be planarized by a planarization process to expose the dummy gate stack 220. For example, the planarization process may include a chemical mechanical planarization (CMP) process. The exposure of the dummy gate stack 220 allows for removal of the dummy gate stack 220. Fig.12 , removing the dummy gate stack 220. Removing the dummy gate stack 220 may include one or more etching processes that are selective to the material of the dummy gate stack 220. For example, the removal of the dummy gate stack 220 may be performed using a selective wet etch, a selective dry etch, or a combination thereof that is selective to the dummy gate stack 220. After removing the dummy gate stack 220, the sidewalls of the channel layer 208 and the sacrificial layer 206 in the channel region 212C are exposed.

[0046] refer to Figure 1 and Fig.13 , the method 100 includes block 118, wherein the plurality of channel layers 208 are released as channel members 2080. After removing the dummy gate stack 220, the sacrificial layer 206 between the channel layers 208 in the channel region 212C is selectively removed. The selective removal of the sacrificial layer 206 releases the channel layers 208 (eg, Fig.12 As shown), to form Fig.13 The channel member 2080 shown. The selective removal of the sacrificial layer 206 forms a gate trench 246, which includes a space between adjacent channel members 2080. The selective removal of the sacrificial layer 206 can be implemented by selective dry etching, selective wet etching or other selective etching processes. An exemplary selective dry etching process can include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. An exemplary selective wet etching process can include APM etching (e.g., ammonium hydroxide-hydrogen peroxide-water mixture).

[0047] refer to Figure 1 and Fig.14, method 100 includes frame 120, wherein a gate structure 250 is formed to surround each released channel member 2080. After releasing the channel member 2080, a gate structure 250 is formed to surround each channel member. Although not explicitly shown, the gate structure 250 includes an interface layer in the channel region 212C that is bonded to the channel member 2080 and the substrate 202, a gate dielectric layer on the interface layer, and a gate electrode layer on the gate dielectric layer. The interface layer may include a dielectric material, such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The gate dielectric layer may include a high-k dielectric material, such as hafnium oxide. Alternatively, the gate dielectric layer may include other high-k dielectric materials, such as titanium oxide (TiO 2 ), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta 2 O 5 ), Hafnium Silicon Oxide (HfSiO 4 )、ZrO 2 ), zirconium oxide silicon (ZrSiO 2 ), lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 )、ZrO、Yttrium oxide (Y 2 O 3 ), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), combinations thereof, or other suitable materials. The gate dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods.

[0048] The gate electrode layer of the gate structure 250 may include a single layer or a multilayer structure, such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a liner layer, a wetting layer, an adhesion layer, a metal alloy or various combinations of metal silicides. For example, the gate electrode layer may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metal materials or combinations thereof. In various embodiments, the gate electrode layer may be formed by ALD, PVD, CVD, electron beam evaporation or other suitable processes. In various embodiments, a CMP process may be performed to remove excess metal, thereby providing a substantially flat top surface of the gate structure. The gate structure includes a portion between the channel members 2080 in the channel region 212C.

[0049] Fig.17 , Fig. 22 , Fig.32 , Fig.37 , Fig.47 and Fig.52 Methods 300, 350, 400, 450, 500 and 550 are used to form Figure 10-14 20. Methods 300 and 350 include forming a bottom dielectric layer to prevent leakage through substrate 202. Methods 400 and 450 include forming a bottom epitaxial layer to reduce leakage through substrate 202. Methods 500 and 550 include forming a bottom epitaxial layer to reduce leakage through substrate 202, and forming a bottom dielectric layer on the bottom epitaxial layer. By way of example and not limitation, methods 300, 400, and 500 deposit a reflowable epitaxial layer to join channel layer 208. Methods 350, 350, and 550 deposit an interface epitaxial layer to join channel layer 208, and then form a reflowable epitaxial layer on the interface epitaxial layer. Methods 300, 350, 400, 450, 500, and 550 are described in more detail below.

[0050] Combine the following Figure 18-21 right Fig.17 The method 300 in FIG.

[0051] refer to Fig.17 and Fig.18, the method 300 includes a block 302, wherein a bottom dielectric layer 235 is formed over the source / drain trench 228. In some embodiments, the bottom dielectric layer 235 includes silicon nitride, silicon carbonitride, silicon oxynitride, or silicon carbonitride oxynitride. In one embodiment, the bottom dielectric layer 235 is formed together with the internal spacer feature 234. In this embodiment, after the dielectric material for the internal spacer feature 234 is deposited over the WIP structure 200, an etch back is performed to expose the end surface of the channel layer 208. Due to limited access, the etch back does not completely remove the dielectric material at the bottom of the source / drain trench 228, thereby forming a bottom dielectric layer 235 covering the substrate 202 in the source / drain region 212SD. After the internal spacer feature 234 is formed, the dielectric material for the bottom dielectric layer 235 is conformally deposited over the source / drain trench 228. Thereafter, a dummy layer, such as a bottom anti-reflective coating (BARC) layer, is deposited over the dielectric material for the bottom dielectric layer 235. The dummy layer is then etched back to have a reduced depth. With the etched back dummy layer protecting the bottom of the dielectric material, the exposed dielectric material is selectively removed. After the etched back dummy layer is selectively removed by ashing or selective etching, the remaining bottom portion of the dielectric material becomes the bottom dielectric layer 235. The bottom dielectric layer 235 completely covers the surface of the substrate 202 to prevent epitaxial deposition on the substrate 202. Fig.18 In some embodiments shown, the bottom dielectric layer 235 can partially or even completely cover the sidewalls of the bottommost inner spacer feature 234 .

[0052] refer to Fig.17 and Fig.19, the method 300 includes a block 304, in which a reflowable epitaxial layer 236 is formed over the source / drain trenches 228. With the bottom dielectric layer 235 covering the substrate 202, the end surface of the channel layer 208 is the only exposed semiconductor surface. This allows the reflowable epitaxial layer 236 to be selectively epitaxially deposited on the exposed semiconductor surface of the channel layer 208. In order to ensure the selective deposition of the reflowable epitaxial layer 236, a growth-etch deposition process or a cyclic deposition process can be used to deposit the reflowable epitaxial layer 236. As the name implies, the growth-etch deposition process includes a growth component (or growth cycle) and an etching component (or etching cycle). The growth component (or growth cycle) selectively deposits the reflowable epitaxial layer 236 primarily on the exposed semiconductor surface, and the etching component (or etching cycle) removes the reflowable epitaxial layer 236 deposited on the non-semiconductor surface. In some embodiments, the selective deposition of the reflowable epitaxial layer 236 may include vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), or molecular beam epitaxy (MBE), wherein the process pressure is between about 1 Torr and about 760 Torr, and the process temperature is between about 600° C. and about 800° C. This process temperature range is important. When the process temperature is below 600° C., the growth rate of the first epitaxial layer may be too slow. When the process temperature is above 800° C., the deposition process may cause damage. When deposited, the reflowable epitaxial layer 236 includes a wavy sidewall profile. Fig.19 In some embodiments shown, despite the use of a deposition-growth deposition process, a portion of the reflowable epitaxial layer 236 may still be in contact with the gate spacer layer 226. In some other embodiments, through precise process control, the surface of the gate spacer layer 226 may be completely free of the reflowable epitaxial layer 236.

[0053] In some embodiments, the reflowable epitaxial layer 236 may include silicon (Si) and germanium (Ge). In some embodiments, the reflowable epitaxial layer 236 may also include carbon (C) to reduce dopant diffusion. When the reflowable epitaxial layer 236 includes carbon (C), the carbon content in the reflowable epitaxial layer 236 may be less than 2%. The reflowable epitaxial layer 236 may be in-situ doped with an n-type dopant, such as phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. In terms of doping concentration, the arsenic (As) concentration in the reflowable epitaxial layer 236 may be less than 5×10 21 Atom / cm 3 The phosphorus (P) concentration in the reflowable epitaxial layer 236 may be less than 5×10 21 Atom / cm 3 , and the antimony (Sb) concentration in the reflowable epitaxial layer 236 may be less than 2×10 21 Atom / cm 3When present, arsenic (As) and antimony (Sb) are doped in the reflowable epitaxial layer 236 more for diffusion control and less for reducing resistance, while phosphorus doping is more for reducing resistance. Note that although the source / drain features 240 are n-type, the reflowable epitaxial layer 236 includes germanium (Ge). The presence of germanium (Ge) in the reflowable epitaxial layer 236 allows it to be reshaped at temperatures between about 600 °C and about 800 °C. Through experiments and simulations, it has been found that the temperature required to reshape a germanium-free epitaxial layer (e.g., an epitaxial layer including silicon) is much higher, e.g., greater than 1000 °C. Such a high process temperature tends to damage the device structures that have already been formed. In some embodiments, the reflowable epitaxial layer 236 may include a germanium content between about 5% and about 60%. This range is important. When the germanium content is less than 5%, it is not sufficient to reduce the flow temperature. When the germanium content is greater than 60%, the reflowable epitaxial layer 236 may have too large a lattice mismatch with the channel member 2080, and the defect density in the reflowable epitaxial layer 236 may be too large to outweigh the benefits brought by the germanium content.

[0054] Reference Fig.17 and Fig. 20 , method 300 includes block 306, in which a heat treatment 1000 is performed to reshape the reflowable epitaxial layer 236. In some embodiments, the heat treatment 1000 may be a chemical-free or local heat treatment, such as laser annealing. As Fig. 20 shown, a heat treatment 1000 is performed on the reflowable epitaxial layer 236 to cause reshaping or reflow, thereby forming a reshaped epitaxial layer 2360. In Fig. 20 , the reshaped epitaxial layer 2360 may include two opposing flat surfaces 236F that are substantially perpendicular to the substrate 202. As Fig. 20 shown, the flat surfaces 236F of the reshaped epitaxial layer 2360 extend substantially along the depth of the source / drain trench 228, allowing unobstructed access to the bottom dielectric layer 235. In Fig. 20 some embodiments shown, the reshaped epitaxial layer 2360 is in direct contact with and spans vertically across the end faces of all the channel layers 208 in the channel region 212C.

[0055] Reference Fig.17 and Fig.21, Method 300 includes block 308, where a low-resistance epitaxial layer 238 is formed over the reshaped epitaxial layer 2360. After reshaping the reflowable epitaxial layer 236 at block 306, the low-resistance epitaxial layer 238 is selectively deposited from the surface of the reshaped epitaxial layer 2360. In some embodiments, vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes can be used to deposit the low-resistance epitaxial layer 238. Since the reshaped epitaxial layer 2360 includes a flat surface instead of an uneven shape, the low-resistance epitaxial layer 238 is less likely to prematurely merge to form voids in the low-resistance epitaxial layer 238. Different from the reflowable epitaxial layer 236, the low-resistance epitaxial layer 238 is not subjected to the heat treatment for reshaping and can include a smaller germanium concentration. In one embodiment, the low-resistance epitaxial layer 238 does not contain germanium. In an alternative embodiment, the low-resistance epitaxial layer 238 includes silicon (Si) and carbon (C), where the carbon content in the low-resistance epitaxial layer 238 is less than 2%. The low-resistance epitaxial layer 238 includes an n-type dopant, such as arsenic (As), phosphorus (P), antimony (Sb), or a combination thereof. In terms of doping concentration, the arsenic (As) concentration in the low-resistance epitaxial layer 238 can be less than 5×10 21 atoms / cm 3 , the phosphorus (P) concentration in the low-resistance epitaxial layer 238 can be less than 5×10 21 atoms / cm 3 , and the antimony (Sb) concentration in the low-resistance epitaxial layer 238 can be less than 2×10 21 atoms / cm 3 . When present, arsenic and antimony are doped more in the low-resistance epitaxial layer 238 for diffusion control and less for reducing resistance, while phosphorus is doped more for reducing resistance. In terms of dopant composition, the phosphorus (P) doping concentration in the low-resistance epitaxial layer 238 is greater than the phosphorus (P) doping concentration in the reflowable epitaxial layer 236 to reduce the parasitic resistance. When both the low-resistance epitaxial layer 238 and the reflowable epitaxial layer 236 include arsenic (As) and / or antimony (Sb), since the reflowable epitaxial layer 236 is closer to the channel, the doping concentration of arsenic and / or antimony in the reflowable epitaxial layer 236 is greater than the doping concentration of arsenic and / or antimony in the low-resistance epitaxial layer 238. In Fig.21 some embodiments shown, the top surface of the low-resistance epitaxial layer 238 can exhibit facets during epitaxial growth. In some alternative embodiments, defects in the low-resistance epitaxial layer 238 can result in a tilted profile (i.e., one side is higher than the other) or a concave profile (i.e., lower in the middle).

[0056] Since the generated source / drain features 240 have n-type conductivity, the low resistance epitaxial layer 238 includes a greater n-type dopant concentration than the reflowable epitaxial layer 236. Empirically, a greater dopant concentration may result in a greater defect concentration. In addition, the germanium (Ge) concentration of the low resistance epitaxial layer 238 is less than the germanium (Ge) concentration of the reflowable epitaxial layer 236. In some implementations, the precursor used to deposit the low resistance epitaxial layer 238 does not contain germanium (Ge). Since the low resistance epitaxial layer 238 includes a greater dopant concentration and the reflowable epitaxial layer 236 undergoes an additional thermal treatment 1000, the low resistance epitaxial layer 238 may have a smaller crystallinity than the reflowable epitaxial layer 236. Since the role of the low resistance epitaxial layer 238 is to reduce parasitic resistance, its volume and thickness should be maximized and greater than the volume and thickness of the reflowable epitaxial layer 236.

[0057] like Fig.21 As shown, the low resistance epitaxial layer 238 extends through the flat surface 236F in the vertical direction to be exposed in the gap 239 defined by the low resistance epitaxial layer 238 and the bottom dielectric layer 235. The low resistance epitaxial layer 238 also extends in the vertical direction between the horizontally aligned channel layers 208, which will be released as Fig.14 The channel member 2080 is shown. The low resistance epitaxial layer 238 is spaced apart from the end surface of the channel layer 208 by the reshaped epitaxial layer 2360. When the method 300 is employed, the source / drain features 240 include the reshaped epitaxial layer 2360 and the low resistance epitaxial layer 238.

[0058] Combine the following Figure 23-31 right Fig. 22 Method 350 in is described.

[0059] refer to Fig. 22 and Fig.23 , the method 350 includes block 302, where a bottom dielectric layer 235 is formed over the source / drain trenches 228. The operations at block 302 have been described above with respect to the method 300. For the sake of brevity, a detailed description of the operations at block 302 is omitted.

[0060] refer to Fig. 22 , Fig.24 and Fig.25, method 300 includes box 310, in which an interface epitaxial layer 237 is deposited over the source / drain trenches 228. With the bottom dielectric layer 235 covering the substrate 202, the end surface of the channel layer 208 is the only exposed semiconductor surface. This allows the interface epitaxial layer 237 to be selectively epitaxially deposited on the exposed semiconductor surface of the channel layer 208. In order to ensure the selective deposition of the interface epitaxial layer 237, a growth-etch deposition process or a cyclic deposition process can be used to deposit the interface epitaxial layer 237. As the name implies, the growth-etch deposition process includes a growth component (or growth cycle) and an etching component (or etching cycle). The growth component (or growth cycle) selectively deposits the interface epitaxial layer 237 primarily on the exposed semiconductor surface, and the etching component (or etching cycle) removes the interface epitaxial layer 237 deposited on the non-semiconductor surface. In some embodiments, the selective deposition of the interface epitaxial layer 237 may include vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), or molecular beam epitaxy (MBE), wherein the process pressure is between about 1 Torr and about 760 Torr, and the process temperature is between about 600° C. and about 800° C. This process temperature range is important. When the process temperature is below 600° C., the growth rate of the first epitaxial layer may be too slow. When the process temperature is above 800° C., the deposition process may cause damage. Fig.24 In some of the embodiments shown, the interfacial epitaxial layer 237 deposited on the end surfaces of the channel layer 208 does not merge over the internal spacer features 234. Fig.25 In some alternative embodiments shown, the interfacial epitaxial layer 237 deposited on the end surface of the channel layer 208 merges over the internal spacer features 234. Fig.25 In the illustrated embodiment, the interface epitaxial layer 237 can contact the internal spacer features 234 except for the bottommost internal spacer features 234 which are covered by the bottom dielectric layer 235 .

[0061] In some embodiments, the interface epitaxial layer 237 includes silicon (Si) and does not contain germanium (Ge). In some embodiments, the interface epitaxial layer 237 may also include carbon (C) to reduce dopant outdiffusion. The interface epitaxial layer 237 may be in-situ doped with an n-type dopant, such as phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. In terms of doping concentration, the n-type dopant concentration in the interface epitaxial layer 237 is less than the n-type dopant concentration in the reflowable epitaxial layer 236 or the low resistance epitaxial layer 238. The arsenic (As) concentration in the interface epitaxial layer 237 may be less than 5×10 21 Atom / cm 3 The phosphorus (P) concentration in the interface epitaxial layer 237 may be less than 5×10 21 Atom / cm 3, and the antimony (Sb) concentration in the interface epitaxial layer 237 may be less than 5×10 21 Atom / cm 3 When present, arsenic and antimony are doped more in the interface epitaxial layer 237 for diffusion control and less for resistance reduction, while phosphorus is doped more for resistance reduction. For this reason, the doping concentration of arsenic or antimony in the interface epitaxial layer 237 is greater than the doping concentration of arsenic or antimony in the subsequently formed reflowable epitaxial layer 236 or low resistance epitaxial layer 238.

[0062] refer to Fig. 22 , Fig.26 and Fig. 27 , the method 300 includes block 312, where a reflowable epitaxial layer 236 is formed over the interface epitaxial layer 237. The operations at block 312 are substantially similar to the operations described with respect to block 304 of the method 300, except that, at block 312, the reflowable epitaxial layer 236 is deposited over the interface epitaxial layer 237. For the sake of brevity, a detailed description of the operations at block 312 is omitted. Fig.26 A reflowable epitaxial layer 236 is shown deposited over an interface epitaxial layer 237 that does not merge over the interior spacer features 234 . Fig. 27 A reflowable epitaxial layer 236 is shown deposited over an interface epitaxial layer 237 that merges over and continues across the interior spacer features 234 .

[0063] refer to Fig. 22 , Fig.28 and Fig.29 , the method 300 includes block 314, where a thermal treatment 1000 is performed to reshape the reflowable epitaxial layer 236. In some embodiments, the thermal treatment 1000 may be a chemical-free treatment or a localized thermal treatment, such as laser annealing. Fig.28 and Fig.29 As shown, a thermal treatment 1000 is performed on the reflowable epitaxial layer 236 to cause reshaping or reflowing to form a reshaped epitaxial layer 2360 . Fig.28 The reflowable epitaxial layer 236 is shown reshaped over the interface epitaxial layer 237 which does not merge over the interior spacer features 234 . Fig.29 The reflowable epitaxial layer 236 is shown reshaped over the interface epitaxial layer 237, which merges over and continues across the interior spacer features 234. Fig.28 and Fig.29 In the embodiment of the present invention, the reshaped epitaxial layer 2360 may include two opposite flat surfaces 236F that are substantially perpendicular to the substrate 202. Fig.28 and Fig.29As shown, the planar surface 236F of the reshaped epitaxial layer 2360 extends substantially along the depth of the source / drain trench 228, allowing unimpeded access to the bottom dielectric layer 235. Fig.28 and Fig.29 In some of the illustrated embodiments, the reshaped epitaxial layer 2360 is in direct contact with the interface epitaxial layer 237 and spans across the interface epitaxial layer 237 in the vertical direction.

[0064] refer to Fig. 22 , Fig.30 and Fig.31 , method 300 includes block 316, where a low resistance epitaxial layer 238 is formed over the reshaped epitaxial layer 2360. The operations at block 316 are substantially similar to the operations described for block 308 of method 300, except that, at block 316, the interface epitaxial layer 237 is located between the reshaped epitaxial layer 2360 and the channel layer 208. For the sake of brevity, a detailed description of the operations at block 316 is omitted. Fig.30 A low resistance epitaxial layer 238 is shown deposited over the interface epitaxial layer 237 which does not merge over the interior spacer features 234 . Fig.31 A low-resistance epitaxial layer 238 is shown deposited on the interface epitaxial layer 237, which merges on and continuously crosses the inner spacer feature 234. In terms of dopant composition, the phosphorus (P) doping concentration in the low-resistance epitaxial layer 238 is greater than the phosphorus (P) doping concentration in the reflowable epitaxial layer 236 to reduce parasitic resistance. When both the low-resistance epitaxial layer 238 and the reflowable epitaxial layer 236 include arsenic and / or antimony, the doping concentration of arsenic and / or antimony in the reflowable epitaxial layer 236 is greater than the doping concentration of arsenic and / or antimony in the low-resistance epitaxial layer 238 because the reflowable epitaxial layer 236 is closer to the channel.

[0065] The low resistance epitaxial layer 238 may have a smaller crystallinity than the interface epitaxial layer 237 and the reflowable epitaxial layer 236 having a low dopant concentration and subjected to the heat treatment 1000. Between the interface epitaxial layer 237 and the reflowable epitaxial layer 236, the interface epitaxial layer 237 may have a greater crystallinity because the interface epitaxial layer 237 is directly bonded to the channel layer 208 and has a lower germanium (Ge) concentration than the reflowable epitaxial layer 236.

[0066] like Fig.30 and Fig.31 As shown, the low resistance epitaxial layer 238 extends through the flat surface 236F in the vertical direction to be exposed in the gap 239 defined by the low resistance epitaxial layer 238 and the bottom dielectric layer 235. The low resistance epitaxial layer 238 also extends in the vertical direction between the horizontally aligned channel layers 208, which will be released as Fig.14 Channel member 2080 is shown. Low resistance epitaxial layer 238 is spaced apart from the end surface of channel layer 208 by reshaped epitaxial layer 2360 and interface epitaxial layer 237. When method 350 is employed, source / drain features 240 include interface epitaxial layer 237, reshaped epitaxial layer 2360, and low resistance epitaxial layer 238.

[0067] Combine the following Figure 33-36 right Fig.32 The method 400 in FIG.

[0068] refer to Fig.32 and Fig.33 , method 400 includes frame 402, in which a bottom epitaxial layer 232 is formed above the source / drain trench 228. In frame 402, the bottom epitaxial layer 232 is selectively deposited above the surface of the substrate 202 exposed in the source / drain trench 228. The function of the bottom epitaxial layer 232 is to prevent leakage through the substrate 202. In some embodiments, the bottom epitaxial layer 232 includes undoped silicon (Si). As used herein, undoped silicon refers to silicon that has not been intentionally doped in an in-situ doping process or an ion implantation process. In some alternative embodiments, the bottom epitaxial layer 232 includes silicon (Si) and is counter-doped with a p-type dopant, such as boron (B). In terms of doping concentration, the boron (B) concentration in the bottom epitaxial layer 232 may be less than 1×10 20 Atom / cm 3 In some other embodiments, the bottom epitaxial layer 232 includes undoped silicon germanium (SiGe). In some alternative embodiments, the bottom epitaxial layer 232 includes silicon germanium (SiGe) and is counter-doped with a p-type dopant, such as boron (B). In terms of doping concentration, the boron (B) concentration in the bottom epitaxial layer 232 may be less than 1×10 20 Atom / cm 3 Although it is desirable that the bottom epitaxial layer 232 has a flush surface with the substrate 202, as Fig.33 As shown, the top surface of the bottom epitaxial layer 232 can be higher or lower than the top surface of the substrate 202. In some examples, the bottom epitaxial layer 232 can have a convex or concave top surface profile. Since the bottom epitaxial layer 232 is epitaxially deposited on the substrate 202, and the substrate 202 is single crystalline, the bottom epitaxial layer 232 can be single crystalline or substantially single crystalline.

[0069] At block 402, to selectively deposit the bottom epitaxial layer 232 on the substrate 202, a catalyst such as silane (SiH 4 ) or dichlorosilane (SiH 2 Cl 2 ) or a silicon precursor such as germanium (GeH 4 ) or digermane (Ge2 H 6 ) and germanium precursors such as nitrogen (N 2 ) or hydrogen (H 2 ) or the like, epitaxially deposits the bottom epitaxial layer 232 over the source / drain trenches 228. Hydrogen chloride (HCl) may be introduced to improve the deposition selectivity so that little or no bottom epitaxial layer 232 is deposited on the sidewalls of the inner spacer features 234, the sidewalls of the channel layer 208, the sidewalls of the gate spacer layer 226, or the top surface of the gate top hard mask layer 222. When the bottom epitaxial layer 232 is formed, the bottom epitaxial layer 232 is in direct contact with the surface of the substrate 202 exposed in the source / drain trenches 228. The bottom epitaxial layer 232 functions as a leakage reduction feature to reduce leakage current through the substrate 202.

[0070] refer to Fig.32 and Fig.34 , the method 400 includes a block 404, in which a reflowable epitaxial layer 236 is formed over the source / drain trench 228. In the case where the bottom epitaxial layer 232 covers the substrate 202, the top surface of the bottom epitaxial layer 232 and the end surface of the channel layer 208 constitute the exposed semiconductor surface in the source / drain trench 228. This allows the reflowable epitaxial layer 236 to be selectively epitaxially deposited on the exposed semiconductor surface of the channel layer 208 and the top surface of the bottom epitaxial layer 232. In order to ensure the selective deposition of the reflowable epitaxial layer 236, a growth-etch deposition process or a cyclic deposition process can be used to deposit the reflowable epitaxial layer 236. As the name implies, the growth-etch deposition process includes a growth component (or growth cycle) and an etching component (or etching cycle). The growth component (or growth cycle) selectively deposits the reflowable epitaxial layer 236 mainly on the exposed semiconductor surface, and the etching component (or etching cycle) removes the reflowable epitaxial layer 236 deposited on the non-semiconductor surface. In some embodiments, the selective deposition of the reflowable epitaxial layer 236 may include vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), or molecular beam epitaxy (MBE), wherein the process pressure is between about 1 Torr and about 760 Torr, and the process temperature is between about 600° C. and about 800° C. This process temperature range is important. When the process temperature is below 600° C., the growth rate of the first epitaxial layer may be too slow. When the process temperature is above 800° C., the deposition process may cause damage.

[0071] In some embodiments, the reflowable epitaxial layer 236 may include silicon (Si) and germanium (Ge). In some embodiments, the reflowable epitaxial layer 236 may also include carbon (C) to reduce dopant diffusion. When the reflowable epitaxial layer 236 includes carbon (C), the carbon content in the reflowable epitaxial layer 236 may be less than 2%. The reflowable epitaxial layer 236 may be in-situ doped with an n-type dopant, such as phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. In terms of doping concentration, the arsenic (As) concentration in the reflowable epitaxial layer 236 may be less than 5×10 21 Atom / cm 3 The phosphorus (P) concentration in the reflowable epitaxial layer 236 may be less than 5×10 21 Atom / cm 3 , and the antimony (Sb) concentration in the reflowable epitaxial layer 236 may be less than 2×10 21 Atom / cm 3 . When present, arsenic (As) and antimony (Sb) are doped more in the reflowable epitaxial layer 236 for diffusion control and less for reducing resistance, while phosphorus is doped more for reducing resistance. It is noted that although the source / drain features 240 are n-type, the reflowable epitaxial layer 236 includes germanium (Ge). The presence of germanium (Ge) in the reflowable epitaxial layer 236 allows it to be reshaped at a temperature between about 600°C and about 800°C. Through experiments and simulations, it has been found that the temperature required to reshape a germanium-free epitaxial layer (e.g., an epitaxial layer including silicon) is much higher, such as greater than 1000°C. Such high process temperatures tend to cause damage to the device structure that has been formed. In some embodiments, the reflowable epitaxial layer 236 may include a germanium content between about 5% and about 60%. This range is important. When the germanium content is less than 5%, it is not enough to reduce the fluidity temperature. When the germanium content is greater than 60%, the reflowable epitaxial layer 236 may have too large a lattice mismatch with the channel member 2080, and the defect density in the reflowable epitaxial layer 236 may be too large to outweigh the benefits of the germanium content.

[0072] refer to Fig.32 and Fig.35 , the method 400 includes block 406, where a thermal treatment 1000 is performed to reshape the reflowable epitaxial layer 236. In some embodiments, the thermal treatment 1000 may be a chemical-free treatment or a localized thermal treatment, such as laser annealing. Fig.35 As shown, a thermal treatment 1000 is performed on the reflowable epitaxial layer 236 to cause reshaping or reflowing, thereby forming a reshaped epitaxial layer 2360. Fig.35 In the embodiment of the present invention, the reshaped epitaxial layer 2360 may include two opposite flat surfaces 236F that are substantially perpendicular to the substrate 202. Fig.35As shown, the planar surface 236F of the reshaped epitaxial layer 2360 extends substantially along the depth of the source / drain trench 228, allowing unimpeded access to the bottom epitaxial layer 232. Fig.35 In some of the illustrated embodiments, the reshaped epitaxial layer 2360 is in direct contact with end surfaces of all channel layers 208 in the channel region 212C and spans across these end surfaces in the vertical direction.

[0073] refer to Fig.32 and Fig.36 , the method 400 includes a block 408, in which a low resistance epitaxial layer 238 is formed on the reshaped epitaxial layer 2360. After the reflowable epitaxial layer 236 is reshaped at block 406, the low resistance epitaxial layer 238 is selectively deposited from the surface of the reshaped epitaxial layer 2360. In some embodiments, the low resistance epitaxial layer 238 may be deposited using vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. Since the reshaped epitaxial layer 2360 includes a flat surface, rather than an uneven shape, the low resistance epitaxial layer 238 is less likely to merge prematurely to form voids in the low resistance epitaxial layer 238. Unlike the reflowable epitaxial layer 236, the low resistance epitaxial layer 238 is not subjected to a thermal treatment for reshaping. In one embodiment, the low resistance epitaxial layer 238 does not contain germanium. In an alternative embodiment, the low resistance epitaxial layer 238 includes silicon (Si) and carbon (C), wherein the carbon content in the low resistance epitaxial layer 238 is less than 2%. The low resistance epitaxial layer 238 includes an n-type dopant, such as arsenic (As), phosphorus (P), antimony (Sb), or a combination thereof. In terms of doping concentration, the arsenic (As) concentration in the low resistance epitaxial layer 238 may be less than 5×10 21 Atom / cm 3 The phosphorus (P) concentration in the low resistance epitaxial layer 238 may be less than 5×10 21 Atom / cm 3 , and the antimony (Sb) concentration in the low resistance epitaxial layer 238 may be less than 2×10 21 Atom / cm 3 In terms of dopant composition, the phosphorus (P) doping concentration in the low resistance epitaxial layer 238 is greater than the phosphorus (P) doping concentration in the reflowable epitaxial layer 236 to reduce parasitic resistance. When both the low resistance epitaxial layer 238 and the reflowable epitaxial layer 236 include arsenic and / or antimony, the doping concentration of arsenic and / or antimony in the reflowable epitaxial layer 236 is greater than the doping concentration of arsenic and / or antimony in the low resistance epitaxial layer 238 because the reflowable epitaxial layer 236 is closer to the channel.

[0074] like Fig.36As shown, the low resistance epitaxial layer 238 extends vertically along the flat surface 236F into the reshaped epitaxial layer 2360. The low resistance epitaxial layer 238 also extends vertically between the plurality of horizontally aligned channel layers 208, which will be released as Fig.14 The channel member 2080 is shown. The low resistance epitaxial layer 238 is spaced apart from the end surface of the channel layer 208 by the reshaped epitaxial layer 2360. The low resistance epitaxial layer 238 is spaced apart from the bottom epitaxial layer 232 by the reshaped epitaxial layer 2360.

[0075] Combine the following Figure 38-46 right Fig.37 Method 450 in is described.

[0076] refer to Fig.37 and Fig.38 , the method 450 includes block 402, where a bottom epitaxial layer 232 is formed over the source / drain trenches 228. The operations at block 402 have been described above with respect to the method 400. For the sake of brevity, a detailed description of the operations at block 402 is omitted.

[0077] refer to Fig.37 , Fig.39 and Fig.40 , the method 450 includes a block 410, wherein an interface epitaxial layer 237 is deposited over the source / drain trench 228. In the case where the bottom epitaxial layer 232 covers the substrate 202, the top surface of the bottom epitaxial layer 232 and the end surface of the channel layer 208 constitute the exposed semiconductor surface in the source / drain trench 228. This allows the interface epitaxial layer 237 to be selectively epitaxially deposited on the exposed semiconductor surface of the channel layer 208 and on the bottom epitaxial layer 232. In order to ensure the selective deposition of the interface epitaxial layer 237, a growth-etch deposition process or a cyclic deposition process can be used to deposit the interface epitaxial layer 237. As the name implies, the growth-etch deposition process includes a growth component (or growth cycle) and an etching component (or etching cycle). The growth component (or growth cycle) selectively deposits the interface epitaxial layer 237 mainly on the exposed semiconductor surface, and the etching component (or etching cycle) removes the interface epitaxial layer 237 deposited on the non-semiconductor surface. In some embodiments, the selective deposition of the interface epitaxial layer 237 may include vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), or molecular beam epitaxy (MBE), wherein the process pressure is between about 1 Torr and about 760 Torr, and the process temperature is between about 600° C. and about 800° C. This process temperature range is important. When the process temperature is below 600° C., the growth rate of the first epitaxial layer may be too slow. When the process temperature is above 800° C., the deposition process may cause damage. Fig.39In some of the embodiments shown, the interfacial epitaxial layer 237 deposited on the end surfaces of the channel layer 208 does not merge over the internal spacer features 234. Fig.40 In some alternative embodiments shown, the interfacial epitaxial layer 237 deposited on the end surface of the channel layer 208 merges over the internal spacer features 234. Fig.40 In the illustrated embodiment, the interface epitaxial layer 237 may be in contact with the internal spacer features 234 except for the bottommost internal spacer structure 234 which is covered by the bottom epitaxial layer 232 .

[0078] In some embodiments, the interface epitaxial layer 237 includes silicon (Si) and does not contain germanium (Ge). In some embodiments, the interface epitaxial layer 237 may also include carbon (C) to reduce dopant outdiffusion. The interface epitaxial layer 237 may be in-situ doped with an n-type dopant, such as phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. In terms of doping concentration, the n-type dopant concentration in the interface epitaxial layer 237 is less than the n-type dopant concentration in the reflowable epitaxial layer 236 or the low resistance epitaxial layer 238. The arsenic (As) concentration in the interface epitaxial layer 237 may be less than 5×10 21 Atom / cm 3 The phosphorus (P) concentration in the interface epitaxial layer 237 may be less than 5×10 21 Atom / cm 3 , and the antimony (Sb) concentration in the interface epitaxial layer 237 may be less than 5×10 21 Atom / cm 3 When present, arsenic and antimony are doped more in the interface epitaxial layer 237 for diffusion control and less for resistance reduction, while phosphorus is doped more for resistance reduction. For this reason, the doping concentration of arsenic or antimony in the interface epitaxial layer 237 is greater than the doping concentration of arsenic or antimony in the subsequently formed reflowable epitaxial layer 236 or low resistance epitaxial layer 238.

[0079] refer to Fig.37 , Fig.41 and Fig.42 , the method 450 includes block 412, where a reflowable epitaxial layer 236 is formed over the interface epitaxial layer 237. The operations at block 412 are substantially similar to the operations described with respect to block 304 of the method 300, except that, at block 412, the reflowable epitaxial layer 236 is deposited over the interface epitaxial layer 237. For the sake of brevity, a detailed description of the operations at block 412 is omitted. Fig.41 A reflowable epitaxial layer 236 is shown deposited over an interface epitaxial layer 237 that does not merge over the interior spacer features 234 . Fig.42A reflowable epitaxial layer 236 is shown deposited over an interface epitaxial layer 237 that merges over and continues across the interior spacer features 234 .

[0080] refer to Fig.37 , Fig.43 and Fig.44 , method 450 includes block 414, where a thermal treatment 1000 is performed to reshape the reflowable epitaxial layer 236. In some embodiments, thermal treatment 1000 may be a chemical-free treatment or a localized thermal treatment, such as laser annealing. Fig.43 and Fig.44 As shown, a thermal treatment 1000 is performed on the reflowable epitaxial layer 236 to cause reshaping or reflowing to form a reshaped epitaxial layer 2360 . Fig.43 The reflowable epitaxial layer 236 is shown reshaped over the interface epitaxial layer 237 which does not merge over the interior spacer features 234 . Fig.44 The reflowable epitaxial layer 236 is shown reshaped over the interface epitaxial layer 237, which merges over and continues across the interior spacer features 234. Fig.43 and Fig.44 In the embodiment of the present invention, the reshaped epitaxial layer 2360 may include two opposite flat surfaces 236F that are substantially perpendicular to the substrate 202. Fig.43 and Fig.44 As shown, the planar surface 236F of the reshaped epitaxial layer 2360 extends substantially along the depth of the source / drain trenches 228 , allowing unimpeded access to the bottom surface of the reshaped epitaxial layer 2360 .

[0081] refer to Fig.37 , Fig.45 and Fig.46, the method 450 includes a block 416, in which a low resistance epitaxial layer 238 is formed on the reshaped epitaxial layer 2360. After the reflowable epitaxial layer 236 is reshaped at block 414, the low resistance epitaxial layer 238 is selectively deposited from the surface of the reshaped epitaxial layer 2360. In some embodiments, the low resistance epitaxial layer 238 may be deposited using vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. Compared to the reflowable epitaxial layer 236, the low resistance epitaxial layer 238 includes a greater dopant concentration to reduce parasitic resistance. Since the reshaped epitaxial layer 2360 includes a flat surface, rather than an uneven shape, the low resistance epitaxial layer 238 is less likely to merge prematurely to form voids in the low resistance epitaxial layer 238. Unlike the reflowable epitaxial layer 236, the low resistance epitaxial layer 238 is not subjected to a heat treatment for reshaping. In one embodiment, the low resistance epitaxial layer 238 does not contain germanium. In an alternative embodiment, the low resistance epitaxial layer 238 includes silicon (Si) and carbon (C), wherein the carbon content in the low resistance epitaxial layer 238 is less than 2%. The low resistance epitaxial layer 238 includes an n-type dopant, such as arsenic (As), phosphorus (P), antimony (Sb), or a combination thereof. In terms of doping concentration, the arsenic (As) concentration in the low resistance epitaxial layer 238 may be less than 5×10 21 Atom / cm 3 The phosphorus (P) concentration in the low resistance epitaxial layer 238 may be less than 5×10 21 Atom / cm 3 , and the antimony (Sb) concentration in the low resistance epitaxial layer 238 may be less than 5×10 21 Atom / cm 3 In terms of dopant composition, the phosphorus (P) doping concentration in the low resistance epitaxial layer 238 is greater than the phosphorus (P) doping concentration in the reflowable epitaxial layer 236 to reduce parasitic resistance. When both the low resistance epitaxial layer 238 and the reflowable epitaxial layer 236 include arsenic and / or antimony, the doping concentration of arsenic and / or antimony in the reflowable epitaxial layer 236 is greater than the doping concentration of arsenic and / or antimony in the low resistance epitaxial layer 238 because the reflowable epitaxial layer 236 is closer to the channel.

[0082] like Fig.45 and Fig.46 As shown, the low resistance epitaxial layer 238 extends vertically along the flat surface 236F into the reshaped epitaxial layer 2360. The low resistance epitaxial layer 238 also extends vertically between the plurality of horizontally aligned channel layers 208, which will be released as Fig.14The channel member 2080 is shown. The low resistance epitaxial layer 238 is spaced apart from the end surface of the channel layer 208 by the reshaped epitaxial layer 2360 and the interface epitaxial layer 237. The low resistance epitaxial layer 238 is spaced apart from the bottom epitaxial layer 232 by the reshaped epitaxial layer 2360 and the interface epitaxial layer 237. When the method 450 is employed, the source / drain feature 240 includes the bottom epitaxial layer 232, the interface epitaxial layer 237, the reshaped epitaxial layer 2360, and the low resistance epitaxial layer 238.

[0083] Combine the following Figure 48-51 right Fig.47 The method 500 in FIG.

[0084] refer to Fig.47 and Fig.48 , the method 500 includes a block 502, in which a bottom epitaxial layer 232 is formed over the source / drain trenches 228. The operations at block 502 are similar to the operations at block 402 described above for the method 400, except that the bottom epitaxial layer 232 in the method 500 is not counter-doped. As described below, a bottom dielectric layer 2350 will cover the top surface of the bottom epitaxial layer 232. Since the bottom dielectric layer 2350 is sufficient to block or reduce leakage into the substrate 202, the bottom epitaxial layer 232 can be undoped and does not need to be counter-doped.

[0085] refer to Fig.47 and Fig.48, Method 500 includes block 504, where a bottom dielectric layer 2350 is formed over the source / drain trench 228. In some embodiments, the bottom dielectric layer 2350 includes silicon nitride, silicon carbonitride, silicon oxynitride, or silicon carbon oxynitride. Different from the bottom dielectric layer 235 formed in Methods 300 and 350, the bottom dielectric layer 2350 is formed after the bottom epitaxial layer 232 and is formed on the bottom epitaxial layer 232. Thus, the bottom dielectric layer 2350 is not formed together with the inner spacer feature 234. In some embodiments, after the inner spacer feature 234 is formed, a dielectric material for the bottom dielectric layer 2350 is conformally deposited over the source / drain trench 228 and the bottom epitaxial layer 232. Then, a dummy layer, such as a bottom anti-reflective coating (BARC) layer, is deposited on the dielectric material for the bottom dielectric layer 2350. Then the dummy layer is etchback to have a reduced depth such that the end face of the channel layer 208 is exposed in the source / drain trench 228. In the case where the etched-back dummy layer protects the bottom of the dielectric material, the exposed dielectric material is selectively removed. After the etched-back dummy layer is selectively removed by stripping, ashing, or selective etching, the remaining bottom of the dielectric material becomes the bottom dielectric layer 2350. The bottom dielectric layer 2350 may completely cover the top surface of the bottom epitaxial layer 232 to prevent epitaxial deposition on the bottom epitaxial layer. In Fig.48 In some embodiments not shown, the bottom dielectric layer 2350 may partially or even completely cover the sidewalls of the bottommost inner spacer feature 234. In Method 500, the role of the bottom epitaxial layer 232 formed at block 502 is to provide a smoother or flatter surface for the deposition of the bottom dielectric layer 2350. It has been observed that such a smoother or flatter surface can result in a bottom dielectric layer 2350 with increased integrity.

[0086] Reference Fig.47 and Fig.49, Method 500 includes block 506, where a reflowable epitaxial layer 236 is formed over the source / drain trench 228. With the bottom dielectric layer 2350 covering the bottom epitaxial layer 232, the end face of the channel layer 208 constitutes the semiconductor surface exposed in the source / drain trench 228. This allows the reflowable epitaxial layer 236 to be selectively epitaxially deposited on the exposed semiconductor surface of the channel layer 208. To ensure the selective deposition of the reflowable epitaxial layer 236, a growth-etch deposition process or a cyclic deposition process can be used to deposit the reflowable epitaxial layer 236. As the name implies, the growth-etch deposition process includes a growth component (or growth cycle) and an etch component (or etch cycle). The growth component (or growth cycle) selectively deposits the reflowable epitaxial layer 236 mainly on the exposed semiconductor surface, and the etch component (or etch cycle) removes the reflowable epitaxial layer 236 deposited on the non-semiconductor surface. In some embodiments, the selective deposition of the reflowable epitaxial layer 236 can include vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), or molecular beam epitaxy (MBE), where the process pressure is between about 1 Torr and about 760 Torr, and the process temperature is between about 600 °C and about 800 °C. This process temperature range is important. When the process temperature is below 600 °C, the growth rate of the first epitaxial layer may be too slow. When the process temperature is above 800 °C, the deposition process may cause damage.

[0087] In some embodiments, the reflowable epitaxial layer 236 can include silicon (Si) and germanium (Ge). In some embodiments, the reflowable epitaxial layer 236 can also include carbon (C) to reduce dopant diffusion. When the reflowable epitaxial layer 236 includes carbon (C), the carbon content in the reflowable epitaxial layer 236 can be less than 2%. The reflowable epitaxial layer 236 can be in-situ doped with an n-type dopant such as phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. In terms of doping concentration, the arsenic (As) concentration in the reflowable epitaxial layer 236 can be less than 5×10 21 atoms / cm 3 , the phosphorus (P) concentration in the reflowable epitaxial layer 236 can be lower than 5×10 21 atoms / cm 3 , and the antimony (Sb) concentration in the reflowable epitaxial layer 236 can be less than 2×10 21 atoms / cm 3. When present, arsenic and antimony are doped more in the reflowable epitaxial layer 236 for diffusion control and less for reducing resistance, while phosphorus is doped more for reducing resistance. It is noted that although the source / drain features 240 are n-type, the reflowable epitaxial layer 236 includes germanium (Ge). The presence of germanium (Ge) in the reflowable epitaxial layer 236 allows it to be reshaped at a temperature between about 600°C and about 800°C. Through experiments and simulations, it has been found that the temperature required to reshape a germanium-free epitaxial layer (e.g., an epitaxial layer including silicon) is much higher, such as greater than 1000°C. Such high process temperatures tend to cause damage to the device structure that has been formed. In some embodiments, the reflowable epitaxial layer 236 may include a germanium content between about 5% and about 60%. This range is important. When the germanium content is less than 5%, it is not enough to reduce the fluidity temperature. When the germanium content is greater than 60%, the reflowable epitaxial layer 236 may have too large a lattice mismatch with the channel member 2080, and the defect density in the reflowable epitaxial layer 236 may be too large to outweigh the benefits of the germanium content.

[0088] refer to Fig.47 and Fig.50 , the method 500 includes block 508, where a thermal treatment 1000 is performed to reshape the reflowable epitaxial layer 236. In some embodiments, the thermal treatment 1000 may be a chemical-free treatment or a localized thermal treatment, such as laser annealing. Fig.50 As shown, a thermal treatment 1000 is performed on the reflowable epitaxial layer 236 to cause reshaping or reflowing, thereby forming a reshaped epitaxial layer 2360. Fig.50 In the embodiment of the present invention, the reshaped epitaxial layer 2360 may include two opposite flat surfaces 236F that are substantially perpendicular to the substrate 202. Fig.50 As shown, the planar surface 236F of the reshaped epitaxial layer 2360 extends substantially along the depth of the source / drain trench 228, allowing unimpeded access to the bottom surface of the reshaped epitaxial layer 2360. Fig.50 In some of the illustrated embodiments, the reshaped epitaxial layer 2360 is in direct contact with end surfaces of all channel layers 208 in the channel region 212C and spans across these end surfaces in the vertical direction.

[0089] refer to Fig.47 and Fig.51, the method 500 includes a block 510, in which a low resistance epitaxial layer 238 is formed on the reshaped epitaxial layer 2360. After the reflowable epitaxial layer 236 is reshaped at block 508, the low resistance epitaxial layer 238 is selectively deposited from the surface of the reshaped epitaxial layer 2360. In some embodiments, the low resistance epitaxial layer 238 may be deposited using vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. Compared to the reflowable epitaxial layer 236, the low resistance epitaxial layer 238 includes a greater dopant concentration to reduce parasitic resistance. Since the reshaped epitaxial layer 2360 includes a flat surface, rather than an uneven shape, the low resistance epitaxial layer 238 is less likely to merge prematurely to form voids in the low resistance epitaxial layer 238. Unlike the reflowable epitaxial layer 236, the low resistance epitaxial layer 238 is not subjected to a heat treatment for reshaping. In one embodiment, the low resistance epitaxial layer 238 does not contain germanium. In an alternative embodiment, the low resistance epitaxial layer 238 includes silicon (Si) and carbon (C), wherein the carbon content in the low resistance epitaxial layer 238 is less than 2%. The low resistance epitaxial layer 238 includes an n-type dopant, such as arsenic (As), phosphorus (P), antimony (Sb), or a combination thereof. In terms of doping concentration, the arsenic (As) concentration in the low resistance epitaxial layer 238 may be less than 5×10 21 Atom / cm 3 The phosphorus (P) concentration in the low resistance epitaxial layer 238 may be less than 5×10 21 Atom / cm 3 , and the antimony (Sb) concentration in the low resistance epitaxial layer 238 may be less than 5×10 21 Atom / cm 3 In terms of dopant composition, the phosphorus (P) doping concentration in the low resistance epitaxial layer 238 is greater than the phosphorus (P) doping concentration in the reflowable epitaxial layer 236 to reduce parasitic resistance. When both the low resistance epitaxial layer 238 and the reflowable epitaxial layer 236 include arsenic and / or antimony, the doping concentration of arsenic and / or antimony in the reflowable epitaxial layer 236 is greater than the doping concentration of arsenic and / or antimony in the low resistance epitaxial layer 238 because the reflowable epitaxial layer 236 is closer to the channel.

[0090] like Fig.51 As shown, the low resistance epitaxial layer 238 extends vertically along the flat surface 236F into the reshaped epitaxial layer 2360. The low resistance epitaxial layer 238 also extends vertically between the plurality of horizontally aligned channel layers 208, which will be released as Fig.142080 is shown. The low resistance epitaxial layer 238 is spaced apart from the end surface of the channel layer 208 by the reshaped epitaxial layer 2360. Both the reshaped epitaxial layer 2360 and the low resistance epitaxial layer 238 are spaced apart from the bottom epitaxial layer 232 by the bottom dielectric layer 2350 and the bottom gap 2390. When the method 500 is employed, the source / drain features 240 include the reshaped epitaxial layer 2360 and the low resistance epitaxial layer 238. The bottom epitaxial layer 232 is spaced apart from the source / drain features 240 by the bottom dielectric layer 2350 and the bottom gap 2390.

[0091] Combine the following Figure 53-61 right Fig.52 Method 550 in is described.

[0092] refer to Fig.52 and Fig.53 , the method 550 includes block 502, where a bottom epitaxial layer 232 is formed over the source / drain trenches 228. The operations at block 502 have been described above with respect to the method 500. For the sake of brevity, a detailed description of the operations at block 502 is omitted.

[0093] refer to Fig.52 and Fig.53 , the method 550 includes block 504, where a bottom dielectric layer 2350 is formed over the bottom epitaxial layer 232. The operations at block 504 have been described above with respect to the method 500. For the sake of brevity, a detailed description of the operations at block 504 is omitted.

[0094] refer to Fig.52 , Fig.54 and Fig.55, the method 550 includes a frame 510, wherein an interface epitaxial layer 237 is deposited over the source / drain trench 228. With the bottom dielectric layer 2350 covering the bottom epitaxial layer 232, the end surface of the channel layer 208 constitutes the exposed semiconductor surface in the source / drain trench 228. This allows the interface epitaxial layer 237 to be selectively epitaxially deposited on the exposed semiconductor surface of the channel layer 208. In order to ensure the selective deposition of the interface epitaxial layer 237, a growth-etch deposition process or a cyclic deposition process can be used to deposit the interface epitaxial layer 237. As the name implies, the growth-etch deposition process includes a growth component (or growth cycle) and an etching component (or etching cycle). The growth component (or growth cycle) selectively deposits the interface epitaxial layer 237 primarily on the exposed semiconductor surface, and the etching component (or etching cycle) removes the interface epitaxial layer 237 deposited on the non-semiconductor surface. In some embodiments, the selective deposition of the interface epitaxial layer 237 may include vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), or molecular beam epitaxy (MBE), wherein the process pressure is between about 1 Torr and about 760 Torr, and the process temperature is between about 600° C. and about 800° C. This process temperature range is important. When the process temperature is below 600° C., the growth rate of the first epitaxial layer may be too slow. When the process temperature is above 800° C., the deposition process may cause damage. Fig.54 In some of the embodiments shown, the interfacial epitaxial layer 237 deposited on the end surfaces of the channel layer 208 does not merge over the internal spacer features 234. Fig.55 In some alternative embodiments shown, an interfacial epitaxial layer 237 deposited on the end surfaces of the channel layer 208 merges over the internal spacer features 234 .

[0095] In some embodiments, the interface epitaxial layer 237 includes silicon (Si) and does not contain germanium (Ge). In some embodiments, the interface epitaxial layer 237 may also include carbon (C) to reduce dopant outdiffusion. The interface epitaxial layer 237 may be in-situ doped with an n-type dopant, such as phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. In terms of doping concentration, the n-type dopant concentration in the interface epitaxial layer 237 is less than the n-type dopant concentration in the reflowable epitaxial layer 236 or the low resistance epitaxial layer 238. The arsenic (As) concentration in the interface epitaxial layer 237 may be less than 5×10 21 Atom / cm 3 The phosphorus (P) concentration in the interface epitaxial layer 237 may be less than 5×10 21 Atom / cm 3 , and the antimony (Sb) concentration in the interface epitaxial layer 237 may be less than 5×10 21 Atom / cm 3When present, arsenic and antimony are doped more in the interface epitaxial layer 237 for diffusion control and less for resistance reduction, while phosphorus is doped more for resistance reduction. For this reason, the doping concentration of arsenic or antimony in the interface epitaxial layer 237 is greater than the doping concentration of arsenic or antimony in the subsequently formed reflowable epitaxial layer 236 or low resistance epitaxial layer 238.

[0096] refer to Fig.52 , Fig.56 and Fig.57 , method 550 includes block 512, where a reflowable epitaxial layer 236 is formed over the interface epitaxial layer 237. The operations at block 512 are substantially similar to the operations described with respect to block 304 of method 300, except that, at block 512, the reflowable epitaxial layer 236 is deposited over the interface epitaxial layer 237 and is spaced apart from the bottom dielectric layer 2350. For the sake of brevity, a detailed description of the operations at block 512 is omitted. Fig.56 A reflowable epitaxial layer 236 is shown deposited over an interface epitaxial layer 237 that does not merge over the interior spacer features 234 . Fig.57 A reflowable epitaxial layer 236 is shown deposited over an interface epitaxial layer 237 that merges over and continues across the interior spacer features 234 .

[0097] refer to Fig.52 , Fig.58 and Fig.59 , method 550 includes block 514, where a thermal treatment 1000 is performed to reshape the reflowable epitaxial layer 236. In some embodiments, thermal treatment 1000 may be a chemical-free treatment or a localized thermal treatment, such as laser annealing. Fig.58 and Fig.59 As shown, a thermal treatment 1000 is performed on the reflowable epitaxial layer 236 to cause reshaping or reflowing to form a reshaped epitaxial layer 2360 . Fig.58 The reflowable epitaxial layer 236 is shown reshaped over the interface epitaxial layer 237 which does not merge over the interior spacer features 234 . Fig.59 The reflowable epitaxial layer 236 is shown reshaped over the interface epitaxial layer 237, which merges over and continues across the interior spacer features 234. Fig.58 and Fig.59 In the embodiment of the present invention, the reshaped epitaxial layer 2360 may include two opposite flat surfaces 236F that are substantially perpendicular to the substrate 202. Fig.58 and Fig.59As shown, the planar surface 236F of the reshaped epitaxial layer 2360 extends substantially along the depth of the source / drain trenches 228 , allowing unimpeded access to the bottom surface of the reshaped epitaxial layer 2360 .

[0098] refer to Fig.52 , Fig.60 and Fig.61 , the method 550 includes a block 516, in which a low resistance epitaxial layer 238 is formed on the reshaped epitaxial layer 2360. After the reflowable epitaxial layer 236 is reshaped at block 514, the low resistance epitaxial layer 238 is selectively deposited from the surface of the reshaped epitaxial layer 2360. In some embodiments, the low resistance epitaxial layer 238 may be deposited using vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. Compared to the reflowable epitaxial layer 236, the low resistance epitaxial layer 238 includes a greater dopant concentration to reduce parasitic resistance. Since the reshaped epitaxial layer 2360 includes a flat surface, rather than an uneven shape, the low resistance epitaxial layer 238 is less likely to merge prematurely to form voids in the low resistance epitaxial layer 238. Unlike the reflowable epitaxial layer 236, the low resistance epitaxial layer 238 is not subjected to a heat treatment for reshaping. In one embodiment, the low resistance epitaxial layer 238 does not contain germanium. In an alternative embodiment, the low resistance epitaxial layer 238 includes silicon (Si) and carbon (C), wherein the carbon content in the low resistance epitaxial layer 238 is less than 2%. The low resistance epitaxial layer 238 includes an n-type dopant, such as arsenic (As), phosphorus (P), antimony (Sb), or a combination thereof. In terms of doping concentration, the arsenic (As) concentration in the low resistance epitaxial layer 238 may be less than 5×10 21 Atom / cm 3 The phosphorus (P) concentration in the low resistance epitaxial layer 238 may be less than 5×10 21 Atom / cm 3 , and the antimony (Sb) concentration in the low resistance epitaxial layer 238 may be less than 5×10 21 Atom / cm 3 In terms of dopant composition, the phosphorus (P) doping concentration in the low resistance epitaxial layer 238 is greater than the phosphorus (P) doping concentration in the reflowable epitaxial layer 236 to reduce parasitic resistance. When both the low resistance epitaxial layer 238 and the reflowable epitaxial layer 236 include arsenic and / or antimony, the doping concentration of arsenic and / or antimony in the reflowable epitaxial layer 236 is greater than the doping concentration of arsenic and / or antimony in the low resistance epitaxial layer 238 because the reflowable epitaxial layer 236 is closer to the channel.

[0099] like Fig.60 and Fig.61As shown, the low-resistance epitaxial layer 238 extends vertically into the reshaped epitaxial layer 2360 along the flat surface 236F. The low-resistance epitaxial layer 238 also extends vertically between a plurality of horizontally aligned channel layers 208, and the channel layers 208 will be released as Fig.14 the channel member 2080 shown. The low-resistance epitaxial layer 238 is spaced from the end faces of the channel layers 208 by the reshaped epitaxial layer 2360 and the interfacial epitaxial layer 237. The interfacial epitaxial layer 237, the reshaped epitaxial layer 2360, and the low-resistance epitaxial layer 238 are vertically spaced from the bottom epitaxial layer 232 by the bottom dielectric layer 2350 and the bottom gap 2390. When the method 550 is employed, the source / drain feature 240 includes the interfacial epitaxial layer 237, the reshaped epitaxial layer 2360, and the low-resistance epitaxial layer 238. The bottom epitaxial layer 232 is spaced from the source / drain feature 240 by the bottom dielectric layer 2350 and the bottom gap 2390.

[0100] In one exemplary aspect, the present disclosure relates to a method. The method includes: forming a fin structure over a substrate, the fin structure including a plurality of channel layers interleaved with a plurality of sacrificial layers; recessing source / drain regions of the fin structure to form source / drain recesses that expose a portion of the substrate and sidewalls of the plurality of channel layers; selectively and partially recessing sidewalls of the plurality of sacrificial layers to form inner spacer recesses; forming inner spacers in the inner spacer recesses; forming a bottom dielectric layer to cover the exposed portion of the substrate; depositing a first epitaxial layer over the inner spacers and the exposed sidewalls of the plurality of channel layers; performing a heat treatment to reshape the first epitaxial layer; and, after performing the heat treatment, depositing a second epitaxial layer over the first epitaxial layer. The first epitaxial layer includes germanium, and the second epitaxial layer is germanium-free.

[0101] In some embodiments, the first epitaxial layer further includes silicon and at least one n-type dopant. In some embodiments, the heat treatment includes a temperature between about 600 °C and about 800 °C. In some embodiments, the second epitaxial layer includes silicon, carbon, and at least one n-type dopant. In some embodiments, prior to performing the heat treatment, the first epitaxial layer includes wavy sidewalls. After performing the heat treatment, the wavy sidewalls become flat sidewalls. In some instances, after depositing the second epitaxial layer, a bottom surface of the second epitaxial layer is spaced from the bottom dielectric layer by a gap. In some embodiments, the method further includes: depositing an interfacial epitaxial layer on the inner spacers and the exposed sidewalls of the plurality of channel layers prior to depositing the first epitaxial layer. In some embodiments, the interfacial epitaxial layer is germanium-free. In some embodiments, the interfacial epitaxial layer includes silicon, carbon, and at least one n-type dopant.

[0102] In another exemplary aspect, the present disclosure relates to a method. The method includes: forming a fin structure on a substrate, the fin structure including a plurality of channel layers interlaced with a plurality of sacrificial layers; recessing a source / drain region of the fin structure to form a source / drain recess, the source / drain recess exposing a portion of the substrate and a sidewall of the plurality of channel layers; selectively and partially recessing the sidewalls of the plurality of sacrificial layers to form an internal spacer recess; forming an internal spacer in the internal spacer recess; forming a bottom epitaxial layer to cover the exposed portion of the substrate; depositing a first epitaxial layer on the exposed sidewalls of the internal spacer and the plurality of channel layers; performing a thermal treatment to reshape the first epitaxial layer; and after performing the thermal treatment, depositing a second epitaxial layer on the first epitaxial layer. The first epitaxial layer includes germanium, and the second epitaxial layer does not contain germanium.

[0103] In some embodiments, the bottom epitaxial layer includes silicon or silicon germanium. In some implementations, the first epitaxial layer also includes silicon and at least one n-type dopant. In some embodiments, the thermal treatment includes a temperature between about 600° C. and about 800° C. In some embodiments, the second epitaxial layer includes silicon, carbon, and at least one n-type dopant. In some embodiments, the method further includes: before depositing the first epitaxial layer, depositing an interface epitaxial layer on the exposed sidewalls of the internal spacer and the plurality of channel layers. The interface epitaxial layer does not contain germanium.

[0104] In another exemplary aspect, the present disclosure relates to a semiconductor structure. The semiconductor structure includes: a base fin protruding from a substrate; a first plurality of nanostructures disposed above a first channel region of the base fin; a second plurality of nanostructures disposed above a second channel region of the base fin; and a source / drain feature disposed between and in contact with the first plurality of nanostructures and the second plurality of nanostructures. The source / drain feature includes: a bottom epitaxial layer extending into the base fin, a first epitaxial layer in direct contact with the first plurality of nanostructures, the second plurality of nanostructures, and the bottom epitaxial layer, a second epitaxial layer disposed above the first epitaxial layer, and a third epitaxial layer disposed above the second epitaxial layer. The first epitaxial layer and the third epitaxial layer do not contain germanium, and the second epitaxial layer includes germanium.

[0105] In some embodiments, the second epitaxial layer includes two flat surfaces to join the third epitaxial layer. In some embodiments, the two flat surfaces span at least two nanostructures in the first plurality of nanostructures and at least two nanostructures in the second plurality of nanostructures in a vertical direction. In some embodiments, a portion of the third epitaxial layer extends between at least two nanostructures in the first plurality of nanostructures and at least two nanostructures in the second plurality of nanostructures. In some embodiments, the bottom epitaxial layer includes silicon or silicon germanium.

[0106] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. It should be appreciated by those skilled in the art that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments introduced herein. It should also be appreciated by those skilled in the art that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A method comprising: forming a fin structure over a substrate, the fin structure comprising a plurality of channel layers interleaved with a plurality of sacrificial layers; Recessing the source / drain region of the fin structure to form a source / drain recess, the source / drain recess exposing a portion of the substrate and sidewalls of the plurality of channel layers; selectively and partially recessing sidewalls of the plurality of sacrificial layers to form inner spacer recesses; forming an internal spacer in the internal spacer recess; forming a bottom dielectric layer to cover the exposed portion of the substrate; depositing a first epitaxial layer over the inner spacers and exposed sidewalls of the plurality of channel layers; performing a thermal treatment to reshape the first epitaxial layer; After performing the heat treatment, depositing a second epitaxial layer on the first epitaxial layer, wherein the first epitaxial layer comprises germanium, Wherein, the second epitaxial layer does not contain germanium.

2. The method according to claim 1, wherein: The first epitaxial layer also includes silicon and at least one n-type dopant.

3. The method according to claim 1, wherein: The thermal treatment includes a temperature between about 600°C and about 800°C.

4. The method according to claim 1, wherein: The second epitaxial layer includes silicon, carbon, and at least one n-type dopant.

5. The method according to claim 1, in, Before performing the heat treatment, the first epitaxial layer comprises a wavy sidewall. After the heat treatment is performed, the wavy sidewall becomes a flat sidewall.

6. The method according to claim 1, wherein: After depositing the second epitaxial layer, a bottom surface of the second epitaxial layer is spaced apart from the bottom dielectric layer by a gap.

7. The method according to claim 1, further comprising: Prior to depositing the first epitaxial layer, an interfacial epitaxial layer is deposited on exposed sidewalls of the inner spacers and the plurality of channel layers.

8. The method according to claim 7, wherein: The interface epitaxial layer does not contain germanium.

9. A method comprising: forming a fin structure over a substrate, the fin structure comprising a plurality of channel layers interleaved with a plurality of sacrificial layers; Recessing the source / drain region of the fin structure to form a source / drain recess, the source / drain recess exposing a portion of the substrate and sidewalls of the plurality of channel layers; selectively and partially recessing sidewalls of the plurality of sacrificial layers to form inner spacer recesses; forming an internal spacer in the internal spacer recess; forming a bottom epitaxial layer to cover the exposed portion of the substrate; depositing a first epitaxial layer over the inner spacers and exposed sidewalls of the plurality of channel layers; performing a thermal treatment to reshape the first epitaxial layer; After performing the heat treatment, depositing a second epitaxial layer on the first epitaxial layer, wherein the first epitaxial layer comprises germanium, Wherein, the second epitaxial layer does not contain germanium. Wherein, the interface epitaxial layer does not contain germanium.

10. A semiconductor structure comprising: a basal fin protruding from the substrate; a first plurality of nanostructures disposed over a first channel region of the substrate fin; a second plurality of nanostructures disposed over a second channel region of the substrate fin; as well as a source / drain feature disposed between and in contact with the first plurality of nanostructures and the second plurality of nanostructures, Wherein, the source / drain characteristics include: a bottom epitaxial layer extending into the substrate fin, a first epitaxial layer in direct contact with the first plurality of nanostructures, the second plurality of nanostructures, and the bottom epitaxial layer, a second epitaxial layer disposed on the first epitaxial layer, and A third epitaxial layer is disposed on the second epitaxial layer, wherein the first epitaxial layer and the third epitaxial layer do not contain germanium, and wherein the second epitaxial layer includes germanium.

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