Integrated circuit device and method of forming same

Abstract

The embodiment of the invention provides a method of forming an integrated circuit device and an integrated circuit device. The method includes forming a stack including a nanostructure channel, an interposer, and a hard mask structure by forming source / drain openings. The method further includes forming a sacrificial gate structure on the stack and forming a spacer layer adjacent the sacrificial gate structure. The method further includes releasing the nanostructure channel by removing the interposer, and forming a gate dielectric on the nanostructure channel and a side surface of the spacer layer. The method further includes forming a reduced gate dielectric by removing portions of the gate dielectric from side surfaces of the spacer layer, portions laterally adjacent the nanostructure channel, and forming a gate metal layer on the reduced gate dielectric and exposed portions of the spacer layer.

Description

Technical Field

[0001] Embodiments of the present application relate to integrated circuit devices and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each smaller and more complex than the previous one. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. This shrinking has also increased the complexity of processing and manufacturing ICs. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a method for forming an integrated circuit device is provided, comprising: forming a stack including a nanostructure channel, an interposer and a hard mask structure by forming source / drain openings; forming a sacrificial gate structure on the stack; forming a spacer layer adjacent to the sacrificial gate structure; releasing the nanostructure channel by removing the interposer layer; forming a gate dielectric on the side surfaces of the nanostructure channel and the spacer layer; forming a reduced gate dielectric by removing a portion of the gate dielectric from the side surfaces of the spacer layer, the portion being laterally adjacent to the nanostructure channel; and forming a gate metal layer on the exposed portions of the reduced gate dielectric and the spacer layer.

[0004] According to another aspect of an embodiment of the present application, a method for forming an integrated circuit device is provided, comprising: forming a stack including alternating nanostructure channels and interposer layers by forming source / drain openings extending through alternating first and second semiconductor layers; releasing the nanostructure channels by removing the interposer layers; forming a gate dielectric on the nanostructure channels and on the side surfaces of the spacer layers, the gate dielectric extending from a first level above the nanostructure channels to a second level below the nanostructure channels; forming protection plugs between the nanostructure channels; selectively growing protection structures on exposed surfaces of the protection plugs; and removing portions of the gate dielectric exposed by the protection plugs.

[0005] According to another aspect of an embodiment of the present application, an integrated circuit device is provided, comprising: a first nanostructure stack; a second nanostructure stack, adjacent to the first nanostructure stack along a first direction; a source / drain, adjacent to the first nanostructure stack along a second direction transverse to the first direction; and a gate structure, surrounding the first nanostructure stack, the gate structure comprising: a gate dielectric, comprising: a first portion, extending between nanostructures of the first nanostructure stack; and a second portion, extending between nanostructures of the second nanostructure stack, the first portion and the second portion being discontinuous in a region between the first nanostructure stack and the second nanostructure stack along the first direction; and a gate metal, located on the gate dielectric, the gate metal extending between the first nanostructure stack, between the second nanostructure stack, and between the first nanostructure stack and the second nanostructure stack continuously located in a region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustration purposes only. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1A and Figure 1B is a schematic cross-sectional side view of a portion of an IC device according to an embodiment of the present disclosure.

[0008] Figure 2A-Figure 17 are views of various embodiments of IC devices at different stages of fabrication in accordance with various aspects of the present disclosure.

[0009] Fig.18 is a flow chart of a method of forming an IC device according to various embodiments. DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for realizing different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0011] In addition, for ease of description, spacing relation terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. In addition to the orientation shown in the figures, the spacing relation terms are intended to encompass different orientations of the device in use or operating processes. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spacing relation descriptors used herein should be interpreted accordingly.

[0012] Terms expressing relative degrees, such as "about", "substantially", etc., should be interpreted as terms that would be understood by a person of ordinary skill in the art based on the current technical specifications.

[0013] The terms "first", "second", and "third", etc. may be used herein to describe a sequence of events or a sequence of elements, but may be interchangeable or varied in some cases. For example, the second layer may be formed on the first layer (e.g., sequentially after the first layer), but in some cases, the first layer may be referred to as the "second layer", "third layer", or "fourth layer", etc., and the second layer may also be referred to as the "first layer", "third layer", or "fourth layer", etc.

[0014] The term "surrounding" may be used to describe a structure that completely or partially surrounds another element or structure, for example, in three dimensions. For example, a first structure may "surround" a second structure on four lateral sides (e.g., left side, right side, front side, and back side) without surrounding the second structure on two vertical sides (e.g., top and bottom). In another example, a first structure may partially wrap around a second structure, for example, by wrapping around three sides (e.g., top, front side, and back side) while leaving other sides (e.g., left side, right side, and bottom) exposed.

[0015] The source / drain regions may be referred to individually or collectively as a source or a drain, depending on the context.

[0016] The present disclosure generally relates to semiconductor devices, and more specifically to field effect transistors (FETs), such as planar FETs, three-dimensional fin FETs (FinFETs), or nanostructured FETs, such as nanosheet FETs (NSFETs), nanowire FETs (NWFETs), gate-all-around FETs (GAAFETs), and the like.

[0017] Improvement of nanostructured device performance under complex device architectures and extreme scaling rules is a challenge for nanosheet FETs. For example, reduction of gate-to-drain capacitance (Cgd) can improve device speed and power efficiency. Including sidewall spacers with low dielectric materials is beneficial for reducing capacitance (Ceff) and improving device performance. However, a gate-last process that forms an active replacement gate after forming the sidewall spacers may result in a significant increase in Cgd. For example, a high-k gate dielectric layer that is advantageously formed over the active semiconductor channel is also formed to cover the entire sidewall spacer.

[0018] In an embodiment of the present disclosure, a high-k gate dielectric layer is selectively removed from the sidewall spacers to reduce Cgd while maintaining the high-k gate dielectric layer internal spacers to reduce or eliminate gate leakage and reliability degradation. Due to the removal of the high-k gate dielectric layer from the sidewall spacers, cell size shrinkage can be improved by increasing the top gate length. Due to the increased volume of the gate metal gap fill, the gate resistance Rg can be reduced.

[0019] The nanostructure transistor structure can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes to allow the creation of patterns with, for example, a pitch smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructure.

[0020] Figure 1A and Figure 1B is a schematic cross-sectional side view of a portion of a nanostructured device 10 according to various embodiments. Figure 1A The view in the XZ plane is shown. Figure 1B The view in the YZ plane orthogonal to the XZ plane is shown. Figure 1A , Figure 1B 10 of nanostructured devices to provide understanding Figure 2A-Figure 18 Background of the technical features and benefits of the various embodiments shown in .

[0021] refer to Figure 1A, nanostructure devices 20A, 20B may be or include one or more N-type FETs (NFETs) or P-type FETs (PFETs). For example, nanostructure device 20A may be a PFET, and nanostructure device 20B may be an NFET. Nanostructure devices 20A, 20B are formed on and / or in substrate 110, and generally include a gate structure 200 that spans and / or surrounds semiconductor channels 22A, 22B, 22C (also referred to as "nanostructures"), and is located above semiconductor fins 32 that protrude from and are separated by isolation structures 36 (see FIG. 1 ). Figure 1B ). The semiconductor channels 22A, 22B, and 22C may be collectively referred to as channels 22. The gate structure 200 controls the current flowing through the channels 22A, 22B, and 22C.

[0022] The nanostructured devices 20A, 20B shown include three channels 22A, 22B, 22C, which are laterally adjacent to the source / drain features 82N, 82P and are covered and surrounded by the gate structure 200. Typically, the number of channels 22 is two or more, such as three or four or more, but can be one in some embodiments. The gate structure 200 controls the flow of current through the channels 22A, 22B, 22C to and from the source / drain features 82N, 82P based on the voltage applied to the gate structure 200 and the source / drain features 82N, 82P.

[0023] In some embodiments, the fin structure 32 includes silicon. In some embodiments, the nanostructure device 20B includes an NFET whose source / drain features 82N include silicon phosphorus (SiP), SiAs, SiSb, SiPAs, SiP:As:Sb, SiGe, combinations thereof, etc. In some embodiments, the nanostructure device 20A includes a PFET whose source / drain features 82P include undoped or doped silicon germanium (SiGe) to form, for example, SiGe:B, SiGe:B:Ga, SiGe:Sn, SiGe:B:Sn, or another suitable semiconductor material. In general, the source / drain features 82N, 82P may include any combination of suitable semiconductor materials and suitable dopants.

[0024] Channels 22A, 22B, and 22C each include a semiconductor material, such as silicon or a silicon compound, such as silicon germanium. In some embodiments, channel 22 is or includes one or more of a semiconductor or a semiconductor alloy, such as Si, SiGe, Ge, GaAs, InGaAs, SiGeSn, GeSn, a two-dimensional material with semiconductor properties, such as MoS 2 , WS 2and combinations thereof. Channels 22A, 22B, 22C are nanostructures (e.g., having at least one dimension in the range of several nanometers), and each channel may also have an elongated shape and extend in the X direction. In some embodiments, channels 22A, 22B, 22C each have a nanowire (NW) shape, a nanosheet (NS) shape, a nanotube (NT) shape, or other suitable nanoscale shapes. The cross-sectional profile of channels 22A, 22B, 22C may be rectangular, circular, square, annular, elliptical, hexagonal, or a combination thereof.

[0025] In some embodiments, the lengths of the channels 22A, 22B, 22C (eg, measured in the X direction) may be different from each other, for example, due to tapering in the fin etching process (see Figure 3A , Figure 3B ). In some embodiments, the length of channel 22C may be less than the length of channel 22B, and the length of channel 22B may be less than the length of channel 22A. For example, due to a channel trimming process used to expand the spacing between channels 22A, 22B, 22C (e.g., measured in the Z-axis direction) to increase the gate structure manufacturing process window, channels 22A, 22B, 22C may not each have a uniform thickness (e.g., along the X-axis direction). For example, the middle portion of each of channels 22A, 22B, 22C may be thinner than the ends of each of channels 22A, 22B, 22C. This shape may be collectively referred to as a "dog bone" shape.

[0026] In some embodiments, the spacing between channels 22A, 22B, 22C (e.g., between channel 22B and channel 22A or channel 22C) is in a range between about 1 nanometer (nm) and about 15 nm, such as between about 5.5 nm and about 10 nm, although ranges above or below the above ranges may also be beneficial. In some embodiments, the thickness of each of channels 22A, 22B, 22C (e.g., measured in the Z direction) is in a range between about 1 nm and about 10 nm, although ranges above or below the above ranges may also be beneficial. In some embodiments, the width of each of channels 22A, 22B, 22C (e.g., measured in the Z direction) is in a range between about 1 nm and about 10 nm, although ranges above or below the above ranges may also be beneficial. Figure 3B The width may be at least about 8 nm as measured in the Y direction as shown, orthogonal to the XZ plane, but in some embodiments the width may be less than 8 nm.

[0027] The gate structure 200 is disposed above and between the channels 22A, 22B, 22C, respectively. In some embodiments, the gate structure 200 is disposed above and between the channels 22A, 22B, 22C, which are silicon channels for N-type devices or germanium silicon channels for P-type devices. In some embodiments, the gate structure 200 includes an interfacial layer (IL) 210, one or more gate dielectric layers 600 on the interfacial layer 210, and a metal core layer 290 on the gate dielectric layer 60. Additional layers, such as one or more work function tuning layers 900 (see Fig.16 ), which may exist on the gate dielectric layer 600 between the gate dielectric layer 600 and the metal core layer 290.

[0028] An interfacial layer 210 is formed on the exposed areas of the channels 22A, 22B, 22C and the top surface of the fin 32. The interfacial layer 210 may be an oxide of the material of the channels 22A, 22B, 22C. The interfacial layer 210 promotes adhesion of the gate dielectric layer 600 to the channels 22A, 22B, 22C. In some embodiments, the thickness of the interfacial layer 210 is about 5 angstroms. to about In some embodiments, the thickness of the interface layer 210 is about An interface layer 210 that is too thin may have voids or insufficient adhesion. An interface layer 210 that is too thick may consume the gate fill window, which is related to threshold voltage tuning and resistance. In some embodiments, the interface layer 210 is doped with a dipole, such as lanthanum, for threshold voltage tuning.

[0029] In some embodiments, the gate dielectric layer 600 includes at least one high-k gate dielectric material, which may refer to a dielectric material having a high dielectric constant greater than the dielectric constant of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include HfO 2 , HfSiO, HfSiN, HfTaO, HfTiO, HfZrO, ZrO 2 、 2 O 5 In some embodiments, the thickness of the gate dielectric layer 600 is about to about The gate dielectric layer 600 may be a single layer or multiple layers.

[0030] In an embodiment of the present disclosure, the gate dielectric layer 600 may be a low-k dielectric layer 600S that covers only a portion of the gate spacer 41, as will be described with reference to FIG. Figure 2A-Figure 18 Reducing the area of ​​the gate dielectric layer 600 covering the gate spacers 41 can reduce the effective capacitance of the device 10 and increase the speed of the device 10 .

[0031] The gate structure 200 also includes a metal core layer 290. The metal core layer 290 may include a conductive material, such as Co, W, Ru, combinations thereof, etc. In some embodiments, the metal core layer 290 is or includes a Co, W, or Ru-based compound or an alloy containing one or more elements, such as Zr, Sn, Ag, Cu, Au, Al, Ca, Be, Mg, Rh, Na, Ir, W, Mo, Zn, Ni, K, Co, Cd, Ru, In, Os, Si, Ge, Mn, combinations thereof, etc. Between the channels 22A, 22B, 22C in the XZ plane, the metal core layer 290 is circumferentially surrounded (in the cross-sectional view) by one or more work function metal layers 900, and then circumferentially surrounded by a gate dielectric layer 600, which is circumferentially or partially surrounded by an interface layer 210.

[0032] like Figure 1A As shown, the nanostructured device 20A, 20B may also include a source / drain contact 120 formed on the source / drain features 82N, 82P. The source / drain contact 120 may include a core layer that is or includes a conductive material, such as tungsten, ruthenium, cobalt, copper, titanium, titanium nitride, tantalum, tantalum nitride, iridium, molybdenum, nickel, aluminum, or a combination thereof. The core layer may be surrounded by one or more liner (or "barrier") layers, such as SiN or TiN, which helps prevent or reduce material from diffusing from the source / drain contact 120 into the source / source contact 120. In some embodiments, the height of the source / drain contact 120 may be in the range of about 1 nm to about 50 nm.

[0033] The silicide layer 118 may be located between the source / drain components 82N, 82P and the source / source contact 120 to at least reduce the source / drain contact resistance. In some embodiments, the silicide layer 118 is or includes TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, YbSi, etc. In some embodiments, the silicide layer 118 is or includes NiSi, CoSi, MnSi, Wsi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, etc. The thickness of the silicide layer 118 may be in the range of about 1nm to about 10nm. A thickness lower than about 1nm may result in insufficient reduction of the contact resistance. A thickness greater than about 10nm may result in an electrical short circuit with the nanostructure 22. In some embodiments, the silicide layer 118 is present below the etch stop layer 131 and in contact with it.

[0034] like Figure 1BAs shown, the nanostructured devices 20A, 20B may further include an interlayer dielectric (ILD) 130. The ILD 130 provides electrical isolation between various components of the nanostructured devices 20A, 20B described above, such as between adjacent pairs of source / drain contacts 120. An etch stop layer (ESL) 131 may be formed before forming the ILD 130, and may be positioned laterally between the ILD 130 and the gate spacers 41, and vertically between the ILD 130 and the source / drain features 82N, 82P. In some embodiments, the etch stop layer 131 is or includes SiN, SiCN, SiC, SiOC, SiOCN, HfO 2 、ZrO 2 , ZrAlOx, HfAlOx, HfSiOx, Al 2 O 3 Or other suitable materials. In some embodiments, the thickness of the etch stop layer 131 is in the range of about 1 nm to about 5 nm. In some embodiments, in the absence of the ILD 130 (e.g., the ILD 130 is completely removed before forming the source / drain contact 120), the etch stop layer 131 can contact the source / source contact 120. For example, before forming the source / drain contact 120, the etch stop layer 131 can be trimmed in the X-axis direction to improve the filling quality of the source / source contact 120.

[0035] Nanostructured devices 20A, 20B include gate spacers 41 disposed on the sidewalls of metal core layer 290 above channel 22C, and internal spacers 74 disposed on the sidewalls of IL 210 and / or gate dielectric layer 600 between channels 22A, 22B, 22C. Internal spacers 74 are also disposed between channels 22A, 22B, 22C. Figure 1A In the illustrated embodiment, the gate spacer 41 includes a first spacer layer 41A and a second spacer layer 41B located on the first spacer layer 41A. The first spacer layer 41A and the second spacer layer 41B may each include a dielectric material, such as a low-k material, such as SiOCN, SiON, SiN, SiCN, SiOC, etc. In some embodiments, the second spacer layer 41B is not present. The materials of the first spacer layer 41A and the second spacer layer 41B may be the same or different from each other. In some embodiments, the upper portion of the second spacer layer 41B may be partially or completely removed (or the first spacer layer 41A may be removed when the second spacer layer 41B is not present) to increase the aspect ratio of the openings forming the source / drain regions 82N, 82P. Figure 1A An embodiment is depicted in which the upper portion of the second spacer layer 41B is not thinned.

[0036] In an embodiment of the present disclosure, the side surface of the gate spacer 41 may be substantially free of the high-k dielectric layer 600. For example, the side surface of the gate spacer 41 may have a percentage of the surface area covered by the high-k dielectric layer 600, but not completely or mostly covered by the high-k dielectric layer 600. The percentage may be in the range of about 2% to about 20%. Figure 2A-Figure 18 A method of reducing the area of ​​the high-k dielectric layer 600 covering the side surfaces of the gate spacers 41 according to various embodiments is described.

[0037] Fig.18 A flow chart of a method 1000 for forming an IC device or a portion thereof from a workpiece according to one or more aspects of the present disclosure is depicted. The method 1000 is merely an example and is not intended to limit the present disclosure to what is explicitly shown in the method 1000. Additional actions may be provided before, during, and after the method 1000, and some of the actions described may be replaced, eliminated, or moved for additional embodiments of the method. For simplicity, not all actions are described in detail. Figure 2A-Figure 17 Partial perspective views and / or cross-sectional views of a workpiece at various stages of fabrication according to an embodiment of the method 1000 are shown to describe the method 1000. For the avoidance of doubt, throughout the figures, the X direction is perpendicular to the Y direction, and the Z direction is perpendicular to the X direction and the Y direction. It should be noted that since the workpiece can be fabricated into a semiconductor device, the workpiece may be referred to as a semiconductor device as the context requires.

[0038] Figures 2A to 17 is a diagram of an intermediate stage in the fabrication of a FET (eg, a nanostructure FET) according to some embodiments.

[0039] exist Figure 2A and Figure 2B In the embodiment of the present invention, a substrate 110 is provided. The substrate 110 may be a semiconductor substrate, such as a bulk semiconductor, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The semiconductor material of the substrate 110 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, gallium aluminum arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates may be used, such as single-layer, multi-layer, or gradient substrates.

[0040] In addition, Figure 2A and Figure 2BIn the embodiment, a multilayer stack 25 or "lattice" of alternating layers of first semiconductor layers 21A, 21B (collectively referred to as first semiconductor layers 21) and second semiconductor layers 23 is formed over substrate 110. In some embodiments, first semiconductor layer 21 can be formed of a first semiconductor material, such as Si, SiGe, Ge, GaAs, InGaAs, GeSn, SiGeSn, MoS, WS 2 The second semiconductor layer 23 may be formed of a second semiconductor material, such as SiGe, Ge, Si, InGaAs, AlGaAs, GeSn, SiGeSn, etc. Each layer 21, 23 of the multilayer stack 25 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), etc. Each layer 21, 23 of the multilayer stack 25 may be formed to have a thickness in the range of about 1 nm to about 10 nm.

[0041] Three first semiconductor layers 21 and four second semiconductor layers 23 are shown. In some embodiments, the multilayer stack 25 may include a fewer or greater number of first semiconductor layers 21 and second semiconductor layers 23. Although the multilayer stack 25 is shown to include the second semiconductor layer 23 as the bottommost layer and the topmost layer, in some embodiments, the bottommost layer and / or the topmost layer of the multilayer stack 25 may be the first semiconductor layer 21.

[0042] Due to the high etching selectivity between the first semiconductor material and the second semiconductor material, the second semiconductor layer 23 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 21 of the first semiconductor material, thereby allowing the first semiconductor layer 21 to be patterned to form a channel region of a nanoFET. In some embodiments, the first semiconductor layer 21 is removed and the second semiconductor layer 23 is patterned to form a channel region. The high etching selectivity allows the first semiconductor layer 21 of the first semiconductor material to be removed without significantly removing the second semiconductor layer 23 of the second semiconductor material, thereby allowing the second semiconductor layer 23 to be patterned to form a channel region of a nanoFET.

[0043] exist Figure 2A and Figure 2B In the embodiment of the present invention, a hard mask layer 28L is formed. The hard mask layer 28L may be a dielectric layer including one or more dielectric materials, such as SiO 2 、Si 3 N 4, SiON, SiCN, SiCON, etc. The hard mask layer 28L can be formed on the uppermost second semiconductor layer 23 by an appropriate deposition process, such as chemical vapor deposition (CVD), including low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), etc. The hard mask layer 28L can be or include one or more layers of SiO, SiN, SiON, SiCN, SiOCN, etc., and its thickness is in the range of about 1 nanometer (nm) to about 10 nm.

[0044] exist Figure 3A and Figure 3B In the embodiment, the fin 32 is formed in the substrate 110, the nanostructures 22, 24 are formed in the multilayer stack 25, and the hard mask structure 28 is also formed, corresponding to Fig.18 Action 1100. In some embodiments, the nanostructures 22, 24 and the fins 32 can be formed by etching grooves in the multilayer stack 25, the hard mask layer 28L and the substrate 110. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching can be anisotropic. The first nanostructure 22A, 22B, 22C (hereinafter also referred to as the "channel 22") is formed by the first semiconductor layer 21, the second nanostructure 24 is formed by the second semiconductor layer 23, and the hard mask structure 28 is formed by the hard mask layer 28L. The distance CD1 between adjacent fins 32 and nanostructures 22, 24 can be about 18nm to about 100nm, but distances less than or greater than the range may also be beneficial and are embodiments of the present invention. To simplify the description, Figure 3A and Figure 3B A portion of a device 10 including two fins 32 is shown in FIG. Fig.18 The method 1000 shown can be extended to any number of fins and is not limited to Figure 3A-Figure 17 Two fins 32 are shown.

[0045] The fins 32 and nanostructures 22, 24 may be patterned by any suitable method. For example, one or more photolithography processes, including double patterning or multiple patterning processes, may be used to form the fins 32 and nanostructures 22, 24. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, allowing a pitch smaller than that obtained using a single direct photolithography process. As an example of a multiple patterning process, a sacrificial layer may be formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins 32.

[0046] Figure 3A and Figure 3BThe fins 32 are shown with tapered sidewalls such that the width of each fin 32 and / or nanostructure 22, 24 increases continuously in a direction toward the substrate 110. In such embodiments, each nanostructure 22, 24 may have a different width and be trapezoidal in shape. In other embodiments, the sidewalls are substantially vertical (non-tapered) such that the widths of the fins 32 and nanostructures 22, 24 are substantially similar and each nanostructure 22, 24 is rectangular in shape.

[0047] exist Figure 3A and Figure 3B In the embodiment of the present invention, an isolation region, an isolation component or an isolation structure 36 is formed adjacent to the fin 32, which may be a shallow trench isolation (STI) region, a shallow trench isolation component and a shallow trench isolation structure. The isolation region 36 may be formed by depositing an insulating material on the substrate 110, the fin 32, the nanostructures 22, 24 and the hard mask structure 28, and between adjacent fins 32, nanostructures 22, 24 and the hard mask structure 28. The insulating material may be an oxide such as silicon oxide, nitride, etc., or a combination thereof, and may be formed by high density plasma CVD (HDP-CVD), flowable CVD (FCVD), etc., or a combination thereof. In some embodiments, a liner (not shown separately) may first be formed along the surface of the substrate 110, the fin 32, the nanostructures 22, 24 and the hard mask structure 28. Thereafter, a core material such as those described above may be formed on the liner.

[0048] The insulating material undergoes a removal process, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc., to remove excess insulating material over nanostructures 22, 24 and hard mask structure 28. After the removal process is completed, the top surface of hard mask structure 28 may be exposed and flush with the insulating material.

[0049] The insulating material is then recessed to form isolation regions 36. After the recessing, the upper portions of the nanostructures 22, 24, the hard mask structure 28, and the fins 32 may protrude from between adjacent isolation regions 36. The isolation regions 36 may have a top surface that is flat, convex, concave, or a combination thereof as shown. In some embodiments, the isolation regions 36 are recessed by an acceptable etching process, such as using, for example, dilute hydrofluoric acid (dHF) to remove oxides, which is selective to the insulating material and leaves the fins 32, the hard mask structure 28, and the nanostructures 22, 24 substantially unchanged.

[0050] FIG. 2A to FIG. 3BOne embodiment of forming fins 32, hard mask structures 28, and nanostructures 22, 24 is shown (e.g., etched later). In some embodiments, fins 32, hard mask structures 28, and / or nanostructures 22, 24 are epitaxially grown or deposited in trenches in a dielectric layer (e.g., etched first). The epitaxial structure may include alternating semiconductor materials such as the first semiconductor material and the second semiconductor material as described above.

[0051] exist Figure 3A and Figure 3B In the embodiment of the present invention, appropriate wells (not shown separately) may be formed in the fins 32, nanostructures 22, 24 and / or isolation regions 36. By using a mask, n-type impurity implantation may be performed in the p-type region of the substrate 110, and p-type impurity implantation may be performed in the n-type region of the substrate 100. Example n-type impurities may include phosphorus, arsenic, antimony, etc. Example p-type impurities may include boron, boron fluoride, indium, etc. Annealing may be performed after implantation to repair implant damage and activate p-type and / or n-type impurities. In some embodiments, in-situ doping during epitaxial growth of the fins 32 and nanostructures 22, 24 may avoid separate implantations, although in-situ doping and implantation doping may be used together.

[0052] exist Figure 4A-4C In, corresponding to Fig.18 In action 1200, a dummy gate structure or sacrificial gate structure 40 is formed on the fin 32, the nanostructures 22, 24 and the hard mask structure 28. A dummy gate layer or sacrificial gate layer 45 is formed on the fin 32 and / or the nanostructures 22, 24. The sacrificial gate layer 45 can be or include a material with a high etching selectivity relative to the isolation region 36. The sacrificial gate layer 45 can be a conductive, semiconductor or non-conductive material, and can be or include amorphous silicon, polycrystalline silicon, polycrystalline silicon germanium, metal nitride, metal silicide, metal oxide and metal. The sacrificial gate layer 45 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition or other techniques for depositing selected materials. The mask layer 47 is formed on the sacrificial gate layer 45 and can include, for example, silicon nitride, silicon oxynitride, etc. In some embodiments, a gate dielectric layer or "liner layer" 43 is formed before the sacrificial gate layer 45 and is formed between the sacrificial gate layer 45 and the fin 32 and / or nanostructures 22, 24. In some embodiments, the liner layer 43 is or includes one or more dielectric materials, such as Si 3 N 4 、SiO 2, SiON, etc., and one or more semiconductors, including Si, SiGe, combinations thereof, etc. The thickness of the liner layer 43 can range from about 0.5 nm to about 10 nm. In some embodiments, the mask layer 47 includes a first mask layer 47A in contact with the sacrificial gate layer 45, and a second mask layer 47B covering and in contact with the first mask layer 47A. The first mask layer 47A can be or include the same or different material as the second mask layer 47B. In some embodiments, before forming the gate dielectric layer 43, the nanostructures 24 can be removed, and then a dielectric layer or an oxide layer can be gap-filled to replace the nanostructures 24.

[0053] A spacer layer 41 is formed on the sidewalls of the mask layer 47 and the sacrificial gate layer 45. As Figure 4A shown, the lower portion of the spacer layer 41 extends downward between adjacent stacks of nanostructures 22, 24 and can land on the upper surface of the isolation region 36. According to some embodiments, the spacer layer 41 is or includes an insulating material, such as SiCON, SiON, SiOF, Si 3 N 4 , SiO 2 , etc., and can have a single-layer structure or a multi-layer structure including multiple dielectric layers. The spacer layer 41 can be formed by depositing a spacer material layer (not shown) above the mask layer 47 and the sacrificial gate layer 45. According to some embodiments, an anisotropic etching process is used to remove portions of the spacer material layer between the sacrificial gate structures 40. In some embodiments, as Figure 4B , Figure 4C shown in detail, the spacer layer 41 includes a first spacer layer 41A in contact with the nanostructures 22C, the gate dielectric layer 43, the sacrificial gate layer 45, and the first and second mask layers 47A, 47B. A second spacer layer 41B of the spacer layer 41 can be in contact with the first spacer layer 41A. The first spacer layer 41A can be or include the same or different material as the second spacer layer 41B. The thickness of the spacer layer 41 can range from about 2 nm to about 20 nm.

[0054] In Figure 5A-5C , by performing an etching process to etch portions of the protruding fins 32, the hard mask structure 28, and / or the nanostructures 22, 24 that are not covered by the sacrificial gate structure 40, source / drain openings 59 are formed. The recess can be anisotropic such that portions of the fins 32 directly below the sacrificial gate structure 40 and the spacer layer 41 are protected and are substantially not etched. According to some embodiments, the top surface of the recessed fins 32 can be substantially coplanar with the top surface of the isolation region 36. According to some other embodiments, as Figure 5A and Figure 5C shown, the top surface of the recessed fins 32 can be lower than the top surface of the isolation region 36. For simplicity, Figure 5AThree vertical stacks of nanostructures 22, 24 after the etching process are depicted. In general, the etching process may be used to form fewer or more vertical stacks of nanostructures 22, 24 than shown above the fin 32. In some embodiments, the second mask layer 47B is exposed after the etching process, for example, due to the removal of upper portions of the spacer layers 41A, 41B during the etching process. Figure 5C Fin spacers 41F are depicted, which are portions of the first and / or second spacer layers 41A, 41B over the isolation regions 36 adjacent to the respective fins 32 .

[0055] exist Fig. 6A and Figure 6B In the process, recess 64 is formed by removing the end of nanostructure 24. For example, a selective etching process is performed to recess the end of nanostructure 24 exposed by source / drain opening 59 without substantially attacking nanostructure 22 or slightly thinning the end of nanostructure 22. After the selective etching process, recess 64 is formed at the location where the removed end of nanostructure 24 was previously located. Then, after recess 64 is formed, internal spacer 74L is formed to fill (partially or completely) the recess in nanostructure 24 formed by the previous selective etching process. Internal spacer 74L can be a suitable dielectric material, such as SiO 2 、Si 3 N 4 , SiON, SiCN, SiCON, etc., are formed by a suitable deposition method, such as PVD, CVD, ALD, etc.

[0056] exist Fig. 7A and Figure 7B In the embodiment, after forming the inner spacer 74L, an etching process, such as an anisotropic etching process, is performed to remove the portion of the inner spacer layer 78L located outside the recess (e.g., on the sidewalls of the nanostructure 22 and the fin 32). The remaining portion of the inner spacer 74L (e.g., the portion disposed within the recess in the nanostructure 24) forms the inner spacer 74. The thickness of the inner spacer 74 may be in the range of about 1 nm to about 10 nm. The thickness may refer to Fig. 7A The thickness in the X-axis direction shown in Fig. 7A The thickness in the Z-axis direction shown in , or both thicknesses.

[0057] In reference 6A to 7BIn the description of forming the internal spacers 74 provided, the internal spacers 74 are formed in the recesses 64 adjacent to the nanostructures 24 between the channels 22 and between the topmost channels 22C and the hard mask structure 28. In some embodiments, before forming the internal spacers 74L, the hard mask structure 28 may be recessed (e.g., removing the ends of the hard mask structure 28) in the same or different etching process as the etching process used to form the recesses 64. Then, during the process of forming the internal spacers 74 adjacent to the recessed nanostructures 24, additional internal spacers may be formed adjacent to the recessed hard mask structure 28. The internal spacers directly adjacent to the hard mask structure 28 have a different etching selectivity than the hard mask structure 28, which is beneficial in providing electrical isolation between the gate structure 200 and the adjacent source / drain 82P, 82N that may replace the hard mask structure 28. Fig. 6A and Fig. 7A The locations of the recesses and internal spacers adjacent to the hard mask structure 28 are depicted in dashed lines in FIG.

[0058] exist Fig. 8A In the embodiment of the present invention, a first semiconductor layer 110A is formed in the source / drain opening 59. In some embodiments, the first semiconductor layer 110A is an undoped silicon layer that can be deposited or epitaxially grown on the exposed surface of the fin 32. The deposition can include one or more operations, such as CVD (which can be ultra-high vacuum chemical vapor deposition (UHV-CVD)), which allows for improved control of the deposition rate and purity of the first semiconductor layer 110A. In some embodiments, a precursor gas containing silicon can be introduced into the processing chamber, and the reaction between them forms a silicon material, which is deposited into the source / drain opening 59. In some embodiments, the upper surface of the first semiconductor layer 110A is substantially coplanar with the upper surface of the fin 32.

[0059] exist Fig. 8AIn the embodiment shown, source / drain regions or "source / drain" 82 are formed. In the embodiment shown, source / drain regions 82 are epitaxially grown from epitaxial material. In some embodiments, source / drain regions 82 exert stress in corresponding channels 22A, 22B, 22C, thereby improving performance. Source / drain regions 82 are formed so that each sacrificial gate structure 40 is disposed between corresponding adjacent pairs of source / drain regions 82. In some embodiments, spacer layer 41 separates source / drain regions 82 from sacrificial gate layer 45 by an appropriate lateral distance to prevent electrical bridging to the gate of a subsequently formed device. Source / drain regions 82 may be or include Si:B, Si:Ga, SiGe:B, SiGe:B:Ga, SiGe:Sn, Si Ge:B:Sn, etc. Source / drain regions 82 may be or include SiP, SiAs, SiSb, SiPAs, SiP:As:Sb, etc. The source / drain region 82 may apply compressive or tensile stress in the channel region. The source / drain region 82 may have a surface protruding from a corresponding surface of the first semiconductor layer 110A and may have a facet. In some embodiments, adjacent source / drain regions 82 may be merged to form a single source / drain region 82 adjacent to two adjacent fins 32.

[0060] exist Fig. 8A and Figure 8B In the embodiment, after forming the source / drain regions 82, an ILD 130 covering the source / drain regions 82 and adjacent to the spacer layer 41 may be formed. In some embodiments, the ESL 131 is formed before forming the ILD 130. The ESL 131 may be formed by depositing a conformal thin layer of a dielectric material different from the ILD 130, such as SiN, SiCN, SiC, SiOC, SiOCN, HfO 2 、ZrO 2 , ZrAlOx, HfAlOx, HfSiOx, Al 2 O 3 Or one or more of other suitable materials. After depositing ESL 131, ILD 130 may be deposited by a suitable process, such as a blanket deposition process, including PVD, CVD, ALD, etc. The material of ILD 130 may include silicon dioxide or a low-k dielectric material (e.g., a material having a dielectric constant (k value) lower than the k value of silicon dioxide (about 3.9)). The low-k dielectric material may include silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), silicon oxycarbide (SiO x C y), spin-on glass (SOG), or a combination thereof. The ILD 130 may be deposited by spin coating, CVD, flowable CVD (FCVD), PECVD, PVD, or other deposition processes.

[0061] Figures 9A-15F is a view depicting the formation of the gate structure 200 having the high-k dielectric layer 600S reduced in size by a selective etching process that removes portions of the high-k dielectric layer 600 from side surfaces of the spacer layer 41 .

[0062] exist Figure 9A-9C In the embodiment, after forming the source / drain 82, the ESL 131, and the ILD 130, a planarization process, such as a chemical mechanical polishing (CMP) process, may be performed on the ILD 130 and the ESL 131. In the planarization process, portions of the hard masks 47A, 47B and the gate spacer 41 are also removed. After the planarization process, the sacrificial gate layer 45 is exposed. The top surfaces of the ILD 130 and the ESL 131 may be coplanar with the top surfaces of the sacrificial gate layer 45 and the gate spacer 41.

[0063] Next, if Figure 9A-9C As shown, the sacrificial gate layer 45 is removed in the etching process, thereby forming an opening 92. In some embodiments, the sacrificial gate layer 45 is removed by an anisotropic dry etching process. For example, the etching process may include a wet etching process or a dry etching process using a reactive gas that selectively etches the sacrificial gate layer 45 without etching the spacer layer 41. The sacrificial gate dielectric 43 (when present) may be used as an etch stop layer when etching the sacrificial gate layer 45. After removing the sacrificial gate layer 45, the sacrificial gate dielectric 43 may be removed. Fig. 9B is along Fig. 9A Perspective view of section line B'-B'.

[0064] Nanostructure 24 is then removed to release nanostructure 22, corresponding to Fig.18 Action 1300. After removing nanostructure 24, nanostructure 22 forms a plurality of nanosheets extending horizontally (e.g., parallel to the main upper surface of substrate 110, such as in the XY plane). In some embodiments, nanostructure 24 is removed by a selective etching process using an etchant that is selective to the material of nanostructure 24, such that nanostructure 24 is removed without substantially attacking nanostructure 22. In some embodiments, the etching process is an isotropic etching process using an etching gas and an optional carrier gas, wherein the etching gas includes F 2 and HF, the carrier gas can be an inert gas such as Ar, He, N 2 , their combinations, etc.

[0065] In some embodiments, nanostructure 24 is removed and nanostructure 22 is patterned to form the channel regions of PFET and NFET. However, in some embodiments, nanostructure 24 may be removed and nanostructure 22 may be patterned to form the channel region of NFET, and nanostructure 22 may be removed and nanostructure 24 may be patterned to form the channel region of PFET. In some embodiments, nanostructure 22 may be removed and nanostructure 24 may be patterned to form the channel region of NFET, and nanostructure 24 may be removed and nanostructure 22 may be patterned to form the channel region of PFET. In some embodiments, nanostructure 22 may be removed and nanostructure 24 may be patterned to form the channel region of PFET and NFET.

[0066] In some embodiments, the nanosheet 22 is reshaped (e.g., thinned) by a further etching process to improve the gate fill window. The reshaping may be performed by an isotropic etching process that is selective to the nanosheet 22. After the reshaping, the nanosheet 22 may have a dog-bone shape, wherein the middle portion of the nanosheet 22 is thinner than the peripheral portion of the nanosheet 22 along the X direction.

[0067] exist Figures 10A-15G In the embodiment, the gate structure 200 is formed in the gate opening 92. To provide a background for understanding the embodiment in which the high-k dielectric layer 600 is reduced to form the reduced high-k dielectric layer 600S, reference is now made to Fig.16 Materials and processes used to form the various layers of the gate structure 200 are described.

[0068] Fig.16 Detailed view of the portion of the gate structure 200 between the channels 22B and 22C. The gate structure 200 generally includes an interfacial layer (IL, or "first IL" below) 210, at least one gate dielectric layer 600, a work function metal layer 900, and a gate fill layer 290. In some embodiments, each replacement gate 200 further includes at least one of a second interfacial layer 240 or a second work function layer 700.

[0069] refer to Fig.16 In some embodiments, the first IL 210 includes an oxide of the semiconductor material of the substrate 110, such as silicon oxide. In other embodiments, the first IL 210 may include another suitable type of dielectric material. The thickness of the first IL 210 is about to about The first IL 210 may be formed by thermal oxidation, CVD, ALD, or the like.

[0070] Still refer to Fig.16, a gate dielectric layer 600 is formed over the first IL 210. In some embodiments, the gate dielectric layer 600 is formed using an atomic layer deposition (ALD) process to precisely control the thickness of the deposited gate dielectric layer 600. In some embodiments, the ALD process is performed using about 40 to 80 deposition cycles at a temperature range of about 200° C. to about 300° C. In some embodiments, the ALD process uses HfCl 4 and / or H 2 O as a precursor. This ALD process can form the first gate dielectric layer 220 to a thickness of about to about within the range.

[0071] In some embodiments, the gate dielectric layer 600 includes a high-k dielectric material, which may refer to a dielectric material having a high dielectric constant greater than the dielectric constant of silicon oxide (k≈3.9). Exemplary high-k dielectric materials include HfO 2 , HfSiO, HfSiN, HfTaO, HfTiO, HfZrO, ZrO 2 、 2 O 5 or a combination thereof. In other embodiments, the gate dielectric layer 600 may include a non-high-k dielectric material, such as silicon oxide. In some embodiments, the gate dielectric layer 600 includes more than one high-k dielectric layer, at least one of the high-k dielectric layers includes a dopant, such as lanthanum, magnesium, yttrium, etc., which can be driven in by an annealing process to modify the threshold voltage of the nanostructured device 20A, 20B. In an embodiment of the present disclosure, the gate dielectric layer 600 is reduced to form a reduced gate dielectric layer 600S.

[0072] Further references Fig.16, an optional second IL 240 is formed on the gate dielectric layer 600 (or the reduced gate dielectric layer 600S), and a second work function layer 700 is formed on the second IL 240. The second IL 240 promotes better metal gate adhesion on the gate dielectric layer 600. In many embodiments, the second IL 240 also provides improved thermal stability for the gate structure 200 and is used to limit the diffusion of metal impurities from the work function metal layer 900 and / or the work function metal layer 700 into the gate dielectric layer 600. In some embodiments, the formation of the second IL 240 is achieved by first depositing a high-k capping layer (not shown for simplicity) on the gate dielectric layer 600. In various embodiments, the high-k capping layer includes one or more of the following: HfSiON, HfTaO, HfTiO, HfAlON, HfSrO or other suitable materials. In one embodiment, the high-k capping layer includes titanium silicon nitride (TiSiN). In some embodiments, the high-k capping layer is deposited by ALD using about 40 to about 100 cycles at a temperature of about 400 degrees Celsius to about 450 degrees Celsius. Thermal annealing is then performed to form the second IL 240, which in some embodiments may be or include TiSiNO. After the second IL 240 is formed by thermal annealing, an atomic layer etch (ALE) controlled by artificial intelligence (AI) may be cyclically performed to remove the high-k capping layer while substantially not removing the second IL 250. Each cycle may include WCl 5 A first pulse of , followed by an Ar purge, followed by an O 2 A second pulse of 200 μA is then followed by another Ar purge. The high-k capping layer is removed to increase the gate fill window for further multi-threshold voltage tuning by metal gate patterning.

[0073] In addition, Fig.16 In some embodiments, after forming the second IL 240 and removing the high-k capping layer, a work function metal layer 700 is optionally formed on the middle gate structure 200 (e.g., on the second ILD 240 or the reduced high-k dielectric layer 600S). The work function metal layer 700 is or includes a metal nitride, such as TiN, WN, MoN, TaN, etc. In a specific embodiment, the work function metal layer 700 is TiN. The thickness of the work function metal layer 700 can range from about 100 Å to about 500 Å. To date The inclusion of the work function metal layer 700 provides additional threshold voltage tuning flexibility. Generally, the work function metal layer 700 increases the threshold voltage of NFET transistor devices and decreases the threshold voltage (magnitude) of PFET transistor devices.

[0074] In some embodiments, the work function metal layer 900 is formed on the work function metal layer 700, and the work function metal layer 900 may include at least one of an N-type work function metal, an in-situ capping layer, or an oxygen barrier layer. The N-type work function metal layer is or includes an N-type metal material, such as TiAlC, TiAl, TaAlC, TaAl, etc. The N-type work function metal layer may be formed by one or more deposition methods, such as CVD, PVD, ALD, plating, and / or other suitable methods, and has a thickness of about and The in-situ capping layer is formed on the N-type work function metal layer. In some embodiments, the in-situ capping layer is or includes TiN, TiSiN, TaN or another suitable material, and has a thickness of about and The oxygen barrier layer is formed on the in-situ capping layer to prevent oxygen from diffusing into the N-type work function metal layer (which would result in an undesirable shift in the threshold voltage). The oxygen barrier layer is formed of a dielectric material that can prevent oxygen from penetrating into the N-type work function metal layer and can protect the N-type work function metal layer from further oxidation. The oxygen barrier layer may include an oxide of silicon, germanium, SiGe, or another suitable material. In some embodiments, the oxygen barrier layer is formed using ALD and has a thickness of about 100 nm. Peace The thickness between.

[0075] Fig.16 A metal core layer or "metal layer" 290 is further shown. In some embodiments, a glue layer (not separately shown) is formed between the oxygen barrier layer of the work function metal layer and the metal core layer 290. The glue layer can promote and / or enhance adhesion between the metal core layer 290 and the work function metal layer 900. In some embodiments, the glue layer can be formed of a metal nitride such as TiN, TaN, MoN, WN, or another suitable material using ALD. In some embodiments, the thickness of the glue layer is about Peace . The metal core layer 290 may be formed on the glue layer and may include a conductive material, such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or a combination thereof. In some embodiments, the metal core layer 290 may be deposited using methods such as CVD, PVD, plating, and / or other suitable processes. In some embodiments, a seam 510, which may be an air gap, is vertically formed in the metal core layer 290 between the channels 22A, 22B, and 22C. In some embodiments, the metal core layer 290 is conformally deposited on the work function metal layer 900. The seam 510 may be formed due to the merging of films deposited on the sidewalls during conformal deposition. In some embodiments, the seam 510 does not exist between adjacent channels 22A, 22B, and 22C.

[0076] In some embodiments, one or more metal layers including the core layer 290 and the work function layers 700, 900 in the PFET device may include Ti, Al, Zn, W, Nb, Co, etc., and the total thickness of the metal layer combination on the gate dielectric layer 600 may be in the range of about 0.5 nm to about 20 nm. In some embodiments, one or more metal layers including the core layer 290 and the work function layers 700, 900 in the NFET device may include Ti and / or Al, etc., and the total thickness of the metal layer combination on the gate dielectric layer 600 may be in the range of about 0.5 nm to about 20 nm. In some embodiments, one or more of the second IL 240, the work function layer 700, and the work function layer 900 may be omitted.

[0077] exist Fig. 10A and Fig. 10B In the embodiment of the present invention, an interfacial layer or "IL" 210 is formed on the exposed surfaces of the channel 22 and the fin 32, similar to the embodiment of the reference Fig.16 In some embodiments, IL 210 includes an oxide of the semiconductor material of channel 22 and / or substrate 110, and may include SiO 2 , SiON, HfSiOx, LaSiOx, YSiOx, AlSiOx, etc. The IL 210 may be formed by chemical oxidation, thermal oxidation, ALD growth, etc. When the material of the channel 22 is different from the material of the fin 32, the material of the IL 210 on the channel 22 may be different from the material of the IL 220 on the fin 32. In some embodiments, the thickness of the IL 210 is about to about Usually, if Fig. 10A and Fig. 10B As shown, IL 210 is not present on (eg, not grown on) hard mask structure 28 or spacer layer 41 .

[0078] After the formation of IL 210, corresponding to Fig.18 In action 1400, the spacer layer 41, the hard mask layer 28, the inner spacer 74 (also Fig. 10B A high-k gate dielectric layer 600 is formed on the exposed surface of the IL 210 (shown in dashed lines in FIG. 1 ) and the IL 210 (e.g., on the channel 22 and the fin 32). The high-k gate dielectric layer 600 may be formed by one or more non-selective growth processes, such as CVD, ALD, etc., and may include one or more dielectric materials, such as HfO 2 、ZrO 2 ,La 2 O 3 、Al 2 O 3, HfZrOx, HfLaOx, HfAlOx, HfYOx, HfSiOx, HfSiON, etc. The thickness of the high-k gate dielectric layer 600 may be in the range of about 0.5 nm to about 5 nm. Fig. 10B As shown, the high-k dielectric layer 600 may completely or substantially completely cover the side surfaces of the gate spacer 41. The gate dielectric layer 600 may extend from a first level H1 above the nanostructure channel to a second level H2 below the nanostructure channel. The first level H1 may be the upper surface of the gate spacer 41, the ILD 130, and / or the ESL 131. The second level H2 may be the upper surface of the isolation region 36 and / or the fin 32. The high-k dielectric layer 600 includes a portion 600A' covering the side surfaces of the gate spacer 41, a portion 600B covering the inner spacer 74, and a portion 600C covering the channel 22 and the hard mask structure 28.

[0079] exist Fig.11A and Fig. 11B In the embodiment, after forming the high-k gate dielectric layer 600, a sacrificial interposer 500 is formed on the high-k dielectric layer 600, for example, on the spacer layer 41, the hard mask layer 28, the inner spacer 74, the channel 22 and the fin 32. The sacrificial interposer 500 can be or include a material suitable for selective growth thereon. In some embodiments, the sacrificial interposer 500 includes TiN, Si, Ge, W, Al 2 O 3 The material of the sacrificial interposer 500 is or includes a material suitable for selectively growing the same material or different materials thereon. For example, tungsten or TiN can be grown on the exposed surface of TiN. In another example, TiN can be grown on TiN or Al 2 O 3 In another example, Si, SiGe or W may be grown on the exposed surface of Si. Sacrificial interposer 500 may be formed by a suitable growth process, such as CVD, ALD, etc., and merged between trenches 22 to protect portion 600B of high-k dielectric layer 600 on inner spacer 74 and portion 600C on trench 22 and on hard mask structure 28. Sacrificial interposer 500 may or may not merge over hard mask structure 28. Fig.11A , the sacrificial interposer 500 is not merged over the hard mask structure 28, resulting in a thin layer of the sacrificial interposer 500 being present on the gate spacers 41 on both sides of the gate opening 92. The thickness of the sacrificial interposer may be in a range of about 1 nm to about 10 nm.

[0080] exist Figures 12A-12DIn FIG. 5 , after depositing the sacrificial interposer 500 , a sacrificial plug or “protection plug” 500 ′ and a protection structure 510 are formed, which may be used as a mask 520 during reduction of the area of ​​the high-k gate dielectric layer 600 to form a reduced high-k gate dielectric layer 600S.

[0081] exist Fig. 12A and Fig. 12B In the embodiment, after depositing the sacrificial interposer 500, the sacrificial material of the sacrificial interposer 500 is trimmed, stopping on the portion 600C of the high-k dielectric layer 600 to remove the sacrificial material from the side surface of the gate spacer 41 by dry etching or wet etching. After the removal operation, the sacrificial plug 500' remains between the nanostructures 22 and between the nanostructure 22C and the hard mask structure 28. The etching of the sacrificial material of the sacrificial interposer 500 that selectively stops on the high-k dielectric layer 600 can be performed by an etching operation, which can include SC1, SC2, HCl, NH 4 OH, H 2 O 2 , combinations thereof, etc. After the etching operation, portions of high-k dielectric layer 600C on ends of nanostructures 22 and ends of hard mask structure 28 may be exposed. An upper surface of hard mask structure 28 may also be exposed after the etching operation.

[0082] Then, in Fig. 12C and Fig.12D In the embodiment, after trimming the sacrificial interposer 500 to form the sacrificial plug 500', a protection structure 510 is grown on the exposed surface of the sacrificial plug 500' to protect the exposed side surface of the portion 600C of the high-k dielectric layer 600 over the channel 22. The growth of the protection structure 510 on the sacrificial plug 500' may be selective, such that the growth occurs on the exposed surface of the sacrificial plug 500' but not on the exposed surface of the high-k dielectric layer 600, such as the channel portion 600C thereof. The selective growth of the protection structure 510 may be or include ALD or CVD. The selective growth may form a second material on the first material of the sacrificial plug 500'. For example, the first material may be TiN and the second material may be W or TiN. In another example, the first material may be Al 2 O 3, the second material may be TiN. In yet another example, the first material may be Si, and the second material may be Si, SiGe, or W. As can be appreciated from the above examples, the second material may be the same as or different from the first material. The growth of the protection structure 510 may initially proceed laterally outward from the sacrificial plug 500', for example in the Y-axis direction. The initially grown portion of the protection structure 510 may then begin to grow in a perpendicular Z-axis direction and eventually merge near the end of the trench 22, resulting in the side surface of the portion 600C of the high-k dielectric layer 600 being covered. In some embodiments, as Fig.12D As shown, due to how the protection structure 510 merges near the channel 22, a notch 510N may exist in the protection structure 510 near the channel 22. Due to the notch 510N, the protection structure 510 may have a non-uniform width in the Y-axis direction along its height in the Z-axis direction. In some embodiments, the width W1 of the protection structure 510 may be in the range of about 1 nm to about 20 nm. In some embodiments, the width W1 of the protection structure 510 may be measured as a percentage of the distance D1 between adjacent stacks of the channel 22, such as Fig.12D As shown. In some embodiments, the percentage is in the range of about 1% to about 40%. For example, the distance D1 can be in the range of about 18nm to about 100nm. In this example, when the distance D1 is about 18nm, the width W1 is about 1nm, resulting in a percentage of about 5% to about 6%.

[0083] After forming the mask 520 including the sacrificial plug 500' and the protection structure 510, a portion 600A" of the high-k dielectric layer 600 may be exposed in the gate trench 92. Since the protection structure 510 partially covers the portion of the high-k dielectric layer 600 between the stacked members of the channel 22, the portion 600A" is slightly smaller than the reference Fig. 10A and Fig. 10B Portion 600A' is described.

[0084] exist Fig.13A and Fig. 13B In the embodiment, after forming the mask 520 including the sacrificial plug 500' and the protection structure 510, the exposed portion 600A" of the high-k dielectric layer 600 is removed from the gate spacer 41, corresponding to Fig.18 Action 1500. The removal of the exposed portion 600A″ of the high-k dielectric layer 600 may be achieved by a selective removal operation that removes material of the high-k dielectric layer 600 from the sidewalls of the gate spacers 41 while leaving a portion 600C of the high-k dielectric layer 600 on the trench 22 protected by the mask 520 including the sacrificial plug 500′ and the protection structure 510. The removal operation may include a high etch selectivity between the materials of the high-k dielectric layer 600 and the protection structure 510, such as for Si and HfO. 2HF or H 2 SO 4 Base wet etch for TiN and HfO 2 HF or NF 3 The removal operation may remove the exposed portion 600A″ on the sidewall of the gate spacer 41 and may remove a portion of the high-k dielectric layer 600 on the upper surface of the hard mask structure 28. Fig.13A and Fig. 13B As shown, the removal operation may additionally remove material of high-k dielectric layer 600 overlying isolation structure 36 , such that an upper surface of isolation structure 36 is exposed in gate opening 92 .

[0085] In some embodiments, Fig. 13C and Fig.13D As shown, after removing portion 600A″ of high-k dielectric layer 600, low-k dielectric spacer layer 42 can be formed on exposed surfaces of gate spacer 41 and isolation structure 36. Low-k dielectric spacer layer 42 can be or include a low-k dielectric material, such as SiO, SiOC, SiN, organic silicate glass (OSG), etc. Low-k dielectric spacer layer 42 can be formed by appropriate deposition operations, such as PVD, CVD, ALD, etc. After forming the low-k dielectric material (which can form a thin conformal layer on the upper surfaces of gate spacer 41, isolation structure 36, and hard mask structure 28), an anisotropic etch can be performed to remove the material of low-k dielectric spacer layer 42 from the upper surface of hard mask structure 28. Forming low-k dielectric spacer layer 42 before removing mask 520 can allow mask 520 to be formed before the low-k dielectric spacer layer 42 is formed. The low-k dielectric spacer layer 42 is formed to protect the space between the channels 22 during the formation of the low-k dielectric spacer layer 42 and prevent the low-k dielectric spacer layer 42 from being formed between the channels 22. This is beneficial to increase the gate fill window after the reduced high-k dielectric layer 600S is formed to deposit one or more layers of the gate structure 200. The formation of the low-k dielectric spacer layer 42 is beneficial to reduce the effective capacitance and improve the reliability of the gate to source / drain contact by reducing leakage. In embodiments where the low-k dielectric spacer layer 42 is not formed, by removing the high-k dielectric layer 600 from the gate spacers 41, the space between the gate spacers 41 can be increased, thereby improving dimensional shrinkage. In some embodiments where the low-k dielectric spacer layer 42 is not formed, the gate resistance (Rg) can be reduced due to the increase in the volume between the gate spacers 41 by removing the high-k dielectric layer 600 from the gate spacers 41.

[0086] exist Figure 14A-14F In the embodiment, after reducing the size of the high-k dielectric layer 600 to form a reduced high-k dielectric layer 600S, and optionally after forming a reference Fig. 13C and Fig.13DAfter the low-k dielectric spacer layer 42 is discussed, the mask 520 can be removed. The protection structure 510 and the sacrificial plug 500' can be stripped by wet etching or dry etching, which stops on the reduced high-k dielectric layer 600S. The wet etching or dry etching may include SC1, SC2, HCl, NH 4 OH, H 2 O 2 , their combinations, etc. Fig.14A and Fig. 14B As shown, the reduced high-k dielectric layer 600S remains on the nanostructures 22 and the internal spacers 74 .

[0087] like Fig.14A and Fig. 14B As shown, the reduced high-k dielectric layer 600S may have a gate spacer portion 600A on the gate spacer 41, an inner spacer portion 600B on the inner spacer 74, and a notch 600N that inherits the profile of the mask 520. Due to the notch 600N, the gate spacer portion 600A may not have a uniform width in the Y-axis direction along its height in the Z-axis direction. In some embodiments, the width W1 of the gate spacer portion 600A may be in the range of about 1 nm to about 20 nm. In some embodiments, the width W1 of the gate spacer portion 600A may be measured as a percentage of the distance D1 between adjacent stacks of the channel 22, such as Fig. 14B As shown. In some embodiments, the percentage is in the range of about 1% to about 40%. For example, the distance D1 can be in the range of about 18nm to about 100nm. In this example, when the distance D1 is about 18nm, the width W1 is about 1nm, resulting in a percentage of about 5% to about 6%. In some embodiments, the reduced high-k dielectric layer 600S can cover a portion of the surface area of ​​the side surface of the gate spacer 41. In some embodiments, the portion can be measured as a percentage of the surface area of ​​the gate spacer 41. For example, the portion of the gate spacer 41 covered by the reduced high-k dielectric layer 600S can be in the range of about 0.5% to about 50%. In some embodiments, the portion is in the range of about 5% to about 40%.

[0088] exist Fig. 14C In the embodiment of the present invention, after removing the mask 520, the hard mask structure 28 can be removed. The etching process for removing the hard mask structure 28 can include wet chemical etching using hydrofluoric acid, hot phosphoric acid, wet chemical etching using CF 4 / CHF 3 The etching process can remove the hard mask structure 28 without substantially attacking the high-k dielectric layer 600S, the isolation region 36, and the gate spacer 41. Fig. 14CIn the illustrated embodiment, the upper surface of the high-k dielectric layer 600C on the hard mask structure 28 may be exposed after the hard mask structure 28 is removed.

[0089] exist Figure 14D-Figure 14F In the embodiment of the present invention, a low-k dielectric spacer layer 42 is formed after removing the mask 520. The formation of the low-k dielectric spacer layer 42 is similar in most aspects to the reference Fig. 13C and Fig.13D Because the low-k dielectric spacer layer 42 is formed without the mask 520 being located between the trenches 22, the low-k dielectric spacer layer 42 can be deposited on the high-k dielectric layer 600C between the trenches 22, as shown in FIG. Fig.14D shown. Fig.14F It is depicted that the low-k dielectric spacer layer 42 may be present on the portions of the gate spacer layer 41 that are exposed after the hard mask structure 28 is removed.

[0090] exist Figure 15A-15I In the embodiment, after removing the mask 520, and optionally after forming the low-k dielectric spacer layer 42, one or more additional layers of the gate structure 200 including the conductive layer 290 are formed in the gate opening 92, corresponding to Fig.18 The conductive layer 290 is as follows: Fig.15A Reference Fig.16 The described additional layers (eg, second IL 240, work function layers 700, 900, or combinations thereof) may be located between conductive layer 290 and reduced high-k dielectric layer 600S and between conductive layer 290 and gate spacers 41 in regions where reduced high-k dielectric layer 600S is not present. Figure 15G is through Fig.15A and Fig. 15B A plan view of the internal spacer 74 taken along the XY plane. Fig.15H is through Fig.15A and Fig. 15B As the area of ​​high-k dielectric layer 600 is reduced to form reduced high-k dielectric layer 600S including portions 600A and 600B, portions 600A and 600B exposing side surfaces of gate spacer 41 and conductive layer 290 may be directly adjacent to or directly contact gate spacer 41 between portions 600A. Figure 15G As shown, since the reduced high-k dielectric layer 600S is in place, the metal layer 290 can directly contact the exposed portions of the gate spacers 41, such as the portions of the gate spacers 41 that are not covered by the inner spacer portions 600B and the gate spacer portions 600A of the reduced high-k dielectric layer 600S. In some embodiments, as shown in FIG. Fig.16As described, additional layers may be located between the metal layer 290 and the gate spacer 41. For example, the second IL 240, the second work function layer 700, the work function tuning layer 900, an optional glue layer, or a combination thereof may be present between the metal layer 290 and the gate spacer 41 without a reduced high-k dielectric layer 600S therebetween. For example, the second IL 240 may be in direct contact with the gate spacer 41. In another example, the second work function layer 700 may be in direct contact with the gate spacer 41. In yet another example, the work function tuning layer 900 may be in direct contact with the gate spacer 41.

[0091] Fig. 15C and Fig.15D An embodiment is depicted where a low-k dielectric spacer layer 42 is present on the portion of the gate spacer layer 41 exposed by the reduced high-k dielectric layer 600S. Fig.15I is through Fig. 15C and Fig.15D 4. In an embodiment where a low-k dielectric spacer layer 42 is present, the conductive layer 290 or the second IL 240 or the work function layer 700, 900 may be separated from the gate spacer 41 by the low-k dielectric spacer layer 42. For example, the second IL 240, the second work function layer 700, the work function tuning layer 900, the optional glue layer, or a combination thereof may be present between the metal layer 290 and the gate spacer 41, with the low-k dielectric spacer layer 42 therebetween. For example, the second IL 240 may be in direct contact with the low-k dielectric spacer layer 42. In another example, the second work function layer 700 may be in direct contact with the low-k dielectric spacer layer 42. In yet another example, the work function tuning layer 900 may be in direct contact with the low-k dielectric spacer layer 42. In some embodiments, a first portion of conductive layer 290 may be separated from gate spacer 41 by reduced high-k dielectric layer 600S, while a second portion of conductive layer 290 may be separated from gate spacer 41 by low-k dielectric spacer layer 42. In some embodiments, an area of ​​the second portion exceeds an area of ​​the first portion.

[0092] Fig.15E and Fig.15F 2 is a diagram depicting an embodiment in which the hard mask structure 28 is not present due to being removed in an operation prior to forming the conductive layer 290. In such an embodiment, the conductive layer 290 and the optional second IL 240 and / or work function layers 700, 900 may fill the space where the hard mask structure 28 was previously present. In some embodiments, in order to physically and electrically isolate the gate structure 200 formed in the portion of the hard mask structure 28 adjacent to the source / drain 82, reference is made to FIG. Figures 6A-7B The inner spacer 74HM described may be located between the gate structure 200 and the source / drain 82, as shown in FIG. Fig.15E and Fig.15FAs shown by the dotted line in .

[0093] exist Fig.17 In the embodiment, after forming the gate structure 200, source / drain openings may be formed in the ILD 130, and source / drain contacts 120 may be formed in the source / drain openings. The silicide regions 118 and the source / drain contacts 120 are formed on the source / drain 82, which may be the source / drain 82P, the source / drain 82N, or a combination thereof.

[0094] In some embodiments, the silicide layer 118 is formed before forming the source / drain contacts 120. For example, an N-type or P-type metal layer can be formed as a conformal thin layer on the exposed portion of the source / drain region 82. The metal layer can be or include one or more of Ni, Co, Mn, W, Fe, Rh, Pd, Ru, Pt, Ir, Os, etc. In some embodiments, the metal layer is or includes one or more of Ti, Cr, Ta, Mo, Zr, Hf, Sc, Ys, Ho, Tb, Gd, Lu, Dy, Er, Yb, or another suitable material. After forming the metal layer, the silicide layer 118 can be formed by annealing the device 10. After annealing, the silicide layer 118 may be or include one or more of NiSi, CoSi, MnSi, WSi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, YbSi, etc. The silicide of the silicide layer 118 may diffuse into the area below the ESL 131. The thickness of the silicide layer 118 may be in the range of about 1 nm to about 10 nm. Below about 1 nm, the contact resistance may be too high. Greater than 10 nm, the silicide layer 118 may be short-circuited with the channel 22C.

[0095] After forming the silicide layer 118, a source / source contact 120 is formed by filling the opening on the source / drain region 82 with, for example, a liner layer and a filling layer. In some embodiments, the source / drain contact 120 is formed by depositing a conductive material such as Co, W, Ru, a combination thereof, or a material including a conductive material such as Co, W, Ru, a combination thereof, or the like. In some embodiments, the source / drain contact 120 is or includes a Co-based, W-based, or Ru-based compound or alloy containing one or more elements, such as Zr, Sn, Ag, Cu, Au, Al, Ca, Be, Mg, Rh, Na, Ir, W, Mo, Zn, Ni, K, Co, Cd, Ru, In, Os, Si, Ge, Mn, a combination thereof, or the like. The source / drain contact 120 lands on the silicide layer 118 and contacts the ESL 131. The present disclosure gives a description of the device 10 and its illustrations with reference to a vertically stacked GAAFET including the nanostructure 22. In some embodiments, the silicide layer 118 and source / drain contacts 120 are formed in and on the source / drain regions 82 of the FinFET device.

[0096] Additional processing may be performed to complete the fabrication of the nanostructure device 20. For example, a gate contact (or gate via) may be formed to electrically couple to the gate structure 200. An interconnect structure may then be formed over the source / drain contacts 120 and the gate contacts. The interconnect structure may include a plurality of dielectric layers (including, for example, a second ILD) surrounding metal features (including conductive traces and conductive vias) that form electrical connections between devices (e.g., nanostructure devices 20A, 20B, 20C) on the substrate 110, as well as electrical connections to IC devices external to the IC device 10.

[0097] Embodiments may provide advantages. By selectively removing portions of the gate dielectric 600 from the gate spacers 41 that are outside the channel 22 and the inner spacers 74, parasitic capacitance may be reduced without reducing the beneficial on-current I ON The selective removal may be achieved by using a mask 520 that includes a sacrificial plug 500' and a protection structure 510 selectively grown thereon.

[0098] According to at least one embodiment, a method for forming an integrated circuit device is provided, comprising: forming a stack including a nanostructure channel, an interposer, and a hard mask structure by forming source / drain openings; forming a sacrificial gate structure on the stack; forming a spacer layer adjacent to the sacrificial gate structure; releasing the nanostructure channel by removing the interposer layer; forming a gate dielectric on side surfaces of the nanostructure channel and the spacer layer; forming a reduced gate dielectric by removing portions of the gate dielectric from side surfaces of the spacer layer, portions laterally adjacent to the nanostructure channel; and forming a gate metal layer on the reduced gate dielectric and exposed portions of the spacer layer.

[0099] In some embodiments, the method further includes, prior to removing the portion of the gate dielectric, selectively growing a protection structure covering an end of the gate dielectric over the nanostructure channel.

[0100] In some embodiments, selectively growing the protection structure includes: forming a plurality of sacrificial interposers between the nanostructure channels; and growing the protection structure on exposed side surfaces of the plurality of sacrificial interposers.

[0101] In some embodiments, growing the protection structure includes growing the protection structure to have a first thickness adjacent to the plurality of sacrificial interposers, the first thickness being greater than a second thickness adjacent to an end of the gate dielectric.

[0102] In some embodiments, removing the portion of the gate dielectric includes removing the portion of the gate dielectric exposed by the sacrificial interposer and the protection structure.

[0103] In some embodiments, the method further includes removing the hard mask structure after removing the portion of the gate dielectric.

[0104] In some embodiments, the method further includes forming a low-k dielectric layer on an exposed surface of the spacer layer over the hard mask structure after removing the portion of the gate dielectric.

[0105] According to at least one embodiment, a method for forming an integrated circuit device is provided, the method comprising: forming a stack including alternating nanostructure channels and interposer layers by forming source / drain openings extending through alternating first and second semiconductor layers; releasing the nanostructure channels by removing the interposer layers; forming a gate dielectric on the nanostructure channels and on side surfaces of a spacer layer, the gate dielectric extending from a first level above the nanostructure channels to a second level below the nanostructure channels; forming protection plugs between the nanostructure channels; selectively growing protection structures on exposed surfaces of the protection plugs; and removing portions of the gate dielectric exposed by the protection plugs.

[0106] In some embodiments, forming the stack includes forming a hard mask structure over an uppermost one of the interposers during forming the source / drain openings.

[0107] In some embodiments, forming the protection plug includes forming one of the protection plugs between the uppermost interposer and the hard mask structure.

[0108] In some embodiments, selectively growing the protection structure includes growing tungsten on the protection plug comprising TiN or Si.

[0109] In some embodiments, selectively growing a protective structure includes 2 O 3 TiN is grown on the protective plug.

[0110] In some embodiments, selectively growing the protection structure includes growing silicon, SiGe, or tungsten on the protection plug including silicon.

[0111] In some embodiments, the method further includes, after removing a portion of the gate dielectric: forming a metal gate layer on the nanostructure channel, the metal gate layer having a first thickness vertically located in the space between the nanostructure channels and a second thickness outside the space, the second thickness being greater than the first thickness.

[0112] According to at least one embodiment, an integrated circuit device is provided, comprising: a first nanostructure stack; a second nanostructure stack, adjacent to the first nanostructure stack along a first direction; a source / drain, adjacent to the first nanostructure stack along a second direction transverse to the first direction; and a gate structure, surrounding the first nanostructure stack, the gate structure comprising: a gate dielectric, comprising: a first portion, extending between nanostructures of the first nanostructure stack; and a second portion, extending between nanostructures of the second nanostructure stack, the first portion and the second portion being discontinuous in a region between the first nanostructure stack and the second nanostructure stack along the first direction; and a gate metal, located on the gate dielectric, the gate metal extending between the first nanostructure stack, between the second nanostructure stack, and between the first nanostructure stack and the second nanostructure stack continuously located in a region.

[0113] In some embodiments, the integrated circuit device further includes: a spacer layer adjacent to the gate dielectric and the gate metal along the second direction.

[0114] In some embodiments, the gate metal directly contacts the spacer layer in the region and is separated from the spacer layer between the first nanostructure stack and between the second nanomaterial stack.

[0115] In some embodiments, the integrated circuit device further comprises: a hard mask structure located above the uppermost nanostructure of the first nanostructure stack; wherein the gate dielectric partially surrounds the hard mask structure.

[0116] In some embodiments, the first portion of the gate dielectric includes an outer portion that extends beyond side surfaces of the nanostructures of the first nanostructure stack along the first direction.

[0117] In some embodiments, the outer portion of the gate dielectric has a first thickness adjacent to a space between two nanostructures of the first nanostructure stack and a second thickness adjacent to ends of the two nanostructures, the first thickness being greater than the second thickness.

[0118] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for realizing the same purpose of the embodiments introduced herein and / or realizing the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present invention, and they can make various changes, substitutions and changes in the present invention without deviating from the spirit and scope of the present invention.

Claims

1. A method for forming an integrated circuit device, comprising: forming a stack including a nanostructured channel, an interposer, and a hard mask structure by forming source / drain openings; forming a sacrificial gate structure on the stack; forming a spacer layer adjacent to the sacrificial gate structure; releasing the nanostructured channel by removing the intervening layer; forming a gate dielectric on the nanostructure channel and on side surfaces of the spacer layer; forming a reduced gate dielectric by removing a portion of the gate dielectric from the side surface of the spacer layer, the portion laterally adjacent to the nanostructure channel; as well as A gate metal layer is formed on the reduced gate dielectric and the exposed portions of the spacer layer.

2. The method according to claim 1, further comprising: Prior to removing the portion of the gate dielectric, a protection structure is selectively grown covering an end of the gate dielectric over the nanostructure channel.

3. The method according to claim 2, wherein: The selectively growing the protection structure comprises: forming a plurality of sacrificial interposing layers between the nanostructure channels; and The protection structure is grown on exposed side surfaces of the plurality of sacrificial interposers.

4. The method according to claim 3, wherein: Growing the protection structure includes growing the protection structure to have a first thickness adjacent to the plurality of sacrificial interposers greater than a second thickness adjacent to the end of the gate dielectric.

5. The method according to claim 1, further comprising: After removing the portion of the gate dielectric, a low-k dielectric layer is formed on the exposed surface of the spacer layer over the hard mask structure.

6. A method of forming an integrated circuit device, comprising: forming a stack including alternating nanostructured channels and interposers by forming source / drain openings extending through alternating first and second semiconductor layers; releasing the nanostructured channel by removing the intervening layer; forming a gate dielectric on the nanostructure channel and on side surfaces of the spacer layer, the gate dielectric extending from a first level above the nanostructure channel to a second level below the nanostructure channel; forming a protective plug between the nanostructure channels; selectively growing a protection structure on an exposed surface of the protection plug; as well as A portion of the gate dielectric exposed by the protection plug is removed.

7. The method according to claim 6, wherein: Forming the stack includes: During the forming of the source / drain openings, a hard mask structure is formed over an uppermost one of the interposers.

8. The method according to claim 7, wherein: Forming the protection plugs includes forming one of the protection plugs between the uppermost interposer and the hard mask structure.

9. The method of claim 6, further comprising, after removing the portion of the gate dielectric: A metal gate layer is formed on the nanostructure channels, wherein the metal gate layer has a first thickness vertically located in the space between the nanostructure channels and a second thickness outside the space, wherein the second thickness is greater than the first thickness.

10. An integrated circuit device comprising: a first nanostructure stack; A second nanostructure stack, adjacent to the first nanostructure stack along a first direction; a source / drain adjacent to the first nanostructure stack along a second direction transverse to the first direction; as well as A gate structure surrounding the first nanostructure stack, the gate structure comprising: Gate dielectrics, including: a first portion extending between nanostructures of the first nanostructure stack; and a second portion extending between nanostructures of the second nanostructure stack, the first portion and the second portion being discontinuous along the first direction in a region between the first nanostructure stack and the second nanostructure stack; and A gate metal is disposed on the gate dielectric, the gate metal extending between the first nanostructure stack, between the second nanostructure stack, and continuously between the first nanostructure stack and the second nanostructure stack in the region.

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