High dv / dt silicon controlled integrated chip and manufacturing method thereof

Abstract

The invention discloses a high dv / dt silicon controlled rectifier integrated chip and a preparation method thereof, the high dv / dt silicon controlled rectifier integrated chip comprises an N-type substrate, the upper surface of the N-type substrate is provided with a first P-type diffusion region, a second P-type diffusion region and a third P-type diffusion region, and the upper end and the lower end of the third P-type diffusion region are provided with a first P-type diffusion region and a second P-type diffusion region; a first N + type diffusion region is arranged on one side, close to the first P type diffusion region, of the upper surface of the second P type diffusion region, a second N + type diffusion region is arranged on the upper surface of the first P-type diffusion region, and two third N + type diffusion regions are arranged at one end of the upper surface of the second P-type diffusion region; the voltage spike caused by a high-frequency switch in the industrial field can be borne, false triggering is prevented, the requirement for a peripheral protection circuit is reduced, the circuit design cost is reduced, and the circuit power consumption is reduced; the design of the light-triggered silicon controlled rectifier can electrically isolate the input side from the output side, thereby improving the anti-interference capability.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a high dv / dt silicon controlled rectifier integrated chip and a manufacturing method thereof. Background Art

[0002] Generally, discrete thyristor devices are difficult to use in the industrial field due to their own performance limitations. The voltage spikes caused by high-frequency switching can easily lead to false triggering of thyristors. It is necessary to add a peripheral RC absorption circuit to improve the thyristor's dv / dt tolerance, which not only increases the circuit design cost, but also increases energy consumption. In order to ensure accurate triggering of thyristors, the design of the drive circuit is also more complicated. At the same time, in order to improve the system's anti-interference ability, it is necessary to increase the isolation circuit design. Summary of the invention

[0003] The object of the present invention is to provide a high dv / dt thyristor integrated chip and a manufacturing method thereof to solve the problems raised in the above background technology.

[0004] To achieve the above-mentioned purpose, the present invention provides the following technical solutions: a high dv / dt thyristor integrated chip, comprising an N-type substrate, wherein a first P-type diffusion region, a second P-type diffusion region and a third P-type diffusion region are arranged on the upper surface of the N-type substrate, a first P-type diffusion region and a second P-type diffusion region are arranged at the upper and lower ends of the third P-type diffusion region, a first N+ type diffusion region is arranged on the side of the upper surface of the second P-type diffusion region close to the first P-type diffusion region, a second N+ type diffusion region is arranged on the upper surface of the first P-type diffusion region, two third N+ type diffusion regions are arranged at one end of the upper surface of the second P-type diffusion region, and the two third N+ type diffusion regions are connected by setting an N-type depletion region.

[0005] Preferably, the first P-type diffusion region is arranged at one end of the upper surface of the N-type substrate, the second P-type diffusion region and the third P-type diffusion region are arranged at the other end of the upper surface of the N-type substrate, and the second P-type diffusion region and the third P-type diffusion region are connected by setting a P-type diffusion resistor.

[0006] Preferably, a first POLY is disposed on the upper surface of the first P-type diffusion region, a second POLY is disposed on the upper surface of the second P-type diffusion region, and a third POLY is disposed between the first P-type diffusion region and the second P-type diffusion region on the upper surface of the N-type substrate.

[0007] Preferably, a thyristor anode lead window is provided on the upper surface of the first P-type diffusion region, a thyristor cathode lead window is provided on the upper surface of the first N+ type diffusion region, and a plurality of lead windows are provided on the side of the second P-type diffusion region close to the third P-type diffusion region and on the upper surface of the third P-type diffusion region; an anode electrode is provided on the upper surface of the first P-type diffusion region, and cathode electrodes, a first metal and a second metal are provided on the upper surfaces of the second P-type diffusion region and the third P-type diffusion region.

[0008] Preferably, a circle of N+ type cutoff ring is arranged around the first P-type diffusion region, the second P-type diffusion region and the third P-type diffusion region; a passivation layer, silicon nitride and TEOS are arranged on the surface of the N-type substrate; and the first P-type diffusion region is provided with gate oxide.

[0009] The present invention also provides a method for preparing a high dv / dt thyristor integrated chip, the preparation method specifically comprising the following steps: S1, select resistivity 60-80Ω·cm, thickness 275~285μm and <100> N-type silicon wafer with different crystal orientations; S2, perform an oxidation; S3, etching the oxide layer in the active area; S4, photolithography of the first POLY, the second POLY, the third POLY, the silicon nitride, the first N+ type diffusion region, the second N+ type diffusion region, the third N+ type diffusion region and the TEOS; S5, reverse-etching the anode electrode, the cathode electrode, the first metal, and the second metal.

[0010] Preferably, the step S2 specifically includes the following steps: a1. Grow a thermal oxide layer with a thickness of 1.2 μm; a2, opening the windows of the first P-type diffusion region, the second P-type diffusion region and the third P-type diffusion region, and etching the oxide layer in the windows; a3. Boron injection dose 6.5e14~8e14 / cm 2 , injection energy 30~50 keV, injection angle 7°; a4, opening the first P-type diffusion region, the second P-type diffusion region, and the P-type diffusion resistor window, and etching the oxide layer in the window; a5. Boron injection dose 1.2e13~2.5e13 / cm 2 , injection energy 30~50 keV, injection angle 7°; a6, the junction depth of the first P-type diffusion region, the second P-type diffusion region and the third P-type diffusion region is 4-5 μm, and the junction depth of the first P-type diffusion region, the second P-type diffusion region and the P-type diffusion resistor is 2.5-3 μm; a7. Etch the first P-type diffusion region, the second P-type diffusion region, the third P-type diffusion region, the first P-type diffusion region, the second P-type diffusion region and the oxide layer inside the P-type diffusion resistor window.

[0011] Preferably, the step S3 specifically includes the following steps: b1, generate a gate oxide layer with a thickness of 280A; b2. Opening the N-type depletion region window; b3, the arsenic injection dose is 3.5e12~4e12 / cm2, the injection energy is 100~120 keV, and the injection angle is 7°; b4. Etch the oxide layer in the active area cleanly.

[0012] Preferably, the step S4 specifically includes the following steps: c1. Generate an oxide layer with a thickness of 400A; c2. Depositing the phosphorus-doped first POLY, the second POLY and the third POLY, wherein the thickness of the first POLY, the second POLY and the third POLY is 5000A; c3, opening the windows outside the first POLY, the second POLY and the third POLY regions, and etching the POLY in the windows; c4, opening the first N+ type diffusion region, the second N+ type diffusion region, the third N+ type diffusion region and the N+ type cut-off ring window; c5, implantation dose 6e15 / cm2, implantation energy 60~80keV, implantation angle 7°; c6. Depositing a TEOS film with a thickness of 1150A; c7, deposit BPSG, BPSG thickness 11150A, and perform high temperature reflow after deposition; c8, depositing the silicon nitride, the thickness of the silicon nitride is 900 Å; c9, depositing the TEOS, wherein the TEOS thickness is greater than 40000 Å; c10. Etching the TEOS and the silicon nitride to form an oblique angle terminal.

[0013] Preferably, the step S5 specifically includes the following steps: d1. Open the thyristor anode lead window, the thyristor cathode lead window and the lead window; d2. Deposit metal aluminum, the thickness of which is greater than 3 μm; d3. Etch away the aluminum metal outside the anode electrode, the cathode electrode, the first metal and the second metal regions.

[0014] Compared with the prior art, the present invention has the following beneficial effects: 1. The present invention discloses a high dv / dt thyristor integrated chip and a preparation method thereof. The dv / dt can reach 12000V / μs at room temperature and 6000V / μs at high temperature (85°C). The chip can withstand voltage spikes caused by high-frequency switches in the industrial field, prevent false triggering, reduce the demand for peripheral protection circuits, reduce circuit design costs, and reduce circuit power consumption. The design of the light-triggered thyristor can electrically isolate the input side from the output side, thereby improving anti-interference capability.

[0015] 2. The present invention provides a high dv / dt thyristor integrated chip and a preparation method thereof, which realizes an off-state voltage of 800V in the case of shallow junction through the structural design of metal field plates and angled thick oxygen terminals. It does not require the structural design of multiple floating field rings, thereby reducing the waste of chip area. It also does not require the deep junction structure like a planar thyristor, which can greatly reduce the time for diffusion and junction pushing during manufacturing and improve production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a specific schematic diagram of the overall structure of the present invention; Figure 2 It is a cross-sectional schematic diagram of the A section of the present invention; Figure 3 It is a schematic cross-sectional view at B of the present invention; Figure 4 is an equivalent circuit diagram of the present invention; In the figure: 110, N-type substrate; 111, N+ type cutoff ring; 121, first P type diffusion region; 122, second P type diffusion region; 123, third P type diffusion region; 124, P-type diffusion resistor; 131, first P-type diffusion region; 132, second P-type diffusion region; 141, first N+ type diffusion region; 142, second N+ type diffusion region; 143, third N+ type diffusion region; 150, N type depletion region; 161, first POLY; 162, second POLY; 163, third POLY; 171, thyristor anode lead window; 172, thyristor cathode lead window; 173, lead window; 181, anode electrode; 182, cathode electrode; 183, first metal; 184, second metal; 191, passivation layer; 192, silicon nitride; 193, TEOS; 194, gate oxide. DETAILED DESCRIPTION

[0017] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0018] In the description of the present invention, it is necessary to understand that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicating orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0019] In the description of this patent, it should be noted that, unless otherwise clearly specified and limited, the terms "installation", "connection" and "setting" should be understood in a broad sense, for example, it can be fixed connection, setting, or detachable connection, setting, or integrated connection, setting. For ordinary technicians in this field, the specific meanings of the above terms in this patent can be understood according to specific circumstances.

[0020] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "several" is two or more, unless otherwise clearly and specifically defined.

[0021] Example See also Figure 1-4As shown, the present invention provides a high dv / dt thyristor integrated chip technical solution: comprising an N-type substrate 110, wherein the upper surface of the N-type substrate 110 is provided with a first P-type diffusion region 121, a second P-type diffusion region 122 and a third P-type diffusion region 123, wherein the first P-type diffusion region 121 is provided at one end of the upper surface of the N-type substrate 110, the second P-type diffusion region 122 and the third P-type diffusion region 123 are provided at the other end of the upper surface of the N-type substrate 110, the second P-type diffusion region 122 and the third P-type diffusion region 123 are connected by providing a P-type diffusion resistor 124, and the first P-type diffusion region 121, the second P-type diffusion region 122 and the third P-type diffusion region 123 are connected by providing a P-type diffusion resistor 124, and the first P-type diffusion region 121, the second P-type diffusion region 122 and the third A circle of N+ type cutoff ring 111 is arranged around the P-type diffusion region 123; the first P-type diffusion region 131 and the second P-type diffusion region 132 are arranged at the upper and lower ends of the third P-type diffusion region 123, the first P-type diffusion region 131 is provided with a gate oxide 194, a first N+ type diffusion region 141 is arranged on the side of the upper surface of the second P-type diffusion region 122 close to the first P-type diffusion region 121, a second N+ type diffusion region 142 is arranged on the upper surface of the first P-type diffusion region 131, two third N+ type diffusion regions 143 are arranged at one end of the upper surface of the second P-type diffusion region 132, and the two third N+ type diffusion regions 143 are connected by setting an N-type depletion region 150.

[0022] Furthermore, a first POLY 161 is disposed on the upper surface of the first P-type diffusion region 131 , a second POLY 162 is disposed on the upper surface of the second P-type diffusion region 132 , and a third POLY 163 is disposed between the first P-type diffusion region 131 and the second P-type diffusion region 132 on the upper surface of the N-type substrate 110 .

[0023] Furthermore, a thyristor anode lead window 171 is provided on the upper surface of the first P-type diffusion region 121, a thyristor cathode lead window 172 is provided on the upper surface of the first N+ type diffusion region 141, and a plurality of lead windows 173 are provided on the side of the second P-type diffusion region 122 close to the third P-type diffusion region 123 and on the upper surface of the third P-type diffusion region 123; an anode electrode 181 is provided on the upper surface of the first P-type diffusion region 121, and a cathode electrode 182, a first metal 183 and a second metal 184 are provided on the upper surfaces of the second P-type diffusion region 122 and the third P-type diffusion region 123.

[0024] Furthermore, a passivation layer 191 , silicon nitride 192 and TEOS 193 are disposed on the surface of the N-type substrate 110 .

[0025] Furthermore, the thyristor is composed of a four-layer structure consisting of a first P-type diffusion region 121, an N-type substrate 110, a second P-type diffusion region 122 and a first N+ type diffusion region 141; the enhancement-type NMOS tube uses the first P-type diffusion region 131 as a p-well, the second N+ type diffusion region 142 as a source and drain, and the first POLY 161 as a gate; the depletion-type NMOS tube uses the second P-type diffusion region 132 as a P-well, the third N+ type diffusion region 143 as a source and drain, the second POLY 162 as a gate, and the N-type depletion region 150 as a conductive channel; the capacitor is a flat-plate capacitor composed of an N-type substrate 110, a gate oxide 194, and a third POLY 163.

[0026] Furthermore, if Figure 4 It can be shown that the thyristor is equivalently replaced by PNP (Q1) and NPN (Q2) transistors with the base and collector connected to each other. The principle of achieving high dv / dt is as follows: when the voltage between AK rises rapidly, such as encountering a voltage spike, the positive electrode potential of capacitor C will be instantly pulled up, and the voltage across the capacitor cannot change suddenly. Therefore, the negative electrode of capacitor C, that is, the gate potential of M1 is also pulled up. When the gate voltage Vgs of M1 is greater than the threshold voltage Vth, M1 is turned on, and the base of transistor Q2, that is, the gate of the thyristor, is pulled to the ground potential, blocking the trigger path of the thyristor. The gate and source of M2 are short-circuited, Vgs is equal to 0, and M2 is always on. state; therefore, after the voltage spike, the capacitor C is discharged through the conduction path of M2, and the gate voltage of M1 gradually drops to 0. At this time, Vgs is less than Vth, and M1 recovers from the on state to the off state. At this time, the circuit recovers to the normal working state, and the thyristor can be triggered normally; when the voltage between AK is stable, the base of Q2 is illuminated to generate photocurrent. When this current is greater than the trigger current of the thyristor, the thyristor will be turned on; in the steady state, the low-resistance conduction state of M2 makes it impossible for the capacitor C to accumulate charge, and the gate of M1 is always pulled to the ground potential. M1 is in the off state, avoiding the false triggering of the protection mechanism, which causes the thyristor to fail to conduct normally.

[0027] The present invention provides a method for preparing a high dv / dt thyristor integrated chip, the preparation method specifically comprising the following steps: S1, select resistivity 60-80Ω·cm, thickness 275~285μm and <100> N-type silicon wafer with different crystal orientations; S2, perform an oxidation; a1. Grow a thermal oxide layer with a thickness of 1.2 μm; a2. Open the windows of the first P-type diffusion region 121, the second P-type diffusion region 122 and the third P-type diffusion region 123, and etch the oxide layer in the windows; a3. Boron injection dose 6.5e14~8e14 / cm 2, injection energy 30~50 keV, injection angle 7°; a4, opening the windows of the first P-type diffusion region 131, the second P-type diffusion region 132, and the P-type diffusion resistor 124, and etching the oxide layer in the windows; a5. Boron injection dose 1.2e13~2.5e13 / cm 2 , injection energy 30~50 keV, injection angle 7°; a6, the junction depth of the first P-type diffusion region 121, the second P-type diffusion region 122 and the third P-type diffusion region 123 is 4-5 μm, and the junction depth of the first P-type diffusion region 131, the second P-type diffusion region 132 and the P-type diffusion resistor 124 is 2.5-3 μm; a7, etching the oxide layer in the window of the first P-type diffusion region 121, the second P-type diffusion region 122, the third P-type diffusion region 123, the first P-type diffusion region 131, the second P-type diffusion region 132 and the P-type diffusion resistor 124; S3, etching the oxide layer in the active area; b1, generate a gate oxide 194 oxide layer, the gate oxide 194 oxide layer has a thickness of 280A; b2. Open the N-type depletion region 150 window; b3, the arsenic injection dose is 3.5e12~4e12 / cm2, the injection energy is 100~120 keV, and the injection angle is 7°; b4. Etch the oxide layer in the active area cleanly S4, photolithography of the first POLY 161, the second POLY 162, the third POLY 163, the silicon nitride 192, the first N+ type diffusion region 141, the second N+ type diffusion region 142, the third N+ type diffusion region 143 and the TEOS 193; c1. Generate an oxide layer with a thickness of 400A; c2. Depositing a phosphorus-doped first POLY161, a second POLY162 and a third POLY163, the thickness of the first POLY161, the second POLY162 and the third POLY163 is 5000A; c3. Open the windows outside the first POLY161, the second POLY162 and the third POLY163 areas, and etch the POLY in the windows; c4. Open the windows of the first N+ type diffusion region 141, the second N+ type diffusion region 142, the third N+ type diffusion region 143 and the N+ type cut-off ring 111; c5, implantation dose 6e15 / cm2, implantation energy 60~80keV, implantation angle 7°; c6. Depositing a TEOS film with a thickness of 1150A; c7, deposit BPSG, BPSG thickness 11150A, and perform high temperature reflow after deposition; c8, depositing a silicon nitride 192 film, the thickness of the silicon nitride 192 is 900 Å; c9, depositing TEOS193, the thickness of TEOS193 is greater than 40000A; c10, etching TEOS 193 and silicon nitride 192 to form an angled terminal; S5, reversely engraving the anode electrode 181, the cathode electrode 182, the first metal 183 and the second metal 184; d1. Open the thyristor anode lead window 171, the thyristor cathode lead window 172 and the lead window 173; d2. Deposit metal aluminum, the thickness of which is greater than 3 μm; d3. Etch away the metal aluminum outside the anode electrode 181, the cathode electrode 182, the first metal 183 and the second metal 184 areas.

[0028] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments. The above embodiments and descriptions are only preferred examples of the present invention and are not intended to limit the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A high dv / dt thyristor integrated chip, comprising an N-type substrate (110), characterized in that: The upper surface of the N-type substrate (110) is provided with a first P-type diffusion region (121), a second P-type diffusion region (122) and a third P-type diffusion region (123); the upper and lower ends of the third P-type diffusion region (123) are provided with a first P-type diffusion region (131) and a second P-type diffusion region (132); a first N+ type diffusion region (141) is provided on the upper surface of the second P-type diffusion region (122) on a side close to the first P-type diffusion region (121); a second N+ type diffusion region (142) is provided on the upper surface of the first P-type diffusion region (131); two third N+ type diffusion regions (143) are provided on one end of the upper surface of the second P-type diffusion region (132); and the two third N+ type diffusion regions (143) are connected by providing an N-type depletion region (150).

2. The high dv / dt thyristor integrated chip according to claim 1, characterized in that: The first P-type diffusion region (121) is arranged at one end of the upper surface of the N-type substrate (110), the second P-type diffusion region (122) and the third P-type diffusion region (123) are arranged at the other end of the upper surface of the N-type substrate (110), and the second P-type diffusion region (122) and the third P-type diffusion region (123) are connected by arranging a P-type diffusion resistor (124).

3. The high dv / dt thyristor integrated chip according to claim 1, characterized in that: A first POLY (161) is arranged on the upper surface of the first P-type diffusion region (131), a second POLY (162) is arranged on the upper surface of the second P-type diffusion region (132), and a third POLY (163) is arranged between the first P-type diffusion region (131) and the second P-type diffusion region (132) on the upper surface of the N-type substrate (110).

4. The high dv / dt thyristor integrated chip according to claim 1, characterized in that: A thyristor anode lead window (171) is provided on the upper surface of the first P-type diffusion region (121), a thyristor cathode lead window (172) is provided on the upper surface of the first N+ type diffusion region (141), and a plurality of lead windows (173) are provided on one side of the second P-type diffusion region (122) close to the third P-type diffusion region (123) and on the upper surface of the third P-type diffusion region (123); an anode electrode (181) is provided on the upper surface of the first P-type diffusion region (121), and a cathode electrode (182), a first metal (183) and a second metal (184) are provided on the upper surfaces of the second P-type diffusion region (122) and the third P-type diffusion region (123).

5. The high dv / dt thyristor integrated chip according to claim 1, characterized in that: An N+ type cut-off ring (111) is arranged around the first P-type diffusion region (121), the second P-type diffusion region (122) and the third P-type diffusion region (123); a passivation layer (191), silicon nitride (192) and TEOS (193) are arranged on the surface of the N-type substrate (110); and a gate oxide (194) is arranged on the first P-type diffusion region (131).

6. A method for preparing a high dv / dt thyristor integrated chip according to any one of claims 1 to 5, characterized in that: The preparation method specifically comprises the following steps: S1, select resistivity 60-80Ω·cm, thickness 275~285μm and <100> N-type silicon wafer with different crystal orientations; S2, perform an oxidation; S3, etching the oxide layer in the active area; S4, photolithography of the first POLY (161), the second POLY (162), the third POLY (163), the silicon nitride (192), the first N+ type diffusion region (141), the second N+ type diffusion region (142), the third N+ type diffusion region (143), and the TEOS (193); S5. Reverse-etching the anode electrode (181), the cathode electrode (182), the first metal (183), and the second metal (184).

7. The method for preparing a high dv / dt thyristor integrated chip according to any one of claim 6, characterized in that: The step S2 specifically includes the following steps: a1. Grow a thermal oxide layer with a thickness of 1.2 μm; a2, opening windows of the first P-type diffusion region (121), the second P-type diffusion region (122) and the third P-type diffusion region (123), and etching the oxide layer in the windows; a3. Boron injection dose 6.5e14~8e14 / cm 2 , injection energy 30~50 keV, injection angle 7°; a4, opening the windows of the first P-type diffusion region (131), the second P-type diffusion region (132), and the P-type diffusion resistor (124), and etching the oxide layer in the windows; a5. Boron injection dose 1.2e13~2.5e13 / cm 2 , injection energy 30~50 keV, injection angle 7°; a6, the junction depth of the first P-type diffusion region (121), the second P-type diffusion region (122) and the third P-type diffusion region (123) is 4-5 μm, and the junction depth of the first P-type diffusion region (131), the second P-type diffusion region (132) and the P-type diffusion resistor (124) is 2.5-3 μm; a7. Etching the oxide layer in the windows of the first P-type diffusion region (121), the second P-type diffusion region (122), the third P-type diffusion region (123), the first P-type diffusion region (131), the second P-type diffusion region (132) and the P-type diffusion resistor (124).

8. The method for preparing a high dv / dt thyristor integrated chip according to any one of claim 6, characterized in that: The step S3 specifically comprises the following steps: b1. Generate a gate oxide (194) oxide layer with a thickness of 280A; b2. Opening the N-type depletion region (150) window; b3, the arsenic injection dose is 3.5e12~4e12 / cm2, the injection energy is 100~120 keV, and the injection angle is 7°; b4. Etch the oxide layer in the active area cleanly.

9. The method for preparing a high dv / dt thyristor integrated chip according to any one of claim 6, characterized in that: The step S4 specifically comprises the following steps: c1. Generate an oxide layer with a thickness of 400A; c2. Depositing the first POLY (161), the second POLY (162) and the third POLY (163) doped with phosphorus, wherein the thickness of the first POLY (161), the second POLY (162) and the third POLY (163) is 5000A; c3, opening windows outside the regions of the first POLY (161), the second POLY (162) and the third POLY (163), and etching the POLY within the windows; c4, opening the windows of the first N+ type diffusion region (141), the second N+ type diffusion region (142), the third N+ type diffusion region (143) and the N+ type cut-off ring (111); c5, implantation dose 6e15 / cm2, implantation energy 60~80keV, implantation angle 7°; c6. Depositing a TEOS film with a thickness of 1150A; c7, deposit BPSG, BPSG thickness 11150A, and perform high temperature reflow after deposition; c8, depositing the silicon nitride (192), wherein the thickness of the silicon nitride (192) is 900 Å; c9, depositing the TEOS (193), wherein the thickness of the TEOS (193) is greater than 40000 Å; c10. Etching the TEOS (193) and the silicon nitride (192) to form an angled terminal.

10. The method for preparing a high dv / dt thyristor integrated chip according to any one of claim 6, characterized in that: The step S5 specifically comprises the following steps: d1. Opening the thyristor anode lead window (171), the thyristor cathode lead window (172), and the lead window (173); d2. Deposit metal aluminum, the thickness of which is greater than 3 μm; d3. Etch away the metal aluminum outside the regions of the anode electrode (181), the cathode electrode (182), the first metal (183) and the second metal (184).

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