Integrated circuit including bipolar transistor

Abstract

The embodiment of the invention relates to an integrated circuit including a bipolar transistor. The invention relates to an integrated circuit including one or more rows of transistors and a method. In one embodiment, an integrated circuit includes a bipolar transistor row including a plurality of first conductive regions, a second conductive region, and a common base located between the first conductive region and the second conductive region. An insulating trench is in contact with each bipolar transistor in the row of bipolar transistors. A conductive layer is on the insulating trench and the common base, between the first conductive regions. The spacer layer is between the conductive layer and the first conductive region.

Description

[0001] Divisional Application Instructions

[0002] This application is a divisional application of the Chinese patent application with the application date of April 4, 2019, application number 201910272414.2, and name “Integrated Circuit Including Bipolar Transistors”. Technical Field

[0003] The present disclosure relates to integrated circuits, and more particularly to the connection of bipolar transistors.The present disclosure is more particularly applicable to forming arrays of memory cells. Background Art

[0004] The memory is usually in the form of an array comprising word lines and columns (or bit lines). A memory cell containing binary information is located at each intersection of a word line and a bit line.

[0005] In phase change memory, each memory cell includes a layer of phase change material, the lower part of which is in contact with a resistive element. Phase change material is a material that can change from a crystalline phase to an amorphous phase (or vice versa). This change is caused by an increase in the temperature of the resistive element through which the current is conducted. The difference in resistance between the amorphous phase of the material and its crystalline phase is used to define two memory states, such as 0 and 1.

[0006] In the example of a phase change memory, the memory cells are controlled, for example, by bipolar transistors that conduct or do not conduct current for heating a resistive element. The memory cells belonging to the same bit line are connected by a conductor covering the phase change material, and the memory cells belonging to the same word line are connected together by the base of the bipolar transistor (e.g., by a base common to all transistors of the same word line).

[0007] For example, binary information of a memory cell of a phase change memory is accessed by measuring the resistance between a bit line and a word line of the memory cell. Summary of the invention

[0008] In one embodiment, the present disclosure provides an integrated circuit including a row of bipolar transistors. The row of bipolar transistors includes a plurality of first conductive regions, a second conductive region, and a common base, the common base being located between the first conductive region and the second region. An insulating trench contacts each of the bipolar transistors in the row of transistors. A conductive layer is located on the insulating trench and the common base, and is located between the first conductive region. A spacer layer is located between the conductive layer and the first conductive region.

[0009] According to one embodiment, the conductive layer includes polysilicon.

[0010] According to one embodiment, the conductive layer is separated from the common base by a metal layer.

[0011] According to one embodiment, the electrically conductive material comprises a metal.

[0012] According to one embodiment, each transistor controls a memory cell of a phase change memory.

[0013] According to one embodiment, the conductive layer is connected to the interconnect network through a single via.

[0014] According to one embodiment, the plurality of first conductive regions contact the base, and the base contacts the second conductive regions.

[0015] According to an embodiment, each of the transistors in a row comprises a second conductive region.

[0016] According to one embodiment, at least part of the conductive layer is covered with insulating strips and polysilicon strips.

[0017] In another embodiment, the present disclosure provides a method, which includes: forming a row of bipolar transistors having a common base, the common base being located between a plurality of first conductive regions and a second conductive region, the first conductive regions being separated from each other by insulator walls, and an insulating trench being in contact with the row of transistors; forming a cavity in the insulating trench and the insulator walls, the side surfaces of the first conductive regions being exposed in the cavity; forming a spacer layer in the cavity, the spacer layer covering the exposed side surfaces of the first conductive regions and the side surfaces of the insulating trench in the cavity; and filling the cavity with a conductive material.

[0018] According to an embodiment, forming the cavity comprises forming an etch mask comprising strips extending in the direction of the transistor row and extending partly over the first conductive region, partly over the wall of the insulator and partly over the insulating trench.

[0019] According to one embodiment, the conductive material is polysilicon.

[0020] According to one embodiment, a metal layer is deposited in the cavity and on the spacer layer before filling the cavity with the conductive material.

[0021] According to one embodiment, the electrically conductive material comprises a metal.

[0022] According to one embodiment, the metal layer is titanium.

[0023] The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a simplified cross-sectional view of a bipolar transistor with a common base;

[0025] Figure 2is a simplified perspective view of one embodiment of a bipolar transistor;

[0026] Figure 3 yes Figure 2 A simplified top view of an embodiment of the invention;

[0027] Figure 4 It is shown Figure 2 and Figure 3 A perspective view of a manufacturing step of an embodiment of the present invention;

[0028] Figure 5A and Figure 5B They are shown respectively Figure 2 and Figure 3 A perspective view and a top view of another manufacturing step of an embodiment of the present invention;

[0029] Fig. 6A It shows Figure 2 and Figure 3 A top view of another manufacturing step of an embodiment of the present invention;

[0030] Figure 6B and Figure 6C They are shown respectively Figure 2 and Figure 3 Another manufacturing step of an embodiment of Fig. 6A sectional views along the BB' plane and the CC' plane;

[0031] Fig. 7A It shows Figure 2 and Figure 3 A top view of another manufacturing step of an embodiment of the present invention; and

[0032] Figure 7B and Figure 7C They are shown respectively Figure 2 and Figure 3 Another manufacturing step of an embodiment of Fig. 7A Cross-sectional view along the BB' plane and CC' plane. DETAILED DESCRIPTION

[0033] In the various drawings, the same elements are designated with the same reference numerals, and the various drawings are not drawn to scale. For the sake of clarity, only those steps and elements useful for understanding the described embodiments are shown and described in detail. In particular, only transistors are shown. Memory cells and the interconnection networks to which they can be connected are not described in detail.

[0034] In the following description, when referring to terms defining relative positions (such as the terms "top", "bottom", "upper" or "lower", etc.), reference is made to the orientation of the relevant elements in the drawings. Unless otherwise indicated, the terms "approximately" and "substantially" are used herein to specify a tolerance of plus or minus 10%, preferably plus or minus 5%, of the value in question.

[0035] Figure 1 is a simplified cross-sectional view of a portion of an integrated circuit comprising four bipolar transistors 2, for example of the PNP type. The bipolar transistors considered are vertical bipolar transistors, i.e. bipolar transistors whose different parts (base and the region forming the two conducting terminals, i.e. emitter and collector) are superposed on each other. A portion of an equivalent circuit diagram is also shown.

[0036] Transistor 2 (or T1 and T2 in the equivalent circuit diagram) includes a common collector 4 (or C) formed by a layer of P-type semiconductor material. Transistor 2 also includes a common base 6 (or B). Base 6 is formed by a layer of N-type semiconductor material (e.g. silicon) covering collector 4. Base 6 is covered with a layer 7 containing emitter 8 (or E1 and E2).

[0037] The emitter 8 (or E1 and E2) is located above the base 6 and in contact with the base 6. Each emitter 8 is formed by a region made of a P-type semiconductor material (such as silicon). The emitters 8 are separated from each other by insulator walls 12. Figure 1 In FIG. 4 , four emitters 8 are shown.

[0038] An insulator layer 14 covers the emitter 8 and the wall 12. Vias 16 pass through the insulator layer 14 up to the emitter 8 to couple them to components (not shown). For example, the vias 16 couple the emitter 8 to a metallization level of an interconnect network. The vias 16 can also couple the emitter 8 to a phase change material via a resistive element to form a memory cell of a phase change memory controlled by a bipolar transistor 2. The four transistors 2 then belong to the same word line of the memory.

[0039] The contact regions 17 of the base 6 are regularly distributed. These regions are made of N-type semiconductor material above and in contact with the base 6 and are separated from the emitter 8 by the insulating wall 12. The regions 17 are more heavily doped than the base 6. The regions 17 are coupled to external connection terminals (not shown) through vias 18 (similar to the vias 16) and through an interconnection network (not shown).

[0040] exist Figure 1In the example of , every four emitters 8 form a region 17. In some embodiments, there may be fewer regions 17 because there are emitters 8. Since the surface area of ​​each region 17 corresponds at least to the surface area of ​​the emitter 8, reducing the number of regions 17 makes it possible to increase the number of transistors in a row of the same length.

[0041] However, the semiconductor material of the base 6, for example silicon, has a relatively high resistance. Therefore, parasitic resistors are present, two of which are shown in the equivalent circuit diagram and designated by reference numerals R1 and R2, wherein the resistance between two transistors or between a transistor and the region 17 can be greater than 1 kΩ, for example. Such parasitic resistances are higher when the emitter and / or the region are further away.

[0042] On the one hand, it may be desirable for all transistors 2 to have the same parasitic resistance, which can be obtained by forming one region 17 for each transistor, and on the other hand, it may be desirable to reduce the surface area of ​​each transistor row, which can be obtained by forming a single region 17 per transistor row. One solution is to make a compromise by regularly forming regions 17 in each row.

[0043] However, the resistance between an emitter 8 and the nearest region 17 is different for all emitters 8. Furthermore, the presence of region 17 limits the number of emitters 8 and therefore the number of memory cells that can be formed on a row of a given length.

[0044] In addition, during the manufacture of certain components (such as certain memories), it is preferred to have Figure 1 Polysilicon densities cannot be achieved in the case of bipolar transistor controlled memories.

[0045] Figure 2 is a simplified perspective view of one embodiment of a bipolar transistor 19. A portion of an equivalent circuit diagram showing the transistor T and its connections is also shown.

[0046] Figure 3 yes Figure 2 A top view of an embodiment of the present invention.

[0047] Figure 2 and Figure 3 An array of eight bipolar transistors is shown, divided into two rows 20 and 22, each row comprising four transistors. Each bipolar transistor 19 controls a memory cell, for example, of a phase change memory. The rows 20 and 22 then control the word lines of the phase change memory, and the columns of the array control the bit lines of the memory. Each transistor comprises a base (B) and two semiconductor regions forming conductive terminals (emitter (E) and collector (C)).

[0048] As in Figure 2 As shown in the figure, each row 20 or 22 of transistors 19 includes a region 24 forming a collector, which is common to the entire row in this example. The region 24 is formed by a layer of semiconductor material (e.g., P-type). Each region 24 of a row 20 or 22 is covered with a base 26 common to the transistors in the row, and the base 26 is formed by a layer of semiconductor material (e.g., N-type).

[0049] Region 28 is made of semiconductor material, forms the emitter and is Figure 2 and Figure 3 As shown, region 28 is formed above and in contact with base 26. Each transistor 19 also includes a via 38 that passes through an insulator layer (not shown) covering emitter 28. For example, via 38 enables the transistor to be connected to a resistive element (not shown) of a phase change memory or to an interconnect network.

[0050] The rows of bipolar transistors 19 are separated from each other by insulating trenches 32 and 33, which are made, for example, of conventional oxidation for insulation or are STI (“shallow trench isolation”) trenches, for example, made of silicon oxide, and which extend in a first direction and are deep enough (without completely passing through the substrate) to insulate transistors 19 of different rows from each other. Figure 2 and Figure 3 Two insulating trenches 32 and 33 are shown, trench 32 separating row 20 from row 22, and trench 33 separating row 22 from a row not shown. Each insulating trench is considered here to be associated with a row of bipolar transistors parallel to and in contact with the trench. Trench 32 is here associated with row 20, and trench 33 is here associated with row 22.

[0051] The main conductive strip 34 extends opposite to each of the insulating trenches 32 and 33. Each main conductive strip 34 is, for example, long enough to face all emitters of the transistor row associated with the corresponding trench. An auxiliary conductive strip 36 extends from each main conductive strip 34 between the emitters 28 of the same transistor row. More specifically, the auxiliary strip 36 extends along a portion of the length of the emitter 28. The conductive strip 36 extends in a second direction orthogonal to the first direction. Therefore, each emitter 28 of a given row is separated from each adjacent emitter by the auxiliary conductive strip 36. The auxiliary conductive strip 36 contacts the common base 26 and is interconnected by the main conductive strip 34 to form a comb. According to one embodiment, the main conductive strip 34 and the auxiliary conductive strip 36 are made of polysilicon. According to one embodiment, a metal layer (not shown) is inserted between each conductive strip and the base 26 to improve electrical contact. The metal layer is, for example, made of titanium. The metal layer has, for example, a thickness in the range of 1nm to 20nm. According to another embodiment, the conductive strip is made entirely of metal.

[0052] Conductive strips 34 and 36 are separated from region 28 and from other rows of conductive strips 34 and 36 by insulating walls 30 (for example made of silicon oxide). The insulating walls comprise in particular insulating spacers.

[0053] Each main conductive strip 34 can be coupled to an external connection terminal (not shown) by one or more connections (preferably a single connection for each main conductive strip 34). Each connection is formed by neutralizing a transistor location, i.e., although a transistor is formed at that location, it is not connected to anything. Vias are then formed at each of these locations to couple the conductive strip to an external connection terminal via an interconnect network.

[0054] Each emitter 28 is separated from the auxiliary conductive strip 36 from the contact zone with the base by a portion of the insulating wall 30 having a size substantially equal to the size of the portion of the insulating wall situated between the other emitters and the auxiliary conductive strip. Therefore, the parasitic resistor designated by the reference symbol R in the equivalent circuit diagram and formed in the base has a resistance that is the same for all bipolar transistors 19 and is less than Figure 1 The parasitic resistor has a resistance of . The main conductive strip 34 and the auxiliary conductive strip 36 are made of polysilicon, and they form a parasitic resistor, the resistance of which is less than Figure 1 The resistance of the parasitic resistor formed in the base between the emitter 8 is, for example, 10 times to 100 times smaller.

[0055] The distance separating the emitters depends on the manufacturing method of the bipolar transistor. With current technology, the minimum distance that can be manufactured is about 100nm.

[0056] For voltage values ​​used in the memory (eg, 4V maximum), the minimum silicon oxide thickness for suitable insulation between two conductive elements (ie, for example, emitter 28 and conductive strips 34 and 36) is believed to be approximately 10 nm.

[0057] Thus, conductive strips 34 and 36 having a width in the range of, for example, 25 nm to 40 nm may be formed between portions of insulating wall 30 having a thickness greater than 10 nm. Portions of the insulating wall provide insulation between emitter 28 and conductive strips 34 and 36 deemed suitable.

[0058] More generally, the width of conductive strips 34 and 36 is selected based on the width of insulator wall 30 and the voltages they must be able to insulate.

[0059] Figure 4 , Figure 5A , Figure 5B , FIG. 6A to FIG. 6C as well as 7A to 7C The diagram shows the manufacturing Figure 2 The method of the structure shown in .

[0060] Figure 4 The steps of first forming the transistor 19 (i.e., collector, base, and emitter) in the substrate are illustrated. The steps include: forming and doping the layers forming the collector 24, base 26, and emitter 28; forming trenches 32 separating the rows of transistors; and forming insulator walls 35 separating the emitters 28. These steps are performed, for example, by conventional manufacturing processes. For example, the transistor is formed as close to the prior art as possible. The distance between the two emitters is, for example, in the range from 80 nm to 150 nm.

[0061] Figure 5A and Figure 5B It shows Figure 2 and Figure 3 A perspective view and a top view of another manufacturing step of an embodiment of the present invention are shown.

[0062] During this step, an etching mask (not shown) is formed. The etching mask comprises one strip for each transistor row, each strip partially covering the emitter 28, partially covering the adjacent trench 32 and partially covering the adjacent wall 35. A selective etch is then performed to remove the insulator of the trench 32 and the insulator of the wall 35 from the unprotected areas. The etching is performed until the layer 26 is exposed. The mask is then removed.

[0063] Thus, a strip 37 of insulating material remains, which extends partly between the emitters of the same row and partly along these emitters.

[0064] Cavities 38 are thus formed. Cavities 38 are substantially comb-shaped, ie they comprise main cavities 40 extending along the same row of emitters 28 and auxiliary cavities 42 each extending between two adjacent emitters 28 in the same row.

[0065] FIG. 6A to FIG. 6C is a top view showing another manufacturing step of the embodiment and Fig. 6A Cross-sectional view along the BB' plane and CC' plane.

[0066] During this step, spacers 44 are formed on the walls of the cavity 38. The spacers 44 are made of silicon oxide, for example.

[0067] The size of the spacer 44 is small enough so that the exposed portion 46 of the base 26 of the auxiliary cavity 42 is not completely covered by the spacer. Therefore, the portion 46 of the base 26 is always at least partially exposed between the emitters of the same transistor row. In addition, the main cavity 40 is not completely filled. Therefore, the cavity 42 of the same transistor row is connected to the corresponding cavity 40.

[0068] 7A to 7C is a top view showing another manufacturing step of the embodiment and Fig. 7A Cross-sectional view along the BB' plane and CC' plane.

[0069] During this step, a metal layer 46, for example titanium, is deposited on the bottom of the cavity 38 and on the spacers 44. The cavity 38 is then filled with polysilicon 48 to form the main strip 34 in the region 40 and the auxiliary strip 36 in the region 42.

[0070] As a variant, the metal layer 46 may be omitted.

[0071] As a variant, metal may be used instead of polysilicon.

[0072] It could be designed to directly etch a comb-like trench with semiconductor material in the walls 35 and trench 32, however, such etching with current methods is imprecise, especially at angles. Therefore, the etching may reach the emitter 28 and make contact, and thus result in a direct electrical connection between the emitter and the conductive strips 34 and 36 (base).

[0073] Forming spacers 44 after the etching step has the advantage of ensuring that insulating material is present between the emitter and conductive strips 34 and 36 .

[0074] According to one embodiment, in order to increase the polysilicon density, polysilicon strips covering the insulator strips may be formed on the layer including the emitter. Such strips may extend in a direction (second direction) orthogonal to the direction of the transistor rows, for example, on at least some of the auxiliary strips 36. These strips may be formed during the formation of the insulator and the gate conductors of the MOS transistors.

[0075] As a variant, for other applications in which some transistors are connected in parallel as a whole, the main conductive strip 34 located in the insulating trench separating the rows of transistors can interconnect the auxiliary conductive strip 36 located between the emitters of two rows of transistors.

[0076] An advantage of the described embodiment is that the parasitic resistors between the base contact region and the different emitters have a lower resistance than in conventional implementations and are substantially the same for all transistors.

[0077] Another advantage of the described embodiment is that the interconnection of the contact area with the base, i.e. the auxiliary conductive strip 36, is not carried out via an interconnection network. Therefore, it is not necessary to provide enough space for metallization between the lower level metallizations of the interconnection network coupled to two adjacent emitters. Therefore, the distance between the two emitters depends only on the resolution of the mask used in the manufacture, the thickness of the insulator enabling the supplied voltage to be properly insulated and the thickness of the conductive strip.

[0078] Another advantage of the described embodiments is the increase in transistor density and therefore the density of memory cells. In the case where each word line comprises a single connection to the interconnect network, compared to a 10-bit ... Figure 1 Compared with the structure of the types in Figure 2 and Figure 3 The length of the description line is reduced by approximately 35%.

[0079] Specific embodiments have been described. Various changes, modifications and improvements will occur to those skilled in the art. In particular, the bipolar transistors described with respect to the drawings are PNP bipolar transistors. However, they may be NPN bipolar transistors.

[0080] Additionally, the transistors described in this disclosure have been described in the context of transistors controlling memory cells, and more particularly phase change memory cells. However, the described embodiments may also be implemented for rows of transistors with a common base used in other fields.

[0081] Various embodiments with different variations have been described above. It should be noted that those skilled in the art can combine various elements of these various embodiments and variations without showing any inventive step.

[0082] Such changes, modifications and improvements are intended to be part of the present disclosure and are intended to be within the spirit and scope of the present disclosure. Therefore, the foregoing description is exemplary only and is not intended to be limiting. The various embodiments described above may be combined to provide additional embodiments. Based on the above detailed description, these and other changes may be made to the embodiments. Generally, in the claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalents to which such claims are assigned. Therefore, the claims are not limited by the present disclosure.

Claims

1. A device, include: A plurality of bipolar transistors are arranged along a first direction, wherein the plurality of bipolar transistors include: A plurality of first conductive regions having a first conductivity type; a second conductive region having the first conductivity type; a common base located between the first conductive region and the second conductive region, the common base having a second conductive type different from the first conductive type, the second conductive region and the common base extending continuously below each of the plurality of first conductive regions; an isolation trench in contact with each bipolar transistor in the plurality of bipolar transistor rows; A comb-shaped conductive layer, wherein a first portion of the conductive layer extends on the insulating trench along the first direction, and a plurality of second portions of the conductive layer extend between adjacent first conductive regions along a second direction transverse to the first direction; and A spacer layer is located between the conductive layer and the first conductive region. 2 . The device of claim 1 , further comprising a metal layer located between the conductive layer and the common base.

3. An apparatus as claimed in claim 1, wherein each bipolar transistor of the plurality of bipolar transistors, in use, controls a corresponding memory cell in a phase change memory. The device of claim 1 , wherein the conductive layer is connected to an interconnect network through a single via. 5 . The device of claim 1 , wherein the plurality of first conductive regions contact the base, and the base contacts the second conductive region.

6. The device of claim 1, wherein the conductive layer is at least partially covered with insulating strips and polysilicon strips.

7. A method, include: A first row of transistors arranged along a first direction is formed, wherein the first row of transistors comprises: a first conductive region having a first dopant type; a common base located on the first conductive region, the common base having a second dopant type, the second dopant type being opposite to the first dopant type; a plurality of second conductive regions located on the common base, the plurality of second conductive regions having the first dopant type, each of the transistors in the first row comprising a corresponding second conductive region; and a first insulating trench extending along the first direction and contacting each transistor in the first row of transistors; forming a conductive layer on the first insulating trench and the common base, the conductive layer having a first portion and a plurality of second portions, the first portion extending along the first direction, the plurality of second portions extending from the first portion along a second direction, the second direction being transverse to the first direction, each of the plurality of second portions of the conductive layer extending between adjacent second conductive regions of the second conductive region; and A spacer layer is formed between the conductive layer and the second conductive region. 8 . The method of claim 7 , further comprising forming a metal layer between the conductive layer and the common base, wherein the conductive layer comprises polysilicon.

9. The method according to claim 7, further comprising: include: A second row of transistors arranged along the first direction is formed, and the transistors of the second row are separated from the transistors of the first row by the insulating trench.

10. The method according to claim 9, further comprising: include: A second insulating trench extending in the first direction and contacting each of the transistors in the second row is formed, the transistors in the second row being between the first insulating trench and the second insulating trench.

11. A method, include: Forming a plurality of bipolar transistors arranged along a first direction, the forming of the plurality of bipolar transistors comprising: forming a plurality of first conductive regions having a first conductivity type; forming a second conductive region having the first conductivity type; and forming a common base between the first conductive region and the second conductive region, the common base having a second conductive type different from the first conductive type, the second conductive region and the common base extending continuously below each of the plurality of first conductive regions; forming an isolation trench in contact with each bipolar transistor in the plurality of bipolar transistor rows; forming a comb-shaped conductive layer, wherein a first portion of the conductive layer extends on the insulating trench along the first direction, and a plurality of second portions of the conductive layer extend between adjacent first conductive regions along a second direction transverse to the first direction; and A spacer layer is formed between the conductive layer and the first conductive region. 12 . The method of claim 11 , further comprising forming a metal layer between the conductive layer and the common base.

13. The method of claim 11, wherein each bipolar transistor of the plurality of bipolar transistors is configured to control a corresponding memory cell in a phase change memory.

14. The method of claim 11, further comprising connecting the conductive layer to an interconnect network through a single via. 15 . The method of claim 11 , wherein the plurality of first conductive regions contact the base, and the base contacts the second conductive region.

16. The method of claim 11, further comprising at least partially covering the conductive layer with insulating strips and polysilicon strips. The method of claim 11 , wherein the conductive layer comprises polysilicon.

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