Diode device and forming method thereof

Abstract

The invention discloses a diode device and a forming method thereof. The diode device comprises a substrate; the well region is positioned in the substrate; a gate structure on the well region; the first doped region and the second doped region are located in the well region on the two sides of the gate structure respectively, the doping type of the first doped region is opposite to that of the well region, the doping type of the second doped region is the same as that of the well region, and the doping concentration of the second doped region is higher than that of the well region; the transition doped region is located in the well region between the second doped region and the gate structure, the doping type of the transition doped region is the same as that of the first doped region, and the doping concentration of the transition doped region is lower than that of the first doped region. Therefore, the diode device can be rapidly triggered, the turn-on voltage and the turn-on time of the diode device are reduced, rapid clamping of the diode device is realized, and the performance of the diode device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a diode device and a method for forming the same. Background Art

[0002] Electrostatic discharge (ESD) may damage the internal circuits of components, directly affecting the normal service life of the product, or even causing damage to the product. Therefore, when designing a chip, it is necessary to design an electrostatic discharge protection device on the port inside the chip.

[0003] Diode devices have been widely used in the field of electrostatic protection due to their advantages such as simple structure, low leakage current, and simple manufacturing process. However, as the silicon-on-insulator (SOI) process node gradually develops to below 65nm, the requirements for diode devices are becoming increasingly stringent.

[0004] At present, in the field of Radio Frequency SOI (RFSOI), there are Human Body Mode (HBM) and Charge-Device Mode (CDM). Since the Charge-Device Mode (CDM) event has a faster discharge time and a larger current, the clamping time and robustness of the diode device are required to be higher. However, in the field of SOI electrostatic protection, the fast clamping of diode devices needs to be further developed.

[0005] Therefore, the performance of existing electrostatic discharge protection devices needs to be improved urgently. Summary of the invention

[0006] The technical problem solved by the present invention is to provide a diode device and a method for forming the same, so as to improve the performance of the diode device.

[0007] To solve the above technical problems, an embodiment of the present invention provides a diode device, comprising: a substrate; a well region located in the substrate; a gate structure located on the well region; a first doping region and a second doping region respectively located in the well region on both sides of the gate structure, the doping type of the first doping region is opposite to that of the well region, the doping type of the second doping region is the same as that of the well region, and the doping concentration of the second doping region is higher than the doping concentration of the well region; a transition doping region located in the well region between the second doping region and the gate structure, the doping type of the transition doping region is the same as that of the first doping region, and the doping concentration of the transition doping region is lower than the doping concentration of the first doping region.

[0008] Optionally, the diode device further includes: a plurality of gate structures located on the well region, with a first doped region or a second doped region between adjacent gate structures.

[0009] Optionally, the diode device also includes: the doping type of the well region is P-type doping ions, the doping type of the first doping region is N-type doping ions, the doping type of the second doping region is P-type doping ions, and the doping type of the transition doping region is N-type doping ions.

[0010] Optionally, the diode device also includes: the doping type of the well region is N-type doping ions, the doping type of the first doping region is P-type doping ions, the doping type of the second doping region is N-type doping ions, and the doping type of the transition doping region is P-type doping ions.

[0011] Optionally, the diode device further includes: the transition doping region is in contact with the second doping region.

[0012] Optionally, the diode device further includes: the substrate includes a first semiconductor layer, an insulating layer located on the surface of the first semiconductor layer, and a second semiconductor layer located on the insulating layer; and the bottom of the well region is in contact with the top surface of the insulating layer.

[0013] Optionally, the diode device further includes: the number of layers of the second semiconductor layer is a combination of one or more layers, and the material of the second semiconductor layer includes: single crystal silicon, silicon germanium or germanium.

[0014] Optionally, the diode device further includes: an isolation structure located in the substrate, wherein the isolation structure surrounds the well region.

[0015] Optionally, the diode device further includes: a conductive structure located on a top surface of the first doping region and a top surface of the second doping region, wherein the conductive structure is electrically connected to the first doping region and the second doping region.

[0016] Optionally, the diode device further includes: a contact layer located on the top surface of the first doped region, the top surface of the second doped region, and the top surface of the transition doped region; and the conductive structure is located on the surface of the contact layer.

[0017] Optionally, the first doping region and the second doping region have the same depth in a direction perpendicular to the substrate, and the transition doping region has a smaller depth than the first doping region in a direction perpendicular to the substrate.

[0018] Optionally, the depth of the first doping region, the second doping region and the transition doping region in a direction perpendicular to the substrate ranges from 30 nanometers to 200 nanometers.

[0019] Optionally, the ion doping concentration of the first doping region is 2.0×10 13 atom / cm 3 Up to 8×10 15 atom / cm 3 The ion doping concentration of the second doping region is 1.0×10 13 atom / cm 3 Up to 9×10 15 atom / cm 3 The doping concentration of the transition doping region is 0.8×10 13 atom / cm 3 to 7.2×10 15 atom / cm 3 .

[0020] Correspondingly, the technical solution of the present invention also provides a method for forming a diode device, including: providing a substrate; forming a well region in the substrate; forming a gate structure on the well region; forming a first doping region and a second doping region in the well regions on both sides of the gate structure, respectively, the doping type of the first doping region is opposite to that of the well region, the doping type of the second doping region is the same as that of the well region, and the doping concentration of the second doping region is higher than the doping concentration of the well region; forming a transition doping region in the well region between the second doping region and the gate structure, the doping type of the transition doping region is the same as that of the first doping region, and the doping concentration of the transition doping region is lower than the doping concentration of the first doping region.

[0021] Optionally, the method for forming the diode device further includes: forming a plurality of gate structures on the well region, and forming a first doped region or a second doped region between adjacent gate structures.

[0022] Optionally, the method for forming the first doping region includes: performing a first ion implantation process on the substrate to form a well region; and performing a second ion implantation process on the well region to form the first doping region.

[0023] Optionally, the method for forming the second doping region includes: performing a third ion implantation process on the well region to form the second doping region.

[0024] Optionally, the method for forming the transition doping region includes: performing a fourth ion implantation process on the well region to form the transition doping region, wherein the transition doping region is in contact with the second doping region.

[0025] Optionally, the doping type of the first ion implantation process is P-type ions, the ion implantation energy of the first ion implantation process is 50 KeV, and the ion implantation dose of the first ion implantation process is 1.0×10 12 atom / cm2 Up to 9×10 12 atom / cm 2 The doping type of the second ion implantation process is N-type ions, the ion implantation energy of the second ion implantation process is 5KeV to 100KeV, and the ion implantation dose of the second ion implantation process is 1.0×10 13 atom / cm 2 Up to 9×10 15 atom / cm 2 The doping type of the third ion implantation process is P-type ions, the ion implantation energy of the third ion implantation process is 5KeV to 100KeV, and the ion implantation dose of the third ion implantation process is 2.0×10 13 atom / cm 2 Up to 8×10 15 atom / cm 2 ; The doping type of the fourth ion implantation treatment is N-type ions, the ion implantation energy of the fourth ion implantation treatment is less than the ion implantation energy of the second ion implantation treatment, and the ion implantation dose of the fourth ion implantation treatment is less than the ion implantation dose of the second ion implantation treatment.

[0026] Optionally, the doping type of the first ion implantation process is N-type ions, the ion implantation energy of the first ion implantation process is 50 KeV, and the ion implantation dose of the first ion implantation process is 1.0×10 12 atom / cm 2 Up to 9×10 12 atom / cm 2 The doping type of the second ion implantation process is P-type ions, the ion implantation energy of the second ion implantation process is 5KeV to 100KeV, and the ion implantation dose of the second ion implantation process is 2.0×10 13 atom / cm 2 Up to 8×10 15 atom / cm 2 The doping type of the third ion implantation process is N-type ions, the ion implantation energy of the third ion implantation process is 5KeV to 100KeV, and the ion implantation dose of the third ion implantation process is 1.0×10 13 atom / cm 2 Up to 9×10 15 atom / cm 2 ; The doping type of the fourth ion implantation treatment is P-type ions, the ion implantation energy of the fourth ion implantation treatment is less than the ion implantation energy of the second ion implantation treatment, and the ion implantation dose of the fourth ion implantation treatment is less than the ion implantation dose of the second ion implantation treatment.

[0027] Optionally, the substrate includes a first semiconductor layer, an insulating layer located on the surface of the first semiconductor layer, and a second semiconductor layer located on the insulating layer; the bottom of the well region is in contact with the top surface of the insulating layer.

[0028] Optionally, the second semiconductor layer has one or more layers, and the material of the second semiconductor layer includes: single crystal silicon, silicon germanium or germanium.

[0029] Optionally, the method for forming the diode device also includes: after forming the well region, etching both sides of the well region until the insulating layer is exposed to form a shallow trench; depositing an initial isolation structure in the shallow trench; and planarizing the initial isolation structure to form an isolation structure.

[0030] Optionally, the method for forming the gate structure includes: after forming the well region, depositing a gate structure on a top surface of the well region, wherein the gate structure exposes a portion of the top surface of the well region.

[0031] Optionally, the method for forming the diode device further includes: after forming the gate structure, depositing a contact layer on top surfaces of the first doping region, the second doping region, and the transition doping region.

[0032] Optionally, the method for forming the diode device further includes: after forming the contact layer, forming a conductive structure on the surface of the contact layer at the top of the first doping region and the second doping region, wherein the conductive structure is electrically connected to the first doping region and the second doping region.

[0033] Optionally, the first doping region and the second doping region have the same depth in a direction perpendicular to the substrate, and the transition doping region has a smaller depth than the first doping region in a direction perpendicular to the substrate.

[0034] Optionally, the depth of the first doping region, the second doping region and the transition doping region in a direction perpendicular to the substrate ranges from 30 nanometers to 200 nanometers.

[0035] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0036] In the diode device provided by the technical solution of the present invention, the first doped region located in the well region, the transition doped region, and the gate structure constitute a MOS tube, and the first doped region located in the well region and the second doped region constitute a PN junction, that is, a diode device, so that the diode device can be quickly triggered by the MOS tube, thereby reducing the turn-on voltage and turn-on time of the diode device, realizing the rapid clamping of the diode device, and improving the performance of the diode device. In addition, the technical solution of the present invention controls the connection mode of the gate structure, thereby controlling the turn-on and turn-off of the MOS tube, so that the diode device is in two states of triggering and non-triggering. When the diode device is in the triggered state, the MOS tube is turned on, and the conductivity between the second doped region and the first doped region to form a PN junction increases, thereby reducing the turn-on time of the diode device, so that the diode device can handle the charging device mode (with faster discharge time and larger current) event, and by adjusting the voltage applied to the gate structure, the turn-on voltage and turn-on time of the diode device are regulated; when the diode device is in the non-triggered state, the MOS tube is turned off, and the second doped region and the first doped region form a PN junction that is normally turned on, so that the diode device can handle the human body discharge mode (slow discharge time and small current) event, thereby reducing the power consumption of the diode device.

[0037] Furthermore, by adjusting the depth of the transition doping region perpendicular to the substrate surface, the area of ​​the well region is increased, thereby increasing the conductivity between the first doping region and the second doping region (ie, the PN junction), reducing the turn-on time of the diode device, and improving the performance of the diode device.

[0038] Furthermore, the diode device provided by the technical solution of the present invention can be formed on different substrates, thereby improving the uniformity and stability of the manufacturing process.

[0039] In the method for forming a diode device provided by the technical solution of the present invention, the first doped region in the well region, the transition doped region, and the gate structure constitute a MOS tube, and the first doped region in the well region and the second doped region constitute a PN junction, that is, a diode device, so that the diode device can be quickly triggered by the MOS tube, thereby reducing the turn-on voltage and turn-on time of the diode device, realizing rapid clamping of the diode device, and improving the performance of the diode device. In addition, the technical solution of the present invention controls the connection mode of the gate structure to control the opening and closing of the MOS tube, so that the diode device is in two states: triggered and untriggered. When the diode device is in the triggered state, the MOS tube is turned on, and the conductivity between the second doped region and the first doped region to form a PN junction is increased, thereby reducing the turn-on time of the diode device, so that the diode device can handle the charging device mode (with faster discharge time and larger current) event, and by adjusting the voltage applied to the gate structure, the turn-on voltage and turn-on time of the diode device are regulated; when the diode device is in the untriggered state, the MOS tube is turned off, and the second doped region and the first doped region form a PN junction that is normally turned on, so that the diode device can handle the human body discharge mode (slow discharge time and small current) event, thereby reducing the power consumption of the diode device.

[0040] Furthermore, by adjusting the depth of the transition doping region perpendicular to the substrate surface, the area of ​​the well region is increased, thereby increasing the conductivity between the first doping region and the second doping region (PN junction), reducing the turn-on time of the diode device, and improving the performance of the diode device.

[0041] Furthermore, the diode device provided by the technical solution of the present invention can be formed on different substrates, thereby improving the uniformity and stability of the manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a schematic diagram of the structure of a diode device;

[0043] Figures 2 to 7 is a structural schematic diagram of a process for forming a diode device in one embodiment of the present invention;

[0044] Figures 8 to 12 It is a structural schematic diagram of the formation process of a diode device in another embodiment of the present invention. DETAILED DESCRIPTION

[0045] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0046] As described in the background art, it is necessary to improve the performance of diode devices.

[0047] Figure 1 It is a structural diagram of a diode device.

[0048] Please refer to Figure 1 The diode device includes: a substrate, the substrate includes a first semiconductor layer 100, an insulating layer 101 located on the surface of the first semiconductor layer 100, and a second semiconductor layer (not shown in the figure) located on the insulating layer 101, the substrate includes a well region 102 arranged along a first direction X parallel to the substrate surface; a plurality of mutually discrete first doping regions 103 located in the well region 102, and the plurality of first doping regions 103 are arranged along the first direction X; and a plurality of mutually discrete second doping regions 104 located in the well region 102.

[0049] In this embodiment, the diode device further includes: an isolation structure 105 located in the substrate, and the isolation structure 105 surrounds the well region.

[0050] In this embodiment, the diode device further includes: a gate layer 106 located on the top surface of the well region 102 .

[0051] In the above scheme, the first doped region 103, the second doped region 104 and the gate layer 106 form a PN junction, that is, a diode device. By applying a voltage to the gate layer, the second doped region 104 and the first doped region 103 are conductive, triggering the diode device, and then quickly clamping the voltage to achieve electrostatic protection. Since the Charge-Device Mode (CDM) event has a faster discharge time and a larger current, the clamping time and robustness of the diode device are required to be higher.

[0052] However, the turn-on time of the diode device in the above solution is only related to the conduction time of the PN junction, so that the turn-on time of the diode device cannot be reduced, and further when a Charge-Device Mode (CDM) event occurs, the voltage cannot be clamped in time, resulting in damage to the device under high voltage.

[0053] In order to solve the above technical problems, in the diode device provided by the technical solution of the present invention, the first doped region located in the well region, the transition doped region, and the gate structure constitute a MOS tube, and the first doped region located in the well region and the second doped region constitute a PN junction, that is, a diode device, so that the diode device can be quickly triggered by the MOS tube, thereby reducing the turn-on voltage and turn-on time of the diode device, realizing rapid clamping of the diode device, and improving the performance of the diode device. In addition, the technical solution of the present invention controls the connection mode of the gate structure to control the opening and closing of the MOS tube, so that the diode device is in two states: triggered and untriggered. When the diode device is in the triggered state, the MOS tube is turned on, and the conductivity between the second doped region and the first doped region to form a PN junction is increased, thereby reducing the turn-on time of the diode device, so that the diode device can handle the charging device mode (with faster discharge time and larger current) event, and by adjusting the voltage applied to the gate structure, the turn-on voltage and turn-on time of the diode device are regulated; when the diode device is in the untriggered state, the MOS tube is turned off, and the second doped region and the first doped region form a PN junction that is normally turned on, so that the diode device can handle the human body discharge mode (slow discharge time and small current) event, thereby reducing the power consumption of the diode device.

[0054] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0055] Figures 2 to 7 It is a structural schematic diagram of the formation process of a diode device in one embodiment of the present invention.

[0056] Please refer to Figure 2 , providing a substrate; forming a well region I in the substrate.

[0057] In this embodiment, the substrate includes a first semiconductor layer 200, an insulating layer 201 located on the surface of the first semiconductor layer 200, and a second semiconductor layer (not shown in the figure) located on the insulating layer 201; the bottom of the well region I is in contact with the top surface of the insulating layer 201.

[0058] The second semiconductor layer (not shown in the figure) is used to provide a holding space for the first doping region to the third doping region and the transition doping region to be formed subsequently.

[0059] The second semiconductor layer (not shown in the figure) has one or more layers. The material of the second semiconductor layer (not shown in the figure) includes: single crystal silicon, silicon germanium or germanium.

[0060] In this embodiment, the material of the second semiconductor layer (not shown in the figure) is single crystal silicon.

[0061] The substrate material also includes silicon carbide, silicon germanium, and a multi-component semiconductor material composed of group III-V elements. Among them, the multi-component semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0062] The method for forming the well region I includes: performing a first ion implantation process on the substrate to form the well region I.

[0063] In this embodiment, the doping type of the first ion implantation process is P-type ions, the ion implantation energy of the first ion implantation process is 50 KeV, and the ion implantation dose of the first ion implantation process is 1.0×10 12 atom / cm 2 Up to 9×10 12 atom / cm 2 .

[0064] In another embodiment, the doping type of the first ion implantation process is N-type ions, the ion implantation energy of the first ion implantation process is 50 KeV, and the ion implantation dose of the first ion implantation process is 1.0×10 12 atom / cm 2 Up to 9×10 12 atom / cm 2 .

[0065] In this embodiment, the width of the well region I ranges from 1 micrometer to 8 micrometers, and the depth of the well region I ranges from 30 nanometers to 200 nanometers.

[0066] The method for forming the diode device also includes: after forming the well region I, etching both sides of the well region I until the insulating layer 201 is exposed to form a shallow trench; depositing an initial isolation structure 202 in the shallow trench; and planarizing the initial isolation structure 202 to form an isolation structure 202.

[0067] The shallow trench (not shown in the figure) is used to accommodate the isolation structure 202 formed subsequently.

[0068] In this embodiment, the depth of the shallow trench is consistent with that of the second semiconductor layer.

[0069] In another embodiment, the depth of the shallow trench is 10 nanometers greater than the thickness of the second semiconductor layer, that is, the shallow trench is overetched by 10 nanometers to achieve electrical isolation between different diode devices.

[0070] The isolation structure 202 is used to avoid electrical crosstalk between adjacent electrostatic discharge protection devices.

[0071] The method of forming the isolation structure 202 includes one or more of chemical vapor deposition, physical deposition, atomic layer deposition, and jet vapor deposition, and the reaction temperature ranges from 400 degrees Celsius to 800 degrees Celsius.

[0072] In this embodiment, the isolation structure 202 is formed by chemical vapor deposition.

[0073] Planarization methods include mechanical polishing, chemical polishing, fluid polishing, and chemical mechanical polishing.

[0074] In this embodiment, the planarization process is performed by mechanical polishing.

[0075] In this embodiment, the material of the isolation structure 202 includes silicon oxide.

[0076] Please refer to Figure 3 , a gate structure 203 is formed on the well region I.

[0077] The method for forming the gate structure 203 includes: after forming the well region I, depositing the gate structure 203 on the top surface of the well region I, wherein the gate structure 203 exposes a portion of the top surface of the well region I.

[0078] In this embodiment, the material of the gate structure 203 includes polysilicon.

[0079] The method for forming the gate structure 203 includes: depositing an initial gate structure 203 (not shown in the figure) on the top surface of the well region I, forming a mask layer on the surface of the initial gate structure 203 (not shown in the figure), the mask layer (not shown in the figure) exposing a portion of the surface of the initial gate structure 203 (not shown in the figure); using the mask layer as a mask, etching the initial gate structure 203 (not shown in the figure) to form a plurality of discrete gate structures 203.

[0080] The process of etching the initial gate layer includes wet etching or dry etching. Wet etching is a technique of etching by immersing the etching material in an etching solution. It is a pure chemical etching with excellent selectivity. Wet etching is isotropic. Dry etching includes isotropic radial etching, reactive ion etching, sputtering etching, ion milling, ion beam assisted etching, reactive ion beam etching, etc. Dry etching is anisotropic.

[0081] In this embodiment, the process of etching the initial gate structure 203 is wet etching.

[0082] The gate structure 203 is formed by one or more methods including chemical vapor deposition, physical deposition, atomic layer deposition, and jet vapor deposition. The deposition gas includes hydrogen and monosilane. The reaction temperature ranges from 400 degrees Celsius to 800 degrees Celsius.

[0083] In this embodiment, the width of the gate structure 203 is in the range of 0.2 micrometers to 2 micrometers.

[0084] The connection modes of the gate structure 203 include: gate floating, gate grounding and gate bias; when the connection mode of the gate structure 203 is gate floating, gate grounding or the bias voltage applied to the gate structure is 0V, the turn-on voltage of the diode device is greater than 2V.

[0085] When the bias voltage applied to the gate structure 203 increases, the turn-on voltage of the diode decreases, and the turn-on time of the diode also decreases. In a specific embodiment, when the bias voltage applied to the gate structure 203 is 0.5V, the turn-on voltage of the diode is 1.5V, and the turn-on time range of the diode is 0 nanoseconds to 2 nanoseconds; when the bias voltage applied to the gate structure 203 is 1V, the turn-on voltage of the diode is 1V, and the turn-on time range of the diode is 0 nanoseconds to 2 nanoseconds.

[0086] Please refer to Figure 4 A first doping region 204 and a second doping region 205 are respectively formed in the well region I on both sides of the gate structure 203, wherein the doping type of the first doping region 204 is opposite to that of the well region I, the doping type of the second doping region 205 is the same as that of the well region I, and the doping concentration of the second doping region 205 is higher than the doping concentration of the well region I.

[0087] In this embodiment, the first doped region 204 is located between the gate structure 203 and the isolation structure 202 .

[0088] The method for forming the first doping region 204 includes: performing a second ion implantation process on the well region I to form the first doping region 204 .

[0089] The method for forming the second doping region 205 includes: performing a third ion implantation process on the well region I to form the second doping region 205 .

[0090] In this embodiment, the doping type of the second ion implantation process is N-type ions, the ion implantation energy of the second ion implantation process is 5KeV to 100KeV, and the ion implantation dose of the second ion implantation process is 1.0×10 13 atom / cm 2 Up to 9×10 15 atom / cm2 .

[0091] In this embodiment, the doping type of the third ion implantation process is P-type ions, the ion implantation energy of the third ion implantation process is 5KeV to 100KeV, and the ion implantation dose of the third ion implantation process is 2.0×10 13 atom / cm 2 Up to 8×10 15 atom / cm 2 .

[0092] In this embodiment, the width of the first doping region 204 ranges from 0.3 microns to 2 microns, and the depth of the first doping region 204 ranges from 30 nanometers to 200 nanometers; the width of the second doping region 205 ranges from 0.3 to 2 microns, and the depth of the second doping region 205 ranges from 30 nanometers to 200 nanometers.

[0093] Please refer to Figure 5 A transition doping region 206 is formed in the well region I between the second doping region 205 and the gate structure 203 , and the doping type of the transition doping region 206 is the same as that of the first doping region 204 , and the doping concentration of the transition doping region 206 is lower than the doping concentration of the first doping region 204 .

[0094] The method for forming the transition doping region 206 includes: performing a fourth ion implantation process on the well region I to form the transition doping region 206 , wherein the transition doping region 206 is in contact with the second doping region 205 .

[0095] The doping concentration of the transition doping region 206 is 0.4 to 0.9 times the doping concentration of the first doping region 204 .

[0096] In this embodiment, the doping type of the fourth ion implantation treatment is N-type ions, the ion implantation energy of the fourth ion implantation treatment is less than the ion implantation energy of the second ion implantation treatment, and the ion implantation dose of the fourth ion implantation treatment is less than the ion implantation dose of the second ion implantation treatment.

[0097] In this embodiment, the first doping region 204 and the second doping region 205 have the same depth in the direction perpendicular to the substrate, and the transition doping region 206 has a smaller depth than the first doping region 204 in the direction perpendicular to the substrate.

[0098] In this embodiment, the width of the transition doping region 206 ranges from 0.2 micrometers to 2 micrometers, and the depth of the transition doping region 206 ranges from 30 nanometers to 200 nanometers.

[0099] By adjusting the depth of the transition doping region 206 perpendicular to the substrate surface, the area of ​​the well region I is increased, thereby increasing the conductivity between the first doping region 204 and the second doping region 205 (ie, the PN junction), reducing the turn-on time of the diode device, and improving the performance of the diode device.

[0100] In this embodiment, the first doped region 204, the well region I and the transition doped region 206 constitute a MOS transistor.

[0101] In the connection mode of the gate bias, since different biases are applied to the gate structure 203, the MOS tube is controlled to be turned on or off, thereby adjusting different turn-on voltages of the diode device.

[0102] Please refer to Figure 6 After forming the gate structure 203 , a contact layer 207 is deposited on the top surfaces of the first doping region 204 , the second doping region 205 , and the transition doping region 206 .

[0103] In this embodiment, the material of the contact layer 207 is metal silicide.

[0104] The metal silicide material may be titanium silicide, cobalt silicide, nickel platinum silicide or the like.

[0105] Please refer to Figure 7 After the contact layer 207 is formed, a conductive structure 208 is formed on the surface of the contact layer 207 at the top of the first doping region 204 and the second doping region 205 , and the conductive structure 208 is electrically connected to the first doping region 204 and the second doping region 205 .

[0106] The conductive structure 208 includes a plurality of conductive plugs.

[0107] The material of the conductive structure 208 includes a metallic conductive material.

[0108] In this embodiment, the conductive structure 208 is made of aluminum.

[0109] In this embodiment, the first doped region 204 is electrically connected to the cathode terminal through the conductive structure 208 , and the second doped region 205 is electrically connected to the anode terminal through the conductive structure 208 .

[0110] Figures 8 to 12 It is a structural schematic diagram of the formation process of a diode device in another embodiment of the present invention.

[0111] exist Figure 2 Based on Figure 8 , a gate structure 301 is formed on the well region I.

[0112] The method for forming the gate structure 301 includes: after forming the well region I, depositing the gate structure 301 on the top surface of the well region I, wherein the gate structure 301 exposes a portion of the top surface of the well region I.

[0113] In this embodiment, the material of the gate structure 301 includes polysilicon.

[0114] The method for forming the gate structure 301 includes: depositing an initial gate structure 301 (not shown in the figure) on the top surface of the well region I, forming a mask layer on the surface of the initial gate structure 301 (not shown in the figure), the mask layer (not shown in the figure) exposing a portion of the surface of the initial gate structure 301 (not shown in the figure); using the mask layer as a mask, etching the initial gate structure 301 (not shown in the figure) to form a plurality of discrete gate structures 301.

[0115] The process of etching the initial gate layer includes wet etching or dry etching. Wet etching is a technique of etching by immersing the etching material in an etching solution. It is a pure chemical etching with excellent selectivity. Wet etching is isotropic. Dry etching includes isotropic radial etching, reactive ion etching, sputtering etching, ion milling, ion beam assisted etching, reactive ion beam etching, etc. Dry etching is anisotropic.

[0116] In this embodiment, the process of etching the initial gate structure 301 is wet etching.

[0117] The gate structure 301 is formed by one or more of chemical vapor deposition, physical deposition, atomic layer deposition, and jet vapor deposition. The deposition gas includes hydrogen and monosilane. The reaction temperature ranges from 400 degrees Celsius to 800 degrees Celsius.

[0118] In this embodiment, the width of the gate structure 301 is in a range of 0.2 micrometers to 2 micrometers.

[0119] The connection modes of the gate structure 301 include: gate floating, gate grounding and gate bias; when the connection mode of the gate structure 301 is gate floating, gate grounding or the bias voltage applied to the gate is 0V, the turn-on voltage of the diode device is greater than 2V.

[0120] When the bias voltage applied to the gate structure 301 increases, the turn-on voltage of the diode decreases, and the turn-on time of the diode also decreases. In a specific embodiment, when the bias voltage applied to the gate structure 301 is 0.5V, the turn-on voltage of the diode is 1.5V, and the turn-on time range of the diode is 0 nanoseconds to 2 nanoseconds; when the bias voltage applied to the gate structure 301 is 1V, the turn-on voltage of the diode is 1V, and the turn-on time range of the diode is 0 nanoseconds to 2 nanoseconds.

[0121] Please refer to Fig. 9 , a first doping region 302 and a second doping region 303 are respectively formed in the well region I on both sides of the gate structure 301, the doping type of the first doping region 302 is opposite to that of the well region I, the doping type of the second doping region 303 is the same as that of the well region I, and the doping concentration of the second doping region 303 is higher than the doping concentration of the well region I.

[0122] In this embodiment, the first doped region 302 is located between adjacent gate structures 301 .

[0123] The method for forming the first doping region 302 includes: performing a second ion implantation process on the well region I to form the first doping region 302 .

[0124] The method for forming the second doping region 303 includes: performing a third ion implantation process on the well region I to form the second doping region 303 .

[0125] In this embodiment, the doping type of the second ion implantation process is P-type ions, the ion implantation energy of the second ion implantation process is 5KeV to 100KeV, and the ion implantation dose of the second ion implantation process is 2.0×10 13 atom / cm 2 Up to 8×10 15 atom / cm 2 .

[0126] In this embodiment, the doping type of the third ion implantation process is N-type ions, the ion implantation energy of the third ion implantation process is 5KeV to 100KeV, and the ion implantation dose of the third ion implantation process is 1.0×10 13 atom / cm 2 Up to 9×10 15 atom / cm 2 .

[0127] In this embodiment, the width of the first doping region 302 ranges from 0.3 microns to 2 microns, and the depth of the first doping region 302 ranges from 30 nanometers to 200 nanometers; the width of the second doping region 303 ranges from 0.3 to 2 microns, and the depth of the second doping region 303 ranges from 30 nanometers to 200 nanometers.

[0128] Please refer to Fig.10 A transition doping region 304 is formed in the well region I between the second doping region 303 and the gate structure 301, and the doping type of the transition doping region 304 is the same as that of the first doping region 302, and the doping concentration of the transition doping region 304 is lower than the doping concentration of the first doping region 302.

[0129] The method for forming the transition doping region 304 includes: performing a fourth ion implantation process on the well region I to form the transition doping region 304 , wherein the transition doping region 304 is in contact with the second doping region 303 .

[0130] In this embodiment, the doping type of the fourth ion implantation treatment is P-type ions, the ion implantation energy of the fourth ion implantation treatment is less than the ion implantation energy of the second ion implantation treatment, and the ion implantation dose of the fourth ion implantation treatment is less than the ion implantation dose of the second ion implantation treatment.

[0131] In this embodiment, the first doping region 302 and the second doping region 303 have the same depth in the direction perpendicular to the substrate, and the transition doping region 304 has a smaller depth than the first doping region 302 in the direction perpendicular to the substrate.

[0132] In this embodiment, the width of the transitional doping region 304 ranges from 0.2 micrometers to 2 micrometers, and the depth of the transitional doping region 304 ranges from 30 nanometers to 200 nanometers.

[0133] By adjusting the depth of the transition doping region 304 perpendicular to the substrate surface, the area of ​​the well region I is increased, thereby increasing the conductivity between the first doping region 302 and the second doping region 303 (ie, the PN junction), reducing the turn-on time of the diode device, and improving the performance of the diode device.

[0134] Please refer to Fig.11 After forming the gate structure 301 , a contact layer 305 is deposited on the top surfaces of the first doping region 302 , the second doping region 303 and the transition doping region 304 .

[0135] In this embodiment, the material of the contact layer 305 is metal silicide.

[0136] The metal silicide material may be titanium silicide, cobalt silicide, nickel platinum silicide or the like.

[0137] Please refer to Fig.12 After the contact layer 305 is formed, a conductive structure 306 is formed on the surface of the contact layer 305 at the top of the first doping region 302 and the second doping region 303 , and the conductive structure 306 is electrically connected to the first doping region 302 and the second doping region 303 .

[0138] The conductive structure 306 includes a plurality of conductive plugs.

[0139] The material of the conductive structure 306 includes a metallic conductive material.

[0140] In this embodiment, the conductive structure 306 is made of aluminum.

[0141] In this embodiment, the first doped region 302 is electrically connected to the anode terminal through the conductive structure 306 , and the second doped region 303 is electrically connected to the cathode terminal through the conductive structure 306 .

[0142] Please continue to refer to Fig.12 The technical solution of the present invention also provides a diode device, comprising: a substrate; a well region I located in the substrate; a gate structure 301 located on the well region I; a first doping region 302 and a second doping region 303 located in the well region I on both sides of the gate structure 301, respectively, wherein the doping type of the first doping region 302 is opposite to that of the well region I, the doping type of the second doping region 303 is the same as that of the well region I, and the doping concentration of the second doping region 303 is higher than the doping concentration of the well region I; a transition doping region 304 located in the well region I between the second doping region 303 and the gate structure 301, wherein the doping type of the transition doping region 304 is the same as that of the first doping region 302, and the doping concentration of the transition doping region 304 is lower than the doping concentration of the first doping region 302.

[0143] In this embodiment, the diode device further includes: a plurality of gate structures 301 located on the well region I, and a first doping region 302 or a second doping region 303 is provided between adjacent gate structures 301 .

[0144] In this embodiment, the diode device also includes: the doping type of the well region I is P-type doping ions, the doping type of the first doping region 302 is N-type doping ions, the doping type of the second doping region 303 is P-type doping ions, and the doping type of the transition doping region 304 is N-type doping ions.

[0145] In this embodiment, the diode device also includes: the doping type of the well region I is N-type doping ions, the doping type of the first doping region 302 is P-type doping ions, the doping type of the second doping region 303 is N-type doping ions, and the doping type of the transition doping region 304 is P-type doping ions.

[0146] In this embodiment, the diode device further includes: the transition doping region 304 is in contact with the second doping region 303 .

[0147] In this embodiment, the substrate includes a first semiconductor layer 200, an insulating layer 202 located on the surface of the first semiconductor layer 200, and a second semiconductor layer (not shown in the figure) located on the insulating layer 202; the bottom of the well region I is in contact with the top surface of the insulating layer 202.

[0148] In this embodiment, the second semiconductor layer (not shown in the figure) has one or more layers, and the material of the second semiconductor layer (not shown in the figure) includes: single crystal silicon, silicon germanium or germanium.

[0149] In this embodiment, the diode device further includes: an isolation structure located in the substrate, wherein the isolation structure surrounds the well region I.

[0150] In this embodiment, the diode device further includes: a conductive structure 306 located on the top surface of the first doping region 302 and the top surface of the second doping region 303 , and the conductive structure 306 is electrically connected to the first doping region 302 and the second doping region 303 .

[0151] In this embodiment, the diode device further includes: a contact layer 305 located on the top surface of the first doping region 302 , the top surface of the second doping region 303 , and the top surface of the transition doping region 304 ; and the conductive structure 306 is located on the surface of the contact layer 305 .

[0152] In this embodiment, the first doping region 302 and the second doping region 303 have the same depth in the direction perpendicular to the substrate, and the transition doping region 304 has a smaller depth than the first doping region 302 in the direction perpendicular to the substrate.

[0153] In this embodiment, the depth of the first doping region 302 , the second doping region 303 , and the transition doping region 304 in a direction perpendicular to the substrate ranges from 30 nanometers to 200 nanometers.

[0154] In this embodiment, the ion doping concentration of the first doping region 302 is 2.0×10 13 atom / cm 3 Up to 8×10 15 atom / cm 3The ion doping concentration of the second doping region 303 is 1.0×10 13 atom / cm 3 Up to 9×10 15 atom / cm 3 The doping concentration of the transition doping region 304 is 0.8×10 13 atom / cm 3 to 7.2×10 15 atom / cm 3 .

[0155] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A diode device, It is characterized in that include: substrate; a well region located in the substrate; a gate structure located on the well region; A first doping region and a second doping region respectively located in the well regions on both sides of the gate structure, wherein the doping type of the first doping region is opposite to that of the well region, the doping type of the second doping region is the same as that of the well region, and the doping concentration of the second doping region is higher than the doping concentration of the well region; A transition doping region is located in the well region between the second doping region and the gate structure, wherein the doping type of the transition doping region is the same as that of the first doping region, and the doping concentration of the transition doping region is lower than the doping concentration of the first doping region.

2. The diode device according to claim 1, It is characterized in that Also includes: A plurality of gate structures are located on the well region, and a first doping region or a second doping region is provided between adjacent gate structures.

3. The diode device according to claim 2, It is characterized in that Also includes: The doping type of the well region is P-type doping ions, the doping type of the first doping region is N-type doping ions, the doping type of the second doping region is P-type doping ions, and the doping type of the transition doping region is N-type doping ions.

4. The diode device according to claim 2, It is characterized in that Also includes: The doping type of the well region is N-type doping ions, the doping type of the first doping region is P-type doping ions, the doping type of the second doping region is N-type doping ions, and the doping type of the transition doping region is P-type doping ions.

5. The diode device according to claim 1, It is characterized in that Also includes: The transition doping region is in contact with the second doping region.

6. The diode device according to claim 1, It is characterized in that The substrate comprises a first semiconductor layer, an insulating layer located on the surface of the first semiconductor layer, and a second semiconductor layer located on the insulating layer; The bottom of the well region contacts the top surface of the insulating layer.

7. The diode device according to claim 6, It is characterized in that The second semiconductor layer has one or more layers, and the material of the second semiconductor layer includes: single crystal silicon, silicon germanium or germanium.

8. The diode device according to claim 1, It is characterized in that Also includes: An isolation structure is located in the substrate, and the isolation structure surrounds the well region.

9. The diode device according to claim 1, It is characterized in that Also includes: A conductive structure is located on the top surface of the first doping region and the top surface of the second doping region, and the conductive structure is electrically connected to the first doping region and the second doping region.

10. The diode device according to claim 9, It is characterized in that Also includes: A contact layer located on the top surface of the first doped region, the top surface of the second doped region, and the top surface of the transition doped region; The conductive structure is located on the surface of the contact layer.

11. The diode device according to claim 1, It is characterized in that The first doping region and the second doping region have the same depth in a direction perpendicular to the substrate, and the transition doping region has a smaller depth than the first doping region in a direction perpendicular to the substrate.

12. The diode device according to claim 11, It is characterized in that The depths of the first doping region, the second doping region and the transition doping region in a direction perpendicular to the substrate range from 30 nanometers to 200 nanometers.

13. The diode device according to claim 1, It is characterized in that The ion doping concentration of the first doping region is 2.0×10 13 atom / cm 3 Up to 8×10 15 atom / cm 3 The ion doping concentration of the second doping region is 1.0×10 13 atom / cm 3 Up to 9×10 15 atom / cm 3 The doping concentration of the transition doping region is 0.8×10 13 atom / cm 3 to 7.2×10 15 atom / cm 3 .

14. A method for forming a diode device, It is characterized in that include: providing a substrate; forming a well region in the substrate; forming a gate structure on the well region; forming a first doping region and a second doping region in the well regions on both sides of the gate structure respectively, wherein the doping type of the first doping region is opposite to that of the well region, the doping type of the second doping region is the same as that of the well region, and the doping concentration of the second doping region is higher than the doping concentration of the well region; A transition doping region is formed in the well region between the second doping region and the gate structure. The doping type of the transition doping region is the same as that of the first doping region, and the doping concentration of the transition doping region is lower than the doping concentration of the first doping region.

15. The method for forming a diode device according to claim 14, It is characterized in that Also includes: A plurality of gate structures are formed on the well region, and a first doping region or a second doping region is formed between adjacent gate structures.

16. The method for forming a diode device according to claim 15, It is characterized in that The method for forming the first doping region includes: performing a first ion implantation process on the substrate to form a well region; and performing a second ion implantation process on the well region to form the first doping region.

17. The method for forming a diode device according to claim 16, It is characterized in that The method for forming the second doping region includes: performing a third ion implantation process on the well region to form the second doping region.

18. The method for forming a diode device according to claim 17, It is characterized in that The method for forming the transition doping region includes: performing a fourth ion implantation process on the well region to form the transition doping region, wherein the transition doping region is in contact with the second doping region.

19. The method for forming a diode device according to claim 18, It is characterized in that The doping type of the first ion implantation process is P-type ions, the ion implantation energy of the first ion implantation process is 50 KeV, and the ion implantation dose of the first ion implantation process is 1.0×10 12 atom / cm 2 Up to 9×10 12 atom / cm 2 The doping type of the second ion implantation process is N-type ions, the ion implantation energy of the second ion implantation process is 5KeV to 100KeV, and the ion implantation dose of the second ion implantation process is 1.0×10 13 atom / cm 2 Up to 9×10 15 atom / cm 2 The doping type of the third ion implantation process is P-type ions, the ion implantation energy of the third ion implantation process is 5KeV to 100KeV, and the ion implantation dose of the third ion implantation process is 2.0×10 13 atom / cm 2 Up to 8×10 15 atom / cm 2 ; The doping type of the fourth ion implantation treatment is N-type ions, the ion implantation energy of the fourth ion implantation treatment is less than the ion implantation energy of the second ion implantation treatment, and the ion implantation dose of the fourth ion implantation treatment is less than the ion implantation dose of the second ion implantation treatment.

20. The method for forming a diode device according to claim 18, It is characterized in that The doping type of the first ion implantation process is N-type ions, the ion implantation energy of the first ion implantation process is 50 KeV, and the ion implantation dose of the first ion implantation process is 1.0×10 12 atom / cm 2 Up to 9×10 12 atom / cm 2 The doping type of the second ion implantation process is P-type ions, the ion implantation energy of the second ion implantation process is 5KeV to 100KeV, and the ion implantation dose of the second ion implantation process is 2.0×10 13 atom / cm 2 Up to 8×10 15 atom / cm 2 The doping type of the third ion implantation process is N-type ions, the ion implantation energy of the third ion implantation process is 5KeV to 100KeV, and the ion implantation dose of the third ion implantation process is 1.0×10 13 atom / cm 2 Up to 9×10 15 atom / cm 2 ; The doping type of the fourth ion implantation treatment is P-type ions, the ion implantation energy of the fourth ion implantation treatment is less than the ion implantation energy of the second ion implantation treatment, and the ion implantation dose of the fourth ion implantation treatment is less than the ion implantation dose of the second ion implantation treatment.

21. The method for forming a diode device according to claim 14, It is characterized in that The substrate comprises a first semiconductor layer, an insulating layer located on the surface of the first semiconductor layer and a second semiconductor layer located on the insulating layer; the bottom of the well region is in contact with the top surface of the insulating layer.

22. The method for forming a diode device according to claim 21, It is characterized in that The second semiconductor layer has one or more layers, and the material of the second semiconductor layer includes: single crystal silicon, silicon germanium or germanium.

23. The method for forming a diode device according to claim 22, It is characterized in that Also includes: After forming the well region, etching the two sides of the well region until the insulating layer is exposed to form a shallow trench; depositing an initial isolation structure in the shallow trench; The initial isolation structure is planarized to form an isolation structure.

24. The method for forming a diode device according to claim 14, It is characterized in that The method for forming the gate structure comprises: after forming the well region, depositing the gate structure on the top surface of the well region, wherein the gate structure exposes a portion of the top surface of the well region.

25. The method for forming a diode device according to claim 24, It is characterized in that Also includes: After forming the gate structure, a contact layer is deposited on top surfaces of the first doping region, the second doping region and the transition doping region.

26. The method for forming a diode device according to claim 25, It is characterized in that Also includes: After the contact layer is formed, a conductive structure is formed on the surface of the contact layer at the top of the first doping region and the second doping region, and the conductive structure is electrically connected to the first doping region and the second doping region.

27. The method for forming a diode device according to claim 14, It is characterized in that The first doping region and the second doping region have the same depth in a direction perpendicular to the substrate, and the transition doping region has a smaller depth than the first doping region in a direction perpendicular to the substrate.

28. The method for forming a diode device according to claim 27, It is characterized in that The depths of the first doping region, the second doping region and the transition doping region in a direction perpendicular to the substrate range from 30 nanometers to 200 nanometers.

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