Semiconductor device

Abstract

A semiconductor device includes: a first lower pattern extending in a first direction and including first and second sidewalls opposing in a second direction and upper and lower surfaces opposing in a third direction; a channel separation structure extending in the first direction and contacting a first sidewall of the first lower pattern; a field insulating film contacting a second sidewall of the first lower pattern; a first channel pattern on an upper surface of the first lower pattern and including first sheet patterns spaced apart from each other in a third direction and contacting the channel separation structure; a first source / drain pattern contacting the first channel pattern and the channel separation structure; a contact blocking pattern on the first source / drain pattern and formed of an insulating material and having an upper surface on the same plane as an upper surface of the channel separation structure; a first backside source / drain contact within the first lower pattern and connected to the first source / drain pattern; and a backside wiring on a lower surface of the first lower pattern and connected to the first backside source / drain contact.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] As a scaling technology for increasing the density of integrated circuit devices, a concept of a multi-gate transistor has been proposed in which a silicon body in the form of a fin or a nanowire is formed on a substrate and a gate is formed on a surface of the silicon body.

[0003] The multi-gate transistor takes advantage of its three-dimensional (3D) channel, allowing for easy up- and down-scaling. In addition, the multi-gate transistor provides improved control over current without the need to increase the gate length. In addition, the multi-gate transistor effectively mitigates the short channel effect (SCE), which is a phenomenon in which the potential of the channel region is affected by the drain voltage.

[0004] Meanwhile, as the pitch size of semiconductor devices decreases, there is a need to study methods of reducing capacitance between contacts and ensuring electrical stability. Summary of the invention

[0005] Provided is a semiconductor device capable of improving device performance and integration density.

[0006] According to one aspect of the disclosure, a semiconductor device includes: a first lower pattern extending in a first direction and including a first sidewall, a second sidewall, an upper surface, and a lower surface, wherein the first sidewall and the second sidewall are opposite to each other in the second direction, and wherein the upper surface and the lower surface are opposite to each other in a third direction; a channel separation structure extending in the first direction and contacting the first sidewall of the first lower pattern; a field insulating film contacting the second sidewall of the first lower pattern; a first channel pattern, on an upper surface of the first lower pattern, the first channel pattern including a plurality of first sheet patterns spaced apart from each other in the third direction, wherein the plurality of first sheet patterns are in contact with the channel separation structure; a first source / drain pattern, in contact with the first channel pattern and the channel separation structure; a contact barrier pattern, on the first source / drain pattern, wherein the contact barrier pattern is formed of an insulating material, and wherein the contact barrier pattern includes an upper surface that is in the same plane as the upper surface of the channel separation structure; a first back side source / drain contact, within the first lower pattern and connected to the first source / drain pattern; and a back side wiring, on the lower surface of the first lower pattern, wherein the back side wiring is connected to the first back side source / drain contact.

[0007] According to one aspect of the disclosure, a semiconductor device includes: a first trench separation structure extending in a first direction; a second trench separation structure spaced apart from the first trench separation structure in the second direction and extending in the first direction; a first lower pattern between the first trench separation structure and the second trench separation structure, contacting the first trench separation structure and including a first upper surface and a first lower surface, wherein the first upper surface and the first lower surface are opposite to each other; a second lower pattern between the first trench separation structure and the second trench separation structure, wherein the second lower pattern is in contact with the second trench separation structure, extending in the first direction and including a second upper surface and a second lower surface, wherein the first upper surface and the second lower surface are opposite to each other; a field insulating film between the first lower pattern and the second lower pattern; a first channel pattern, on the first upper surface, the first channel pattern includes a plurality of first sheet patterns spaced apart from each other in a third direction, wherein the plurality of first sheet patterns are in contact with the first trench separation structure; and a second channel pattern, on the second upper surface, the second channel pattern includes a plurality of second sheet patterns spaced apart from each other in the third direction. , wherein the plurality of second sheet patterns are in contact with the second channel separation structure; the first source / drain pattern is in contact with the first channel pattern and the first channel separation structure; the second source / drain pattern is in contact with the second channel pattern and the second channel separation structure; the source / drain separation structure is between the first source / drain pattern and the second source / drain pattern, the source / drain separation structure includes an upper surface that is in the same plane as the upper surface of the first channel separation structure; a contact barrier pattern is on the first source / drain pattern, wherein the contact barrier pattern is formed of an insulating material The present invention relates to a first channel separation structure and a second channel separation structure, wherein the contact barrier pattern includes an upper surface that is in the same plane as the upper surface of the first channel separation structure; a source / drain contact on and connected to the second source / drain pattern, wherein the source / drain contact includes an upper surface that is in the same plane as the upper surface of the second channel separation structure; a back source / drain contact within the first lower pattern and connected to the first source / drain pattern; and a back wiring on the first lower surface and the second lower surface, wherein the back wiring is connected to the back source / drain contact.

[0008] According to one aspect of the disclosure, a semiconductor device includes: a lower pattern extending in a first direction and including an upper surface and a lower surface, wherein the upper surface and the lower surface are opposite to each other in a second direction; a channel separation structure extending in the first direction and contacting the lower pattern; a channel pattern on an upper surface of the lower pattern, the channel pattern including a plurality of sheet patterns spaced apart from each other in the second direction, wherein the plurality of sheet patterns are in contact with the channel separation structure; a first source / drain pattern on the lower pattern and in contact with the channel pattern; a second source / drain pattern on the lower pattern, wherein the second source / drain pattern is in contact with the channel pattern and the channel separation structure and is spaced apart from the first source / drain pattern in the first direction; and a gate structure between the first source / drain pattern and the second source / drain pattern, wherein the gate structure a structure on the lower pattern and in contact with the channel separation structure; a contact barrier pattern on the first source / drain pattern, wherein the contact barrier pattern is formed of an insulating material, and wherein the contact barrier pattern includes an upper surface that is in the same plane as the upper surface of the channel separation structure; a source / drain contact on the second source / drain pattern and connected to the second source / drain pattern, the source / drain contact including an upper surface that is in the same plane as the upper surface of the contact barrier pattern; a back side source / drain contact in the lower pattern and connected to the first source / drain pattern; and a back side wiring on the lower surface of the lower pattern, wherein the back side wiring is connected to the back side source / drain contact.

[0009] It should be noted that the effects of the present disclosure are not limited to the above-mentioned effects, and other effects of the present disclosure will be clear from the following description.

[0010] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects and features of the present disclosure will become more apparent by describing in detail example embodiments of the present disclosure with reference to the attached drawings.

[0012] Figure 1 is a layout diagram of a semiconductor device according to one or more embodiments of the present disclosure.

[0013] Figure 2 , Figure 3 , Figure 4 and Figure 5 Along the Figure 1 Cross-sectional views taken along lines AA, BB, CC and DD.

[0014] Figure 6is a diagram illustrating a specific surface corresponding to a specific flake pattern according to one or more embodiments of the present disclosure.

[0015] Figure 7 It is shown Figure 1 A plan view of an example of a portion P.

[0016] Figure 8 It is shown Figure 4 An enlarged cross-sectional view of an example of portion Q.

[0017] Fig. 9 It is shown Figure 5 An enlarged cross-sectional view of an example of portion S.

[0018] Fig.10 It is shown Figure 1 A plan view of another example of portion P.

[0019] Fig.11 and Fig.12 It is shown Figure 5 An enlarged cross-sectional view of an example of portion S.

[0020] Fig.13 is a diagram illustrating a semiconductor device according to one or more embodiments of the present disclosure.

[0021] Fig.14 and Fig.15 is a diagram illustrating a semiconductor device according to one or more embodiments of the present disclosure.

[0022] Fig.16 and Fig.17 is a diagram illustrating a semiconductor device according to one or more embodiments.

[0023] Fig.18 and Fig.19 is a diagram illustrating a semiconductor device according to one or more embodiments of the present disclosure.

[0024] Fig. 20 is a diagram illustrating a semiconductor device according to one or more embodiments of the present disclosure.

[0025] Fig.21 and Fig. 22 is a diagram illustrating a semiconductor device according to one or more embodiments of the present disclosure.

[0026] Fig.23 and Fig.24 is a diagram illustrating a semiconductor device according to one or more embodiments of the present disclosure.

[0027] Figures 25 to 42 is a diagram illustrating an intermediate step of a method of manufacturing a semiconductor device according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0028] It should be understood that the terms "first", "second", "third", etc. used to describe various elements, component domains, layers and / or parts herein are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part, and are not used for limitation. Therefore, without departing from the essence and scope of the present disclosure, the first element, first component, first region, first layer or first part described below may also be referred to as the second element, second component, second region, second layer or second part.

[0029] In the following description, the same reference numerals refer to the same elements throughout the specification. As used herein, multiple "units", "modules", "components" and "blocks" can be implemented as a single component, or a single "unit", "module", "component" and "block" can include multiple components.

[0030] It will be understood that when an element is referred to as being “connected to” or “connected to” another element, the element may be directly or indirectly connected to the other element.

[0031] Furthermore, when a component “includes” or “comprises” an element, unless there is a specific description contrary thereto, the component may further include other elements, rather than excluding other elements.

[0032] Throughout the specification, when a member is “on” another member, this includes not only a case where the member is in contact with the other member but also a case where another member exists between the two members.

[0033] Here, the expressions "at least one of a, b or c" and "at least one of a, b and c" mean "only a", "only b", "only c", "both a and b", "both a and c", "both b and c" and "all of a, b and c".

[0034] As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0035] With respect to any method or process described herein, identification codes may be used to facilitate description, but are not intended to indicate the order of each step or operation. Unless the context clearly indicates otherwise, each step or operation may be performed in an order different from the order shown. Unless the disclosed context clearly indicates otherwise, one or more steps or operations may be omitted.

[0036] Transistors including nanowires or nanosheets are described as examples of semiconductor devices according to one or more embodiments of the present disclosure, but the present disclosure is not limited thereto. The technical principles described herein are also applicable to field effect transistors (FETs) based on two-dimensional (2D) materials and their heterostructures.

[0037] In addition, the semiconductor device according to one or more embodiments of the present disclosure may include a fin FET (FinFET) tunnel FET and a three-dimensional (3D) transistor including a channel region characterized by a fin-shaped pattern. In addition, the semiconductor device according to one or more embodiments of the present disclosure may include other types of transistors (such as a bipolar junction transistor, a lateral double diffused metal oxide semiconductor (LDMOS) transistor, etc.).

[0038] In the following we will refer to Figures 1 to 9 A semiconductor device according to one or more embodiments of the present disclosure is described.

[0039] Figure 1 is a layout diagram of a semiconductor device according to one or more embodiments of the present disclosure. Figure 2 , Figure 3 , Figure 4 and Figure 5 Along the Figure 1 Cross-sectional views taken along lines AA, BB, CC and DD. Figure 6 is a diagram illustrating a specific surface corresponding to a specific flake pattern according to one or more embodiments of the present disclosure. Figure 7 It is shown Figure 1 A plan view of an example of a portion P. Figure 8 It is shown Figure 4 An enlarged cross-sectional view of an example of portion Q. Fig. 9 It is shown Figure 5 An enlarged cross-sectional view of an example of portion S.

[0040] Specifically, Figure 7 is a plan view taken between the source / drain contacts ( 180 and 280 ) and the uppermost sheet patterns ( NS1 and NS2 ).

[0041] Reference Figures 1 to 9According to one or more embodiments of the present disclosure, the semiconductor device may include a first lower pattern BP1, a second lower pattern BP2, a third lower pattern BP3, a fourth lower pattern BP4, a first channel pattern CH1, a second channel pattern CH2, a third channel pattern CH3, a fourth channel pattern CH4, a first channel separation structure CCW1, a second channel separation structure CCW2, a first gate electrode 120, a second gate electrode 220, a third gate electrode 320, a fourth gate electrode 420, a first source / drain pattern 150, a second source / drain pattern 250, a third source / drain pattern 350, a fourth source / drain pattern 450, a contact barrier pattern 285, a gate separation structure GCS, a first back side source / drain contact 175, a third back side source / drain contact 375, a first back side wiring 290, and a second back side wiring 295.

[0042] The substrate 100 may have a first surface 100US and a second surface 100BS opposite to each other in the third direction D3. The first gate electrode 120, the second gate electrode 220, the third gate electrode 320, the fourth gate electrode 420, the first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, the fourth source / drain pattern 450, the first channel pattern CH1, the second channel pattern CH2, the third channel pattern CH3, and the fourth channel pattern CH4 may be disposed on the first surface 100US of the substrate 100, and the first surface 100US of the substrate 100 may be an upper surface of the substrate 100. The second surface 100BS of the substrate 100 opposite to the first surface 100US of the substrate 100 may be a lower surface of the substrate 100.

[0043] The substrate 100 may include an insulating material and may contain at least one of silicon oxide, silicon nitride, and a combination thereof. Figures 25 to 38 As shown in FIG. 1 , the substrate 100 may be formed through a deposition process after removing the support substrate 200 .

[0044] The first lower pattern BP1 and the second lower pattern BP2 may protrude from the substrate 100 in the third direction D3. The first lower pattern BP1 and the second lower pattern BP2 may protrude from the first surface 100US of the substrate. The first lower pattern BP1 and the second lower pattern BP2 may extend longitudinally in the first direction D1. The first lower pattern BP1 and the second lower pattern BP2 may be spaced apart from each other in the second direction D2.

[0045] Similarly, the third lower pattern BP3 and the fourth lower pattern BP4 may protrude from the substrate 100 in the third direction D3. The third lower pattern BP3 and the fourth lower pattern BP4 may protrude from the first surface 100US of the substrate 100. The third lower pattern BP3 and the fourth lower pattern BP4 may extend longitudinally in the first direction D1. The third lower pattern BP3 and the fourth lower pattern BP4 may be spaced apart from each other in the second direction D2.

[0046] For example, the third direction D3 may correspond to the thickness of the substrate 100. The first direction D1 and the second direction D2 intersect the third direction D3. The first direction D1 intersects the second direction D2.

[0047] The first and third lower patterns BP1 and BP3 may be disposed between the second and fourth lower patterns BP2 and BP4. The first lower pattern BP1 may be disposed between the second and third lower patterns BP2 and BP3. The first and third lower patterns BP1 and BP3 may be separated by a fin trench FT extending in the first direction D1.

[0048] The first lower pattern BP1 will be described in more detail below as an example. The first lower pattern BP1 may include a first side wall BP1_SW1 and a second side wall BP1_SW2 opposite to each other in the second direction D2. The first side wall BP1_SW1 and the second side wall BP1_SW2 of the first lower pattern BP1 may extend in the first direction D1. The second side wall BP1_SW2 of the first lower pattern BP1 may be defined by the fin trench FT. The first side wall BP1_SW1 of the first lower pattern BP1 may not be defined by the fin trench FT.

[0049] Similarly, each of the second lower pattern BP2, the third lower pattern BP3, and the fourth lower pattern BP4 may include a first sidewall and a second sidewall opposite to each other in the second direction D2. For example, the second sidewall BP1_SW2 of the first lower pattern BP1 and the second sidewall of the third lower pattern BP3 may be defined by the fin trench FT so that the second sidewall BP1_SW2 of the first lower pattern BP1 may face the second sidewall of the third lower pattern BP3.

[0050] The first lower pattern BP1 may include an upper surface BP1_US and a lower surface BP1_BS opposite to each other in the third direction D3. The second lower pattern BP2 may include an upper surface BP2_US and a lower surface opposite to each other in the third direction D3. The third lower pattern BP3 may include an upper surface BP3_US and a lower surface BP3_BS opposite to each other in the third direction. The fourth lower pattern BP4 may include an upper surface BP4_US and a lower surface BP4_BS opposite to each other in the third direction. The lower surface BP1_BS of the first lower pattern BP1, the lower surface of the second lower pattern BP2, the lower surface BP3_BS of the third lower pattern BP3, and the lower surface of the fourth lower pattern BP4 may face the first surface 100US of the substrate 100. The substrate 100 may be disposed on the lower surface BP1_BS of the first lower pattern BP1, the lower surface of the second lower pattern BP2, the lower surface BP3_BS of the third lower pattern BP3, and the lower surface of the fourth lower pattern BP4.

[0051] For example, the first lower pattern BP1, the second lower pattern BP2, the third lower pattern BP3, and the fourth lower pattern BP4 may contact the substrate 100. The inserted insulating cover layer may be disposed on the first surface 100US of the substrate 100. The inserted insulating cover layer may be disposed between the substrate 100 and the first lower pattern BP1 and between the substrate 100 and the second lower pattern BP2. The inserted insulating cover layer may be disposed between the substrate 100 and the third lower pattern BP3 and between the substrate 100 and the fourth lower pattern BP4. The inserted insulating cover layer may include an insulating material different from the substrate 100.

[0052] The first lower pattern BP1 and the second lower pattern BP2 may be disposed in a region where transistors of the same conductivity type are formed. The third lower pattern BP3 and the fourth lower pattern BP4 may also be disposed in a region where transistors of the same conductivity type are formed. For example, the first lower pattern BP1 may be disposed in a P-type metal oxide semiconductor (PMOS) formation region, and the third lower pattern BP3 may be disposed in an N-type metal oxide semiconductor (NMOS) formation region. Alternatively, the first lower pattern BP1 and the third lower pattern BP3 may be disposed in a PMOS formation region. Alternatively, the first lower pattern BP1 and the third lower pattern BP3 may be disposed in an NMOS formation region.

[0053] Each of the first lower pattern BP1, the second lower pattern BP2, the third lower pattern BP3, and the fourth lower pattern BP4 may be formed by partially etching the support substrate 200, or may include an epitaxial layer grown from the support substrate 200. The first lower pattern BP1, the second lower pattern BP2, the third lower pattern BP3, and the fourth lower pattern BP4 may include an elemental semiconductor material such as silicon (Si) or germanium (Ge). The first lower pattern BP1, the second lower pattern BP2, the third lower pattern BP3, and the fourth lower pattern BP4 may also include a compound semiconductor such as a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0054] The Group IV-IV compound semiconductor may be a binary or ternary compound including at least two of carbon (C), Si, Ge, and tin (Sn), or may be a compound formed by doping the binary or ternary compound with a Group IV element.

[0055] Group III-V compound semiconductors may be binary, ternary, or quaternary compounds formed by combining at least one Group III element such as aluminum Al, gallium (Ga), and indium (In) with a Group V element such as phosphorus (P), arsenic (As), or antimony (Sb).

[0056] The first lower pattern BP1 and the second lower pattern BP2 may include the same material. The third lower pattern BP3 and the fourth lower pattern BP4 may include the same material.

[0057] The field insulating film 105 may be disposed on the substrate 100. For example, the field insulating film 105 may be disposed on the first surface 100US of the substrate 100. The field insulating film 105 may at least partially fill the fin trench FT separating the first lower pattern BP1 and the third lower pattern BP3.

[0058] From a cross-sectional perspective, the first and second lower patterns BP1 and BP2 may be disposed between portions of the field insulating film 105 adjacent to each other in the second direction D2, and the third and fourth lower patterns BP3 and BP4 may be disposed between portions of the field insulating film 105 adjacent to each other in the second direction D2.

[0059] The field insulating film 105 is not disposed on the upper surface BP1_US of the first lower pattern BP1 , the upper surface BP2_US of the second lower pattern BP2 , the upper surface BP3_US of the third lower pattern BP3 , and the upper surface BP4_US of the fourth lower pattern BP4 .

[0060] The field insulating film 105 may contact the second side wall BP1_SW2 of the first lower pattern BP1 and the second side wall of the third lower pattern BP3. For example, the field insulating film 105 may completely cover the second side wall BP1_SW2 of the first lower pattern BP1 and the second side wall of the third lower pattern BP3. Alternatively, the field insulating film 105 may only cover a portion of the second side wall BP1_SW2 of the first lower pattern BP1 and / or a portion of the second side wall of the third lower pattern BP3.

[0061] The field insulating film 105 may include an upper surface 105US and a lower surface 105BS opposite to each other in the third direction D3 . The lower surface 105BS of the field insulating film 105 may face the substrate 100 .

[0062] For example, the lower surface 105BS of the field insulating film 105 may contact the substrate 100. Alternatively, in the case where an interposed insulating cover layer is disposed between the substrate 100 and the first, second, third, and fourth lower patterns BP1, BP2, BP3, and BP4, the lower surface 105BS of the field insulating film may contact the interposed insulating cover layer.

[0063] The upper surface 105US of the field insulating film 105 is shown to be flat, but the present disclosure is not limited thereto. The field insulating film 105 may include, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof. The field insulating film 105 is shown as a single-layer film, but the present disclosure is not limited thereto.

[0064] A plurality of first channel patterns CH1 may be disposed on the first lower pattern BP1. The first channel pattern CH1 may overlap the first lower pattern BP1 in the third direction D3. The first channel patterns CH1 may be aligned in the first direction D1.

[0065] A plurality of second channel patterns CH2 may be disposed on the second lower pattern BP2. The second channel pattern CH2 may overlap the second lower pattern BP2 in the third direction D3. The second channel pattern CH2 may be aligned in the first direction D1. The second channel pattern CH2 may be disposed to correspond to the first channel pattern CH1. The first channel pattern CH1 and its corresponding second channel pattern CH2 may be spaced apart from each other in the second direction D2.

[0066] A plurality of third channel patterns CH3 may be disposed on the third lower pattern BP3. The third channel pattern CH3 may overlap the third lower pattern BP3 in the third direction D3. The third channel patterns CH3 may be aligned in the first direction D1.

[0067] A plurality of fourth channel patterns CH4 may be disposed on the fourth lower pattern BP4. The fourth channel pattern CH4 may overlap the fourth lower pattern BP4 in the third direction D3. The fourth channel pattern CH4 may be aligned in the first direction D1. The fourth channel pattern CH4 may be disposed to correspond to the third channel pattern CH3. The fourth channel pattern CH4 and its corresponding third channel pattern CH3 may be spaced apart from each other in the second direction D2.

[0068] The first to fourth channel patterns CH1, CH2, CH3, and CH4 may each include a plurality of sheet patterns spaced apart from each other in the third direction D3. The first to fourth channel patterns CH1, CH2, CH3, and CH4 are each illustrated as including three sheet patterns, but the present disclosure is not limited thereto.

[0069] Each of the first channel patterns CH1 may include a plurality of first sheet patterns NS1. The first sheet pattern NS1 may be disposed on an upper surface BP1_US of the first lower pattern BP1. The first sheet pattern NS1 may be arranged on the first lower pattern BP1 in the third direction D3. The first sheet patterns NS1 may be spaced apart from each other in the third direction D3. Each of the first sheet patterns NS1 may have an upper surface NS1_US and a lower surface NS1_BS that are opposite to each other in the third direction D3. For example, the upper surface NS1_US of the uppermost first sheet pattern NS1 may correspond to the upper surface of the array of the first channel patterns CH1.

[0070] Each of the third sheet patterns CH3 may include a plurality of third sheet patterns NS3. The third sheet patterns NS3 may be disposed on the upper surface BP3_US of the third lower pattern BP3. The third sheet patterns NS3 may be arranged on the third lower pattern BP3 in the third direction D3. The third sheet patterns NS3 may be spaced apart from each other in the third direction D3. Each of the third sheet patterns NS3 may have an upper surface NS3_US and a lower surface NS3_BS opposite to each other in the third direction D3.

[0071] Each of the second channel patterns CH2 may include a plurality of second sheet patterns NS2. The second sheet patterns NS2 may be disposed on the upper surface BP2_US of the second lower pattern BP2. The second sheet patterns NS2 may be spaced apart from each other in the third direction D3. Each of the fourth channel patterns CH4 may include a plurality of fourth sheet patterns NS4. The fourth sheet pattern NS4 may be disposed on the upper surface BP4_US of the fourth lower pattern BP4. The fourth sheet patterns NS4 may be spaced apart from each other in the third direction D3.

[0072] The first sheet pattern NS1 will be described in more detail below as an example. Figure 6 As shown in , each of the first sheet patterns NS1 may have first side walls NS1_SW1 opposite to each other in the first direction D1 and second side walls NS1_SW2 opposite to each other in the second direction D2. An upper surface NS1_US and a lower surface NS1_BS of each of the first sheet patterns NS1 may be connected by the first side wall NS1_SW1 and the second side wall NS1_SW2 of the corresponding first sheet pattern NS1. The first side wall NS1_SW1 of each of the first sheet patterns NS1 may be connected to and in contact with the first source / drain pattern 150. The above description of the first sheet pattern NS1 may be directly applicable to the second sheet pattern NS2, the third sheet pattern NS3, and the fourth sheet pattern NS4.

[0073] The first sheet pattern NS1, the second sheet pattern NS2, the third sheet pattern NS3, and the fourth sheet pattern NS4 may include one of an elemental semiconductor material (e.g., Si or Ge), a group IV-IV compound semiconductor, and a group III-V compound semiconductor. The first sheet pattern NS1 and the second sheet pattern NS2 may include the same material as the first lower pattern BP1 or a material different from the first lower pattern BP1. The third sheet pattern NS3 and the fourth sheet pattern NS4 may include the same material as the third lower pattern BP3 or a material different from the third lower pattern BP3.

[0074] The first sheet pattern NS1, the second sheet pattern NS2, the third sheet pattern NS3, and the fourth sheet pattern NS4 may be Si lower patterns including Si. The first sheet pattern NS1, the second sheet pattern NS2, the third sheet pattern NS3, and the fourth sheet pattern NS4 may be Si sheet patterns including Si.

[0075] The first channel separation structure CCW1 may be disposed on the first surface 100US of the substrate 100. The first channel separation structure CCW1 may be disposed between the first lower pattern BP1 and the second lower pattern BP2. The first channel separation structure CCW1 may extend in the first direction D1.

[0076] The first channel separation structure CCW1 may separate the first lower pattern BP1 and the second lower pattern BP2. The first channel separation structure CCW1 may separate the first channel pattern CH1 and the second channel pattern CH2. The first lower pattern BP1 and the second lower pattern BP2 may cover a portion of a sidewall of the first channel separation structure CCW1. The sidewall of the first channel separation structure CCW1 may extend in the first direction D1.

[0077] The first channel separation structure CCW1 may contact the first and second lower patterns BP1 and BP2. The first channel separation structure CCW1 may contact the first sidewall BP1_SW1 of the first and second lower patterns BP1 and BP2. The first sidewall BP1_SW1 of the first lower pattern BP1 may face the first sidewall of the second lower pattern BP2.

[0078] The first channel pattern CH1 and the second channel pattern CH2 may be in contact with the first channel separation structure CCW1. The first sheet pattern NS1 and the second sheet pattern NS2 may be in contact with the first channel separation structure CCW1. The first sheet pattern NS1 and the second sheet pattern NS2 may protrude from the sidewall of the first channel separation structure CCW1 in the second direction D2. For example, one of the second sidewalls NS1_SW2 of each of the first sheet patterns NS1 may be in contact with the first channel separation structure CCW1, and one of the second sidewalls of each of the second sheet patterns NS2 may be in contact with the first channel separation structure CCW1.

[0079] The second channel separation structure CCW2 may be disposed on the first surface 100US of the substrate 100. The second channel separation structure CCW2 may be disposed between the third lower pattern BP3 and the fourth lower pattern BP4. The second channel separation structure CCW2 may extend in the first direction D1. The second channel separation structure CCW2 may be spaced apart from the first channel separation structure CCW1 in the second direction D2.

[0080] The second channel separation structure CCW2 may separate the third lower pattern BP3 and the fourth lower pattern BP4. The second channel separation structure CCW2 may separate the third channel pattern CH3 and the fourth channel pattern CH4. The third lower pattern BP3 and the fourth lower pattern BP4 may cover a portion of a sidewall of the second channel separation structure CCW2. The sidewall of the second channel separation structure CCW2 may extend in the first direction D1.

[0081] The second channel separation structure CCW2 may contact the third and fourth lower patterns BP3 and BP4. The second channel separation structure CCW2 may contact the first sidewalls of the third and fourth lower patterns BP3 and BP4. The first sidewall of the third lower pattern BP3 may face the first sidewall of the fourth lower pattern BP4.

[0082] The third channel pattern CH3 and the fourth channel pattern CH4 contact the second channel separation structure CCW2. The third sheet pattern NS3 and the fourth sheet pattern NS4 contact the second channel separation structure CCW2. The third sheet pattern NS3 and the fourth sheet pattern NS4 may protrude from the sidewall of the second channel separation structure CCW2 in the second direction D2. One of the second sidewalls of each of the third sheet patterns NS3 contacts the second channel separation structure CCW2. One of the second sidewalls of each of the fourth sheet patterns NS4 contacts the second channel separation structure CCW2.

[0083] The first trench separation structure CCW1 and the second trench separation structure CCW2 may include an insulating material. The first trench separation structure CCW1 and the second trench separation structure CCW2 may include silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), aluminum oxide (AlO) and at least one of a combination thereof, but the present disclosure is not limited thereto. Although the first channel separation structure CCW1 and the second channel separation structure CCW2 are shown as a single-layer film, the present disclosure is not limited thereto. Since the first channel separation structure CCW1 and the second channel separation structure CCW2 are formed simultaneously, the first channel separation structure CCW1 and the second channel separation structure CCW2 may include the same material.

[0084] The description of the second trench separation structure CCW2 may be substantially the same as that of the first trench separation structure CCW1 , and thus, the description of the first trench separation structure CCW1 may be directly applicable to the second trench separation structure CCW2 . The shape of the first trench separation structure CCW1 will be described later.

[0085] A depth H11 from the upper surface BP1_US of the first lower pattern BP1 to the lowermost portion of the first channel separation structure CCW1 may be smaller than a depth H12 from the upper surface BP1_US of the first lower pattern BP1 to the lower surface 105BS of the field insulating film 105 .

[0086] The gate separation structure GCS may be disposed on the first surface 100US of the substrate 100 . The gate separation structure GCS may extend in the first direction D1 . The gate separation structure GCS may be disposed on the field insulating film 105 . A portion of the gate separation structure GCS may be disposed within the upper interlayer insulating film 190 .

[0087] The gate separation structure GCS may contact the field insulation film 105. The gate separation structure GCS may protrude in the third direction D3 beyond the upper surface 105US of the field insulation film 105. For example, a portion of the gate separation structure GCS may be embedded in the field insulation film 105.

[0088] The gate separation structure GCS may be disposed between the first and second channel separation structures CCW1 and CCW2. The first, second, third, and fourth channel patterns CH1, CH2, CH3, and CH4 may be disposed between the gate separation structure GCS and the first and second channel separation structures CCW1 and CCW2.

[0089] For example, a depth H11 from the upper surface BP1_US of the first lower pattern BP1 to the lowermost portion of the first channel separation structure CCW1 may be greater than a depth H13 from the upper surface BP1_US of the first lower pattern BP1 to the lowermost portion of the gate separation structure GCS, but the present disclosure is not limited thereto.

[0090] The gate separation structure GCS includes an insulating material. For example, the gate separation structure GCS may include SiN, SiON, SiO 2 At least one of SiOCN, SiBN, SiOBN, SiOC, AlO, and combinations thereof. Although the gate separation structure GCS is shown as a single layer, the present disclosure is not limited thereto.

[0091] The first, second, third and fourth gate structures GS1, GS2, GS3 and GS4 may be disposed on the first surface 100US of the substrate 100 and may contact the upper surface 105US of the field insulating film 105.

[0092] The first gate structure GS1 may be disposed between the first channel separation structure CCW1 and the gate separation structure GCS. The first gate structure GS1 may contact the first channel separation structure CCW1 and the gate separation structure GCS. The first gate structures GS1 may be adjacent to each other in the first direction D1.

[0093] The first gate structure GS1 may be disposed on the first lower pattern BP1. For example, the first gate structure GS1 may contact an upper surface BP1_US of the first lower pattern BP1. The first channel pattern CH1 may be disposed between the first gate structure GS1 and the first channel separation structure CCW1. The first sheet pattern NS1 may be disposed between the first gate structure GS1 and the first channel separation structure CCW1. From a cross-sectional perspective, when the first sheet pattern NS1 contacts the first channel separation structure CCW1, the first gate structure GS1 may not surround the first sheet pattern NS1.

[0094] The first gate structure GS1 may include a first gate electrode 120 and a first gate insulating film 130. The first gate electrode 120 may be disposed on the first lower pattern BP1. The first gate insulating film 130 may be disposed between the first gate electrode 120 and the first channel pattern CH1. For example, the first gate insulating film 130 may be disposed between the first gate electrode 120 and the first sheet pattern NS1.

[0095] The first gate insulating film 130 may extend along the upper surface 105US of the field insulating film 105 and the upper surface BP1_US of the first lower pattern BP1. The first gate insulating film 130 may contact the upper surface 105US of the field insulating film 105 and the upper surface BP1_US of the first lower pattern BP1. Figure 4 As shown in , the first gate insulating film 130 may extend along the sidewall of the first channel separation structure CCW1. The first gate electrode 120 may not contact the sidewall of the first channel separation structure CCW1. The first gate insulating film 130 may not extend along the sidewall of the gate separation structure GCS. The first gate electrode 120 may contact the sidewall of the gate separation structure GCS. The first gate insulating film 130 may be disposed along a portion of the periphery of the first sheet pattern NS1.

[0096] The first gate structure GS1 may include a first internal gate structure INT_GS1. The first internal gate structure INT_GS1 may be disposed between the first lower pattern BP1 and the first sheet pattern NS1 and between first sheet patterns NS1 adjacent to each other in the third direction D3. The first internal gate structure INT_GS1 contacts an upper surface BP1_US of the first lower pattern BP1, an upper surface NS1_US of the first sheet pattern NS1, and a lower surface NS1_BS of the first sheet pattern NS1. The first gate insulating film 130 included in the first internal gate structure INT_GS1 may contact a first source / drain pattern 150 to be described later.

[0097] The description of the second gate structure GS2 , the third gate structure GS3 , and the fourth gate structure GS4 may be substantially the same as the description of the first gate structure GS1 , and therefore, only the second gate structure GS2 , the third gate structure GS3 , and the fourth gate structure GS4 will be briefly described below.

[0098] The second gate structure GS2 may be disposed between the first channel separation structure CCW1 and the gate separation structure GCS. The second gate structure GS2 may contact the first channel separation structure CCW1 and the gate separation structure GCS. The first channel separation structure CCW1 may be disposed between the first gate structure GS1 and the second gate structure GS2. The second gate structures GS2 may be adjacent to each other in the first direction D1. The second gate structure GS2 may be spaced apart from the first gate structure GS1 in the second direction D2.

[0099] The second gate structure GS2 may be disposed on the second lower pattern BP2. For example, the second gate structure GS2 may contact an upper surface BP2_US of the second lower pattern BP2. The second channel pattern CH2 may be disposed between the second gate structure GS2 and the first channel separation structure CCW1. The second sheet pattern NS2 may be disposed between the second gate structure GS2 and the first channel separation structure CCW1. The second gate structure GS2 may include a second gate electrode 220 and a second gate insulating film 230. The second gate structure GS2 may include a second internal gate structure, and the second internal gate structure may be disposed between the second lower pattern BP2 and the second sheet pattern NS2 and between second sheet patterns NS2 adjacent to each other in the third direction D3.

[0100] The third gate structure GS3 may be disposed between the second channel separation structure CCW2 and the gate separation structure GCS. The third gate structure GS3 may contact the second channel separation structure CCW2 and the gate separation structure GCS. The third gate structures GS3 may be adjacent to each other in the first direction D1. The third gate structure GS3 may be spaced apart from the first gate structure GS1 in the second direction D2.

[0101] The third gate structure GS3 may be disposed on the third lower pattern BP3. For example, the third gate structure GS3 may contact the upper surface BP3_US of the third lower pattern BP3. The third channel pattern CH3 may be disposed between the third gate structure GS3 and the second channel separation structure CCW2. The third sheet pattern NS3 may be disposed between the third gate structure GS3 and the second channel separation structure CCW2. The third gate structure GS3 may include a third gate electrode 320 and a third gate insulating film 330. The third gate structure GS3 may include a third internal gate structure INT_GS3, and the third internal gate structure INT_GS3 may be disposed between the third lower pattern BP3 and the third sheet pattern NS3 and between the third sheet patterns NS3 adjacent to each other in the third direction D3. The third gate insulating film 330 included in the third internal gate structure INT_GS3 may contact the third source / drain pattern 350 to be described below.

[0102] The fourth gate structure GS4 may be disposed between the second channel separation structure CCW2 and the gate separation structure GCS. The fourth gate structure GS4 may contact the second channel separation structure CCW2 and the gate separation structure GCS. The second channel separation structure CCW2 may be disposed between the third gate structure GS3 and the fourth gate structure GS4. The fourth gate structures GS4 may be adjacent to each other in the first direction D1. The fourth gate structure GS4 may be spaced apart from the third gate structure GS3 in the second direction D2.

[0103] The fourth gate structure GS4 may be disposed on the fourth lower pattern BP4. For example, the fourth gate structure GS4 may contact the upper surface BP4_US of the fourth lower pattern BP4. The fourth channel pattern CH4 may be disposed between the fourth gate structure GS4 and the second channel separation structure CCW2. The fourth sheet pattern NS4 may be disposed between the fourth gate structure GS4 and the second channel separation structure CCW2. The fourth gate structure GS4 may include a fourth gate electrode 420 and a fourth gate insulating film 430. The fourth gate structure GS4 may include a fourth internal gate structure, and the fourth internal gate structure may be disposed between the fourth lower pattern BP4 and the fourth sheet pattern NS4 and between fourth sheet patterns NS4 adjacent to each other in the third direction D3.

[0104] In such Figure 2 and Figure 3 In the cross-sectional view, the upper surface 120US of the first gate electrode 120 and the upper surface 320US of the third gate electrode 320 are shown as concave surfaces, but the present disclosure is not limited thereto. Alternatively, the upper surface 120US of the first gate electrode 120 and the upper surface 320US of the third gate electrode 320 may also be flat.

[0105] In such Figure 4 In the cross-sectional view, the upper surface 120US of the first gate electrode 120 and the upper surface of the second gate electrode 220 may be flat, and the upper surface 320US of the third gate electrode 320 and the upper surface of the fourth gate electrode 420 may be flat.

[0106] The first gate electrode 120, the second gate electrode 220, the third gate electrode 320, and the fourth gate electrode 420 may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride. The first gate electrode 120, the second gate electrode 220, the third gate electrode 320, and the fourth gate electrode 420 may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlCN), titanium aluminum carbide (TiAlC), titanium carbide (TiC), carbonitride (CNT), or the like. At least one of tantalum (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (NiPt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof, but the present disclosure is not limited thereto. Here, the conductive metal oxide and the conductive metal oxynitride may include oxidized forms of the above materials, but the present disclosure is not limited thereto.

[0107] The first gate insulating film 130, the second gate insulating film 230, the third gate insulating film 330 and the fourth gate insulating film 430 may include silicon oxide, silicon nitride oxide, silicon nitride or a high-k material having a dielectric constant greater than that of silicon oxide. The high-k material may include, for example, at least one of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide and lead zinc niobate.

[0108] Although the first gate insulating film 130, the second gate insulating film 230, the third gate insulating film 330 and the fourth gate insulating film 430 are shown as single-layer films, the present disclosure is not limited thereto. Alternatively, the first gate insulating film 130, the second gate insulating film 230, the third gate insulating film 330 and the fourth gate insulating film 430 may include a stack of multiple films. For example, the first gate insulating film 130 may include an interface layer and a high-k insulating film that may be disposed between the first channel pattern CH1 and the first gate electrode 120. For example, the interface film may not be formed along the contour of the upper surface 105US of the field insulating film 105.

[0109] The semiconductor device according to one or more embodiments of the present disclosure may include a negative capacitance (NC) field effect transistor (FET) using a negative capacitor. For example, the first gate insulating film 130, the second gate insulating film 230, the third gate insulating film 330, and the fourth gate insulating film 430 may each include a ferroelectric material film having a ferroelectric property and a paraelectric material film having a paraelectric property.

[0110] The ferroelectric material film may have a negative capacitance, and the paraelectric material film may have a positive capacitance. For example, if two or more capacitors are connected in series and have a positive capacitance, the total capacitance of the two or more capacitors may be lower than the capacitance of each of the two or more capacitors. On the contrary, if at least one of the two or more capacitors has a negative capacitance, the total capacitance of the two or more capacitors may have a positive value and may be greater than the absolute value of the capacitance of each of the two or more capacitors.

[0111] If a ferroelectric material film having negative capacitance and a paraelectric material film having positive capacitance are connected in series, the total capacitance of the ferroelectric material film and the paraelectric material film can be increased. Therefore, a transistor having a ferroelectric material film can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0112] The ferroelectric material film may have ferroelectric properties. The ferroelectric material film may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. For example, hafnium zirconium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr). In another example, hafnium zirconium oxide may be a compound of hafnium (Hf), Zr, and oxygen (O).

[0113] The ferroelectric material film may further include a dopant. For example, the dopant may include at least one of Al, Ti, Nb, lanthanum (La), yttrium (Y), magnesium (Mg), Si, calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), Ge, scandium (Sc), strontium (Sr), and Sn. The type of dopant may vary depending on the material type of the ferroelectric material film.

[0114] If the ferroelectric material film includes hafnium oxide, the dopant of the ferroelectric material film may include at least one of Gd, Si, Zr, Al, and Y, for example.

[0115] If the dopant of the ferroelectric material film is Al, the ferroelectric material film may include about 3 atomic percent ("at %) to about 8 at % Al. Here, the ratio of the dopant in the ferroelectric material film may refer to the ratio of the amount of Al in the ferroelectric material film to the sum of the amounts of Hf and Al.

[0116] If the dopant of the ferroelectric material film is Si, the ferroelectric material film may include about 2 at% to about 10 at% Si. If the dopant of the ferroelectric material film is Y, the ferroelectric material film may include about 2 at% to about 10 at% Y. If the dopant of the ferroelectric material film is Gd, the ferroelectric material film may include about 1 at% to about 7 at% Gd. If the dopant of the ferroelectric material film is Zr, the ferroelectric material film may include about 50 at% to about 80 at% Zr.

[0117] The paraelectric material film may have paraelectric properties. The paraelectric material film may include, for example, at least one of silicon oxide and high-k metal oxide. The high-k metal oxide may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but the present disclosure is not limited thereto.

[0118] The ferroelectric material film and the paraelectric material film may include the same material. The ferroelectric material film may have ferroelectric properties, while the paraelectric material film may not have ferroelectric properties. For example, if the ferroelectric material film and the paraelectric material film include hafnium oxide, the hafnium oxide included in the ferroelectric material film may have a different crystal structure from the hafnium oxide included in the paraelectric material film.

[0119] The ferroelectric material film may be thick enough to exhibit ferroelectric properties. The ferroelectric material film may have a thickness of, for example, about 0.5 nm to about 10 nm, but the present disclosure is not limited thereto. Since the critical thickness capable of exhibiting ferroelectric properties may vary depending on the type of ferroelectric material, and therefore the thickness of the ferroelectric material film may vary depending on the type of ferroelectric material included in the ferroelectric material film.

[0120] For example, the first gate insulating film 130, the second gate insulating film 230, the third gate insulating film 330, and the fourth gate insulating film 430 may each include a ferroelectric material film. In another example, the first gate insulating film 130, the second gate insulating film 230, the third gate insulating film 330, and the fourth gate insulating film 430 may each include a plurality of ferroelectric material films spaced apart from each other. The first gate insulating film 130, the second gate insulating film 230, the third gate insulating film 330, and the fourth gate insulating film 430 may each have a structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0121] The first gate spacer 140 may be disposed on the sidewall of the first gate structure GS1. The second gate spacer 240 may be disposed on the sidewall of the second gate structure GS2. The third gate spacer 340 may be disposed on the sidewall of the third gate structure GS3. The fourth gate spacer may be disposed on the sidewall of the fourth gate structure GS4.

[0122] For example, the first gate spacer 140 may not be disposed between the first lower pattern BP1 and the first sheet pattern NS1 and between the first sheet patterns NS1 adjacent to each other in the third direction D3, and the third gate spacer 340 may not be disposed between the third lower pattern BP3 and the third sheet pattern NS3 and between the third sheet patterns NS3 adjacent to each other in the third direction D3.

[0123] The first gate spacer 140, the second gate spacer 240, and the third gate spacer 340 may include SiN, SiON, SiO 2 , SiOCN, SiBN, SiOBN, SiOC, and combinations thereof. Although the first gate spacer 140 , the second gate spacer 240 , and the third gate spacer 340 are illustrated as a single layer, the present disclosure is not limited thereto.

[0124] The first gate covering pattern 145 may be disposed on the first gate structure GS1 and the second gate structure GS2. The first gate covering pattern 145 may be disposed on the upper surface 120US of the first gate electrode 120 and the upper surface of the second gate electrode 220. The upper surface 145US of the first gate covering pattern 145 may be in the same plane as the upper surface GCS_US of the gate separation structure GCS.

[0125] The second gate capping pattern 345 may be disposed on the third gate structure GS3 and the fourth gate structure GS4. The second gate capping pattern 345 may be disposed on the upper surface 320US of the third gate electrode 320 and the upper surface of the fourth gate electrode 420. The upper surface 345US of the second gate capping pattern 345 may be in the same plane as the upper surface GCS_US of the gate separation structure GCS.

[0126] exist Figure 4 In the cross-sectional view of , the first gate covering pattern 145 may be disposed on the first channel separation structure CCW1. The first gate covering pattern 145 may be disposed on the upper surface CCW1_US of the first channel separation structure CCW1. The second gate covering pattern 345 may be disposed on the second channel separation structure CCW2. The second gate covering pattern 345 may be disposed on the upper surface CCW2_US of the second channel separation structure CCW2. Based on the lower surface 105BS of the field insulating film 105, the upper surface CCW1_US of the first channel separation structure CCW1 may be lower than the upper surface GCS_US of the gate separation structure GCS. Based on the lower surface 105BS of the field insulating film 105, the upper surface CCW2_US of the second channel separation structure CCW2 may be lower than the upper surface GCS_US of the gate separation structure GCS.

[0127] The first gate capping pattern 145 and the second gate capping pattern 345 may include at least one of SiN, SiON, SiCN, SiOCN, and a combination thereof.

[0128] The first source / drain pattern 150 may be disposed on the first lower pattern BP1. The first source / drain pattern 150 may be disposed adjacent to the first gate structure GS1 in the first direction D1. The first source / drain pattern 150 may be disposed between the first channel separation structure CCW1 and the gate separation structure GCS.

[0129] The first source / drain pattern 150 is connected to the first channel pattern CH1. The first source / drain pattern 150 may contact the first channel pattern CH1. The first source / drain pattern 150 may contact the first sheet pattern NS1. For example, the first source / drain pattern 150 may contact the first internal gate structure INT_GS1.

[0130] The first source / drain pattern 150 may include a first lower connection semiconductor pattern 150_1 and a first upper connection semiconductor pattern 150_2. The first lower connection semiconductor pattern 150_1 may be connected to the first backside source / drain contact 175 and may not be connected to the first source / drain contact 180. The first upper connection semiconductor pattern 150_2 may be connected to the first source / drain contact 180 and may not be connected to the first backside source / drain contact 175.

[0131] The second source / drain pattern 250 may be disposed on the second lower pattern BP2. The second source / drain pattern 250 may be disposed adjacent to the second gate structure GS2 in the first direction D1. The second source / drain pattern 250 may be disposed between the first channel separation structure CCW1 and the gate separation structure GCS.

[0132] The second source / drain pattern 250 is connected to the second channel pattern CH2. The second source / drain pattern 250 may contact the second channel pattern CH2. Similar to the first source / drain pattern 150, the second source / drain pattern 250 may include a second upper connection semiconductor pattern connected to the second source / drain contact 280 and a second lower connection semiconductor pattern connected to the second source / drain contact 280. Fig. 22 A second back side source / drain contact 275 is formed.

[0133] The third source / drain pattern 350 may be disposed on the third lower pattern BP3. The third source / drain pattern 350 may be disposed adjacent to the third gate structure GS3 in the first direction D1. The third source / drain pattern 350 may be disposed between the second channel separation structure CCW2 and the gate separation structure GCS.

[0134] The third source / drain pattern 350 is connected to the third channel pattern CH3. The third source / drain pattern 350 may contact the third channel pattern CH3. The third source / drain pattern 350 may contact the third sheet pattern NS3. For example, the third source / drain pattern 350 may contact the third internal gate structure INT_GS3.

[0135] The third source / drain pattern 350 may include a third lower connection semiconductor pattern 350_1 and a third upper connection semiconductor pattern 350_2. The third lower connection semiconductor pattern 350_1 may be connected to the third backside source / drain contact 375 and may not be connected to the third source / drain contact 380. The third upper connection semiconductor pattern 350_2 may be connected to the third source / drain contact 380 and may not be connected to the third backside source / drain contact 375.

[0136] The fourth source / drain pattern 450 may be disposed on the fourth lower pattern BP4. The fourth source / drain pattern 450 may be disposed adjacent to the fourth gate structure GS4 in the first direction D1. The fourth source / drain pattern 450 may be disposed between the second channel separation structure CCW2 and the gate separation structure GCS.

[0137] The fourth source / drain pattern 450 is connected to the fourth channel pattern CH4. The fourth source / drain pattern 450 may contact the fourth channel pattern CH4. Similar to the third source / drain pattern 350, the fourth source / drain pattern 450 may include a fourth upper connection semiconductor pattern connected to the fourth source / drain contact 480 and a fourth lower connection semiconductor pattern connected to the fourth backside source / drain contact.

[0138] The first channel separation structure CCW1 may be disposed between the first source / drain pattern 150 and the second source / drain pattern 250. The first source / drain pattern 150 and the second source / drain pattern 250 may be spaced apart from each other in the second direction D2.

[0139] The first source / drain pattern 150 and the second source / drain pattern 250 may contact the first channel separation structure CCW1. For example, the first source / drain pattern 150 and the second source / drain pattern 250 may contact the sidewall of the first channel separation structure CCW1.

[0140] For example, a portion of the first source / drain pattern 150 may overlap with the first channel separation structure CCW1 in the third direction D3. The first source / drain pattern 150 may include an overlapping portion 150_OVR overlapping with the first channel separation structure CCW1 in the third direction D3. A portion of the first source / drain pattern 150 may be disposed above the first channel separation structure CCW1. A portion of the second source / drain pattern 250 may overlap with the first channel separation structure CCW1 in the third direction D3. A portion of the second source / drain pattern 250 may be disposed above the first channel separation structure CCW1.

[0141] The second channel separation structure CCW2 may be disposed between the third source / drain pattern 350 and the fourth source / drain pattern 450. The third source / drain pattern 350 and the fourth source / drain pattern 450 may be spaced apart from each other in the second direction D2.

[0142] The third source / drain pattern 350 and the fourth source / drain pattern 450 may contact the second channel separation structure CCW2. For example, the third source / drain pattern 350 and the fourth source / drain pattern 450 may contact the sidewall of the second channel separation structure CCW2.

[0143] For example, portions of the third and fourth source / drain patterns 350 and 450 may overlap the second channel separation structure CCW2 in the third direction D3. Portions of the third and fourth source / drain patterns 350 and 450 may be disposed over the second channel separation structure CCW2.

[0144] The first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450 may be disposed on the first surface 100US of the substrate 100. The first source / drain pattern 150 may be included in the source / drain of a transistor using the first sheet pattern NS1 as a channel region. The second source / drain pattern 250 may be included in the source / drain of a transistor using the second sheet pattern NS2 as a channel region. The third source / drain pattern 350 may be included in the source / drain of a transistor using the third sheet pattern NS3 as a channel region. The fourth source / drain pattern 450 may be included in the source / drain of a transistor using the fourth sheet pattern NS4 as a channel region.

[0145] The first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450 may include an epitaxial pattern. The first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450 may be a semiconductor pattern including a semiconductor material.

[0146] The first source / drain pattern 150 and the second source / drain pattern 250 may include a dopant of the same conductivity type. The first source / drain pattern 150 and the second source / drain pattern 250 may include a p-type dopant or an n-type dopant. The third source / drain pattern 350 and the fourth source / drain pattern 450 may include a dopant of the same conductivity type. The third source / drain pattern 350 and the fourth source / drain pattern 450 may include a p-type dopant or an n-type dopant. The p-type dopant may include at least one of boron (B) and Ga, but the present disclosure is not limited thereto. The n-type dopant may include at least one of P, As, Sb, and bismuth (Bi), but the present disclosure is not limited thereto.

[0147] A height H14 from the lower surface 105BS of the field insulating film 105 to the upper surface of the first channel pattern CH1 may be less than a height H16 from the lower surface 105BS of the field insulating film 105 to the uppermost portion of the first source / drain pattern 150. For example, an upper surface 150US of the first source / drain pattern 150 includes the uppermost portion of the first source / drain pattern 150. The uppermost portion of the first source / drain pattern 150 may be a portion of the first source / drain pattern 150 farthest from the lower surface 105BS of the field insulating film 105. The height of the upper surface 150US of the first source / drain pattern 150 may be measured in the first source / drain pattern 150 where the first contact silicide film 155 is not formed.

[0148] The sacrificial semiconductor pattern 160SC may be disposed in the first, second, third, and fourth lower patterns BP1, BP2, BP3, and BP4. The sacrificial semiconductor pattern 160SC may be disposed between the first, second, third, and fourth lower patterns BP1, BP2, BP3, and BP4 and the substrate 100.

[0149] The sacrificial semiconductor pattern 160SC may overlap the first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450 in the third direction D3. The first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450 may be disposed on the sacrificial semiconductor pattern 160SC. The sacrificial semiconductor pattern 160SC may be disposed under the first upper connection semiconductor pattern 150_2, the second upper connection semiconductor pattern, the third upper connection semiconductor pattern 350_2, and the fourth upper connection semiconductor pattern.

[0150] The sacrificial semiconductor pattern 160SC will be described hereinafter by taking the sacrificial semiconductor pattern in the first lower pattern BP1 as an example. The sacrificial semiconductor pattern 160SC may extend to the lower surface BP1_BS of the first lower pattern BP1. If the first lower pattern BP1 contacts the first surface 100US of the substrate 100, the sacrificial semiconductor pattern 160SC may contact the substrate 100. Alternatively, the lowermost portion of the sacrificial semiconductor pattern 160SC may not extend to the lower surface BP1_BS of the first lower pattern based on the first surface 100US of the substrate 100. A portion of the first lower pattern BP1 may be disposed between the substrate 100 and the sacrificial semiconductor pattern 160SC.

[0151] The sacrificial semiconductor pattern 160SC may include a material having an etch selectivity with respect to the first, second, third, and fourth lower patterns BP1, BP2, BP3, and BP4. When the first, second, third, and fourth lower patterns BP1, BP2, BP3, and BP4 are Si patterns, the sacrificial semiconductor pattern 160SC may include silicon germanium (SiGe), but the present disclosure is not limited thereto.

[0152] The sacrificial pattern covering film 160IP may be disposed between the first source / drain pattern 150 and the sacrificial semiconductor pattern 160SC and between the second source / drain pattern 250 and the sacrificial semiconductor pattern 160SC. The sacrificial pattern covering film 160IP may be disposed between the third source / drain pattern 350 and the sacrificial semiconductor pattern 160SC and between the fourth source / drain pattern 450 and the sacrificial semiconductor pattern 160SC.

[0153] The sacrificial pattern covering film 160IP may include a material having an etching selectivity with respect to the first lower pattern BP1, the second lower pattern BP2, the third lower pattern BP3, and the fourth lower pattern BP4. The sacrificial pattern covering film 160IP may have an etching selectivity with respect to the first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450. For example, the sacrificial pattern covering film 160IP may include a semiconductor material. Alternatively, the sacrificial pattern covering film 160IP may include an insulating material.

[0154] The first trench separation structure CCW1 and the second trench separation structure CCW2 will be described hereinafter mainly focusing on the first trench separation structure CCW1. That is, the description of the first trench separation structure CCW1 can be directly applicable to the second trench separation structure CCW2.

[0155] Reference Figure 1 , Figure 4 , Figure 5 and Figures 7 to 9 , the first channel separation structure CCW1 may include a first region CCW1_R1 and a second region CCW1_R2. The first region CCW1_R1 of the first channel separation structure CCW may be a region within the first channel separation structure CCW1 that contacts the first gate structure GS1 and the second gate structure GS2. The first region CCW1_R1 of the first channel separation structure CCW1 may overlap with the first gate structure GS1 and the second gate structure GS2 in the second direction D2. The second region CCW1_R2 of the first channel separation structure CCW1 may be a region within the first channel separation structure CCW1 that contacts the first source / drain pattern 150 and the second source / drain pattern 250. The second region CCW1_R2 of the first channel separation structure CCW1 may overlap with the first source / drain pattern 150 and the second source / drain pattern 250 in the second direction D2.

[0156] For example, Figure 8 is a cross-sectional view showing the shape of the first region CCW1_R1 of the first trench separation structure CCW1, Fig. 9 is a cross-sectional view showing the shape of the second region CCW1_R2 of the first trench separation structure CCW1.

[0157] Reference Figure 4 and Figure 8 , the width of the first trench separation structure CCW1 in the second direction D2 may continuously increase as it moves away from the bottom surface 105BS of the field insulating film 105 .

[0158] Reference Figure 5 and Fig. 9, the second region CCW1_R2 of the first channel separation structure CCW1 may include a first portion CCW1_R21 and a second portion CCW1_R22, wherein the width of the first channel separation structure CCW1 increases as it moves away from the lower surface 105BS of the field insulating film 105. In both the first portion CCW1_R21 and the second portion CCW1_R22, the width of the first channel separation structure CCW1 in the second direction D2 may continue to increase as it moves away from the lower surface 105BS of the field insulating film 105.

[0159] The second portion CCW1_R22 of the second region CCW1_R2 of the first channel separation structure CCW1 may be disposed on the first portion CCW1_R21 of the second region CCW1_R2 of the first channel separation structure CCW1. The second portion CCW1_R22 of the second region CCW1_R2 of the first channel separation structure CCW1 may be directly connected to the first portion CCW1_R21 of the second region CCW1_R2 of the first channel separation structure CCW1.

[0160] There may be a step between the first portion CCW1_R21 and the second portion CCW1_R22 of the second region CCW1_R2 of the first channel separation structure CCW1. In other words, the width W21 of the uppermost portion of the first channel separation structure CCW1 may be greater in the first portion CCW1_R21 of the second region CCW1_R2 than in the second portion CCW1_R22 of the second region CCW1_R2. In other words, the width W21 of the uppermost portion of the first portion CCW1_R21 of the second region CCW1_R2 of the first channel separation structure CCW1 may be greater than the width W22 of the lowermost portion of the second portion CCW1_R22 of the second region CCW1_R2 of the first channel separation structure CCW1.

[0161] The first portion CCW1_R21 of the second region CCW1_R2 of the first trench separation structure CCW1 may include a first width center line WCL1 extending in the third direction D3. The second portion CCW1_R22 of the second region CCW1_R2 of the first trench separation structure CCW1 may include a second width center line WCL2 extending in the third direction D3. The first width center lines WCL1 may be aligned with the second width center lines WCL2 in the third direction D3, respectively. In other words, the extensions of the first width center lines WCL1 may overlap with the second width center lines WCL2, respectively.

[0162] For example, the first width center line WCL1 may be an imaginary line that bisects the width W21 of the corresponding uppermost portion of the first portion CCW1_R21 of the second region CCW1_R2 of the first trench separation structure CCW1. For example, the second width center line WCL2 may be an imaginary line that bisects the width W22 of the lowermost portion CCW1_R22 of the second region CCW1_R2 of the first trench separation structure CCW1.

[0163] A height H15 from the lower surface 105BS of the field insulating film 105 to the uppermost portion of the first portion CCW1_R21 of the second region CCW1_R2 of the first channel separation structure CCW1 may be less than a height H16 from the lower surface 105BS of the field insulating film 105 to the uppermost portion of the first source / drain pattern 150 .

[0164] A portion of the first source / drain pattern 150 may overlap the first portion CCW1_R21 of the second region CCW1_R2 of the first channel separation structure CCW1 in the third direction D3. An overlapping portion 150_OVR of the first source / drain pattern 150 may overlap the first portion CCW1_R21 of the second region CCW1_R2 of the first channel separation structure CCW1 in the third direction D3. An overlapping portion 150_OVR of the first source / drain pattern 150 may be disposed above the first portion CCW1_R21 of the second region CCW1_R2 of the first channel separation structure CCW1.

[0165] Portions of the second source / drain pattern 250 may overlap the first portion CCW1_R21 of the second region CCW1_R2 of the first channel separation structure CCW1 in the third direction D3. Portions of the second source / drain pattern 250 may be disposed above the first portion CCW1_R21 of the second region CCW1_R2 of the first channel separation structure CCW1.

[0166] Although the first portion CCW1_R21 and the second portion CCW1_R22 of the second region CCW1_R2 of the first trench separation structure CCW1 are shown as having no clear boundary therebetween, the present disclosure is not limited thereto. Alternatively, the first portion CCW1_R21 of the second region CCW1_R2 of the first trench separation structure CCW1 may be clearly separated from the second portion CCW1_R22 of the second region CCW1_R2 of the first trench separation structure CCW1 by a boundary.

[0167] Reference Figure 4 and Figure 5A height H15 from the lower surface 105BS of the field insulating film 105 to the uppermost portion of the first portion CCW1_R21 of the second region CCW1_R2 of the first channel separation structure CCW1 may be smaller than a height H14 from the lower surface 105BS of the field insulating film 105 to the upper surface of the first channel pattern CH1.

[0168] In such Figure 5 In the cross-sectional view of FIG. 1 , the upper surface CCW1_US of the first channel separation structure CCW1 may be in the same plane as the upper surface GCS_US of the gate separation structure GCS.

[0169] The upper surface CCW1_US of the first channel separation structure CCW1 may be lower in the first region CCW1_R1 of the first channel separation structure CCW1 than in the second region CCW1_R2. The height from the lower surface 105BS of the field insulating film 105 to the upper surface CCW1_US of the first channel separation structure CCW1 may be smaller in the first region CCW1_R1 than in the second region CCW1_R2.

[0170] For example, Figure 7 It may be a plan view taken at a height level of the second portion CCW1_R22 of the second region CCW1_R2 of the first trench separation structure CCW1.

[0171] Reference Figure 7 , a width W11 of the first channel separation structure CCW1 between the first gate structure GS1 and the second gate structure GS2 in the second direction D2 may be different from a width W12 between the first source / drain pattern 150 and the second source / drain pattern 250 in the second direction D2. For example, a width W11 of the first channel separation structure CCW1 between the first gate structure GS1 and the second gate structure GS2 in the second direction D2 may be greater than a width W12 between the first source / drain pattern 150 and the second source / drain pattern 250 in the second direction D2.

[0172] The first source / drain pattern 150 may overlap the first channel separation structure CCW1 in the second direction D2 by a first overlap width W13. The second source / drain pattern 250 may overlap the first channel separation structure CCW1 in the second direction D2 by a second overlap width W14. For example, the first overlap width W13 may be the same as the second overlap width W14.

[0173] The source / drain etch stop film 185 may extend along outer sidewalls of the first gate spacer 140 and the third gate spacer 340 and along sidewalls of the first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450. The source / drain etch stop film 185 may also extend along the upper surface 105US of the field insulating film 105.

[0174] Portions of the source / drain etch stop film 185 may extend along sidewalls of the first and second channel separation structures CCW1 and CCW2. The source / drain etch stop film 185 on the sidewalls of the first and second channel separation structures CCW1 and CCW2 may be portions of the source / drain etch stop film 185 that remain unremoved after manufacturing the first, second, third, and fourth source / drain contacts 180, 280, 380, and 480.

[0175] The source / drain etch stop film 185 may extend along upper surfaces of the first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450 that are not connected to the first source / drain contact 180, the second source / drain contact 280, the third source / drain contact 380, and the fourth source / drain contact 480. For example, the source / drain etch stop film 185 may extend along an upper surface 150US of the first lower connection semiconductor pattern, an upper surface 350US of the second lower connection semiconductor pattern, and an upper surface of the fourth lower connection semiconductor pattern. The upper surface 150US of the first lower connection semiconductor pattern may be an upper surface 150US of the first source / drain pattern 150, and the upper surface 350US of the third lower connection semiconductor pattern may be an upper surface of the third source / drain pattern 350.

[0176] The source / drain etch stop film 185 may not extend along the sidewalls of the first and second gate capping patterns 145 and 345. Alternatively, the source / drain etch stop film 185 may extend along the sidewalls of the first and second gate capping patterns 145 and 345.

[0177] The source / drain etch stop film 185 may include at least one of SiN, SiON, SiOCN, SiBN, SiOBN, SiOC, and a combination thereof.

[0178] If the source / drain etch stop film 185 includes the same material as the first channel separation structure CCW1, the boundary between the source / drain etch stop film 185 and the first channel separation structure CCW1 may not be distinguished. Similarly, if the source / drain etch stop film 185 includes the same material as the second channel separation structure CCW2, the boundary between the source / drain etch stop film 185 and the second channel separation structure CCW2 may not be distinguished. In this case, the source / drain etch stop film 185 extending in the third direction D3 on the first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450 may appear as a part of the first channel separation structure CCW1 and / or the second channel separation structure CCW2.

[0179] However, the source / drain etch stopper film 185 may not be formed.

[0180] The upper interlayer insulating film 190 may be disposed on the first surface 100US of the substrate 100. The upper interlayer insulating film 190 may be disposed on the source / drain etch stop film 185. The upper interlayer insulating film 190 may be disposed on the first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450.

[0181] The upper interlayer insulating film 190 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material. The low-k material may have a dielectric constant less than 3.9, which is a dielectric constant of silicon oxide.

[0182] The first source / drain contact 180 may be disposed on the first source / drain pattern 150. The first source / drain contact 180 may be disposed on the first upper connection semiconductor pattern 150_2. The first source / drain contact 180 is not disposed on the first lower connection semiconductor pattern 150_1.

[0183] The first source / drain pattern 150 may be disposed between the first source / drain contact 180 and the sacrificial semiconductor pattern 160SC. For example, the first upper connection semiconductor pattern 150_2 may be disposed between the first source / drain contact 180 and the sacrificial semiconductor pattern 160SC.

[0184] The first source / drain contact 180 is electrically connected to the first source / drain pattern 150. The first source / drain contact 180 may be electrically connected to the first upper connection semiconductor pattern 150_2. The first source / drain contact 180 may not be electrically connected to the first lower connection semiconductor pattern 150_1.

[0185] The first source / drain contact 180 may be disposed between the first channel separation structure CCW1 and the gate separation structure GCS. The first source / drain contact 180 may be disposed on the upper interlayer insulating film 190. Although the upper interlayer insulating film 190 is shown as not being disposed between the sidewall of the first source / drain contact 180 and the first channel separation structure CCW1, the present disclosure is not limited thereto. The upper surface 180US of the first source / drain contact 180 may be in the same plane as the upper surface CCW1_US of the first channel separation structure CCW1.

[0186] The second source / drain contact 280 may be disposed on the second source / drain pattern 250. The second source / drain contact 280 is electrically connected to the second source / drain pattern 250. The second source / drain contact 280 may be disposed on the second upper connection semiconductor pattern to be electrically connected thereto.

[0187] The second source / drain contact 280 may be disposed between the first channel separation structure CCW1 and the gate separation structure GCS. The second source / drain contact 280 may be disposed on the upper interlayer insulating film 190. Although the upper interlayer insulating film 190 is shown as not being disposed between the sidewall of the second source / drain contact 280 and the first channel separation structure CCW1, the present disclosure is not limited thereto.

[0188] The third source / drain contact 380 may be disposed on the third source / drain pattern 350. The third source / drain contact 380 may be disposed on the third upper connection semiconductor pattern 350_2. The third source / drain contact 380 is not disposed on the third lower connection semiconductor pattern 350_1. The third source / drain contact 380 may be electrically connected to the third upper connection semiconductor pattern 350_2. An upper surface 380US of the third source / drain contact 380 may be in the same plane as an upper surface CCW2_US of the second channel separation structure CCW2.

[0189] The fourth source / drain contact 480 may be disposed on the fourth source / drain pattern 450. The fourth source / drain contact 480 may be disposed on the fourth upper connection semiconductor pattern. The fourth source / drain contact 480 is not disposed on the fourth lower connection semiconductor pattern. The fourth source / drain contact 480 may be electrically connected to the fourth upper connection semiconductor pattern within the fourth source / drain pattern 450.

[0190] The first source / drain contact 180 , the second source / drain contact 280 , the third source / drain contact 380 , and the fourth source / drain contact 480 may be complete source / drain contacts disposed on the first surface 100US of the substrate 100 .

[0191] The first contact silicide film 155 may be disposed between the first source / drain contact 180 and the first source / drain pattern 150. The second contact silicide film 255 may be disposed between the second source / drain contact 280 and the second source / drain pattern 250. The third contact silicide film 355 may be disposed between the third source / drain contact 380 and the third source / drain pattern 350. The fourth contact silicide film 455 may be disposed between the fourth source / drain contact 480 and the fourth source / drain pattern 450.

[0192] Although the first source / drain contact 180, the second source / drain contact 280, the third source / drain contact 380, and the fourth source / drain contact 480 are shown as having a single-layer conductive film structure, the present disclosure is not limited thereto. Alternatively, the first source / drain contact 180, the second source / drain contact 280, the third source / drain contact 380, and the fourth source / drain contact 480 may have a multi-layer conductive film structure including a barrier film and a plug film. The first source / drain contact 180, the second source / drain contact 280, the third source / drain contact 380, and the fourth source / drain contact 480 may include at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material. The first contact silicide film 155 , the second contact silicide film 255 , the third contact silicide film 355 , and the fourth contact silicide film 455 may include a metal silicide material.

[0193] The 2D material may include a 2D allotrope or a 2D compound. For example, the 2D material may include at least one of graphene, boron nitride (BN), molybdenum sulfide, molybdenum selenide, tungsten sulfide, tungsten selenide, and tantalum sulfide, but the present disclosure is not limited thereto. That is, the 2D material is not specifically limited.

[0194] The contact barrier pattern 285 may be disposed on the first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450 that are not connected to the first source / drain contact 180, the second source / drain contact 280, the third source / drain contact 380, and the fourth source / drain contact 480. The contact barrier pattern 285 may be disposed on the first lower connection semiconductor pattern 150_1 and the third lower connection semiconductor pattern 350_1. The contact barrier pattern 285 may be disposed on the second lower connection semiconductor pattern and the fourth lower connection semiconductor pattern.

[0195] The contact barrier patterns 285 may be disposed on the upper interlayer insulating film 190. Each of the contact barrier patterns 285 may include an upper surface 285US and a lower surface 285BS that are opposite to each other in the third direction D3. The lower surface 285BS of the contact barrier pattern 285 may face the first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450.

[0196] For example, the upper surface 285US of the contact barrier pattern 285 may be in the same plane as the upper surface 145US of the first gate capping pattern 145 and the upper surface 345US of the second gate capping pattern 345. Figure 5 In the cross-sectional view of , the upper surface 285US of the contact barrier pattern 285 may be in the same plane as the upper surface CCW1_US of the first channel separation structure CCW1 and the upper surface CCW2_US of the second channel separation structure CCW2.

[0197] The contact barrier pattern 285 may not contact the first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450. For example, the contact barrier pattern 285 may not contact a portion of the source / drain etch stop film 185 extending along the upper surface 150US of the first source / drain pattern 150. That is, the contact barrier pattern 285 may not contact a portion of the source / drain etch stop film 185 extending along the upper surface of the first lower connection semiconductor pattern 150_1.

[0198] A depth d11 from the upper surface CCW1_US of the first channel separation structure CCW1 to the uppermost portion of the first source / drain pattern 150 may be greater than a depth d12 from the upper surface CCW1_US of the first channel separation structure CCW1 to the lower surface 285BS of the contact barrier pattern 285 .

[0199] Alternatively, the contact barrier pattern 285 may contact a portion of the source / drain etch stop film 185 extending along the upper surface 150US of the first source / drain pattern 150 . The contact barrier pattern 285 may not penetrate the source / drain etch stop film 185 .

[0200] The contact barrier pattern 285 may include or be formed of an insulating material. The contact barrier pattern 285 may include a material having an etching selectivity relative to the upper interlayer insulating film 190. For example, the contact barrier pattern 285 may include at least one of SiN, SiON, SiOCN, SiBN, SiOBN, SiOC, and combinations thereof.

[0201] The first backside wiring 290 and the second backside wiring 295 may be disposed within the substrate 100. The first backside wiring 290 and the second backside wiring 295 may be disposed on the lower surface BP1_BS of the first lower pattern BP1, the lower surface BP2_BS of the second lower pattern BP2, the lower surface BP3_BS of the third lower pattern BP3, and the lower surface BP4_BS of the fourth lower pattern BP4. Although the first backside wiring 290 and the second backside wiring 295 are shown to extend in the first direction D1, the present disclosure is not limited thereto.

[0202] For example, the first backside wiring 290 and the second backside wiring 295 may include a line portion and a via portion. The via portion of the first backside wiring 290 may protrude from the line portion of the first backside wiring 290 in the third direction D3. The via portion of the second backside wiring 295 may protrude from the line portion of the second backside wiring 295 in the third direction D3. The first backside wiring 290 and the second backside wiring 295 may not include a via portion.

[0203] The first backside source / drain contact 175 may be disposed within the first lower pattern BP1 . The first backside source / drain contact 175 may be disposed between the first source / drain pattern 150 and the first backside wiring 290 .

[0204] The first back side source / drain contact 175 may be connected to the first source / drain pattern 150. The first back side source / drain contact 175 may electrically connect the first source / drain pattern 150 and the first back side wiring 290. For example, the first back side source / drain contact 175 may electrically connect the first lower connection semiconductor pattern 150_1 and the first back side wiring 290. The first back side wiring 290 may not be electrically connected to the first source / drain contact 180. The first back side source / drain contact 175 is not connected to the first upper connection semiconductor pattern 150_2. For example, Figure 5 As shown in , the second source / drain contact 280 may not be connected to the first backside wiring 290. Each of the third source / drain contact 380 and the fourth source / drain contact 480 may not be connected to the second backside wiring 295.

[0205] The third backside source / drain contact 375 may be disposed within the third lower pattern BP3 . The third backside source / drain contact 375 may be disposed between the third source / drain pattern 350 and the second backside wiring 295 .

[0206] The third backside source / drain contact 375 may be connected to the third source / drain pattern 350. The third backside source / drain contact 375 may electrically connect the third source / drain pattern 350 and the second backside wiring 295. For example, the third backside source / drain contact 375 may electrically connect the third lower connection semiconductor pattern 350_1 and the second backside wiring 295. The second backside wiring 295 may not be electrically connected to the third source / drain contact 380. The third backside source / drain contact 375 may not be connected to the third upper connection semiconductor pattern 350_2.

[0207] Alternatively, the second backside source / drain contact 275 may connect the first backside wiring 290 and the second source / drain pattern 250 , and the fourth backside source / drain contact may connect the second backside wiring 295 and the fourth source / drain pattern 450 .

[0208] The first backside contact silicide film 156 may be disposed between the first backside source / drain contact 175 and the first source / drain pattern 150. The third backside contact silicide film 356 may be disposed between the third backside source / drain contact 375 and the third source / drain pattern 350. Alternatively, the second backside contact silicide film may be disposed between the second backside source / drain contact and the second source / drain pattern 250. The fourth backside contact silicide film may be disposed between the fourth backside source / drain contact and the fourth source / drain pattern 450.

[0209] The first back side source / drain contact 175 and the third back side source / drain contact 375 are shown as a single layer of conductive film, but the present disclosure is not limited thereto. Optionally, the first back side source / drain contact 175 and the third back side source / drain contact 375 may have a multilayer conductive film structure including a barrier film and a filling film. The first back side wiring 290 and the second back side wiring 295 are shown as a single layer of conductive film, but the present disclosure is not limited thereto. Optionally, the first back side wiring 290 and the second back side wiring 295 may have a multilayer conductive film structure including a barrier film and a filling film.

[0210] The first backside source / drain contact 175 and the third backside source / drain contact 375 may include, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a 2D material. The first backside wiring 290 and the second backside wiring 295 may include, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a 2D material. The first backside contact silicide film 156 and the third backside contact silicide film 356 may include a metal silicide material.

[0211] The first source / drain pattern 150 and the third source / drain pattern 350 are shown as being connected to different backside wirings from each other, but the present disclosure is not limited thereto. The first source / drain pattern 150 and the third source / drain pattern 350 may be connected to the first backside wiring 290 or the second backside wiring 295. In this case, the width of the backside wiring connected to the first source / drain pattern 150 and the third source / drain pattern 350 may be greater than the width of the first backside wiring 290 and the second backside wiring 295.

[0212] The front side source / drain contact may not be formed on the source / drain pattern connected to the back side source / drain contact. If the front side source / drain contact is formed on the source / drain pattern connected to the back side source / drain contact, unnecessary capacitance may be generated between the front side source / drain contact and the gate electrode.

[0213] However, since the front side source / drain contacts are not formed on the source / drain patterns connected to the back side source / drain contacts, no capacitance is generated between the front side source / drain contacts and the gate electrode. As a result, the performance and reliability of the semiconductor device can be improved.

[0214] Fig.10 and Fig.11 is a diagram illustrating a semiconductor device according to one or more embodiments of the present disclosure. Fig.12 1 is a diagram showing a semiconductor device according to one or more embodiments of the present disclosure. Figures 1 to 9 The differences in the described embodiments are described Figures 10 to 12 Embodiment of the invention.

[0215] Fig.10 It is shown Figure 1 A plan view of another example of portion P. Fig.11 and Fig.12 It is shown Figure 5 An enlarged cross-sectional view of an example of portion S.

[0216] Reference Fig.10 and Fig.11 , the first overlapping width W13 may be different from the second overlapping width W14.

[0217] For example, a width W13 of the first source / drain pattern 150 overlapping the first channel separation structure CCW1 in the second direction D2 may be greater than a width W14 of the second source / drain pattern 250 overlapping the first channel separation structure CCW1 in the second direction D2.

[0218] The first width centerline WCL1 may be spaced apart from the second width centerline WCL2 in the second direction D2. The first width centerline WCL1 may not be aligned with the second width centerline WCL2 in the third direction D3. An extension of the first width centerline WCL1 may not intersect the second width centerline WCL2.

[0219] Although a portion of the second source / drain pattern 250 is shown as overlapping the first portion CCW1_R21 of the second region CCW1_R2 of the first channel separation structure CCW1 in the third direction D3, the present disclosure is not limited thereto. That is, the second source / drain pattern 250 may not include a portion overlapping the first portion CCW1_R21 of the second region CCW1_R2 of the first channel separation structure CCW1.

[0220] Reference Fig.12 , the second region CCW1_R2 of the first channel separation structure CCW1 may further include a third portion CCW1_R23 disposed between the first portion CCW1_R21 and the second portion CCW1_R22 of the second region CCW1_R2 of the first channel separation structure CCW1 .

[0221] In the third portion CCW1_R23 of the second region CCW1_R2 of the first trench separation structure CCW1 , the width of the first trench separation structure CCW1 in the second direction D2 may decrease as being farther from the lower surface 105BS of the field insulating film.

[0222] The first portion CCW1_R21 and the third portion CCW1_R23 of the second region CCW1_R2 of the first trench separation structure CCW1 are shown without a clear boundary therebetween, but the present disclosure is not limited thereto. Alternatively, the first portion CCW1_R21 of the second region CCW1_R2 of the first trench separation structure CCW1 may be clearly separated from the third portion CCW1_R23 of the second region CCW1_R2 of the first trench separation structure CCW1 by a boundary.

[0223] Fig.13 is a diagram illustrating a semiconductor device according to one or more embodiments of the present disclosure. Fig.14 and Fig.15 1 is a diagram showing a semiconductor device according to one or more embodiments of the present disclosure. Figures 1 to 9 The differences in the described embodiments are described Figures 13 to 15 Embodiment of the invention.

[0224] Reference Fig.13, a depth H11 from the upper surface BP1_US of the first lower pattern BP1 to the lowermost portion of the first channel separation structure CCW1 may be equal to a depth H12 from the upper surface BP1_US of the first lower pattern BP1 to the lower surface 105BS of the field insulating film 105 .

[0225] The first and second trench separation structures CCW1 and CCW2 may extend to the first surface 100US of the substrate 100 .

[0226] Reference Fig.14 and Fig.15 , sacrificial semiconductor pattern ( Figure 2 , Figure 3 and Figure 5 The “160SC” of FIG. 1 may not be disposed in the first lower pattern BP1, the second lower pattern BP2, the third lower pattern BP3, and the fourth lower pattern BP4.

[0227] No sacrificial semiconductor pattern may be disposed between the substrate 100 and the first, second, third, and fourth source / drain patterns 150, 250, 350, and 450. No sacrificial semiconductor pattern may be disposed under the first, second, third, and fourth source / drain patterns 150, 250, 350, and 450 connected to the first, second, third, and fourth source / drain contacts 180, 280, 380, and 480.

[0228] For example, no sacrificial semiconductor pattern may be disposed between the substrate 100 and the first upper connection semiconductor pattern 150_2 of the first source / drain pattern 150 .

[0229] Fig.16 and Fig.17 1 is a diagram showing a semiconductor device according to one or more embodiments. Figures 1 to 9 The differences in the described embodiments are described Fig.16 and Fig.17 Embodiment of the invention.

[0230] Reference Fig.16 and Fig.17 , the semiconductor device according to one or more embodiments of the present disclosure may further include a first lower insulating pattern BDI1 , a second lower insulating pattern BDI2 , a third lower insulating pattern BDI3 , and a fourth lower insulating pattern BDI4 .

[0231] The first lower insulating pattern BDI1 may be disposed between the first lower pattern BP1 and the first channel pattern CH1. The first lower insulating pattern BDI1 may contact an upper surface BP1_US of the first lower pattern BP1. The first lower insulating pattern BDI1 may be disposed between the first lower pattern BP1 and the first gate structure GS1.

[0232] The second lower insulating pattern BDI2 may be disposed between the second lower pattern BP2 and the second channel pattern CH2. The second lower insulating pattern BDI2 may contact the upper surface BP2_US of the second lower pattern BP2. The second lower insulating pattern BDI2 may be disposed between the second lower pattern BP2 and the second gate structure GS2.

[0233] The third lower insulating pattern BDI3 may be disposed between the third lower pattern BP3 and the third channel pattern CH3. The third lower insulating pattern BDI3 may contact an upper surface BP3_US of the third lower pattern BP3. The third lower insulating pattern BDI3 may be disposed between the third lower pattern BP3 and the third gate structure GS3.

[0234] The fourth lower insulating pattern BDI4 may be disposed between the fourth lower pattern BP4 and the fourth channel pattern CH4. The fourth lower insulating pattern BDI4 may contact the upper surface BP4_US of the fourth lower pattern BP4. The fourth lower insulating pattern BDI4 may be disposed between the fourth lower pattern BP4 and the fourth gate structure GS4.

[0235] The first lower insulating pattern BDI1 may be spaced apart from the second lower insulating pattern BDI2 in the second direction D2. The first trench separation structure CCW1 may separate the first lower insulating pattern BDI1 and the second lower insulating pattern BDI2 from each other.

[0236] The third lower insulating pattern BDI3 may be spaced apart from the fourth lower insulating pattern BDI4 in the second direction D2. The second channel separation structure CCW2 may separate the third lower insulating pattern BDI3 and the fourth lower insulating pattern BDI4 from each other.

[0237] The first lower insulating pattern BDI1, the second lower insulating pattern BDI2, the third lower insulating pattern BDI3, and the fourth lower insulating pattern BDI4 may not extend along the upper surface 105US of the field insulating film 105. The first lower insulating pattern BDI1, the second lower insulating pattern BDI2, the third lower insulating pattern BDI3, and the fourth lower insulating pattern BDI4 may not cover the upper surface 105US of the field insulating film 105.

[0238] For example, each first lower insulating pattern BDI1 may include an upper surface and a lower surface opposite to each other in the third direction D3. The lower surface of the first lower insulating pattern BDI1 may contact the upper surface BP1_US of the first lower pattern BP1. The upper surface of the first lower insulating pattern BDI1 may be higher than the upper surface 105US of the field insulating film 105 based on the lower surface 105BS of the field insulating film 105. The upper surface of the first lower insulating pattern BDI1 may protrude beyond the upper surface 105US of the field insulating film 105.

[0239] The first gate structure GS1 will be described hereinafter as an example The first gate insulating film 130 may contact an upper surface of the first lower insulating pattern BDI1.

[0240] The first lower insulating pattern BDI1, the second lower insulating pattern BDI2, the third lower insulating pattern BDI3 and the fourth lower insulating pattern BDI4 may include at least one of SiN, SiON, SiCN and SiOCN. Alternatively, the first lower insulating pattern BDI1, the second lower insulating pattern BDI2, the third lower insulating pattern BDI3 and the fourth lower insulating pattern BDI4 may include silicon oxide.

[0241] Fig.18 and Fig.19 1 is a diagram showing a semiconductor device according to one or more embodiments of the present disclosure. Fig.16 and Fig.17 The embodiments are described by referring to the differences of the described embodiments.

[0242] Reference Fig.18 and Fig.19 , each of the first channel patterns CH1 may further include a first dummy sheet pattern NSD1 disposed between the first lower insulating pattern BDI1 and the first sheet pattern NS1. The first dummy sheet pattern NSD1 may contact the first lower insulating pattern BDI1.

[0243] Each of the second channel patterns CH2 may further include a second dummy sheet pattern NSD2 disposed between the second lower insulating pattern BDI2 and the second sheet pattern NS2. The second dummy sheet pattern NSD2 may contact the second lower insulating pattern BDI2.

[0244] Each of the third channel patterns CH3 may further include a third dummy sheet pattern NSD3 disposed between the third lower insulating pattern BDI3 and the third sheet pattern NS3. The third dummy sheet pattern NSD3 may contact the third lower insulating pattern BDI3.

[0245] Each of the fourth channel patterns CH4 may further include a fourth dummy sheet pattern NSD4 disposed between the fourth lower insulating pattern BDI4 and the fourth sheet pattern NS4. The fourth dummy sheet pattern NSD4 may contact the fourth lower insulating pattern BDI4.

[0246] The thickness of the dummy sheet patterns (NSD1, NSD2, NSD3, and NSD4) in the third direction D3 is smaller than the thickness of the sheet patterns (NS1, NS2, NS3, and NS4) in the third direction D3. The dummy sheet patterns (NSD1, NSD2, NSD3, and NSD4) may include the same material as the sheet patterns (NS1, NS2, NS3, and NS4).

[0247] Hereinafter, the first dummy sheet pattern NSD1 will be described as an example Since the first dummy sheet pattern NSD1 contacts the upper surface of the first lower insulating pattern BDI1 , the first gate insulating film 130 may not contact the upper surface of the first lower insulating pattern BDI1 .

[0248] Fig. 20 1 is a diagram showing a semiconductor device according to one or more embodiments of the present disclosure. Figures 1 to 9 The differences in the described embodiments are described Fig. 20 Embodiment of the invention.

[0249] Reference Fig. 20 , the semiconductor device according to one or more embodiments of the present disclosure may further include an inner spacer 340IN, and the inner spacer 340IN may be disposed between the third source / drain pattern 350 and the third internal gate structure INT_GS3.

[0250] The inner spacer 340IN may be disposed between the third lower pattern BP3 and the third sheet pattern NS3 and between the third sheet patterns NS3 adjacent to each other in the third direction D3 The third inner gate structure INT_GS3 may not contact the third source / drain pattern 350 .

[0251] The inner spacer 340IN may include, for example, SiN, SiON, SiO 2 , at least one of SiOCN, SiBN, SiOBN, SiOC and combinations thereof.

[0252] The inner spacer 340IN may also be disposed in the first lower pattern ( Figure 2 Between the first sheet patterns NS1 and the first sheet patterns NS1 adjacent to each other in the third direction D3.

[0253] Fig.21 and Fig. 22is a diagram showing a semiconductor device according to one or more embodiments of the present disclosure. For convenience, the description will mainly focus on Figures 1 to 9 Different aspects of the description.

[0254] Specifically, Fig.21 is a layout diagram showing a semiconductor device according to one or more embodiments of the present disclosure, and Fig. 22 It is along Fig.21 A cross-sectional view taken along line DD.

[0255] Reference Fig.21 and Fig. 22 , the first back side source / drain contact 175 and the second back side source / drain contact 275 may be adjacent to each other in the second direction D2.

[0256] The second backside source / drain contact 275 may be disposed within the second lower pattern BP2 . The second contact silicide film 256 may be disposed between the second backside source / drain contact 275 and the second source / drain pattern 250 .

[0257] The first channel separation structure CCW1 may be disposed between the first back side source / drain contact 175 and the second back side source / drain contact 275. The first source / drain pattern 150 connected to the first back side source / drain contact 175 and the second source / drain pattern 250 connected to the second back side source / drain contact 275 may both contact the single first channel separation structure CCW1. The first source / drain pattern 150 connected to the first back side source / drain contact 175 and the second source / drain pattern 250 connected to the second back side source / drain contact 275 may be aligned in the second direction D2.

[0258] The first back side source / drain contacts 175 and the second back side source / drain contacts 275 adjacent in the second direction D2 may be connected to the first back side wiring 290 .

[0259] The contact barrier pattern 285 may be disposed on the first source / drain pattern 150 and the second source / drain pattern 250. The contact barrier pattern 285 may extend in the second direction D2. A single contact barrier pattern 285 may be disposed on a plurality of first source / drain patterns 150 or second source / drain patterns 250.

[0260] For example, the contact barrier pattern 285 may be disposed on the first channel separation structure CCW1. The contact barrier pattern 285 may intersect the first channel separation structure CCW1.

[0261] From a cross-sectional perspective, when a single contact barrier pattern 285 is disposed on the first source / drain pattern 150 or the second source / drain pattern 250, the contact barrier pattern 285 may cover the upper surface of the first channel separation structure CCW1. From a cross-sectional perspective, based on the first surface 100US of the substrate 100, the upper surface GCS_US of the gate separation structure may be higher than the upper surface of the first channel separation structure CCW1.

[0262] Fig.23 and Fig.24 1 is a diagram showing a semiconductor device according to one or more embodiments of the present disclosure. Figures 1 to 9 The differences in the described embodiments are described Fig.23 and Fig.24 Embodiment of the invention.

[0263] Specifically, Fig.23 is a layout diagram showing a semiconductor device according to one or more embodiments of the present disclosure, and Fig.24 It is along Fig.23 A cross-sectional view taken along line DD.

[0264] Reference Fig.23 and Fig.24 The semiconductor device according to one or more embodiments of the present disclosure may further include a source / drain separation structure SCS, and the source / drain separation structure SCS may be disposed on the field insulating film 105 .

[0265] The source / drain separation structure SCS may be disposed on the upper surface 105US of the field insulating film 105. The source / drain separation structure SCS may not contact the field insulating film 105.

[0266] The source / drain separation structure SCS may be disposed between the gate separation structures GCS adjacent to each other in the first direction D1. Alternatively, the gate separation structure GCS may be disposed between the source / drain separation structures SCS adjacent to each other in the first direction D1. The source / drain separation structure SCS and the gate separation structure GCS may be alternately disposed along the first direction D1.

[0267] The first source / drain pattern 150 may be disposed between the source / drain separation structure SCS and the first channel separation structure CCW1. The second source / drain pattern 250 may be disposed between the source / drain separation structure SCS and the first channel separation structure CCW1. The third source / drain pattern 350 may be disposed between the source / drain separation structure SCS and the second channel separation structure CCW2. The fourth source / drain pattern 450 may be disposed between the source / drain separation structure SCS and the second channel separation structure CCW2.

[0268] The upper surface SCS_US of the source / drain separation structure SCS may be in the same plane as the upper surface GCS_US of the gate separation structure GCS. The upper surface SCS_US of the source / drain separation structure SCS may be in the same plane as the upper surface CCW1_US of the first channel separation structure CCW1. The upper surface SCS_US of the source / drain separation structure SCS may be in the same plane as the upper surface CCW2_US of the second channel separation structure CCW2. The upper surface SCS_US of the source / drain separation structure SCS may be in the same plane as the upper surface 285US of the contact barrier pattern 285.

[0269] For example, a height of the source / drain separation structure SCS in the third direction D3 may be smaller than a height of the gate separation structure GCS in the third direction D3.

[0270] For example, a depth d13 from the upper surface CCW1_US of the first channel separation structure CCW1 to the lower surface of the source / drain separation structure SCS may be greater than a depth d12 from the upper surface CCW1_US of the first channel separation structure CCW1 to the lower surface 285BS of the contact barrier pattern 285. Alternatively, in another example, the depth d13 from the upper surface CCW1_US of the first channel separation structure CCW1 to the lower surface of the source / drain separation structure SCS may be equal to a depth d12 from the upper surface CCW1_US of the first channel separation structure CCW1 to the lower surface 285BS of the contact barrier pattern 285.

[0271] The source / drain separation structure SCS may include, for example, at least one of SiN, SiON, SiOCN, SiBN, SiOBN, SiOC, and a combination thereof.

[0272] Figures 25 to 42 is a diagram illustrating an intermediate step of a method of manufacturing a semiconductor device according to one or more embodiments of the present disclosure.

[0273] Reference Figure 25 to Figure 27 , a first lower pattern BP1 , a second lower pattern BP2 , a third lower pattern BP3 , and a fourth lower pattern BP4 may be formed on the support substrate 200 .

[0274] The support substrate 200 may be formed of or include a semiconductor material. The support substrate 200 may be a Si substrate or a silicon-on-insulator (SOI) substrate. Alternatively, the support substrate 200 may include, for example, SiGe, SiGe-on-insulator (SGOI), indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but the present disclosure is not limited thereto.

[0275] A first pre-down pattern and a second pre-down pattern may be formed on the support substrate 200. The fin trench FT may separate the first pre-down pattern and the second pre-down pattern.

[0276] First and second channel separation structures CCW1 and CCW2 may be formed on the support substrate 200. The first channel separation structure CCW1 may divide the first pre-lower pattern to form first and second lower patterns BP1 and BP2. The second channel separation structure CCW2 may divide the second pre-lower pattern to form third and fourth lower patterns BP3 and BP4.

[0277] During the formation of the first lower pattern BP1, the second lower pattern BP2, the third lower pattern BP3, and the fourth lower pattern BP4, a pre-channel pattern may be formed on the first lower pattern BP1, the second lower pattern BP2, the third lower pattern BP3, and the fourth lower pattern BP4. Each pre-channel pattern may include a sacrificial pattern and an active pattern alternately stacked. The active pattern may be later turned into a sheet pattern through a subsequent process.

[0278] A dummy gate electrode may be formed on the first, second, third, and fourth lower patterns BP1, BP2, BP3, and BP4. The dummy gate electrode may intersect the pre-channel pattern.

[0279] After forming the dummy gate electrode, a sacrificial semiconductor pattern 160SC may be formed within the first lower pattern BP1, the second lower pattern BP2, the third lower pattern BP3, and the fourth lower pattern BP4. Alternatively, the sacrificial semiconductor pattern 160SC may be formed only in regions connected to the first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450 to be formed within the first lower pattern BP1, the second lower pattern BP2, the third lower pattern BP3, and the fourth lower pattern BP4. Then, a sacrificial pattern cover film 160IP may be formed on the sacrificial semiconductor pattern 160SC.

[0280] Unlike what has been described, the sacrificial semiconductor pattern 160SC may be formed before forming the first to fourth lower patterns BP1, BP2, BP3, and BP4. In this case, the sacrificial semiconductor pattern 160SC may be formed within the first and second pre-lower patterns.

[0281] The first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450 may be formed on the first lower pattern BP1, the second lower pattern BP2, the third lower pattern BP3, and the fourth lower pattern BP4. For example, the first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450 may be formed on the sacrificial pattern cover film 160IP. The first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450 may be formed within the pre-channel pattern.

[0282] A source / drain etch stop film 185 and an upper interlayer insulating film 190 may be formed on the first source / drain pattern 150 , the second source / drain pattern 250 , the third source / drain pattern 350 , and the fourth source / drain pattern 450 .

[0283] After forming the upper interlayer insulating film 190, the dummy gate electrode may be removed. As a result, the pre-channel pattern may be exposed. The sacrificial pattern may be removed from within the exposed pre-channel pattern, thereby forming the first channel pattern CH1, the second channel pattern CH2, the third channel pattern CH3, and the fourth channel pattern CH4.

[0284] After forming the first, second, third, and fourth channel patterns CH1, CH2, CH3, and CH4, a pre-gate electrode 120PR and a pre-gate insulating film 130PR may be formed. A pre-gate capping pattern 145PR may be formed on the pre-gate electrode 120PR and the pre-gate insulating film 130PR.

[0285] Reference Figures 28 to 30 , a gate separation structure GCS may be formed on the field insulating film 105 .

[0286] A gate separation structure GCS may be formed between the first channel separation structure CCW1 and the second channel separation structure CCW2. The pre-gate electrode 120PR and the pre-gate insulating film 130PR may be patterned by the gate separation structure GCS. As a result, the first gate electrode 120, the second gate electrode 220, the third gate electrode 320, the fourth gate electrode 420, the first gate insulating film 130, the second gate insulating film 230, the third gate insulating film 330, and the fourth gate insulating film 430 may be formed. The gate separation structure GCS may cut the pre-gate capping pattern 145PR. As a result, the first gate capping pattern 145 and the second gate capping pattern 345 may be formed.

[0287] A source / drain separation structure SCS may be formed within the upper interlayer insulating film 190. A source / drain separation structure SCS may be formed between the first channel separation structure CCW1 and the second channel separation structure CCW2. A source / drain separation structure SCS may be formed between source / drain patterns adjacent to each other along the second direction D2. For example, a source / drain separation structure SCS may be formed between the first source / drain pattern 150 and the third source / drain pattern 350.

[0288] Alternatively, the gate separation structure GCS may be formed between source / drain patterns adjacent to each other along the second direction D2. In this case, the source / drain separation structure SCS may not be formed.

[0289] Reference Fig.31 and Fig.32 , a contact barrier pattern hole 285H may be formed in the upper interlayer insulating film 190 .

[0290] During the formation of the contact barrier pattern hole 285H, a portion of the source / drain etch stop film 185 and the first gate capping pattern 145 may be etched. During the formation of the contact barrier pattern hole 285H, a portion of the source / drain separation structure SCS may be etched. The contact barrier pattern hole 285H does not expose the first source / drain pattern 150.

[0291] Reference Fig.33 and Fig.34 , a contact barrier pattern 285 may be formed within the upper interlayer insulating film 190 .

[0292] The contact barrier pattern 285 fills the contact barrier pattern hole 285H. The contact barrier pattern 285 may be formed of an insulating material having an etch selectivity with respect to the upper interlayer insulating film 190.

[0293] Reference Fig.35 and Fig.36 , the upper interlayer insulating film 190 and the source / drain etching stopper film 185 may be removed. As a result, the first source / drain contact hole 180H, the second source / drain contact hole 280H, the third source / drain contact hole 380H, and the fourth source / drain contact hole 480H may be formed.

[0294] The first source / drain contact hole 180H, the second source / drain contact hole 280H, the third source / drain contact hole 380H, and the fourth source / drain contact hole 480H respectively expose the first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450. Since the contact barrier pattern 285 has an etching selectivity to the upper interlayer insulating film 190, the first source / drain contact hole 180H is not formed in the region where the contact barrier pattern 285 is formed.

[0295] Reference Fig.37 and Fig.38 , a first source / drain contact 180 , a second source / drain contact 280 , a third source / drain contact 380 and a fourth source / drain contact 480 may be formed on the first source / drain pattern 150 , the second source / drain pattern 250 , the third source / drain pattern 350 and the fourth source / drain pattern 450 , respectively.

[0296] A first source / drain contact 180, a second source / drain contact 280, a third source / drain contact 380, and a fourth source / drain contact 480 may be formed in the first source / drain contact hole 180H, the second source / drain contact hole 280H, the third source / drain contact 380H, and the fourth source / drain contact hole 480H, respectively. The first source / drain contact 180, the second source / drain contact 280, the third source / drain contact 380, and the fourth source / drain contact 480 are electrically connected to the first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350, and the fourth source / drain pattern 450, respectively.

[0297] A first contact silicide film 155, a second contact silicide film 255, a third contact silicide film 355 and a fourth contact silicide film 455 may be formed between the “first source / drain contact 180, the second source / drain contact 280, the third source / drain contact 380 and the fourth source / drain contact 480” and the “first source / drain pattern 150, the second source / drain pattern 250, the third source / drain pattern 350 and the fourth source / drain pattern 450”.

[0298] Reference Figures 37 to 40 , the supporting substrate 200 may be removed.

[0299] The first lower pattern BP1, the second lower pattern BP2, the third lower pattern BP3, the fourth lower pattern BP4 and the field insulating film 105 may be exposed. The sacrificial semiconductor pattern 160SC may be exposed.

[0300] Reference Figures 39 to 42, a backside mask pattern BS_MASK may be formed on the first lower pattern BP1 , the second lower pattern BP2 , the third lower pattern BP3 , the fourth lower pattern BP4 , and the field insulating film 105 .

[0301] For example, the backside mask pattern BS_MASK may include an opening. The opening of the backside mask pattern BS_MASK may overlap the “sacrificial semiconductor pattern 160SC formed in a region where the backside source / drain contacts are to be formed” in the third direction D3.

[0302] The sacrificial semiconductor pattern 160SC and the sacrificial pattern cover film 160IP may be removed using the backside mask pattern BS_MASK. As a result, a backside source / drain contact hole 175H may be formed. The backside source / drain contact hole 175H may expose the first source / drain pattern 150.

[0303] Refer again Figure 2 and Figure 5 , a first back side source / drain contact 175 may be formed in the back side source / drain contact hole 175H. The first back side source / drain contact 175 may be connected to the first source / drain pattern 150. For example, the first back side source / drain contact 175 may be connected to the first lower connection semiconductor pattern 150_1. A first back side contact silicide film 156 may be formed between the first back side source / drain contact 175 and the first source / drain pattern 150.

[0304] By removing the backside mask pattern BS_MASK, the first to fourth lower patterns BP1, BP2, BP3, BP4 and the field insulating film 105 may be exposed. Thereafter, the substrate 100 may be formed. The first and second backside wirings 290 and 295 may be formed within the substrate 100.

[0305] Alternatively, the substrate 100 may be formed with the backside mask pattern BS_MASK still present.

[0306] Those skilled in the art will appreciate that variations and modifications of the disclosed embodiments discussed herein can be made without substantially departing from the principles of the present disclosure.

Claims

1. A semiconductor device comprising: a first lower pattern extending in the first direction and comprising a first sidewall, a second sidewall, an upper surface, and a lower surface, wherein the first sidewall and the second sidewall are opposite to each other in the second direction, and wherein the upper surface and the lower surface are opposite to each other in the third direction; a trench separation structure extending in a first direction and contacting a first sidewall of the first lower pattern; a field insulating film contacting a second side wall of the first lower pattern; a first channel pattern, on an upper surface of the first lower pattern, the first channel pattern including a plurality of first sheet patterns spaced apart from each other in a third direction, wherein the plurality of first sheet patterns are in contact with the channel separation structure; a first source / drain pattern in contact with the first channel pattern and the channel separation structure; a contact barrier pattern on the first source / drain pattern, wherein the contact barrier pattern is formed of an insulating material, and wherein the contact barrier pattern includes an upper surface that is in the same plane as an upper surface of the channel separation structure; a first backside source / drain contact within the first lower pattern and connected to the first source / drain pattern; and A backside wiring is on a lower surface of the first lower pattern, wherein the backside wiring is connected to the first backside source / drain contacts.

2. The semiconductor device according to claim 1, further comprising: one or more source / drain etch stop films extending along an upper surface of the field insulating film and sidewalls of the first source / drain pattern; as well as one or more interlayer insulating films, on the one or more source / drain etch stop films, Wherein, the contact barrier pattern is on the one or more interlayer insulating films.

3. The semiconductor device according to claim 2, wherein: A depth from an upper surface of the channel separation structure to an uppermost portion of the first source / drain pattern is greater than a depth from an upper surface of the channel separation structure to a lower surface of the contact barrier pattern.

4. The semiconductor device according to claim 1, further comprising: Source / drain separation structure, on the field insulating film, The first source / drain pattern is arranged between the source / drain separation structure and the channel separation structure. The upper surface of the source / drain separation structure and the upper surface of the channel separation structure are in the same plane, and The depth from the upper surface of the channel separation structure to the lower surface of the source / drain separation structure is greater than or equal to the depth from the upper surface of the channel separation structure to the lower surface of the contact barrier pattern.

5. The semiconductor device according to claim 4, further comprising: a gate structure on the first lower pattern, wherein the gate structure is in contact with the channel separation structure; and a gate separation structure on the field insulating film, wherein the gate separation structure is in contact with the gate structure, The gate structure is between the gate separation structure and the channel separation structure. The upper surface of the source / drain separation structure and the upper surface of the gate separation structure are in the same plane, and The height of the source / drain separation structure is smaller than the height of the gate separation structure.

6. The semiconductor device according to claim 1, further comprising: a gate structure on the first lower pattern, wherein the gate structure is in contact with the channel separation structure; and a gate separation structure on the field insulating film and extending in a first direction, The gate structure and the first source / drain pattern are between the channel separation structure and the gate separation structure.

7. The semiconductor device according to claim 1, further comprising: a second lower pattern spaced apart from the first lower pattern in the second direction and extending in the first direction; a second channel pattern, on an upper surface of the second lower pattern, the second channel pattern comprising a plurality of second sheet patterns, wherein the plurality of second sheet patterns are spaced apart from each other in a third direction; a second source / drain pattern contacting the second channel pattern and the channel separation structure; and a source / drain contact on and connected to the second source / drain pattern, Wherein, the second lower pattern is in contact with the channel separation structure, wherein the plurality of second sheet-like patterns are in contact with the trench separation structure, The upper surface of the source / drain contact is in the same plane as the upper surface of the channel separation structure, and Therein, the source / drain contacts are not connected to the backside wiring.

8. The semiconductor device according to claim 7, further comprising: The sacrificial semiconductor pattern, within the second lower pattern, The second source / drain pattern is between the sacrificial semiconductor pattern and the source / drain contact.

9. The semiconductor device according to claim 1, further comprising: a second lower pattern spaced apart from the first lower pattern in the second direction and extending in the first direction; a second channel pattern, on an upper surface of the second lower pattern, the second channel pattern comprising a plurality of second sheet patterns, wherein the plurality of second sheet patterns are spaced apart from each other in a third direction; a second source / drain pattern in contact with the second channel pattern and the channel separation structure; a second backside source / drain contact within the second lower pattern, wherein the second backside source / drain contact is connected to the second source / drain pattern; and A second backside wiring is on a lower surface of the first lower pattern, wherein a second backside source / drain contact is connected to the second backside wiring.

10. The semiconductor device according to claim 1, further comprising: A lower insulating pattern is between the first lower pattern and the first channel pattern, wherein the lower insulating pattern contacts an upper surface of the first lower pattern.

11. The semiconductor device according to claim 1, in, In a region where the channel separation structure contacts the first source / drain pattern, the channel separation structure includes a first portion and a second portion, The width of the trench separation structure in the second direction increases as it moves away from the lower surface of the field insulating film. wherein the second portion of the trench separation structure is on the first portion of the trench separation structure, and The width of the uppermost portion of the first portion of the trench separation structure is greater than the width of the lowermost portion of the second portion of the trench separation structure.

12. The semiconductor device according to claim 11, wherein A height from a lower surface of the field insulating film to an uppermost portion of the first portion of the channel separation structure is smaller than a height from a lower surface of the field insulating film to an uppermost portion of the first source / drain pattern.

13. The semiconductor device according to claim 12, wherein: A portion of the first source / drain pattern overlaps the first portion of the channel separation structure in the third direction.

14. The semiconductor device according to claim 1, wherein A depth from an upper surface of the first lower pattern to a lowermost portion of the trench separation structure is less than or equal to a depth from an upper surface of the first lower pattern to a lower surface of the field insulating film.

15. A semiconductor device comprising: A first trench separation structure extending in a first direction; a second trench separation structure spaced apart from the first trench separation structure in the second direction and extending in the first direction; a first lower pattern between the first trench separation structure and the second trench separation structure, contacting the first trench separation structure, and including a first upper surface and a first lower surface, wherein the first upper surface and the first lower surface are opposite to each other; a second lower pattern between the first trench separation structure and the second trench separation structure, wherein the second lower pattern contacts the second trench separation structure, extends in the first direction, and includes a second upper surface and a second lower surface, wherein the first upper surface and the second lower surface are opposite to each other; a field insulating film between the first lower pattern and the second lower pattern; a first channel pattern, on the first upper surface, the first channel pattern comprising a plurality of first sheet patterns spaced apart from each other in a third direction, wherein the plurality of first sheet patterns are in contact with the first channel separation structure; a second channel pattern, on the second upper surface, the second channel pattern comprising a plurality of second sheet patterns spaced apart from each other in a third direction, wherein the plurality of second sheet patterns are in contact with the second channel separation structure; a first source / drain pattern in contact with the first channel pattern and the first channel separation structure; a second source / drain pattern in contact with the second channel pattern and the second channel separation structure; a source / drain separation structure between the first source / drain pattern and the second source / drain pattern, the source / drain separation structure comprising an upper surface that is in the same plane as an upper surface of the first channel separation structure; a contact barrier pattern on the first source / drain pattern, wherein the contact barrier pattern is formed of an insulating material, and wherein the contact barrier pattern includes an upper surface that is in the same plane as an upper surface of the first trench separation structure; a source / drain contact on and connected to the second source / drain pattern, wherein the source / drain contact includes an upper surface that is in the same plane as an upper surface of the second channel separation structure; a backside source / drain contact within the first lower pattern and connected to the first source / drain pattern; and A backside wiring is on the first lower surface and the second lower surface, wherein the backside wiring is connected to the backside source / drain contacts.

16. The semiconductor device according to claim 15, further comprising: The sacrificial semiconductor pattern, within the second lower pattern, The second source / drain pattern is between the sacrificial semiconductor pattern and the source / drain contact.

17. The semiconductor device according to claim 15, wherein: The source / drain contacts are not connected to the backside wiring.

18. The semiconductor device according to claim 15, wherein The contact barrier pattern does not contact the first source / drain pattern.

19. The semiconductor device according to claim 15, further comprising: a first lower insulating pattern between the first lower pattern and the first channel pattern, wherein the first lower insulating pattern contacts the first upper surface; and A second lower insulating pattern is between the second lower pattern and the second channel pattern, wherein the second lower insulating pattern contacts the second upper surface.

20. A semiconductor device comprising: a lower pattern extending in the first direction and including an upper surface and a lower surface, wherein the upper surface and the lower surface are opposite to each other in the second direction; a trench separation structure extending in a first direction and contacting the lower pattern; a channel pattern, on an upper surface of the lower pattern, the channel pattern comprising a plurality of sheet-like patterns spaced apart from each other in a second direction, wherein the plurality of sheet-like patterns are in contact with the channel separation structure; a first source / drain pattern on the lower pattern and in contact with the channel pattern; a second source / drain pattern on the lower pattern, wherein the second source / drain pattern contacts the channel pattern and the channel separation structure and is spaced apart from the first source / drain pattern in the first direction; a gate structure between the first source / drain pattern and the second source / drain pattern, wherein the gate structure is on the lower pattern and in contact with the channel separation structure; a contact barrier pattern on the first source / drain pattern, wherein the contact barrier pattern is formed of an insulating material, and wherein the contact barrier pattern includes an upper surface that is in the same plane as an upper surface of the channel separation structure; a source / drain contact on and connected to the second source / drain pattern, the source / drain contact including an upper surface in the same plane as an upper surface of the contact barrier pattern; a backside source / drain contact within the lower pattern and connected to the first source / drain pattern; and A backside wiring is on a lower surface of the lower pattern, wherein the backside wiring is connected to the backside source / drain contacts.

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