Integrated circuit device and manufacturing method thereof

Abstract

The inventive concept relates to an integrated circuit device and a method of manufacturing the same. The integrated circuit device includes: a fin-type active region extending in a first horizontal direction on a substrate; a gate line disposed on the fin-type active region on the substrate and extending in a second horizontal direction intersecting the first horizontal direction; a source / drain region disposed on the fin-type active region and disposed adjacent to the gate line in a first horizontal direction; a source / drain contact disposed on the source / drain region; an upper insulating structure disposed on the gate line and including an etch stop film and an interlayer insulating film; a source / drain via contact passing through the upper insulating structure and connected to the source / drain contact; and an air gap disposed between the etch stop film and the source / drain via contact and overlapping a portion of the source / drain via contact in a horizontal direction.

Description

Technical Field

[0001] The inventive concept relates to integrated circuit devices and methods of manufacturing the same. Background Art

[0002] The development of the electronics industry has led to high capacity and high integration of integrated circuit devices. As the capacity and integration of integrated circuit devices increase, it is necessary to ensure the reliability of integrated circuit devices. Summary of the invention

[0003] The inventive concepts provide an integrated circuit device having improved functional characteristics and electrical reliability and a method of manufacturing the same.

[0004] According to one aspect of the inventive concept, an integrated circuit device is provided, which includes: a fin-type active region extending in a first horizontal direction on a substrate; a gate line arranged on the fin-type active region on the substrate and extending in a second horizontal direction intersecting the first horizontal direction; a source / drain region arranged on the fin-type active region and adjacent to the gate line in the first horizontal direction; a source / drain contact arranged on the source / drain region; an upper insulating structure arranged on the gate line and including an etch stop film and an interlayer insulating film; a source / drain path contact passing through the upper insulating structure and connected to the source / drain contact; and an air gap arranged between the etch stop film and the source / drain path contact and overlapping with a portion of the source / drain path contact in the horizontal direction.

[0005] According to another aspect of the inventive concept, a method for manufacturing an integrated circuit device is provided, the method comprising: forming a source / drain region on a substrate and a source / drain contact on the source / drain region; forming an upper insulating structure on the source / drain contact, the upper insulating structure comprising an etch stop film and an interlayer insulating film disposed on the etch stop film; forming a through hole in the interlayer insulating film; forming a horizontal recess in the etch stop film; forming a recessed portion in a portion of the source / drain contact; and forming a source / drain path contact in the recessed portion, in a portion of the horizontal recess, and in the through hole.

[0006] According to one aspect of the inventive concept, an integrated circuit device is provided, comprising: a fin-type active region extending in a first horizontal direction on a substrate; a nanosheet stack facing a fin top surface at a position spaced apart from a fin top surface of the fin-type active region in a vertical direction and comprising at least one nanosheet; a gate line surrounding the at least one nanosheet on the fin-type active region and extending in a second horizontal direction intersecting the first horizontal direction; a source / drain region disposed on the fin-type active region and adjacent to the gate line in the first horizontal direction; a source / drain contact disposed on the source / drain region; a gate dielectric film contacting a bottom surface and a sidewall of the gate line; a pair of insulating spacers disposed on the side of the gate line; The gate line is disposed on the wall and is separated from the gate line in a first horizontal direction and a gate dielectric film is disposed therebetween; a cover insulating pattern is disposed on the top surface of the gate line and the top surface of the gate dielectric film and between the pair of insulating spacers; an upper insulating structure is disposed on the cover insulating pattern and the gate line and includes an etch stop film and an interlayer insulating film; and a source / drain path contact passes through the upper insulating structure and is connected to the source / drain contact, wherein the source / drain path contact includes: an upper region passing through the interlayer insulating film; and a lower region disposed at a lower end portion of the upper region and passing through the etch stop film, wherein the etch stop film includes an air gap surrounding the lower region in the horizontal direction and overlapping with the lower region in the horizontal direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The embodiments will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a view showing a plan layout of a unit block of an integrated circuit device according to an embodiment;

[0009] Figure 2 is a plan layout diagram for describing an integrated circuit device according to an embodiment;

[0010] Figure 3 is along Figure 2 A cross-sectional view taken along the line X1-X1';

[0011] Figure 4 It is shown Figure 3 an enlarged cross-sectional view of a portion “EX1”;

[0012] Figure 5 is along Figure 2 A cross-sectional view taken along line Y1-Y1';

[0013] Figure 6 For along Figure 2 A cross-sectional view taken along line Y2-Y2'; and

[0014] Figures 7 to 19 According to the implementation method Figure 2 The cross-sectional views taken along the line X1 - X1 ′ shown in the process sequence are used to describe a method of manufacturing an integrated circuit device. DETAILED DESCRIPTION

[0015] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. The same components in the drawings are denoted by the same reference numerals, and repeated description thereof may be omitted.

[0016] The present disclosure allows for various changes and many embodiments, and specific embodiments will be shown in the drawings and described in detail in the written description. However, this is not intended to limit the embodiments to a specific mode of practice, and it will be understood that all changes, equivalents, and substitutes that do not depart from the spirit and technical scope of the inventive concept are included in the present disclosure. In the present disclosure, when certain detailed descriptions obscure the essence of the inventive concept, they may be omitted.

[0017] Figure 1 is a view showing a plan layout of a unit block of an integrated circuit device according to an embodiment.

[0018] refer to Figure 1 The cell block 12 of the integrated circuit device 100 may include a plurality of logic cells LC including circuit patterns forming various circuits. The plurality of logic cells LC may be arranged in a matrix along a first horizontal direction (X direction) and a second horizontal direction (Y direction) in the cell block 12 .

[0019] The plurality of logic cells LC may have a function of performing various logic functions. The plurality of logic cells LC may include a circuit pattern having a layout designed according to a Placement and Routing (PnR) method to perform at least one logic function. In an embodiment, the plurality of logic cells LC may include a plurality of standard cells. In an embodiment, at least some of the plurality of logic cells LC may perform the same logic function. In some embodiments, at least some of the plurality of logic cells LC may perform different logic functions.

[0020] The plurality of logic cells LC may include various types of logic cells, which include a plurality of circuit elements. For example, each of the plurality of logic cells LC may include, but is not limited to, AND, NAND, OR, NOR, XOR, XNOR, inverter (INV), adder (ADD), buffer (BUF), delay (DLY), filter (FIL), multiplexer (MXT / MXIT), OR / AND / inverter (OAI), AND / OR (A / O), AND / OR / inverter (AOI), D flip-flop, reset flip-flop, master-slave flip-flop, latch circuit element, or a combination thereof.

[0021] In the cell block 12, the plurality of logic cells LC may be arranged in a plurality of rows (including rows R1, R2, R3, R4, R5, or R6). The plurality of rows may have the same width along the first horizontal direction (X direction). In addition, at least some of the plurality of logic cells LC may have the same height. However, the inventive concept is not limited to Figure 1 As shown, at least some of the plurality of logic cells LC may have different widths and heights.

[0022] The area of ​​each of the plurality of logic cells LC included in the cell block 12 of the integrated circuit device 100 may be defined by a cell boundary CBD. A cell contact portion CBC may be provided where the cell boundaries CBD meet. The cell contact portion CBC may be provided between two logic cells LC adjacent to each other in the first horizontal direction (X direction) or the second horizontal direction (Y direction) among the plurality of logic cells LC.

[0023] In an embodiment, two logic cells LC adjacent to each other in the first horizontal direction (X direction) and disposed in the row R1, R2, R3, R4, R5, or R6 may contact each other at the cell contact portion CBC without a space therebetween. In some embodiments, two logic cells LC adjacent to each other in the first horizontal direction (X direction) and disposed in the row R1, R2, R3, R4, R5, or R6 may be spaced apart from each other with a distance therebetween.

[0024] In an embodiment, among the plurality of logic cells LC in the row R1, R2, R3, R4, R5, or R6, two logic cells LC adjacent to each other may perform the same function. In this case, the two adjacent logic cells LC may have the same structure. In some embodiments, among the plurality of logic cells LC in one of the rows R1, R2, R3, R4, R5, or R6, two logic cells LC adjacent to each other may perform different functions.

[0025] In an embodiment, a logic cell LC selected from among a plurality of logic cells LC included in the cell block 12 of the integrated circuit device 100 and another logic cell LC adjacent to the selected logic cell LC in the second horizontal direction (Y direction) may be symmetrical to each other, and a cell contact portion CBC is disposed therebetween. For example, a reference logic cell LC_R in the third row R3 and a lower logic cell LC_L in the second row R2 may be symmetrical to each other, and a cell contact portion CBC is disposed therebetween. In addition, a reference logic cell LC_R in the third row R3 and an upper logic cell LC_H in the fourth row R4 may be symmetrical to each other, and a cell contact portion CBC is disposed therebetween.

[0026] Despite Figure 1The cell block 12 includes six rows R1, R2, ..., and R6, but this is only an example. The cell block 12 may include various numbers of rows, and a row may include various numbers of logic cells.

[0027] The cell block 12 of the integrated circuit device 100 may include a plurality of ground lines VSS and a plurality of power lines VDD. One selected from the plurality of ground lines VSS or the plurality of power lines VDD may be arranged between a plurality of rows R1, R2, R3, R4, R5, and R6 of a plurality of logic cells LC arranged along a first horizontal direction (X direction). The plurality of ground lines VSS and the plurality of power lines VDD may extend along the first horizontal direction (X direction) and may be alternately arranged to be spaced apart from each other along a second horizontal direction (Y direction). For example, the plurality of ground lines VSS and the plurality of power lines VDD may be alternately arranged between the plurality of rows R1, R2, R3, R4, R5, and R6 of the plurality of logic cells LC. Therefore, each of the plurality of ground lines VSS and the plurality of power lines VDD may be arranged at the cell boundary CBD of the logic cell LC along the second horizontal direction (Y direction).

[0028] Figure 2 is a plan layout diagram for describing an integrated circuit device according to an embodiment.

[0029] Figure 3 is along Figure 2 A cross-sectional view taken along line X1-X1'.

[0030] Figure 4 It is shown Figure 3 An enlarged cross-sectional view of part “EX1”.

[0031] Figure 5 is along Figure 2 A cross-sectional view taken along line Y1-Y1'.

[0032] Figure 6 is along Figure 2 A cross-sectional view taken along line Y2-Y2'.

[0033] refer to Figures 2 to 6 , an integrated circuit device 100 including a field effect transistor having a gate-all-around structure including an active region having a nanowire or nanosheet structure and a gate surrounding the active region will be described.

[0034] refer to Figures 2 to 6 , the integrated circuit device 100 may include two logic cells LC adjacent to each other in the second horizontal direction (Y direction), and the path power rail VPR is disposed therebetween. In an embodiment, the path power rail VPR may represent Figure 1 The ground line VSS.

[0035] The integrated circuit device 100 may include a substrate 102 having a backside surface 102B and a plurality of fin-type active regions F1 protruding from the substrate 102 (see FIG. Figure 3 ). The plurality of fin type active regions F1 may define a plurality of trench regions T1 in the substrate 102 opposite to the backside surface 102B. The plurality of fin type active regions F1 may extend parallel to each other along a first horizontal direction (X direction) on the substrate 102, and the plurality of fin type active regions F1 may be arranged in a second horizontal direction (Y direction).

[0036] The substrate 102 may include a semiconductor such as Si or Ge or may include a compound semiconductor such as SiGe, SiC, GaAs, InAs, InGaAs, or InP. The terms "SiGe", "SiC", "GaAs", "InAs", "InGaAs", and "InP" used herein each refer to a material including an element included in each term, and may not refer to a chemical formula representing a stoichiometric relationship. The substrate 102 may include a conductive region such as a well doped with an impurity or a structure doped with an impurity.

[0037] The device isolation film 112 may be located in the trench region T1 (see Figure 5 ). The device isolation film 112 may cover at least a portion of a sidewall of each of the plurality of fin type active regions F1 in the plurality of trench regions T1. The device isolation film 112 may be formed of a silicon oxide film, but is not limited thereto.

[0038] The via power rail VPR may extend in the vertical direction (Z direction) between a pair of fin-type active regions F1 selected from among the plurality of fin-type active regions F1 and adjacent to each other and between a pair of source / drain regions 130 disposed on the pair of fin-type active regions F1. The via power rail VPR may pass through the device isolation film 112 in the vertical direction (Z direction). For example, the upper surface of the via power rail VPR may be located at a height higher than the upper surface of the device isolation film 112 in the vertical direction (Z direction).

[0039] The via insulating spacer 190P may be disposed on the sidewall of the via power rail VPR. For example, the sidewall of the via power rail VPR may be surrounded by the via insulating spacer 190P. In some embodiments, the via power rail VPR may include a metal wiring layer and a conductive barrier layer surrounding the metal wiring layer. The metal wiring layer may be formed of Ru, Co, W, or a combination thereof. The conductive barrier layer may be formed of Ti, TiN, Ta, TaN, or a combination thereof. The via insulating spacer 190P may be formed of a material selected from silicon nitride (SiN), silicon carbide (SiOC), silicon oxynitride (SiON), or silicon carbon oxynitride (SiOCN). The terms "SiN", "SiOC", and "SiON" used herein each refer to a material including the elements included in each term, and may not refer to a chemical formula representing a stoichiometric relationship. For example, silicon nitride (SiN) may be Si3N4.

[0040] In an implementation, the substrate 102 may include a backside power structure PWS. The backside power structure PWS may pass through the substrate 102 in a vertical direction (Z direction) at a position overlapping the via power rail VPR in the vertical direction (Z direction). The backside power structure PWS may include a backside power rail BPW and an insulating liner structure ILS covering a sidewall of the backside power rail BPW.

[0041] In an embodiment, each of the via insulating spacer 190P and the insulating liner structure ILS may be formed of silicon nitride (SiN), silicon oxycarbide (SiOC), silicon oxynitride (SiON), silicon carbon oxynitride (SiOCN), or a combination thereof. The terms "SiN", "SiOC", "SiON", "SiOCN", and "SiO" used herein each refer to a material including an element included in each term, and may not refer to a chemical formula representing a stoichiometric relationship. In an embodiment, silicon nitride (SiN) may be Si3N4. Silicon oxide (SiO) may be SiO2.

[0042] In some embodiments, the backside power rail BPW may include a metal wiring layer and a conductive barrier layer surrounding the metal wiring layer. The more detailed configuration of the metal wiring layer and the conductive barrier layer forming the backside power rail BPW may be substantially the same as the configuration described for the metal wiring layer and the conductive barrier layer forming the via power rail VPR.

[0043] The backside power structure PWS may be spaced apart from a pair of source / drain regions 130 disposed on the side of the via power rail VPR, and the device isolation film 112 is disposed therebetween. The backside power structure PWS may be spaced apart from a pair of fin-type active regions F1 on the side of the via power rail VPR, and the substrate 102 is disposed therebetween. Therefore, the backside power rail BPW may be spaced apart from a pair of source / drain regions 130 disposed on the side of the via power rail VPR, and the device isolation film 112 is disposed therebetween. The backside power rail BPW may be spaced apart from a pair of fin-type active regions F1 on the side of the via power rail VPR, and the substrate 102 is disposed therebetween. The insulating liner structure ILS may cover the sidewall of the backside power rail BPW in the second horizontal direction (Y direction). The backside power rail BPW may be spaced apart from a pair of fin-type active regions F1 disposed on the side of the via power rail VPR, and the insulating liner structure ILS and the substrate 102 are disposed therebetween.

[0044] A plurality of gate lines 160 may be disposed on a plurality of fin-type active regions F1 (see Figure 3 ). The plurality of gate lines 160 may extend along a second horizontal direction (Y direction), which may be substantially perpendicular to the first horizontal direction (X direction). The plurality of nanosheet stacks NSS may be disposed on the fin top surface FT of each of the plurality of fin type active regions F1 in an area where the plurality of fin type active regions F1 and the plurality of gate lines 160 intersect each other. Each of the plurality of nanosheet stacks NSS may include at least one nanosheet facing the fin top surface FT at a position spaced apart from the fin top surface FT of the fin type active region F1 in a vertical direction (Z direction). The term "nanosheet" used herein may refer to a conductive structure having a cross section substantially perpendicular to a direction along which current may flow. The nanosheet may include a nanowire.

[0045] The plurality of nanosheet stacks NSS may include a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3 that overlap each other in a vertical direction (Z direction) in each fin type active region F1. The first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may have different vertical distances (Z direction distances) from the fin top surface FT of the fin type active region F1. The plurality of gate lines 160 may surround the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack NSS that overlap in a vertical direction (Z direction).

[0046] Despite Figure 2The nanosheet stack NSS may have a substantially quadrilateral planar shape, but the inventive concept is not limited thereto. The nanosheet stack NSS may have any of various planar shapes according to the planar shape of each of the fin-type active region F1 and the gate line 160. In an example, a plurality of nanosheet stacks NSS and a plurality of gate lines 160 may be disposed on the fin-type active region F1, and the plurality of nanosheet stacks NSS may be arranged along a first horizontal direction (X direction) on the fin-type active region F1. However, the number of nanosheet stacks NSS and the number of gate lines 160 disposed on one fin-type active region F1 are not particularly limited.

[0047] Each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack NSS may be used as a channel region. In an embodiment, each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may have a thickness selected in the range of about 4 nanometers (nm) to about 6 nm, but is not limited thereto. The thickness of each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may refer to a dimension along a vertical direction (Z direction). In an embodiment, the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may have substantially the same thickness along the vertical direction (Z direction). In some embodiments, at least some of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 may have different thicknesses along the vertical direction (Z direction). In an embodiment, each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack NSS may include a Si layer, a SiGe layer, or a combination thereof.

[0048] The first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in one nanosheet stack NSS may have the same size or similar sizes in the first horizontal direction (X direction). In some embodiments, at least some of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in one nanosheet stack NSS may have different sizes in the first horizontal direction (X direction). Figure 3 Each of the plurality of nanosheet stacks NSS includes three nanosheets, but the inventive concept is not limited thereto. For example, the nanosheet stack NSS may include at least one nanosheet, and the number of nanosheets forming the nanosheet stack NSS is not particularly limited.

[0049] Each of the plurality of gate lines 160 may include a main gate portion 160M and a plurality of sub-gate portions 160S. The main gate portion 160M may be disposed on the top surface of the nanosheet stack NSS. For example, the main gate portion 160M may cover the top surface of the nanosheet stack NSS and may extend along the second horizontal direction (Y direction). The plurality of sub-gate portions 160S may be integrally connected to the main gate portion 160M and may each be disposed between the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3, and between the first nanosheet N1 and the fin-type active region F1. In the vertical direction (Z direction), the thickness of each of the plurality of sub-gate portions 160S may be less than the thickness of the main gate portion 160M.

[0050] A plurality of recesses R1 may be provided in the fin-type active region F1. The vertical level of the lowest surface of each of the plurality of recesses R1 may be lower than the vertical level of the fin top surface FT of the fin-type active region F1. The term "vertical level" used herein may refer to a distance from the backside surface 102B of the substrate 102 along a vertical direction (Z direction or -Z direction). Here, the -Z direction may be a direction opposite to the Z direction.

[0051] A plurality of source / drain regions 130 may be disposed in the plurality of recesses R1. Each of the plurality of source / drain regions 130 may be disposed at a position adjacent to at least one gate line 160 selected from among the plurality of gate lines 160. Each of the plurality of source / drain regions 130 may have a surface facing the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the adjacent nanosheet stack NSS (see FIG. Figure 2 ). Each of the plurality of source / drain regions 130 may contact the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the adjacent nanosheet stack NSS.

[0052] Each of the plurality of gate lines 160 may be formed of a metal, a metal nitride, a metal carbide, or a combination thereof. The metal may be selected from Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. The metal nitride may be selected from TiN or TaN. The metal carbide may be TiAlC. However, examples of materials for the plurality of gate lines 160 are not limited thereto.

[0053] The gate dielectric film 152 may be disposed between the nanosheet stack NSS and the gate line 160. In an embodiment, the gate dielectric film 152 may have a structure in which an interface dielectric film and a high-k dielectric film are stacked. The interface dielectric film may be formed of a low-k dielectric material film (e.g., a silicon oxide film, a silicon oxynitride film, or a combination thereof) having a dielectric constant of about 9 or less. In some embodiments, the interface dielectric film may be omitted. The high-k dielectric film may be formed of a material having a higher dielectric constant than the silicon oxide film. For example, the high-k dielectric film may have a dielectric constant of about 10 to 25. The high-k dielectric film may be formed of hafnium oxide, but is not limited thereto.

[0054] The cover insulating pattern 168 may be disposed on the top surface of each of the gate dielectric film 152 and the gate line 160. For example, the top surface of each of the gate dielectric film 152 and the gate line 160 may be covered by the cover insulating pattern 168. The cover insulating pattern 168 may be formed of a silicon nitride film. An outer insulating spacer 118 may be disposed on the sidewall of each of the gate line 160 and the cover insulating pattern 168. For example, the sidewall of each of the gate line 160 and the cover insulating pattern 168 may be covered by the outer insulating spacer 118. The outer insulating spacer 118 may cover the sidewall of the main gate portion 160M on the top surface of each of the plurality of nanosheet stacks NSS. The outer insulating spacer 118 may be spaced apart from the gate line 160, and the gate dielectric film 152 is disposed therebetween.

[0055] A plurality of recessed side insulating spacers 119 disposed on sidewalls of the source / drain regions 130 may be disposed on a top surface of the device isolation film 112. In some embodiments, each of the plurality of recessed side insulating spacers 119 may be integrally connected to an outer insulating spacer 118 disposed adjacent thereto.

[0056] Each of the plurality of outer insulating spacers 118 and the plurality of recessed side insulating spacers 119 may be formed of silicon nitride, silicon oxide, SiCN, SiBN, SiON, SiOCN, SiBCN, SiOC, or a combination thereof. The terms "SiCN", "SiBN", "SiON", "SiOCN", "SiBCN", and "SiOC" used herein each refer to a material including an element included in each term, and may not refer to a chemical formula representing a stoichiometric relationship.

[0057] The metal silicide film 172 may be disposed on the top surface of each of the plurality of source / drain regions 130. The metal silicide film 172 may include a metal formed of Ti, W, Ru, Nb, Mo, Hf, Ni, Co, Pt, Yb, Tb, Dy, Er, or Pd. For example, the metal silicide film 172 may be formed of titanium silicide, but is not limited thereto.

[0058] The insulating liner 142 may be disposed on the plurality of source / drain regions 130, the plurality of metal silicide films 172, and the plurality of outer insulating spacers 118. On the substrate 102, the plurality of source / drain regions 130, the plurality of metal silicide films 172, and the plurality of outer insulating spacers 118 may be covered by the insulating liner 142. In some embodiments, the insulating liner 142 may be omitted. The inter-gate insulating film 144 may be disposed on the insulating liner 142. When the insulating liner 142 is omitted, the inter-gate insulating film 144 may contact the plurality of source / drain regions 130. In an embodiment, the insulating liner 142 may be formed of silicon nitride, SiCN, SiBN, SiON, SiOCN, SiBCN, or a combination thereof, but is not limited thereto. The inter-gate insulating film 144 may be formed of a silicon oxide film, but is not limited thereto.

[0059] A sidewall of each of the plurality of sub-gate portions 160S included in the plurality of gate lines 160 may be spaced apart from the source / drain region 130, and a gate dielectric film 152 is disposed therebetween. The gate dielectric film 152 may be disposed between the sub-gate portion 160S included in the gate line 160 and each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3, and between the sub-gate portion 160S included in the gate line 160 and the source / drain region 130.

[0060] A plurality of nanosheet stacks NSS may be disposed on the fin top surface FT of each of the plurality of fin active regions F1 in an area where the plurality of fin active regions F1 and the plurality of gate lines 160 intersect each other, and may face the fin top surface of the fin active region F1 at a position spaced apart from the fin active region F1. On the substrate 102, a plurality of nanosheet transistors may be disposed on portions where the plurality of fin active regions F1 and the plurality of gate lines 160 intersect each other.

[0061] A plurality of source / drain contacts CA may be disposed on the plurality of source / drain regions 130. Each of the plurality of source / drain contacts CA may pass through the inter-gate insulating film 144 and the insulating liner 142 in the vertical direction (Z direction), and may contact the metal silicide film 172. Each of the plurality of source / drain contacts CA may be configured to be electrically connected to the source / drain region 130 through the metal silicide film 172. Each of the plurality of source / drain contacts CA may be spaced apart from the main gate portion 160M in the first horizontal direction (X direction), and an outer insulating spacer 118 may be disposed therebetween.

[0062] The plurality of source / drain contacts CA may include a conductive barrier pattern 174 and a contact plug 176 sequentially stacked on the source / drain region 130. The conductive barrier pattern 174 may be disposed on the bottom surface and the sidewall of the contact plug 176. For example, the conductive barrier pattern 174 may surround and contact the bottom surface and the sidewall of the contact plug 176. Each of the plurality of source / drain contacts CA may pass through the inter-gate insulating film 144 and the insulating liner 142, and may extend in the vertical direction (Z direction). The conductive barrier pattern 174 may be located between the metal silicide film 172 and the contact plug 176. The conductive barrier pattern 174 may have a surface contacting the metal silicide film 172 and a surface contacting the contact plug 176.

[0063] In some embodiments, the conductive barrier pattern 174 may be formed of a metal or a metal nitride. For example, the conductive barrier pattern 174 may be formed of Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof, but is not limited thereto. The contact plug 176 may be formed of molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), or aluminum (Al), a combination thereof, or an alloy thereof, but is not limited thereto.

[0064] The source / drain contacts CA adjacent to the pass power rail VPR among the plurality of source / drain contacts CA may be spaced apart from the pass power rail VPR in the second horizontal direction (Y direction) (see Figure 2 ).

[0065] The upper insulating structure 180 may be disposed on a top surface of each of the plurality of source / drain contacts CA, the plurality of cap insulating patterns 168, and the inter-gate insulating film 144. For example, a top surface of each of the plurality of source / drain contacts CA, the plurality of cap insulating patterns 168, and the inter-gate insulating film 144 may be covered by the upper insulating structure 180. The upper insulating structure 180 may include an etch stop film 182 and an interlayer insulating film 184 sequentially stacked on each of the plurality of source / drain contacts CA, the plurality of cap insulating patterns 168, and the inter-gate insulating film 144.

[0066] In some embodiments, the etch stop film 182 may be formed of silicon carbide (SiC), SiN, nitrogen-doped silicon carbide (SiC:N), SiOC, AlN, AlON, AlO, AlOC, or a combination thereof. The interlayer insulating film 184 may be formed of an oxide film, a nitride film, an ultra-low k (ULK) film having an ultra-low dielectric constant K of about 2.2 to about 2.4, or a combination thereof. For example, the interlayer insulating film 184 may be formed of a tetraethyl orthosilicate (TEOS) film, a high-density plasma (HDP) oxide film, a borophosphosilicate glass (BPSG) film, a flowable chemical vapor deposition (FCVD) oxide film, a SiON film, a SiN film, a SiOC film, a SiCOH film, or a combination thereof.

[0067] A plurality of source / drain via contacts VA may be disposed on the plurality of source / drain contacts CA. Each of the plurality of source / drain via contacts VA may pass through the upper insulating structure 180 to contact the source / drain contact CA. Each of the plurality of source / drain regions 130 may be configured to be electrically connected to the source / drain via contact VA through the metal silicide film 172 and the source / drain contact CA. The bottom surface of each of the plurality of source / drain via contacts VA may contact the top surface of the source / drain contact CA.

[0068] In some embodiments, each of the plurality of source / drain via contacts VA may include an upper region 121 and a lower region 123 (see Figure 4 ). The upper region 121 of the source / drain via contact VA may pass through the interlayer insulating film 184. The upper region 121 may pass through the interlayer insulating film 184, and a sidewall of the upper region 121 may contact the interlayer insulating film 184. The lower region 123 may be located at a lower end portion of the upper region 121. The lower region 123 may pass through the etch stop film 182.

[0069] In an embodiment, the integrated circuit device 100 may include an air gap AG. For example, the etch stop film 182 may be formed to include a plurality of openings. The openings in the etch stop film 182 may expose the upper surfaces of the outer insulating spacer 118, the insulating liner 142, and the inter-gate insulating film 144. A plurality of source / drain via contacts VA may be disposed in the openings. The width of the source / drain via contact VA in the first horizontal direction (X direction) may be smaller than the width of the opening in the etch stop film 182. The space between the sidewalls of the etch stop film 182 and the plurality of source / drain via contacts VA may form a plurality of air gaps AG. The plurality of air gaps AG may be disposed between the plurality of source / drain via contacts VA and the etch stop film 182. The plurality of air gaps AG may overlap with the lower region 123 of the source / drain via contact VA in the horizontal direction. In this case, the height of the air gap AG may be substantially the same as the height of the etch stop film 182. For example, the vertical level of the top surface of the air gap AG may be substantially the same as the vertical level of the top surface of the etch stop film 182. In addition, the vertical level of the bottom surface of the air gap AG may be substantially the same as the vertical level of the bottom surface of the etch stop film 182. For example, the top surface of the air gap AG and the top surface of the etch stop film 182 may be collinear. In addition, for example, the bottom surface of the air gap AG and the bottom surface of the etch stop film 182 may be collinear.

[0070] In an embodiment, each of the plurality of lower regions 123 may have a shape having a width that decreases as the vertical level increases. For example, the horizontal width of the lower region 123 may decrease toward the upper region 121. However, the shape of the lower region 123 is not limited thereto, and the shape of the lower region 123 may be variously formed.

[0071] In some embodiments, the air gap AG may surround the lower region 123 of the source / drain via contact VA in the horizontal direction. Therefore, the shape of the air gap AG may correspond to the shape of the lower region 123. In an embodiment, the air gap AG may have an inverted trapezoidal shape in which the upper surface is longer than the lower surface. For example, the horizontal width of the top surface of the air gap AG may be greater than the horizontal width of the bottom surface of the air gap AG.

[0072] In some embodiments, a plurality of source / drain via contacts VA may include a plurality of protrusions 123a, respectively. A plurality of protrusions 123a may each be disposed at the lower end portion of the lower region 123. A plurality of protrusions 123a may protrude toward a plurality of source / drain contacts CA. For example, the upper portions of the conductive barrier pattern 174 and the contact plug 176 may form a concave shape in the source / drain contacts of the plurality of source / drain contacts CA. The protrusions in the plurality of protrusions 123a may be disposed in a convex shape so that the plurality of protrusions 123a may protrude toward the plurality of source / drain contacts CA. The plurality of protrusions 123a may include a curved surface protruding toward the plurality of source / drain contacts CA.

[0073] In some embodiments, the plurality of source / drain contacts CA may include a plurality of recessed portions R2. The recessed portions R2 may be recessed toward the source / drain region 130. Therefore, the vertical level of the top surface of the conductive barrier pattern 174 may be equal to or higher than the vertical level of the top surface of the contact plug 176. In the process of forming the recessed portions R2, upper portions of the conductive barrier pattern 174 and the contact plug 176 may be removed. The top surface of the recessed portion R2 may include a concave curved surface. The recessed portion R2 may contact the protrusion 123a (see FIG. 1 ) of the source / drain via contact VA. Figure 4 ).

[0074] In an implementation, a plurality of air gaps AG may be formed between the plurality of source / drain via contacts VA and the etch stop film 182 , and a capacitance value of the integrated circuit device 100 may be reduced.

[0075] In addition, a plurality of air gaps AG may be formed between the plurality of source / drain via contacts VA and the etch stop film 182, and the function of the integrated circuit device 100 may be improved. In detail, the capacitance and resistance of the integrated circuit device may be reduced by the air gaps AG surrounding the source / drain via contacts VA, and the RC delay of the integrated circuit device 100 may be reduced.

[0076] The air gap AG may be filled with, for example, a vacuum, a gas, or a gas mixture. For example, the air gap AG may include a gas mixture other than air.

[0077] Furthermore, during the formation of the protrusion 123 a , the conductive barrier pattern 174 formed of a high resistance material may be removed, and the protrusion 123 a having a relatively low resistance may fill the location of the conductive barrier pattern 174 , and the resistance of the integrated circuit device 100 may be reduced.

[0078] In some embodiments, the upper region 121, the lower region 123, and the protrusion 123a of the source / drain via contact VA may include the same material. For example, each of the upper region 121, the lower region 123, and the protrusion 123a may include a contact plug formed of molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), a combination thereof, or an alloy thereof (but not limited thereto). In some embodiments, the plurality of source / drain via contacts VA may further include a conductive barrier pattern surrounding a portion of the contact plug. The conductive barrier pattern included in the plurality of source / drain via contacts VA may be formed of a metal or a metal nitride. For example, the conductive barrier pattern may be formed of Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof (but not limited thereto).

[0079] In an embodiment, the upper region 121, the lower region 123, and the protrusion 123a may be formed integrally. The source / drain via contact VA including the upper region 121, the lower region 123, and the protrusion 123a may have an anchor shape, but is not limited thereto. In the case where the source / drain via contact VA has an anchor shape, structural stability may be improved. For example, the source / drain via contact VA including the upper region 121 and the lower region 123 may have a convergent / divergent shape in the vertical direction (Z direction), and the reduced width is provided at the portion where the upper region 121 and the lower region 123 meet. The shape of the source / drain via contact VA may improve the structural stability of the integrated circuit device 100.

[0080] The gate contact CB may be disposed on the gate line 160. The gate contact CB may pass through the upper insulating structure 180 and the capping insulating pattern 168 in the vertical direction (Z direction) and may be connected to the gate line 160. A bottom surface of the gate contact CB may contact a top surface of the gate line 160.

[0081] In some embodiments, the gate contact CB may include a contact plug formed of molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), a combination thereof, or an alloy thereof (but not limited thereto). In an embodiment, the gate contact CB may further include a conductive barrier pattern surrounding a portion of the contact plug. The conductive barrier pattern included in the gate contact CB may be formed of a metal or a metal nitride. For example, the conductive barrier pattern may be formed of Ti, Ta, W, TiN, TaN, WN, WCN, TiSiN, TaSiN, WSiN, or a combination thereof (but not limited thereto).

[0082] The via power rail VPR and the via insulating spacer 190P may pass through the upper insulating structure 180, the cap insulating pattern 168, the gate line 160, the inter-gate insulating film 144, the insulating liner 142, and the device isolation film 112 in the vertical direction (Z direction). The portion of the gate line 160 through which the via power rail VPR and the via insulating spacer 190P pass in the vertical direction (Z direction) may be a portion disposed between a pair of adjacent nanosheet stacks NSS among a plurality of nanosheet stacks NSS. The via power rail VPR may be spaced apart from the gate line 160 in the horizontal direction (e.g., the second horizontal direction (Y direction)), and the via insulating spacer 190P is disposed between the via power rail VPR and the gate line 160. The via power rail VPR and the via insulating spacer 190P may be spaced apart from the source / drain region 130 in the horizontal direction (e.g., the second horizontal direction (Y direction)).

[0083] A backside power structure PWS including a backside power rail BPW and an insulating liner structure ILS may be located at a position overlapping the gate line 160 in a vertical direction (Z direction). The backside power structure PWS may be spaced apart from the plurality of nanosheet stacks NSS with a device isolation film 112 disposed therebetween.

[0084] A top surface of each of the upper insulating structure 180, the plurality of source / drain via contacts VA, and the gate contact CB may be covered by an upper insulating film 192. A constituent material of the upper insulating film 192 is substantially the same as a constituent material of the above-described interlayer insulating film 184.

[0085] The plurality of upper wiring layers M1 may pass through the upper insulating film 192. Each of the plurality of upper wiring layers M1 may be connected to one source / drain via contact VA selected from among the plurality of source / drain via contacts VA, or to one gate contact CB selected from among the plurality of gate contacts CB located below the plurality of upper wiring layers M1. Each of the plurality of upper wiring layers M1 may be formed of molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), a combination thereof, or an alloy thereof (but not limited thereto).

[0086] The plurality of upper wiring layers M1 may include a power connection conductive layer PCL connected to the via power rail VPR on the via power rail VPR. One source / drain via contact VA selected from among the plurality of source / drain via contacts VA may be connected between the source / drain contact CA and the power connection conductive layer PCL at a position spaced apart from the via power rail VPR along the second horizontal direction (Y direction). A source / drain region 130 connected to the via power rail VPR among the plurality of source / drain regions 130 may be electrically connected to the via power rail VPR through the source / drain contact CA, the source / drain via contact VA, and the power connection conductive layer PCL.

[0087] The front wiring structure FWS may be disposed on a plurality of upper wiring layers M1 and an upper insulating film 192. The front wiring structure FWS may include a plurality of wiring layers MN1, a plurality of via contacts CT1, and an interlayer insulating film 194 covering the plurality of wiring layers MN1 and the plurality of via contacts CT1. The via power rail VPR may be connected to one wiring layer MN1 selected from the plurality of wiring layers MN1 through the upper wiring layer M1 and the via contact CT1. The constituent materials of the plurality of wiring layers MN1 and the plurality of via contacts CT1 are substantially the same as the constituent materials of the plurality of upper wiring layers M1 described above. The constituent materials of the interlayer insulating film 194 are substantially the same as the constituent materials of the interlayer insulating film 184 described above.

[0088] The backside surface 102B of the substrate 102 and the backside power rail BPW may be covered by a backside wiring structure (not shown). The backside wiring structure may have substantially the same configuration as described for the frontside wiring structure FWS. However, the backside wiring structure may include a wiring layer connected to the backside power rail BPW.

[0089] A method of manufacturing an integrated circuit device according to an embodiment will now be described.

[0090] Figures 7 to 19 According to the implementation method Figure 2 The cross-sectional views taken along the line X1 - X1 ′ shown in the process sequence are used to describe a method of manufacturing an integrated circuit device.

[0091] refer to Figures 7 to 19 , describes the manufacturing Figures 2 to 6 The method of the integrated circuit device 100. Figures 7 to 19 In, with Figures 2 to 6 The same components are denoted by the same reference numerals, and their detailed description may be omitted.

[0092] refer to Figure 7 , a substrate 102 may be prepared, and a plurality of sacrificial semiconductor layers 104 and a plurality of nanosheet semiconductor layers NS may be alternately stacked on a front side surface of the substrate 102 .

[0093] The plurality of sacrificial semiconductor layers 104 and the plurality of nanosheet semiconductor layers NS may be formed of semiconductor materials having different etching selectivities. In an embodiment, the plurality of nanosheet semiconductor layers NS may be formed of a Si layer, and the plurality of sacrificial semiconductor layers 104 may be formed of a SiGe layer. In an embodiment, the Ge content in the plurality of sacrificial semiconductor layers 104 may be constant. The SiGe layer forming the plurality of sacrificial semiconductor layers 104 may have a constant Ge content selected in the range of about 5 atomic % to about 60 atomic %, for example, about 10 atomic % to about 40 atomic %. The Ge content in the SiGe layer forming the plurality of sacrificial semiconductor layers 104 may be selected in various ways as desired.

[0094] refer to Figure 8 , can be etched Figure 7 The plurality of sacrificial semiconductor layers 104, the plurality of nanosheet semiconductor layers NS, and the portion of the substrate 102 in the resulting structure are used to form a plurality of fin-type active regions F1 protruding from the substrate 102, and a device isolation film 112 covering the sidewall of each of the plurality of fin-type active regions F1 may be formed (see Figure 5 ). A stack structure of the plurality of sacrificial semiconductor layers 104 and the plurality of nanosheet semiconductor layers NS may remain on the fin top surface FT of each of the plurality of fin type active regions F1.

[0095] A plurality of dummy gate structures DGS may be formed on the stacked structure of the plurality of sacrificial semiconductor layers 104 and the plurality of nanosheet semiconductor layers NS. Each of the plurality of dummy gate structures DGS may extend along the second horizontal direction (Y direction). Each of the plurality of dummy gate structures DGS may have a structure in which an oxide film D122, a dummy gate layer D124, and a cap layer D126 are sequentially stacked. In an embodiment, the oxide film D122 may be formed by oxidizing the plurality of sacrificial semiconductor layers 104 and the plurality of nanosheet semiconductor layers NS (see Figure 7 ) is obtained by forming the surface of each of the dummy gate layer D124. The dummy gate layer D124 may be formed of polysilicon, and the cap layer D126 may be formed of a silicon nitride film.

[0096] After forming a plurality of outer insulating spacers 118 covering sidewalls of the plurality of dummy gate structures DGS, a plurality of recesses R1 may be formed on the fin type active region F1 by etching a portion of the plurality of sacrificial semiconductor layers 104 and the plurality of nanosheet semiconductor layers NS and a portion of the fin type active region F1 and dividing the plurality of nanosheet semiconductor layers NS into a plurality of nanosheet stacks NSS each including a first nanosheet N1, a second nanosheet N2, and a third nanosheet N3 by using the plurality of dummy gate structures DGS and the plurality of outer insulating spacers 118 as etching masks. In order to form the plurality of recesses R1, etching may be performed by using dry etching, wet etching, or a combination thereof.

[0097] refer to Fig. 9 , you can Figure 8 A plurality of source / drain regions 130 filling the plurality of recesses R1 are formed in the resulting structure. To form the plurality of source / drain regions 130, a semiconductor material may be epitaxially grown from a surface of the fin-type active region F1 exposed by the bottom surface of the plurality of recesses R1 and a sidewall of each of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 included in the nanosheet stack NSS.

[0098] An insulating liner 142 may be formed, an inter-gate insulating film 144 may be formed on the insulating liner 142, and then the top surface of the plurality of capping layers D126 may be exposed by etching a portion of each of the insulating liner 142 and the inter-gate insulating film 144. The dummy gate layer D124 may be exposed by removing the plurality of capping layers D126, and the insulating liner 142 and the inter-gate insulating film 144 may be partially removed so that the top surface of the inter-gate insulating film 144 and the top surface of the dummy gate layer D124 are at substantially the same level.

[0099] refer to Fig.10 , can be obtained by Fig. 9The resulting structure removes the dummy gate layer D124 and the oxide film D122 under the dummy gate layer D124 to provide a gate space GS, and the multiple nanosheet stacks NSS can be exposed through the gate space GS. By removing the multiple sacrificial semiconductor layers 104 remaining on the fin-type active region F1 through the gate space GS, the gate space GS can extend to the space between the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 and the space between the first nanosheet N1 and the fin top surface FT. In an embodiment, in order to selectively remove the multiple sacrificial semiconductor layers 104, the etching selectivity difference between the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 and the multiple sacrificial semiconductor layers 104 can be utilized.

[0100] In order to selectively remove the plurality of sacrificial semiconductor layers 104, a liquid or gaseous etchant may be used. In an embodiment, in order to selectively remove the plurality of sacrificial semiconductor layers 104, a CH3COOH-based etchant, such as an etchant including a mixture of CH3COOH, HNO3, and HF, or an etchant including a mixture of CH3COOH, H2O2, and HF may be used, but the inventive concept is not limited thereto.

[0101] refer to Fig.11 , you can Fig.10 A gate dielectric film 152 is formed in the resulting structure, covering the exposed surfaces of the first nanosheet N1, the second nanosheet N2, and the third nanosheet N3 and the fin-type active region F1. The gate dielectric film 152 may be formed using an ALD process.

[0102] refer to Fig.12 , a gate space GS may be formed on the gate dielectric film 152 to fill the gate space GS (see Fig.11 ) and covers the gate line 160 of the top surface of the gate inter-insulating film 144, and the cap insulating pattern 168 covering the top surface of each of the gate line 160 and the gate dielectric film 152 in the gate space GS.

[0103] refer to Fig.13 A source / drain contact hole is formed through the insulating structure including the insulating liner 142 and the gate insulating film 144 to expose the source / drain region 130. Fig.12After forming the resulting structure, the source / drain contact hole can be extended toward the substrate 102 by removing a portion of the source / drain region 130 through the source / drain contact hole. By using an anisotropic etching process, the source / drain contact hole can be extended toward the substrate 102. The metal silicide film 172 can be formed on the source / drain region 130 exposed at the bottom of the source / drain contact hole. In some embodiments, in order to form the metal silicide film 172, a metal liner (not shown) that conformally covers the exposed surface of the source / drain region 130 can be formed, and a process of inducing a reaction between the source / drain region 130 and the metal of the metal liner by heat treatment can be performed. After forming the metal silicide film 172, the remaining portion of the metal liner can be removed. During the process of forming the metal silicide film 172, a portion of the source / drain region 130 may be consumed. For example, at least a portion of the metal silicide film 172 may contact the lower surface of the insulating liner 142. In some embodiments, when the metal silicide film 172 is formed of a titanium silicide film, the metal liner may be formed of a Ti film. A source / drain contact CA including a conductive barrier pattern 174 and a contact plug 176 may be formed on the metal silicide film 172 .

[0104] refer to Fig.14 , can be achieved by Fig.13 An upper insulating structure 180 is formed by sequentially forming an etching stop film 182 and an interlayer insulating film 184 covering the top surface of each of the inter-gate insulating film 144, the plurality of source / drain contacts CA, and the plurality of cap insulating patterns 168 in the resulting structure. A plurality of through holes VH may be formed by etching the interlayer insulating film 184. In this case, the process of forming the plurality of through holes VH by etching the interlayer insulating film 184 may stop on the etching stop film 182.

[0105] refer to Fig.15 , can be etched Fig.14The horizontal recess RL is formed by a portion of the etching stop film 182 in the resulting structure. The horizontal recess RL may be formed by using wet etching (but not limited thereto). In this case, the vertical level of the top surface of the horizontal recess RL may be the same as the vertical level of the top surface of the etching stop film 182, and the vertical level of the bottom surface of the horizontal recess RL may be the same as the vertical level of the bottom surface of the etching stop film 182. For example, the top surface of the horizontal recess RL and the top surface of the etching stop film 182 may be collinear. In addition, for example, the bottom surface of the horizontal recess RL and the bottom surface of the etching stop film 182 may be collinear. In this case, the horizontal depth of the horizontal recess RL may be a depth that can maintain the structural stability of the integrated circuit device 100. The horizontal depth of the horizontal recess RL may be within the range of the depth that can maintain the structural stability of the integrated circuit device 100. For example, the horizontal depth of the horizontal recess RL may be formed in various ways. The etching of the etching stop film 182 and the formation of the horizontal recess RL may expose the sidewall of the etching stop film 182. The sidewall of the etching stop film 182 may be disposed below the interlayer insulating film 184. The horizontal recess RL may define an opening in the etch stop film 182 .

[0106] refer to Fig.16 , can be etched Fig.15 The plurality of recessed portions R2 are formed by portions of the plurality of source / drain contacts CA in the resulting structure. In order to form the plurality of recessed portions R2, etching may be performed by using dry etching, wet etching, or a combination thereof.

[0107] The plurality of recessed portions R2 may have a concave shape toward the source / drain region 130. The plurality of recessed portions R2 may be formed by etching the upper portions of the conductive barrier pattern 174 and the contact plug 176. Therefore, the vertical level of the top surface of the conductive barrier pattern 174 may be equal to or higher than the vertical level of the top surface of the contact plug 176. The top surface of the recessed portion R2 may include a concave curved surface. In addition, the vertical level of the top surface of the conductive barrier pattern 174 and the vertical level of the top surface of the contact plug 176 may be equal to or lower than the vertical level of the top surface of the cap insulating pattern 168.

[0108] refer to Fig.17 , can be obtained from Fig.16The first preliminary conductive pattern is grown in the vertical direction (Z direction) on the top surface of the recessed portion R2 in the resulting structure. The first preliminary conductive pattern can be formed by using selective growth. Therefore, the first preliminary conductive pattern can grow from the top surface of the recessed portion R2 toward the through hole VH. The first preliminary conductive pattern may include a protrusion 123a disposed in the recessed portion R2, a lower region 123 disposed in a portion of the horizontal recess RL, and a preliminary upper region P121 disposed in the lower portion of the through hole VH. For example, the first preliminary conductive pattern may include a protrusion 123a that may fill the recessed portion R2, a lower region 123 that may fill a portion of the horizontal recess RL, and a preliminary upper region P121 that may fill the lower portion of the through hole VH.

[0109] The preliminary upper region P121 and the lower region 123 of the first preliminary conductive pattern may have an anchor shape. The anchor shape may have a convergence portion corresponding to the preliminary upper region P121 and a divergence portion corresponding to the lower region 123. The convergence / divergence shape may be provided in a vertical direction (Z direction) and may have a reduced width provided at a portion where the preliminary upper region P121 and the lower region 123 meet.

[0110] The air gap AG may be formed in a process of growing the first preliminary conductive pattern. The air gap AG may be formed between the lower region 123 and the etch stop film 182 in a horizontal direction. The air gap AG may surround the lower region 123 in a horizontal direction.

[0111] In an embodiment, a plurality of air gaps AG may be formed between the plurality of source / drain via contacts VA and the etch stop film 182, and the capacitance value of the integrated circuit device 100 may be reduced. For example, the plurality of air gaps AG may be formed between the plurality of source / drain via contacts VA and the sidewall of the etch stop film 182. The volume of the air gaps in the plurality of air gaps AG may be smaller than the volume of the horizontal recess RL.

[0112] In addition, a plurality of air gaps AG may be formed between the plurality of source / drain via contacts VA and the etch stop film 182, and the function of the integrated circuit device 100 may be improved. In detail, the air gaps AG may surround the source / drain via contacts VA, may reduce the capacitance and resistance of the integrated circuit device, and may reduce the RC delay of the integrated circuit device 100.

[0113] Furthermore, in the process of forming the protrusion 123 a , the conductive barrier pattern 174 having a high resistance material may be removed, and the protrusion 123 a having a relatively low resistance may fill the position of the conductive barrier pattern 174 , and the resistance of the integrated circuit device 100 may be reduced.

[0114] The air gap AG may be filled with, for example, a vacuum, a gas, or a gas mixture. For example, the air gap AG may include a gas mixture other than air.

[0115] refer to Fig.18 , you can Fig.17 In the resulting structure, a second preliminary conductive pattern is disposed on the first preliminary conductive pattern. The second preliminary conductive pattern may be deposited on the first preliminary conductive pattern and the interlayer insulating film 184. For example, the second preliminary conductive pattern may be deposited by using chemical vapor deposition (CVD) (but not limited thereto). The second preliminary conductive pattern may include a preliminary upper region P121 filling an upper portion of the through hole VH and covering the interlayer insulating film 184.

[0116] The first preliminary conductive pattern and the second preliminary conductive pattern may be formed of the same material. For example, each of the first preliminary conductive pattern and the second preliminary conductive pattern may include a contact plug formed of molybdenum (Mo), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), titanium (Ti), tantalum (Ta), aluminum (Al), a combination thereof, or an alloy thereof (but not limited thereto).

[0117] refer to Fig.19 , can be achieved by removing Fig.18 The interlayer insulating film 184 and the second preliminary conductive pattern in the resulting structure are used to form the source / drain via contact VA. Fig.18 The source / drain via contact VA is formed by interlayer insulating film 184, portions of the first preliminary conductive pattern, and the second preliminary conductive pattern in the resulting structure. The source / drain via contact VA may be formed by using a chemical mechanical polishing (CMP) process or the like.

[0118] The gate contact CB and the pass supply rail VPR can be referenced Figures 14 to 19 The source / drain via contacts VA are formed simultaneously or sequentially. The order of forming the gate contact CB and the via power rail VPR is not particularly limited, and the structures can be formed in different orders.

[0119] Reference Figures 3 to 6 , an upper insulating film 192 and a plurality of upper wiring layers M1 may be disposed on the upper insulating structure 180. The plurality of upper wiring layers M1 may pass through the upper insulating film 192 and may be connected to the source / drain via contact VA. In addition, a gate contact CB and a via power rail VPR may be formed. The plurality of upper wiring layers M1 may be disposed on the via power rail VPR. The plurality of upper wiring layers M1 may include a power connection conductive layer PCL connected to the via power rail VPR. The front side wiring structure FWS may be disposed on the upper insulating film 192 and the plurality of upper wiring layers M1.

[0120] A portion of the substrate 102 may be removed from the backside surface 102B of the substrate 102. For example, the substrate 102 may be thinned, and the backside surface 102B of the substrate 102 may be disposed closer to the fin type active region F1 in the vertical direction (Z direction). In order to remove a portion of the substrate 102, at least one process selected from a mechanical grinding process, a CMP process, a wet etching process, or a combination thereof may be used.

[0121] The integrated circuit device 100 of the inventive concept may be manufactured by forming a backside power structure PWS including a backside power rail BPW and an insulating liner structure ILS, and forming a backside wiring structure (not shown) on a backside surface 120B of a substrate 102 .

[0122] As described above, the embodiments have been shown in the drawings and described in the specification. Although specific terms have been used to describe the embodiments, this is only for the purpose of illustrating the technical ideas of the inventive concept, and is not intended to limit the meaning and scope of the inventive concept described in the claims. Therefore, it will be understood by those skilled in the art that various modifications and other equivalent embodiments can be made therefrom. Therefore, the technical scope of the inventive concept should be defined by the appended claims.

[0123] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

[0124] This application is based on and claims the priority benefit of Korean Patent Application No. 10-2023-0162732 filed in the Korean Intellectual Property Office on November 21, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An integrated circuit device, comprising: A fin-type active region extending in a first horizontal direction on the substrate; a gate line, disposed on the fin-type active region on the substrate and extending in a second horizontal direction intersecting the first horizontal direction; A source / drain region, disposed on the fin-type active region and adjacent to the gate line in the first horizontal direction; A source / drain contact is disposed on the source / drain region; an upper insulating structure, disposed on the gate line and comprising an etching stop film and an interlayer insulating film; a source / drain via contact passing through the upper insulating structure and connected to the source / drain contact; as well as An air gap is provided between the etching stopper film and the source / drain via contact and overlaps a portion of the source / drain via contact in a horizontal direction.

2. The integrated circuit device according to claim 1, wherein A vertical level of a top surface of the air gap is the same as a vertical level of a top surface of the etch stop film, and A vertical level of a bottom surface of the air gap is the same as a vertical level of a bottom surface of the etch stop film.

3. The integrated circuit device of claim 1 , wherein the source / drain via contacts comprise: an upper region passing through the interlayer insulating film; as well as A lower region is located at a lower end portion of the upper region and passes through the etch stop film. 4 . The integrated circuit device according to claim 3 , wherein the lower region has a shape having a horizontal width that decreases toward the upper region. 5 . The integrated circuit device according to claim 3 , wherein the air gap surrounds the lower region in the horizontal direction. 6 . The integrated circuit device of claim 3 , wherein the source / drain via contact further comprises a protrusion protruding from the lower region toward the source / drain contact. 7 . The integrated circuit device of claim 6 , wherein the source / drain contacts include recessed portions contacting the protrusions.

8. The integrated circuit device according to claim 6, wherein the source / drain contacts include a conductive barrier pattern and a contact plug, wherein a vertical level of a top surface of the conductive barrier pattern is greater than or equal to a vertical level of a top surface of the contact plug.

9. The integrated circuit device of claim 3, wherein the upper region and the lower region are formed of the same material. 10 . The integrated circuit device according to claim 1 , wherein the air gap has an inverted trapezoidal shape in which an upper surface is longer than a lower surface.

11. A method of manufacturing an integrated circuit device, the method comprising: forming a source / drain region on the substrate and a source / drain contact on the source / drain region; forming an upper insulating structure on the source / drain contacts, the upper insulating structure comprising an etch stop film and an interlayer insulating film disposed on the etch stop film; forming a through hole in the interlayer insulating film; forming a horizontal recess in the etch stop film; forming a recessed portion in a portion of the source / drain contact; as well as Source / drain via contacts are formed in the recessed portion, in a portion of the horizontal recess, and in the via.

12. The method according to claim 11, wherein the forming of the horizontal recess comprises forming the horizontal recess so that a vertical level of a top surface of the horizontal recess is the same as a vertical level of a top surface of the etch stop film, and a vertical level of a bottom surface of the horizontal recess is the same as a vertical level of a bottom surface of the etch stop film. 13 . The method of claim 11 , wherein the forming of the recessed portion comprises etching an upper portion of a conductive barrier pattern of the source / drain contacts and an upper portion of a contact plug. 14 . The method according to claim 11 , wherein the forming of the source / drain via contact comprises growing the source / drain via contact in a vertical direction from a top surface of the recessed portion.

15. The method of claim 14, wherein the forming of the source / drain via contacts comprises: growing a first preliminary conductive pattern filling the recessed portion, the portion of the horizontal recess, and a lower portion of the through hole; depositing a second preliminary conductive pattern covering an upper portion of the through hole and the interlayer insulating film on the first preliminary conductive pattern; as well as The source / drain via contact is formed by etching a portion of the interlayer insulating film and a portion of the second preliminary conductive pattern.

16. The method according to claim 11, wherein the forming of the source / drain via contact includes further forming an air gap disposed between the etch stop film and the source / drain via contact in a horizontal direction and overlapping a portion of the source / drain via contact in the horizontal direction.

17. An integrated circuit device comprising: A fin-type active region extending in a first horizontal direction on the substrate; a nanosheet stack facing the fin top surface at a position spaced apart from the fin top surface of the fin-type active region in a vertical direction and comprising at least one nanosheet; a gate line, surrounding the at least one nanosheet on the fin-type active area and extending in a second horizontal direction intersecting the first horizontal direction; A source / drain region, disposed on the fin-type active region and adjacent to the gate line in the first horizontal direction; a source / drain contact disposed on the source / drain region; a gate dielectric film contacting a bottom surface and a sidewall of the gate line; a pair of insulating spacers disposed on the sidewalls of the gate line and spaced apart from the gate line in the first horizontal direction with the gate dielectric film disposed therebetween; a cap insulating pattern disposed on a top surface of the gate line and a top surface of the gate dielectric film and between the pair of insulating spacers; an upper insulating structure disposed on the cap insulating pattern and the gate line and including an etching stop film and an interlayer insulating film; as well as a source / drain via contact passing through the upper insulating structure and connected to the source / drain contact, The source / drain path contacts include: an upper region passing through the interlayer insulating film; as well as a lower region disposed at a lower end portion of the upper region and passing through the etching stop film, The etch stop film includes an air gap surrounding the lower region in a horizontal direction and overlapping the lower region in the horizontal direction. 18 . The integrated circuit device according to claim 17 , wherein the lower region has a shape having a horizontal width that decreases toward the upper region.

19. The integrated circuit device of claim 17, wherein the source / drain via contact further comprises a protrusion protruding from the lower region toward the source / drain contact.

20. The integrated circuit device of claim 19, wherein the source / drain contacts include recessed portions contacting the protrusions.

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