Semiconductor device and manufacturing method thereof, power module, power conversion circuit, and vehicle

Abstract

The embodiment of the invention discloses a semiconductor device, a manufacturing method, a power module, a power conversion circuit and a vehicle. The semiconductor device includes a silicon carbide semiconductor body including a first device region and a second device region; the second device region comprises a first conductive type device region and a second conductive type device region; the silicon carbide semiconductor body comprises an electrode arrangement surface; the mobility of the semiconductor graphene layer is greater than that of silicon carbide at the same preset temperature; the first semiconductor graphene layer is located on the electrode setting surface of the first device region, the second semiconductor graphene layer is located on the electrode setting surface of the first conductive type device region, and the third semiconductor graphene layer is located on the electrode setting surface of the second conductive type device region. According to the technical scheme provided by the invention, the electrical properties of semiconductor devices of the monolithic integrated silicon carbide metal-oxide semiconductor field effect transistor and the silicon carbide complementary metal oxide semiconductor are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Silicon carbide (SiC), known for its wide bandgap, high thermal conductivity and high electric field breakdown strength, has superior performance over silicon in wide temperature range, high power and high switching frequency applications. The development of SiC integrated circuits that integrate control systems and power devices onto a single chip is essential to fully realize the potential of SiC in applications where system efficiency and power density are critical.

[0003] One of the main challenges of lateral complementary metal oxide semiconductor (CMOS) integration is the low channel mobility of NMOS and PMOS devices, as well as the mobility difference between p-type and n-type carriers. These technical problems seriously hinder the great potential of SiC in improving system power efficiency and switching performance. In addition, the operating voltages of silicon carbide metal-oxide semiconductor field effect transistors (SiC MOSFETs) and silicon carbide complementary metal oxide semiconductors (SiC CMOS) are different, and their electrical performance is poor after monolithic integration. Summary of the invention

[0004] The present invention provides a semiconductor device and a manufacturing method, a power module, a power conversion circuit and a vehicle to improve the electrical performance of monolithically integrated silicon carbide metal-oxide semiconductor field effect transistors and silicon carbide complementary metal oxide semiconductor semiconductor devices.

[0005] According to one aspect of the present invention, there is provided a semiconductor device, comprising: a silicon carbide semiconductor body, the silicon carbide semiconductor body comprising a first device region and a second device region spaced apart along a first direction, the first direction being perpendicular to a thickness direction of the silicon carbide semiconductor body; the second device region comprising a first conductivity type device region and a second conductivity type device region spaced apart along the first direction; the silicon carbide semiconductor body comprising an electrode setting surface;

[0006] A semiconductor graphene layer, comprising a first semiconductor graphene layer, a second semiconductor graphene layer and a third semiconductor graphene layer, for improving the mobility of the semiconductor device; at the same preset temperature, the mobility of the semiconductor graphene layer is greater than the mobility of silicon carbide; the first semiconductor graphene layer is located on the electrode setting surface of the first device region, the second semiconductor graphene layer is located on the electrode setting surface of the first conductive type device region, and the third semiconductor graphene layer is located on the electrode setting surface of the second conductive type device region;

[0007] In the semiconductor device, the portion located in the first device region is a silicon carbide metal-oxide semiconductor field effect transistor whose conduction current direction is the first direction, and the portion located in the second device region is a silicon carbide complementary metal oxide semiconductor. The silicon carbide complementary metal oxide semiconductor includes a first conductivity type silicon carbide metal-oxide semiconductor field effect transistor located in the first conductivity type device region and whose conduction current direction is the first direction, and a second conductivity type silicon carbide metal-oxide semiconductor field effect transistor located in the second conductivity type device region and whose conduction current direction is the first direction. The silicon carbide metal-oxide semiconductor field effect transistor and the silicon carbide complementary metal oxide semiconductor have different operating voltages.

[0008] According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising:

[0009] A silicon carbide semiconductor body is provided, wherein the silicon carbide semiconductor body comprises a first device region and a second device region spaced apart along a first direction, wherein the first direction is perpendicular to a thickness direction of the silicon carbide semiconductor body; the second device region comprises a first conductivity type device region and a second conductivity type device region spaced apart along the first direction; and the silicon carbide semiconductor body comprises an electrode setting surface;

[0010] Forming a first semiconductor graphene layer, a second semiconductor graphene layer and a third semiconductor graphene layer located on the electrode setting surface in the semiconductor graphene layer, so as to improve the mobility of the semiconductor device, wherein at the same preset temperature, the mobility of the semiconductor graphene layer is greater than the mobility of silicon carbide; the first semiconductor graphene layer is located on the electrode setting surface of the first device region, the second semiconductor graphene layer is located on the electrode setting surface of the first conductive type device region, and the third semiconductor graphene layer is located on the electrode setting surface of the second conductive type device region;

[0011] In the semiconductor device, the portion located in the first device region is a silicon carbide metal-oxide semiconductor field effect transistor whose conduction current direction is the first direction, and the portion located in the second device region is a silicon carbide complementary metal oxide semiconductor. The silicon carbide complementary metal oxide semiconductor includes a first conductivity type silicon carbide metal-oxide semiconductor field effect transistor located in the first conductivity type device region and whose conduction current direction is the first direction, and a second conductivity type silicon carbide metal-oxide semiconductor field effect transistor located in the second conductivity type device region and whose conduction current direction is the first direction. The silicon carbide metal-oxide semiconductor field effect transistor and the silicon carbide complementary metal oxide semiconductor have different operating voltages.

[0012] According to another aspect of the present invention, a power module is provided, comprising a substrate and any semiconductor device described in the embodiments of the present invention, wherein the substrate is used for carrying the semiconductor device.

[0013] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0014] The power conversion circuit includes a circuit board and at least one semiconductor device as described in any of the embodiments of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0015] According to another aspect of the present invention, a vehicle is provided, comprising a load and a power conversion circuit as described in any of the embodiments of the present invention, wherein the power conversion circuit is used to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current, or convert direct current into alternating current and then input it into the load.

[0016] The semiconductor device and manufacturing method, power module, power conversion circuit and vehicle provided by the embodiment of the present invention integrate a semiconductor graphene layer into a SiC complementary metal oxide semiconductor (CMOS) device with a first direction of conduction current and a power SiC MOSFET device with a first direction of conduction current, so as to improve the mobility of the semiconductor device and create a high-performance monolithic power integrated circuit (IC), minimize physical occupation, and make it an ideal choice for advanced electronic applications requiring high performance and reliability. Since the conduction current direction of the SiC MOSFET, the first conductivity type SiC MOSFET and the second conductivity type SiC MOSFET are all in the first direction, and the semiconductor graphene layer is located on the electrode setting surface of the respective device region, under the control of the respective gates, the conduction current flows from the source to the drain through the semiconductor graphene layer. Since the semiconductor graphene layer has high strength, high thermal conductivity, mobility greater than that of silicon carbide and has semiconductor properties, the same hole and electron mobility is ensured, effectively solving the uniformity problem of channel mobility of n-MOS and p-MOS transistors, improving the uniformity of p-channel and n-channel switching speeds, overall efficiency and thermal management efficiency, thereby greatly improving the carrier mobility and channel mobility of SiCMOSFET, the carrier mobility and channel mobility of the first conductivity type SiC MOSFET and the second conductivity type SiC MOSFET in CMOS planar devices; reducing the difference in mobility between carriers of different conductivity types in different planar devices at their respective operating voltages, so as to improve the electrical performance of monolithically integrated silicon carbide metal-oxide semiconductor field effect transistors and silicon carbide complementary metal oxide semiconductor semiconductor devices.

[0017] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0020] Figure 2 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0021] Figure 3 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0022] Figure 4 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0023] Figure 5 yes Figure 4 A schematic diagram of the structure of the relevant steps in FIG.

[0024] Figure 6 yes Figure 4 A schematic diagram of the process included in S110;

[0025] Figure 7-Figure 9 yes Figure 6 A schematic diagram of the structure of each relevant step in the process;

[0026] Fig.10 is a schematic flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0027] Fig.11 yes Fig.10 The schematic diagram of the process included in S1201;

[0028] Fig.12 yes Fig.11 Schematic diagram of the structure of each related step in . DETAILED DESCRIPTION

[0029] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0030] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0031] In order to improve the electrical performance of monolithically integrated silicon carbide metal-oxide semiconductor field effect transistors and silicon carbide complementary metal oxide semiconductor semiconductor devices, the embodiments of the present invention provide the following technical solutions:

[0032] like Figure 1 As shown, Figure 11 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention, wherein the semiconductor device comprises: a silicon carbide semiconductor body 100, wherein the silicon carbide semiconductor body 100 comprises a first device region 001 and a second device region 002 spaced apart along a first direction, wherein the first direction is perpendicular to the thickness direction of the silicon carbide semiconductor body 100; the second device region 002 comprises a first conductive type device region 021 and a second conductive type device region 022 spaced apart along the first direction; the silicon carbide semiconductor body 100 comprises an electrode setting surface 101; a semiconductor graphene layer 200 comprises a first semiconductor graphene layer 201, a second semiconductor graphene layer 202 and a first conductive type device region 021; and a semiconductor graphene layer 200 comprises a first semiconductor graphene layer 201, a second semiconductor graphene layer 202 and a second conductive type device region 022. The three semiconductor graphene layers 203 are used to improve the mobility of the semiconductor device; at the same preset temperature, the mobility of the semiconductor graphene layer 200 is greater than the mobility of silicon carbide; the first semiconductor graphene layer 201 is located on the electrode setting surface 101 of the first device region 001, the second semiconductor graphene layer 202 is located on the electrode setting surface 101 of the first conductive type device region 021, and the third semiconductor graphene layer 203 is located on the electrode setting surface 101 of the second conductive type device region 022; in the semiconductor device, the portion located in the first device region 001 is a silicon carbide metal-oxide semiconductor field effect transistor (SiC The device is a first conductive type SiC MOSFET, the portion located in the second device region 002 is a SiC complementary metal oxide semiconductor (SiC CMOS), the SiC complementary metal oxide semiconductor (SiC CMOS) includes a first conductive type SiC metal-oxide semiconductor field effect transistor (first conductive type SiC MOSFET) located in the first conductive type device region 021 and having a conduction current direction in a first direction, and a second conductive type SiC metal-oxide semiconductor field effect transistor (second conductive type SiC MOSFET) located in the second conductive type device region 022 and having a conduction current direction in the first direction, the SiC metal-oxide semiconductor field effect transistor (SiC MOSFET) and the SiC complementary metal oxide semiconductor (SiC CMOS) have different operating voltages.

[0033] The thickness direction of the silicon carbide semiconductor body 100 is Figure 1 The Y direction, the first direction and Figure 1 The X direction is set parallel to the

[0034] In the embodiment of the present invention, the silicon carbide semiconductor body 100 may include a substrate and an epitaxial layer, or may include only an epitaxial layer. The epitaxial layer is a semiconductor layer formed by a single epitaxial process, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0035] It should be noted that the mobility of the same semiconductor material will change with the change of temperature. In the embodiment of the present invention, it is defined that at the same preset temperature, the mobility of the semiconductor graphene layer 200 is greater than the mobility of silicon carbide. That is, at the same preset temperature, the movement resistance of the carriers in the semiconductor graphene layer 200 is less than the movement resistance of the carriers in silicon carbide, and the semiconductor graphene layer 200 is located on the electrode setting surface 101 of the respective device area, wherein, in the first device area 001, in the silicon carbide metal-oxide semiconductor field effect transistor (SiC MOSFET) with the conduction current direction in the first direction, under the control of the gate, the conduction current flows from the source to the drain through the first semiconductor graphene layer 201. In the second device area 002, in the first conductivity type silicon carbide metal-oxide semiconductor field effect transistor (first conductivity type SiC MOSFET) with the conduction current direction in the first direction, under the control of the gate, the conduction current flows from the source to the drain through the second semiconductor graphene layer 202. In the second device region 002, in a second conductive type silicon carbide metal-oxide semiconductor field effect transistor (second conductive type SiC MOSFET) having an on-current direction in a first direction, under the control of the gate, the on-current flows from the source to the drain through the third semiconductor graphene layer 203. The provision of the semiconductor graphene layer 200 significantly increases the channel carrier mobility in the semiconductor device, thereby reducing the on-resistance of the semiconductor device.

[0036] The semiconductor device provided by the embodiment of the present invention integrates the semiconductor graphene layer 200 into a SiC complementary metal oxide semiconductor (CMOS) device with a first direction of conduction current and a power SiC MOSFET device with a first direction of conduction current, so as to improve the mobility of the semiconductor device and to create a high-performance monolithic power integrated circuit (IC), minimize physical occupation, and make it an ideal choice for advanced electronic applications requiring high performance and reliability. Since the conduction current directions of the SiC MOSFET, the first conductivity type SiC MOSFET, and the second conductivity type SiC MOSFET are all in the first direction, and the semiconductor graphene layer 200 is located on the electrode setting surface 101 of the respective device region, under the control of the respective gates, the conduction current flows from the source to the drain through the semiconductor graphene layer 200. Since the semiconductor graphene layer 200 has high strength, high thermal conductivity, mobility greater than that of silicon carbide and semiconductor properties, the same hole and electron mobility is ensured, the uniformity problem of channel mobility of n-MOS and p-MOS transistors is effectively solved, and the uniformity of switching speed of p-channel and n-channel, overall efficiency and thermal management efficiency are improved, thereby greatly improving the carrier mobility and channel mobility of SiC MOSFET, the carrier mobility and channel mobility of the first conductivity type SiC MOSFET and the second conductivity type SiC MOSFET in CMOS planar devices; reducing the difference in mobility between carriers of different conductivity types in different planar devices at their respective operating voltages, so as to improve the electrical performance of monolithically integrated silicon carbide metal-oxide semiconductor field effect transistors and silicon carbide complementary metal oxide semiconductor semiconductor devices.

[0037] It should be noted that the mobility of the semiconductor graphene layer 200 depends on the growth quality of the material, and can range from tens of cm2 / Vs to about 5000 cm2 / Vs. Preferably, the mobility of the semiconductor graphene layer 200 at room temperature is greater than or equal to 1000 cm2 / Vs, and can even reach about 5500 cm2 / Vs. Room temperature is also called normal temperature or general temperature, which is generally defined as 25 degrees Celsius, and sometimes set to 300K (about 27 degrees Celsius). The mobility required for semiconductor devices is only about tens of cm2 / Vs. Therefore, the semiconductor graphene layer 200 can significantly improve the mobility of semiconductor devices.

[0038] Optional, such as Figure 1 As shown, the band gap of the semiconductor graphene layer 200 is greater than or equal to 0.4 eV. Figure 1 As shown, the band gap of the semiconductor graphene layer 200 is greater than or equal to 0.6 eV.

[0039] Specifically, since the semiconductor graphene layer 200 has high strength, high thermal conductivity, mobility greater than the mobility of silicon carbide and semiconductor properties, its band gap is greater than or equal to 0.4 eV, preferably greater than or equal to 0.6 eV, and the mobility is preferably greater than or equal to 1000 cm2 / Vs, and can even reach about 5500 cm2 / Vs, thereby ensuring the same hole and electron mobility in the conduction channel, effectively solving the uniformity problem of the channel mobility of the first conductivity type SiC MOSFET and the second conductivity type SiC MOSFET, improving the switching speed uniformity of the first conductivity type channel and the second conductivity type channel, and improving the overall efficiency and thermal management efficiency, so that the semiconductor device has a faster response speed.

[0040] Optionally, based on the above technical solution, the side of the silicon carbide semiconductor body 100 close to the electrode setting surface 101 includes a first region 103, a first well region 104, a second region 105, a second well region 106, a third region 107 and a third well region 108; the first region 103 and the first well region 104 are located in the first device region 001 and have opposite conductivity types, the second region 105 and the second well region 106 are located in the first conductivity type device region 021 and have opposite conductivity types, the third region 107 and the third well region 108 are located in the second conductivity type device region 022 and have opposite conductivity types; the first semiconductor graphene layer 201 is connected to the two first regions 103; the second semiconductor graphene layer 202 is located and connected to the two second regions 105; the third semiconductor graphene layer 203 is connected to the two third regions 107.

[0041] Specifically, the above technical solution clearly gives the specific position of the semiconductor graphene layer 200 in the SiC MOSFET with a conduction current direction in the first direction, the first conductivity type SiC MOSFET with a conduction current direction in the first direction in a CMOS planar device, and the second conductivity type SiC MOSFET with a conduction current direction in the first direction.

[0042] Among them, in the first device region 001, in the silicon carbide metal-oxide semiconductor field effect transistor (SiC MOSFET) whose conduction current direction is the first direction, under the control of the gate, the conduction current flows from the source to the drain through the first region 103, the first semiconductor graphene layer 201 and the first region 103. In the second device region 002, in the first conductivity type silicon carbide metal-oxide semiconductor field effect transistor (first conductivity type SiC MOSFET) whose conduction current direction is the first direction, under the control of the gate, the conduction current flows from the source to the drain through the second region 105, the second semiconductor graphene layer 202 and the second region 105. In the second device region 002, in the second conductivity type silicon carbide metal-oxide semiconductor field effect transistor (second conductivity type SiC MOSFET) whose conduction current direction is the first direction, under the control of the gate, the conduction current flows from the source to the drain through the third region 107, the third semiconductor graphene layer 203 and the third region 107.

[0043] Optionally, based on the above technical solution, the semiconductor graphene layer 200 and the silicon carbide semiconductor body 100 are orderly connected through covalent bonds.

[0044] Specifically, a semiconductor graphene layer 200 is grown on a wafer-level SiC semiconductor body. The semiconductor graphene layer 200 is covalently bonded to the silicon carbide semiconductor body 100. The semiconductor graphene layer 200 has high strength, high thermal conductivity and semiconductor properties, and its band gap is greater than or equal to 0.6 eV. As a channel under the isolation gate, the channel mobility can be increased to, for example, about 5500 cm2 / Vs. The semiconductor graphene layer 200 has improved channel mobility, and the superior charge mobility and thermal properties of the semiconductor graphene layer 200 are used to enhance the channel mobility and overall efficiency of SiC MOSFET and SiC CMOS at different operating voltages.

[0045] The essence of the semiconductor graphene layer 200 is a single layer of carbon atoms in the silicon carbide semiconductor body 100, and its thickness is equivalent to the thickness of a single layer of carbon atoms in the silicon carbide semiconductor body 100. The thickness of the semiconductor graphene layer 200 is greater than or equal to 0.2nm and less than or equal to 0.3nm, and its average thickness is about 0.25nm. The bonding between the semiconductor graphene layer 200 and the silicon carbide semiconductor body 100 is orderly and periodically arranged, which can ensure that the semiconductor graphene layer 200 is a two-dimensional semiconductor material.

[0046] Optionally, based on the above technical solution, the operating voltage of the silicon carbide metal-oxide semiconductor field effect transistor (SiC MOSFET) is greater than the operating voltage of the silicon carbide complementary metal oxide semiconductor (SiC CMOS); a first isolation region 003 is provided between the silicon carbide semiconductor body 100 between the first device region 001 and the second device region 002. A second isolation region 004 is provided between the first conductive type device region 021 and the second conductive type device region 022.

[0047] Optionally, when the drift layer of the silicon carbide semiconductor body 100 close to the electrode setting surface 101 is of the first conductivity type, the first isolation region 003 and the second isolation region 004 are located in the drift layer of the silicon carbide semiconductor body 100 close to the electrode setting surface 101, and the first isolation region 003 and the second isolation region 004 are of the second conductivity type. The first isolation region 003 is used to isolate the low-voltage circuit from the high-voltage circuit, highlighting the ability of the architecture to be applicable to various power applications. The second isolation region 004 is used to isolate the p-channel and n-channel MOS devices, making it easy to utilize the properties of the semiconductor graphene layer 200 to ensure the same hole and electron mobility, effectively solving the uniformity problem of the channel mobility of n-MOS and p-MOS transistors, and improving the uniformity of the switching speed of the p-channel and n-channel, the overall efficiency and the thermal management efficiency. Exemplarily, Figure 1 In the figure, the silicon carbide semiconductor body 100 includes a first drift layer 10, a second drift layer 20 and a third drift layer 30 which are stacked in sequence, and the surface of the third drift layer 30 away from the second drift layer 20 is an electrode setting surface 101; the first drift layer 10 is set to the first conductivity type, the second drift layer 20 is set to the second conductivity type, and the third drift layer 30 is set to the first conductivity type. The first isolation region 003 and the second isolation region 004 are located in the third drift layer 30. The conductivity type of the first isolation region 003 and the second isolation region 004 is opposite to the conductivity type of the third drift layer 30.

[0048] Optionally, based on the above technical solution, Figure 1As shown, the semiconductor device further includes: a first insulating layer 109, located on the electrode setting surface 101; a first electrode G1, located on the side of the first insulating layer 109 away from the silicon carbide semiconductor body 100, and located in the first device region 001; a second electrode G2, located on the side of the first insulating layer 109 away from the silicon carbide semiconductor body 100, and located in the first conductive type device region 021; a third electrode G3, located on the side of the first insulating layer 109 away from the silicon carbide semiconductor body 100, and located in the second conductive type device region 022. A fourth electrode S1 and a fifth electrode D1, located in the first device region 001, are connected to the two first regions 103, respectively; a sixth electrode S2 and a seventh electrode D2, located in the first conductive type device region 021, are connected to the two second regions 105, respectively; an eighth electrode S3 and a ninth electrode D3, located in the second conductive type device region 022, are connected to the two third regions 107, respectively.

[0049] Specifically, the first insulating layer 109 is used to insulate the silicon carbide semiconductor body 100 and the first electrode G1, the second electrode G2 and the third electrode G3. Exemplarily, the first electrode G1, the second electrode G2 and the third electrode G3 are polysilicon gates. The second insulating layer 110 is used to insulate the gate and the source and the gate and the drain. Exemplarily, in the fourth electrode S1 and the fifth electrode D1, the fourth electrode S1 is the source and the fifth electrode D1 is the drain; in the sixth electrode S2 and the seventh electrode D2, the sixth electrode S2 is the source and the seventh electrode D2 is the drain; in the eighth electrode S3 and the ninth electrode D3, the eighth electrode S3 is the source and the ninth electrode D3 is the drain.

[0050] The fourth electrode S1 and the fifth electrode D1, the sixth electrode S2 and the seventh electrode D2, and the eighth electrode S3 and the ninth electrode D3 are patterned by the third metal layer M3, and are connected to the silicon carbide semiconductor body 100 through the second metal layer M2, the first metal layer M1, and the conductive hole located inside the second insulating layer 110. Optionally, an ohmic contact layer 111 is also provided in the semiconductor device to achieve better ohmic contact between the source and the silicon carbide semiconductor body 100.

[0051] Optionally, based on the above technical solution, Figure 1 As shown, the first region 103 is located on the electrode setting surface 101, and the first well region 104 is located between the two first regions 103; the second region 105 is located on the electrode setting surface 101, and the second well region 106 is located between the two second regions 105; the third region 107 is located on the electrode setting surface 101, and the third well region 108 is located between the two third regions 107.

[0052] Optionally, based on the above technical solution, the number of first device regions 001 includes multiple; the number of second device regions 002 includes multiple; along the first direction, the first device regions 001 and the second device regions 002 are arranged at intervals; or, along the first direction, at least two first device regions 001 are arranged continuously; at least two second device regions 002 are arranged continuously.

[0053] Specifically, the above technical solution provides an arrangement of a plurality of first device regions 001 and a plurality of second device regions 002 in the first direction.

[0054] Optionally, based on the above technical solution, the second device region 002 includes S first conductive type device regions 021 and Q second conductive type device regions 022, S includes an integer greater than or equal to 1, and Q includes an integer greater than or equal to 1; along the first direction, the first conductive type device region 021 and the second conductive type device region 022 are arranged at intervals; or, S includes an integer greater than or equal to 2, and along the first direction, at least two first conductive type device regions 021 are arranged continuously; Q includes an integer greater than or equal to 2, and along the first direction, at least two second conductive type device regions 022 are arranged continuously.

[0055] Specifically, the above technical solution provides an arrangement of S first conductivity type device regions 021 and Q second conductivity type device regions 022 in the second device region 002 in the first direction.

[0056] Optionally, based on the above technical solution, Figure 2 As shown, Figure 2 It is a structural schematic diagram of another semiconductor device provided by an embodiment of the present invention, wherein the semiconductor graphene layer 200 also includes a fourth semiconductor graphene layer 204; the silicon carbide semiconductor body 100 includes a first silicon carbide semiconductor body 1A and a second silicon carbide semiconductor body 1B; the first silicon carbide semiconductor body 1A is used to support the second silicon carbide semiconductor body 1B; the fourth semiconductor graphene layer 204 is located between the first silicon carbide semiconductor body 1A and the second silicon carbide semiconductor body 1B, and the fourth semiconductor graphene layer 204 and the first silicon carbide semiconductor body 1A are orderly connected through covalent bonds.

[0057] Specifically, the fourth semiconductor graphene layer 204 is located between the first silicon carbide semiconductor body 1A and the second silicon carbide semiconductor body 1B, the fourth semiconductor graphene layer 204 and the first silicon carbide semiconductor body 1A are orderly connected by covalent bonds, and its mobility is greater than the mobility of silicon carbide, and the semiconductor graphene layer 200 is located in the conduction channel under the gate structure, which significantly increases the channel carrier mobility in the semiconductor device, and the channel mobility can be increased to, for example, 5500cm 2 V-1 s -1 The semiconductor graphene layer 200 has improved channel mobility, and the superior charge mobility and thermal characteristics of the semiconductor graphene layer 200 are used to enhance the channel mobility and overall efficiency of SiC MOSFET and SiC CMOS with different operating voltages. In addition, the properties of the semiconductor graphene layer 200 ensure the same hole and electron mobility, effectively solve the uniformity problem of channel mobility of n-MOS and p-MOS transistors, and improve the uniformity of switching speed of p-channel and n-channel, overall efficiency and thermal management efficiency.

[0058] Optionally, based on the above technical solution, Figure 1 As shown, at the same preset temperature, the mobility of the semiconductor graphene layer 200 is greater than that of silicon. Exemplarily, at the same selected room temperature conditions, the room temperature mobility of the semiconductor graphene layer 200 is greater than that of silicon, and the maximum mobility can reach 5500 cm 2 V -1 s -1 , which is about 10 times the room temperature mobility of silicon, greatly increases the channel carrier mobility in the semiconductor device, thereby reducing the on-resistance of the semiconductor device and enhancing the channel mobility and overall efficiency of SiC MOSFET and SiC CMOS at different operating voltages. In addition, the properties of the semiconductor graphene layer 200 ensure the same hole and electron mobility, effectively solving the uniformity problem of channel mobility of n-MOS and p-MOS transistors, and improving the uniformity of switching speed of p-channel and n-channel, overall efficiency and thermal management efficiency.

[0059] Optionally, based on the above technical solution, Figure 3 As shown, Figure 3 3 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention. The semiconductor device further includes a protective layer 300 , which covers the semiconductor graphene layer 200 .

[0060] Specifically, the protective layer 300 is a thin film formed by an atomic layer deposition process, which is used to protect the semiconductor graphene layer 200 and avoid damage to the semiconductor graphene layer 200 during the formation of subsequent film layers, thereby ensuring that the semiconductor graphene layer 200 has a high mobility, thereby increasing the structural stability of the semiconductor device. Optionally, the thickness of the protective layer 300 is relatively thin, and the minimum thickness of the protective layer 300 is 5nm. On the basis of achieving the function of protecting the semiconductor graphene layer 200, it has little effect on the on-resistance of the semiconductor device. Optionally, on the basis of the above technical solution, the protective layer 300 includes a gold protective layer or an aluminum oxide protective layer.

[0061] Specifically, the physical and chemical properties of the gold protective layer or the aluminum oxide protective layer are stable, and can protect the semiconductor graphene layer 200 and avoid damage to the semiconductor graphene layer 200 during the process of epitaxially forming subsequent film layers.

[0062] Optionally, based on the above technical solution, Figure 1-Figure 3 As shown, the silicon carbide semiconductor body 100 also includes a fourth region 112, a fifth region 113 and a sixth region 114; the fourth region 112 is located on the electrode setting surface 101, connected to the first region 103, and located in the first device region 001; the fifth region 113 is located on the electrode setting surface 101, connected to the second region 105, and located in the first conductive type device region 021; the sixth region 114 is located on the electrode setting surface 101, connected to the third region 107, and located in the second conductive type device region 022.

[0063] Specifically, the fourth region 112, the fifth region 113, and the sixth region 114 are used to achieve better ohmic contact between the source and the silicon carbide semiconductor body 100. The conductivity type of the fourth region 112 is the same as the conductivity type of the first well region 104. The conductivity type of the fifth region 113 is the same as the conductivity type of the second well region 106. The conductivity type of the sixth region 114 is the same as the conductivity type of the third well region 108.

[0064] Optionally, based on the above technical solution, Figure 1-Figure 3 As shown, the silicon carbide semiconductor body 100 includes a first drift layer 10, a second drift layer 20 and a third drift layer 30 which are stacked in sequence, and the surface of the third drift layer 30 away from the second drift layer 20 is an electrode setting surface 101; the first drift layer 10 is set to a first conductivity type, the second drift layer 20 is set to a second conductivity type, and the third drift layer 30 is set to a first conductivity type.

[0065] Optionally, based on the above technical solution, Figure 1-Figure 3 As shown, the area of ​​the third drift layer 30 close to the electrode setting surface 101 is reused as a well region of the first conductivity type among the first well region 104, the second well region 106 and the third well region 108, which can simplify the structure of the semiconductor device and reduce the preparation cost.

[0066] Optionally, based on the above technical solution, the first semiconductor graphene layer 201 and the first region 103 have the same conductivity type, the second semiconductor graphene layer 202 and the second region 105 have the same conductivity type, and the third semiconductor graphene layer 203 and the third region 107 have the same conductivity type.

[0067] Specifically, the first semiconductor graphene layer 201 and the first region 103 have the same conductivity type, that is, the first semiconductor graphene layer 201 has the same conductivity type as the silicon carbide metal-oxide semiconductor field effect transistor in the first device region 001 where it is located, which can further increase the carrier concentration of the conduction channel and reduce the on-resistance.

[0068] The second semiconductor graphene layer 202 and the second region 105 have the same conductivity type, that is, the second semiconductor graphene layer 202 has the same conductivity type as the silicon carbide metal-oxide semiconductor field effect transistor in the second device region 002 where it is located, which can further increase the carrier concentration of the conduction channel and reduce the on-resistance.

[0069] The embodiment of the present invention also provides a method for manufacturing a semiconductor device. Figure 4 As shown, Figure 4 1 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention, and the method for manufacturing a semiconductor device comprises the following steps:

[0070] S110. Provide a silicon carbide semiconductor body, wherein the silicon carbide semiconductor body comprises a first device region and a second device region spaced apart along a first direction, wherein the first direction is perpendicular to a thickness direction of the silicon carbide semiconductor body; the second device region comprises a first conductive type device region and a second conductive type device region spaced apart along the first direction; and the silicon carbide semiconductor body comprises an electrode setting surface.

[0071] like Figure 5 As shown, a silicon carbide semiconductor body 100 is provided, which includes a first device region 001 and a second device region 002 spaced apart along a first direction, wherein the first direction is perpendicular to the thickness direction of the silicon carbide semiconductor body 100; the second device region 002 includes a first conductive type device region 021 and a second conductive type device region 022 spaced apart along the first direction; and the silicon carbide semiconductor body 100 includes an electrode setting surface 101.

[0072] Optionally, the side of the silicon carbide semiconductor body 100 close to the electrode setting surface 101 includes a first region 103, a first well region 104, a second region 105, a second well region 106, a third region 107 and a third well region 108; the first region 103 and the first well region 104 are located in the first device region 001 and have opposite conductivity types, the second region 105 and the second well region 106 are located in the first conductivity type device region 021 and have opposite conductivity types, the third region 107 and the third well region 108 are located in the second conductivity type device region 022 and have opposite conductivity types; the first semiconductor graphene layer 201 is connected to the two first regions 103; the second semiconductor graphene layer 202 is located and connected to the two second regions 105; the third semiconductor graphene layer 203 is connected to the two third regions 107.

[0073] Specifically, the above technical solution clearly provides the specific position of the semiconductor graphene layer 200 in the SiC MOSFET with the conduction current direction in the first direction, the first conductivity type SiC MOSFET in the CMOS planar device, and the second conductivity type SiC MOSFET.

[0074] Among them, in the first device region 001, in the planar structured silicon carbide metal-oxide semiconductor field effect transistor (SiC MOSFET), under the control of the gate, the on-current flows from the source to the drain through the first region 103, the first semiconductor graphene layer 201 and the first region 103. In the second device region 002, in the first conductivity type silicon carbide metal-oxide semiconductor field effect transistor (first conductivity type SiC MOSFET) with the on-current direction in the first direction, under the control of the gate, the on-current flows from the source to the drain through the second region 105, the second semiconductor graphene layer 202 and the second region 105. In the second device region 002, in the second conductivity type silicon carbide metal-oxide semiconductor field effect transistor (second conductivity type SiC MOSFET) with the on-current direction in the first direction, under the control of the gate, the on-current flows from the source to the drain through the third region 107, the third semiconductor graphene layer 203 and the third region 107.

[0075] S120, forming a first semiconductor graphene layer, a second semiconductor graphene layer and a third semiconductor graphene layer located on the electrode setting surface in the semiconductor graphene layer, so as to improve the mobility of the semiconductor device. At the same preset temperature, the mobility of the semiconductor graphene layer is greater than the mobility of silicon carbide; the first semiconductor graphene layer is located on the electrode setting surface of the first device region, the second semiconductor graphene layer is located on the electrode setting surface of the first conductive type device region, and the third semiconductor graphene layer is located on the electrode setting surface of the second conductive type device region.

[0076] like Figure 1As shown, a first semiconductor graphene layer 201 , a second semiconductor graphene layer 202 and a third semiconductor graphene layer 203 are formed on the electrode setting surface 101 . The semiconductor graphene layer 200 includes a first semiconductor graphene layer 201, a second semiconductor graphene layer 202 and a third semiconductor graphene layer 203. At the same preset temperature, the mobility of the semiconductor graphene layer 200 is greater than the mobility of silicon carbide; the first semiconductor graphene layer 201 is located on the electrode setting surface 101 of the first device region 001, the second semiconductor graphene layer 202 is located on the electrode setting surface 101 of the first conductive type device region 021, and the third semiconductor graphene layer 203 is located on the electrode setting surface 101 of the second conductive type device region 022; in the semiconductor device, the portion located in the first device region 001 is a silicon carbide metal-oxide semiconductor field effect transistor (SiC MOSFET) with a conduction current direction in a first direction, the portion located in the second device region 002 is a silicon carbide complementary metal oxide semiconductor (SiC CMOS), and the silicon carbide complementary metal oxide semiconductor (SiC CMOS) is a silicon carbide complementary metal oxide semiconductor (SiC CMOS). The CMOS includes a first conductive type silicon carbide metal-oxide semiconductor field effect transistor (first conductive type SiC MOSFET) located in the first conductive type device region 021 and with a first direction of conduction current, and a second conductive type silicon carbide metal-oxide semiconductor field effect transistor (second conductive type SiC MOSFET) located in the second conductive type device region 022 and with a first direction of conduction current, and the operating voltages of the silicon carbide metal-oxide semiconductor field effect transistor (SiC MOSFET) and the silicon carbide complementary metal oxide semiconductor (SiC CMOS) are different. .

[0077] The thickness direction of the silicon carbide semiconductor body 100 is Figure 1 The Y direction, the first direction and Figure 1 The X direction is set parallel to the

[0078] In the embodiment of the present invention, the silicon carbide semiconductor body 100 may include a substrate and an epitaxial layer, or may include only an epitaxial layer. The epitaxial layer is a semiconductor layer formed by a single epitaxial process, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0079] It should be noted that the mobility of the same semiconductor material will change with the change of temperature. In the embodiment of the present invention, it is defined that at the same preset temperature, the mobility of the semiconductor graphene layer 200 is greater than the mobility of silicon carbide. That is, at the same preset temperature, the movement resistance of the carriers in the semiconductor graphene layer 200 is less than the movement resistance of the carriers in silicon carbide, and the semiconductor graphene layer 200 is located on the electrode setting surface 101 of the respective planar structure device area, wherein, in the first device area 001, in the silicon carbide metal-oxide semiconductor field effect transistor (SiCMOSFET) with the conduction current direction in the first direction, under the control of the gate, the conduction current flows from the source to the drain through the first semiconductor graphene layer 201. In the second device area 002, in the first conductivity type silicon carbide metal-oxide semiconductor field effect transistor (first conductivity type SiC MOSFET) with the conduction current direction in the first direction, under the control of the gate, the conduction current flows from the source to the drain through the second semiconductor graphene layer 202. In the second device region 002, in a second conductive type silicon carbide metal-oxide semiconductor field effect transistor (second conductive type SiC MOSFET) having an on-current direction in a first direction, under the control of the gate, the on-current flows from the source to the drain through the third semiconductor graphene layer 203. The provision of the semiconductor graphene layer 200 significantly increases the channel carrier mobility in the semiconductor device, thereby reducing the on-resistance of the semiconductor device.

[0080] The semiconductor device provided by the embodiment of the present invention integrates the semiconductor graphene layer 200 into a SiC complementary metal oxide semiconductor (CMOS) device with a first direction of conduction current and a power SiC MOSFET device with a first direction of conduction current, which helps to improve the mobility of the semiconductor device and aims to create a high-performance monolithic power integrated circuit (IC), minimize physical occupation, and make it an ideal choice for advanced electronic applications that require high performance and reliability. Since the conduction current directions of the SiC MOSFET, the first conductivity type SiC MOSFET, and the second conductivity type SiC MOSFET are all in the first direction, and the semiconductor graphene layer 200 is located on the electrode setting surface 101 of the respective device region, under the control of the respective gates, the conduction current flows from the source to the drain through the semiconductor graphene layer 200. Since the semiconductor graphene layer 200 has high strength, high thermal conductivity, mobility greater than that of silicon carbide and has semiconductor properties, the same hole and electron mobility is ensured, and the uniformity problem of channel mobility of n-MOS and p-MOS transistors is effectively solved, and the uniformity of switching speed of p-channel and n-channel, overall efficiency and thermal management efficiency are improved, thereby greatly improving the carrier mobility and channel mobility of SiC MOSFET, the carrier mobility and channel mobility of the first conductivity type SiC MOSFET and the second conductivity type SiC MOSFET in CMOS planar devices; reducing the difference in mobility between carriers of different conductivity types in different planar devices at their respective operating voltages, so as to improve the electrical performance of monolithically integrated silicon carbide metal-oxide semiconductor field effect transistors and silicon carbide complementary metal oxide semiconductor semiconductor devices.

[0081] It should be noted that the mobility of the semiconductor graphene layer 200 depends on the growth quality of the material, and can range from tens of cm2 / Vs to about 5000 cm2 / Vs. Preferably, the mobility of the semiconductor graphene layer 200 at room temperature is greater than or equal to 1000 cm2 / Vs, and can even reach about 5500 cm2 / Vs. Room temperature is also called normal temperature or general temperature, which is generally defined as 25 degrees Celsius, and sometimes set to 300K (about 27 degrees Celsius). The mobility required for semiconductor devices is only about tens of cm2 / Vs. Therefore, the semiconductor graphene layer 200 can significantly improve the mobility of semiconductor devices.

[0082] Optional, such as Figure 1 As shown, the band gap of the semiconductor graphene layer 200 is greater than or equal to 0.4 eV. Figure 1 As shown, the band gap of the semiconductor graphene layer 200 is greater than or equal to 0.6 eV.

[0083] Specifically, since the semiconductor graphene layer 200 has high strength, high thermal conductivity, mobility greater than that of silicon carbide and semiconductor properties, its band gap is greater than or equal to 0.4 eV, preferably greater than or equal to 0.6 eV, and the mobility is preferably greater than or equal to 1000 cm2 / Vs, and can even reach about 5500 cm2 / Vs, ensuring the same hole and electron mobility in the conduction channel, effectively solving the uniformity problem of the channel mobility of the first conductive type SiC MOSFET and the second conductive type SiC MOSFET, improving the switching speed uniformity of the first conductive type channel and the second conductive type channel, the overall efficiency and thermal management efficiency, so that the semiconductor device has a faster response speed. Optionally, on the basis of the above technical solution, such as Figure 6 As shown, Figure 6 yes Figure 4 The process diagram of S110 includes: S110 provides a silicon carbide semiconductor body including:

[0084] S1101. Provide a first silicon carbide semiconductor body.

[0085] like Figure 7 As shown, a first silicon carbide semiconductor body 1A is provided.

[0086] S1102. Form a fourth semiconductor graphene layer on one side of the first silicon carbide semiconductor body, wherein the semiconductor graphene layer further includes a fourth semiconductor graphene layer.

[0087] like Figure 8 As shown, a fourth semiconductor graphene layer 204 is formed on one side of the first silicon carbide semiconductor body 1A, and the semiconductor graphene layer 200 further includes the fourth semiconductor graphene layer 204 .

[0088] S1103, forming a second silicon carbide semiconductor body on a side of the fourth semiconductor graphene layer away from the first silicon carbide semiconductor body; the silicon carbide semiconductor body includes the first silicon carbide semiconductor body and the second silicon carbide semiconductor body.

[0089] like Fig. 9 As shown, a second silicon carbide semiconductor body 1B is formed on a side of the fourth semiconductor graphene layer 204 away from the first silicon carbide semiconductor body 1A through an epitaxial process; the silicon carbide semiconductor body 100 includes the first silicon carbide semiconductor body 1A and the second silicon carbide semiconductor body 1B.

[0090] S1104, forming a first semiconductor graphene layer, a second semiconductor graphene layer, and a third semiconductor graphene layer on a side of the second silicon carbide semiconductor body away from the fourth semiconductor graphene layer.

[0091] like Fig. 9As shown, a first semiconductor graphene layer 201 , a second semiconductor graphene layer 202 and a third semiconductor graphene layer 203 are formed on a side of the second silicon carbide semiconductor body 1B away from the fourth semiconductor graphene layer 204 .

[0092] Specifically, the fourth semiconductor graphene layer 204 is located between the first silicon carbide semiconductor body 1A and the second silicon carbide semiconductor body 1B, the fourth semiconductor graphene layer 204 and the first silicon carbide semiconductor body 1A are orderly connected by covalent bonds, and its mobility is greater than the mobility of silicon carbide, and the semiconductor graphene layer 200 is located in the conduction channel under the gate structure, which significantly increases the channel carrier mobility in the semiconductor device, and the channel mobility can be increased to, for example, 5500cm 2 V -1 s -1 The semiconductor graphene layer 200 has improved channel mobility, and the superior charge mobility and thermal characteristics of the semiconductor graphene layer 200 are used to enhance the channel mobility and overall efficiency of SiC MOSFET and SiC CMOS with different operating voltages. In addition, the properties of the semiconductor graphene layer 200 ensure the same hole and electron mobility, effectively solve the uniformity problem of channel mobility of n-MOS and p-MOS transistors, and improve the uniformity of switching speed of p-channel and n-channel, overall efficiency and thermal management efficiency.

[0093] Optionally, based on the above technical solution, Fig.10 As shown, Fig.10 is a flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention, Fig.10 A method for manufacturing a semiconductor device and Figure 4 The difference between the semiconductor device manufacturing method shown is that Fig.10 for Figure 4 S120 is further defined, and S120 forms a semiconductor graphene layer including:

[0094] S1201, heating the silicon carbide semiconductor body to a preset temperature so that silicon in the silicon carbide semiconductor body evaporates, thereby forming a semiconductor graphene layer on one side of the silicon carbide semiconductor body.

[0095] like Figure 5 , Figure 8 and Fig. 9 As shown, the silicon carbide semiconductor body 100 is heated to a preset temperature so that the silicon on the surface of the silicon carbide semiconductor body 100 evaporates, thereby forming a semiconductor graphene layer 200 on one side of the silicon carbide semiconductor body 100, wherein the semiconductor graphene layer 200 and the silicon carbide semiconductor body 100 are connected by covalent bonding.

[0096] Specifically, the preparation of the semiconductor graphene layer 200 uses a heated silicon carbide semiconductor body 100. During the heating process, silicon evaporates before carbon, so that the semiconductor graphene layer 200 is spontaneously crystallized on the surface of the silicon carbide semiconductor body 100. Among them, the semiconductor graphene layer 200 is connected to the silicon carbide semiconductor body 100 through covalent bonding during the growth process, and there is no need to form a bonding layer, which simplifies the preparation process and reduces the preparation cost. The semiconductor graphene layer 200 is a two-dimensional semiconductor material. The semiconductor graphene layer 200 and the silicon carbide semiconductor body 100 are orderly bonded and connected through covalent bonds. The semiconductor graphene layer 200 has a very high mobility.

[0097] Optionally, based on the above technical solution, Fig.11 As shown, Fig.11 yes Fig.10 The process diagram included in S1201, S1201 heats the silicon carbide semiconductor body to a preset temperature so that silicon of the silicon carbide semiconductor body evaporates, thereby forming a semiconductor graphene layer on one side of the silicon carbide semiconductor body, including:

[0098] S1201a, arrange the silicon carbide semiconductor layer and one side of the silicon carbide semiconductor body opposite to each other.

[0099] like Fig.12 As shown, a silicon carbide semiconductor layer 400 is provided, and the silicon carbide semiconductor layer 400 and one side of the silicon carbide semiconductor body 100 are arranged opposite to each other.

[0100] S1201b, heating one side of the silicon carbide semiconductor body and the silicon carbide semiconductor layer to a preset temperature so that the carbon surface of the silicon carbide semiconductor layer and one side of the silicon carbide semiconductor body provide a quasi-equilibrium condition between the carbon surface and the silicon surface at the preset temperature; wherein the surface of one side of the silicon carbide semiconductor body is the silicon surface.

[0101] like Fig.12 As shown, one side of the silicon carbide semiconductor body 100 and the silicon carbide semiconductor layer 400 are heated to a preset temperature so that the carbon surface of the silicon carbide semiconductor layer 400 and one side of the silicon carbide semiconductor body 100 provide a quasi-equilibrium condition established between the carbon surface and the silicon surface at the preset temperature; wherein the surface of one side of the silicon carbide semiconductor body 100 is the silicon surface.

[0102] S1201c, silicon on one side of the silicon carbide semiconductor body is evaporated, thereby forming a semiconductor graphene layer on one side of the silicon carbide semiconductor body.

[0103] like Fig.12As shown, during the heating process, silicon is evaporated before carbon, so that a semiconductor graphene layer 200 is spontaneously crystallized on the surface of the silicon carbide semiconductor body 100, wherein the semiconductor graphene layer 200 is connected to the silicon carbide semiconductor body 100 by covalent bonding during the growth process, and there is no need to form a bonding layer, which simplifies the preparation process and reduces the preparation cost. Since the carbon surface of the silicon carbide semiconductor layer 400 and the surface of one side of the silicon carbide semiconductor body 100 provide a quasi-equilibrium condition established between the carbon surface and the silicon surface at a preset temperature, a semiconductor graphene layer 200 with a thickness equal to the thickness of a single layer of carbon atoms can be formed on the surface of one side of the silicon carbide semiconductor body 100. In summary, the essence of the semiconductor graphene layer 200 is a single layer of carbon atoms in the silicon carbide semiconductor body 100, and its thickness is equivalent to the thickness of a single layer of carbon atoms in the silicon carbide epitaxial layer. The thickness of the semiconductor graphene layer 200 is greater than or equal to 0.2nm and less than or equal to 0.3nm, and its average thickness is about 0.25nm. The bonding between the semiconductor graphene layer 200 and the silicon carbide semiconductor body 100 is orderly and periodically arranged, which can ensure that the semiconductor graphene layer 200 is a two-dimensional semiconductor material. The band gap of the semiconductor graphene layer 200 is smaller than the band gap of silicon and is greater than or equal to 0.6 eV.

[0104] Optionally, based on the above technical solution, after forming the semiconductor graphene layer in S120, the step further includes:

[0105] A protection layer is formed on a side of the semiconductor graphene layer away from the silicon carbide semiconductor body.

[0106] like Figure 3 As shown, a protection layer 300 is formed on a side of the semiconductor graphene layer 200 away from the silicon carbide semiconductor body 100 .

[0107] Specifically, the protective layer 300 is a thin film formed by an atomic layer deposition process, which is used to protect the semiconductor graphene layer 200 and avoid damage to the semiconductor graphene layer 200 during the formation of subsequent film layers, thereby ensuring that the semiconductor graphene layer 200 has a high mobility, thereby increasing the structural stability of the semiconductor device. Optionally, the thickness of the protective layer 300 is relatively thin, and the minimum thickness of the protective layer 300 is 5nm. On the basis of achieving the function of protecting the semiconductor graphene layer 200, it has little effect on the on-resistance of the semiconductor device.

[0108] Optionally, based on the above technical solution, the protective layer 300 includes a gold protective layer or an aluminum oxide protective layer.

[0109] Specifically, the physical and chemical properties of the gold protective layer or the aluminum oxide protective layer are stable, and can protect the semiconductor graphene layer 200 and avoid damage to the semiconductor graphene layer 200 during the process of epitaxially forming subsequent film layers.

[0110] An embodiment of the present invention provides a power module, comprising a substrate and at least one semiconductor device according to any embodiment of the present invention, wherein the substrate is used to carry the semiconductor device. Therefore, the beneficial effects of the power module including any semiconductor device according to any embodiment of the present invention are not described in detail here.

[0111] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device described in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0112] Therefore, the power conversion circuit includes the beneficial effects of any semiconductor device described in any embodiment of the present invention, which will not be repeated here.

[0113] An embodiment of the present invention also provides a vehicle, which includes a load and the above-mentioned power conversion circuit, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0114] Therefore, the beneficial effects of the vehicle including any of the power conversion circuit packages described in any embodiment of the present invention will not be repeated here.

[0115] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0116] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: Comprising: a silicon carbide semiconductor body, the silicon carbide semiconductor body comprising a first device region and a second device region spaced apart along a first direction, the first direction being perpendicular to a thickness direction of the silicon carbide semiconductor body; the second device region comprising a first conductive type device region and a second conductive type device region spaced apart along the first direction; the silicon carbide semiconductor body comprising an electrode setting surface; A semiconductor graphene layer, comprising a first semiconductor graphene layer, a second semiconductor graphene layer and a third semiconductor graphene layer, for improving the mobility of the semiconductor device; at the same preset temperature, the mobility of the semiconductor graphene layer is greater than the mobility of silicon carbide; The first semiconductor graphene layer is located on the electrode setting surface of the first device region, the second semiconductor graphene layer is located on the electrode setting surface of the first conductive type device region, and the third semiconductor graphene layer is located on the electrode setting surface of the second conductive type device region; In the semiconductor device, the portion located in the first device region is a silicon carbide metal-oxide semiconductor field effect transistor whose conduction current direction is the first direction, and the portion located in the second device region is a silicon carbide complementary metal oxide semiconductor. The silicon carbide complementary metal oxide semiconductor includes a first conductivity type silicon carbide metal-oxide semiconductor field effect transistor located in the first conductivity type device region and whose conduction current direction is the first direction, and a second conductivity type silicon carbide metal-oxide semiconductor field effect transistor located in the second conductivity type device region and whose conduction current direction is the first direction. The silicon carbide metal-oxide semiconductor field effect transistor and the silicon carbide complementary metal oxide semiconductor have different operating voltages.

2. The semiconductor device according to claim 1, wherein: The band gap of the semiconductor graphene layer is greater than or equal to 0.4 eV.

3. The semiconductor device according to claim 2, characterized in that The band gap of the semiconductor graphene layer is greater than or equal to 0.6 eV.

4. The semiconductor device according to claim 1, wherein: The side of the silicon carbide semiconductor body close to the electrode setting surface includes a first region, a first well region, a second region, a second well region, a third region and a third well region; the first region and the first well region are located in the first device region and have opposite conductivity types, the second region and the second well region are located in the first conductivity type device region and have opposite conductivity types, and the third region and the third well region are located in the second conductivity type device region and have opposite conductivity types; The first semiconductor graphene layer is connected to the two first regions; the second semiconductor graphene layer is located and connected to the two second regions; and the third semiconductor graphene layer is connected to the two third regions.

5. The semiconductor device according to claim 1, wherein: The semiconductor graphene layer and the silicon carbide semiconductor body are connected in order through covalent bonds.

6. The semiconductor device according to claim 1, wherein: The operating voltage of the silicon carbide metal-oxide semiconductor field effect transistor is greater than the operating voltage of the silicon carbide complementary metal oxide semiconductor; A first isolation region is provided between the silicon carbide semiconductor body between the first device region and the second device region; and a second isolation region is provided between the first conductive type device region and the second conductive type device region.

7. The semiconductor device according to claim 4, characterized in that The semiconductor device further comprises: a first insulating layer, located on the electrode setting surface; a first electrode, located on a side of the first insulating layer away from the silicon carbide semiconductor body, and located in the first device region; a second electrode, located on a side of the first insulating layer away from the silicon carbide semiconductor body, and located in the first conductive type device region; a third electrode, located on a side of the first insulating layer away from the silicon carbide semiconductor body, and located in the second conductive type device region; A fourth electrode and a fifth electrode, located in the first device region and connected to the two first regions respectively; A sixth electrode and a seventh electrode are located in the first conductive type device region and are connected to the two second regions respectively; The eighth electrode and the ninth electrode are located in the second conductive type device region and are connected to the two third regions respectively.

8. The semiconductor device according to claim 4, characterized in that: The first region is located on the electrode setting surface, and the first well region is located between two of the first regions; The second region is located on the electrode setting surface, and the second well region is located between two second regions; The third region is located on the electrode setting surface, and the third well region is located between two of the third regions.

9. The semiconductor device according to claim 1, wherein: The number of the first device regions includes a plurality; the number of the second device regions includes a plurality; Along the first direction, the first device region and the second device region are arranged at intervals; Alternatively, along the first direction, at least two of the first device regions are arranged continuously; and at least two of the second device regions are arranged continuously.

10. The semiconductor device according to claim 9, characterized in that The second device region includes S first conductivity type device regions and Q second conductivity type device regions, wherein S includes an integer greater than or equal to 1, and Q includes an integer greater than or equal to 1; Along the first direction, the first conductive type device region and the second conductive type device region are arranged at intervals; Alternatively, the S includes an integer greater than or equal to 2, and at least two first conductive type device regions are continuously arranged along the first direction; the Q includes an integer greater than or equal to 2, and at least two second conductive type device regions are continuously arranged along the first direction.

11. The semiconductor device according to claim 1, wherein: The semiconductor graphene layer further includes a fourth semiconductor graphene layer; The silicon carbide semiconductor body comprises a first silicon carbide semiconductor body and a second silicon carbide semiconductor body; The first silicon carbide semiconductor body is used to support the second silicon carbide semiconductor body; The fourth semiconductor graphene layer is located between the first silicon carbide semiconductor body and the second silicon carbide semiconductor body, and the fourth semiconductor graphene layer and the first silicon carbide semiconductor body are orderly connected through covalent bonds.

12. The semiconductor device according to claim 1 or 11, characterized in that: The semiconductor device further includes a protection layer, wherein the protection layer covers the semiconductor graphene layer.

13. The semiconductor device according to claim 12, characterized in that The protective layer includes a gold protective layer or an aluminum oxide protective layer.

14. The semiconductor device according to claim 4, characterized in that The silicon carbide semiconductor body further includes a fourth region, a fifth region and a sixth region; The fourth region is located on the electrode setting surface, connected to the first region, and located in the first device region; The fifth region is located on the electrode setting surface, connected to the second region, and located in the first conductive type device region; The sixth region is located on the electrode setting surface, connected to the third region, and located in the second conductive type device region.

15. The semiconductor device according to claim 4, characterized in that The silicon carbide semiconductor body comprises a first drift layer, a second drift layer and a third drift layer which are stacked in sequence, and a surface of the third drift layer away from the second drift layer is the electrode setting surface; The first drift layer is set to a first conductivity type, the second drift layer is set to a second conductivity type, and the third drift layer is set to a first conductivity type.

16. The semiconductor device according to claim 15, characterized in that The area of ​​the third drift layer close to the electrode setting surface is reused as a well region of the first conductivity type among the first well region, the second well region and the third well region.

17. The semiconductor device according to claim 4, characterized in that The first semiconductor graphene layer and the first region have the same conductivity type, the second semiconductor graphene layer and the second region have the same conductivity type, and the third semiconductor graphene layer and the third region have the same conductivity type.

18. A method for manufacturing a semiconductor device, characterized in that: include: A silicon carbide semiconductor body is provided, wherein the silicon carbide semiconductor body comprises a first device region and a second device region spaced apart along a first direction, wherein the first direction is perpendicular to a thickness direction of the silicon carbide semiconductor body; the second device region comprises a first conductivity type device region and a second conductivity type device region spaced apart along the first direction; and the silicon carbide semiconductor body comprises an electrode setting surface; Forming a first semiconductor graphene layer, a second semiconductor graphene layer and a third semiconductor graphene layer located on the surface where the electrode is set in the semiconductor graphene layer, so as to improve the mobility of the semiconductor device, wherein at the same preset temperature, the mobility of the semiconductor graphene layer is greater than the mobility of silicon carbide; The first semiconductor graphene layer is located on the electrode setting surface of the first device region, the second semiconductor graphene layer is located on the electrode setting surface of the first conductive type device region, and the third semiconductor graphene layer is located on the electrode setting surface of the second conductive type device region; In the semiconductor device, the portion located in the first device region is a silicon carbide metal-oxide semiconductor field effect transistor whose conduction current direction is the first direction, and the portion located in the second device region is a silicon carbide complementary metal oxide semiconductor. The silicon carbide complementary metal oxide semiconductor includes a first conductivity type silicon carbide metal-oxide semiconductor field effect transistor located in the first conductivity type device region and whose conduction current direction is the first direction, and a second conductivity type silicon carbide metal-oxide semiconductor field effect transistor located in the second conductivity type device region and whose conduction current direction is the first direction. The silicon carbide metal-oxide semiconductor field effect transistor and the silicon carbide complementary metal oxide semiconductor have different operating voltages.

19. The method for manufacturing a semiconductor device according to claim 18, wherein: The band gap of the semiconductor graphene layer is greater than or equal to 0.4 eV.

20. The method for manufacturing a semiconductor device according to claim 19, wherein: The band gap of the semiconductor graphene layer is greater than or equal to 0.6 eV.

21. The method for manufacturing a semiconductor device according to claim 18, wherein: Providing silicon carbide semiconductor bodies includes: providing a first silicon carbide semiconductor body; forming a fourth semiconductor graphene layer on one side of the first silicon carbide semiconductor body, wherein the semiconductor graphene layer further comprises the fourth semiconductor graphene layer; A second silicon carbide semiconductor body is formed on a side of the fourth semiconductor graphene layer away from the first silicon carbide semiconductor body; the silicon carbide semiconductor body includes the first silicon carbide semiconductor body and the second silicon carbide semiconductor body.

22. The method for manufacturing a semiconductor device according to claim 18, wherein: Forming a semiconducting graphene layer includes: The silicon carbide semiconductor body is heated to a preset temperature so that silicon of the silicon carbide semiconductor body evaporates, thereby forming a semiconductor graphene layer on one side of the silicon carbide semiconductor body.

23. The method for manufacturing a semiconductor device according to claim 22, wherein: Heating the silicon carbide semiconductor body to a preset temperature so that silicon of the silicon carbide semiconductor body evaporates, thereby forming a semiconductor graphene layer on one side of the silicon carbide semiconductor body comprises: Arranging the silicon carbide semiconductor layer and one side of the silicon carbide semiconductor body opposite to each other; Heating one side of the silicon carbide semiconductor body and the silicon carbide semiconductor layer to a preset temperature so that the carbon surface of the silicon carbide semiconductor layer and one side of the silicon carbide semiconductor body provide a quasi-equilibrium condition established between the carbon surface and the silicon surface at the preset temperature; wherein the surface of one side of the silicon carbide semiconductor body is a silicon surface; Silicon on one side of the silicon carbide semiconductor body is evaporated, thereby forming the semiconductor graphene layer on the one side of the silicon carbide semiconductor body.

24. The method for manufacturing a semiconductor device according to claim 18 or 22, characterized in that: After forming the semiconductor graphene layer, the method further comprises: A protection layer is formed on a side of the semiconductor graphene layer away from the silicon carbide semiconductor body.

25. A power module, characterized in that: It comprises a substrate and the semiconductor device according to any one of claims 1 to 17, wherein the substrate is used to carry the semiconductor device.

26. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of claims 1 to 17, wherein the semiconductor device is electrically connected to the circuit board.

27. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 26, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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