Semiconductor device and manufacturing method thereof, power module, power conversion circuit, and vehicle

Abstract

The embodiment of the invention discloses a semiconductor device, a manufacturing method, a power module, a power conversion circuit and a vehicle. The semiconductor device includes a silicon carbide semiconductor body; the silicon carbide semiconductor body comprises a first device region and a second device region; the first semiconductor graphene layer is located on the electrode setting surface of the first device area; the second semiconductor graphene layer is located on the electrode setting surface of the second device area; at the same preset temperature, the mobility of the first semiconductor graphene layer and the mobility of the second semiconductor graphene layer are both larger than the mobility of silicon carbide. The first semiconductor graphene layer and the second semiconductor graphene layer are used for improving the mobility of the semiconductor device. According to the technical scheme of the embodiment of the invention, the channel mobility of the NMOS and the PMOS is improved, and the problem that the mobility of carriers of the NMOS and the PMOS is different is solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Wide bandgap semiconductor materials such as silicon carbide (SiC) are widely used in power electronics, automobiles, aerospace and other fields due to their excellent high temperature performance, chemical stability and electronic properties. They have superior performance in wide temperature range, high power and high switching frequency applications. The development of SiC integrated circuits (ICs) that integrate control systems and semiconductor devices on a single chip is crucial to fully realize the potential of SiC.

[0003] Silicon carbide complementary metal oxide semiconductor (CMOS) technology can ensure low power consumption and maintain a certain logic level at different temperatures. SiC CMOS consists of n-channel metal oxide semiconductor (MOS) and p-channel MOS.

[0004] However, the main challenge in preparing CMOS is the low channel mobility of NMOS and PMOS, and the difference in mobility between NMOS and PMOS carriers, which seriously hinders the potential of SiC in improving system power density and switching performance. Summary of the invention

[0005] The present invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle, so as to improve the channel mobility of NMOS and PMOS and solve the problem of the difference in mobility between NMOS and PMOS carriers.

[0006] According to one aspect of the present invention, there is provided a semiconductor device, comprising:

[0007] A silicon carbide semiconductor body, the silicon carbide semiconductor body comprising an electrode setting surface, the silicon carbide semiconductor body being set to a first conductivity type; the silicon carbide semiconductor body further comprising a first device region and a second device region;

[0008] A first semiconductor graphene layer, located on the electrode setting surface of the first device region, is used to improve the mobility of the semiconductor device, and at the same preset temperature, the mobility of the first semiconductor graphene layer is greater than the mobility of silicon carbide;

[0009] A second semiconductor graphene layer, located on the electrode setting surface of the second device region, is used to improve the mobility of the semiconductor device, and at the same preset temperature, the mobility of the second semiconductor graphene layer is greater than the mobility of silicon carbide;

[0010] In the semiconductor device, the portion located in the first device area is a first conductivity type silicon carbide metal-oxide semiconductor field effect transistor whose conduction current direction is the first direction, and the portion located in the second device area is a second conductivity type silicon carbide metal-oxide semiconductor field effect transistor whose conduction current direction is the first direction. The first conductivity type silicon carbide metal-oxide semiconductor field effect transistor and the second conductivity type silicon carbide metal-oxide semiconductor field effect transistor together constitute a silicon carbide complementary metal oxide semiconductor; the first direction is perpendicular to the thickness direction of the silicon carbide semiconductor body.

[0011] Optionally, the band gap of the first semiconductor graphene layer and the second semiconductor graphene layer is greater than or equal to 0.4 eV.

[0012] Optionally, the band gap of the first semiconductor graphene layer and the second semiconductor graphene layer is greater than or equal to 0.6 eV.

[0013] Optionally, the first device region includes a first region and a well region; the first region is set to a first conductivity type and is located on the electrode setting surface, and the well region is set to a second conductivity type and is located between the two first regions; the second device region includes a second region, and the second region is set to a second conductivity type and is located on the electrode setting surface;

[0014] The first semiconductor graphene layer is connected to the two first regions;

[0015] The second semiconductor graphene layer is connected to the two second regions.

[0016] Optionally, the first semiconductor graphene layer and the silicon carbide semiconductor body are orderly connected via covalent bonds; and / or, the second semiconductor graphene layer and the silicon carbide semiconductor body are orderly connected via covalent bonds.

[0017] Optionally, the semiconductor device further comprises:

[0018] A first insulating layer is located on the surface where the electrode is set;

[0019] A first electrode is located in the first device region and on a side of the first insulating layer away from the first semiconductor graphene layer;

[0020] A second electrode is located in the second device region and on a side of the first insulating layer away from the second semiconductor graphene layer;

[0021] The third electrode and the fourth electrode are located in the first device region and on the electrode setting surface, and are connected to the two first regions respectively;

[0022] The fifth electrode and the sixth electrode are located in the second device region and on the electrode setting surface, and are connected to the two second regions respectively.

[0023] Optionally, the first semiconductor graphene layer is set to a first conductivity type;

[0024] And / or, the second semiconductor graphene layer is set to the second conductivity type.

[0025] Optionally, the semiconductor device further includes a first protective layer, and the first protective layer is located on a side of the first semiconductor graphene layer away from the silicon carbide semiconductor body;

[0026] And / or, further comprising a second protective layer, wherein the second protective layer is located on a side of the second semiconductor graphene layer away from the silicon carbide semiconductor body.

[0027] Optionally, the first protective layer includes a gold protective layer or an aluminum oxide protective layer; the second protective layer includes a gold protective layer or an aluminum oxide protective layer.

[0028] Optionally, there are multiple first device regions and multiple second device regions.

[0029] According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising:

[0030] Providing a silicon carbide semiconductor body, the silicon carbide semiconductor body comprising an electrode setting surface, the silicon carbide semiconductor body being set to a first conductivity type; the silicon carbide semiconductor body further comprising a first device region and a second device region;

[0031] A first semiconductor graphene layer is formed on the surface where the electrode is set, the first semiconductor graphene layer is located in the first device region, and is used to improve the mobility of the semiconductor device, and at the same preset temperature, the mobility of the first semiconductor graphene layer is greater than the mobility of silicon carbide;

[0032] A second semiconductor graphene layer is formed on the surface where the electrode is set. The second semiconductor graphene layer is located in the second device area and is used to improve the mobility of the semiconductor device. At the same preset temperature, the mobility of the second semiconductor graphene layer is greater than the mobility of silicon carbide. The portion located in the first device area is a first conductivity type silicon carbide metal-oxide semiconductor field effect transistor with a conduction current direction in the first direction, and the portion located in the second device area is a second conductivity type silicon carbide metal-oxide semiconductor field effect transistor with a conduction current direction in the first direction. The first conductivity type silicon carbide metal-oxide semiconductor field effect transistor and the second conductivity type silicon carbide metal-oxide semiconductor field effect transistor together constitute a silicon carbide complementary metal oxide semiconductor. The first direction is perpendicular to the thickness direction of the silicon carbide semiconductor body.

[0033] Optionally, the band gap of the first semiconductor graphene layer and the second semiconductor graphene layer is greater than or equal to 0.4 eV.

[0034] Optionally, the band gap of the first semiconductor graphene layer and the second semiconductor graphene layer is greater than or equal to 0.6 eV.

[0035] Optionally, forming a first semiconductor graphene layer on the electrode setting surface includes:

[0036] The electrode setting surface is heated to a preset temperature so that silicon on the electrode setting surface evaporates, thereby forming a first semiconductor graphene layer on the electrode setting surface;

[0037] Forming a second semiconductor graphene layer on the electrode setting surface includes:

[0038] The electrode setting surface is heated to a preset temperature so that silicon on the electrode setting surface evaporates, thereby forming a second semiconductor graphene layer on the electrode setting surface.

[0039] Optionally, heating the electrode setting surface to a preset temperature so that silicon on the electrode setting surface evaporates, thereby forming a first semiconductor graphene layer on the electrode setting surface includes:

[0040] Arranging the electrode arrangement surfaces of the first silicon carbide semiconductor layer and the silicon carbide semiconductor body opposite to each other;

[0041] The electrode setting surface is heated to a preset temperature so that the carbon surface of the first silicon carbide semiconductor layer and the electrode setting surface provide a quasi-equilibrium condition between the carbon surface and the silicon surface at the preset temperature; wherein the electrode setting surface is the silicon surface;

[0042] The silicon on the electrode setting surface is evaporated, thereby forming a first semiconductor graphene layer on the electrode setting surface;

[0043] The step of heating the electrode setting surface to a preset temperature so that silicon on the electrode setting surface evaporates, thereby forming a second semiconductor graphene layer on the electrode setting surface comprises:

[0044] Arranging the second silicon carbide semiconductor layer and the electrode arrangement surface of the silicon carbide semiconductor body opposite to each other;

[0045] The electrode setting surface is heated to a preset temperature so that the carbon surface of the second silicon carbide semiconductor layer and the electrode setting surface provide a quasi-equilibrium condition between the carbon surface and the silicon surface at the preset temperature; wherein the electrode setting surface is the silicon surface;

[0046] The silicon on the electrode setting surface is evaporated, thereby forming a second semiconductor graphene layer on the electrode setting surface.

[0047] Optionally, after forming the first semiconductor graphene layer on the electrode setting surface, the method further includes:

[0048] Forming a first protective layer on a side of the first semiconductor graphene layer away from the silicon carbide semiconductor body;

[0049] and / or,

[0050] After forming a second semiconductor graphene layer on the electrode setting surface, the method further includes:

[0051] A second protective layer is formed on a side of the second semiconductor graphene layer away from the silicon carbide semiconductor body.

[0052] According to another aspect of the present invention, a power module is provided, comprising a substrate and at least one semiconductor device according to any one of the embodiments of the present invention, wherein the substrate is used for carrying the semiconductor device.

[0053] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0054] The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of the embodiments of the present invention, wherein the semiconductor device is electrically connected to the circuit board.

[0055] According to another aspect of the present invention, a vehicle is provided, comprising a load and a power conversion circuit as in any embodiment of the present invention, wherein the power conversion circuit is used to convert AC and / or DC power into AC and / or DC power and then input the converted power into the load.

[0056] According to the technical solution of the embodiment of the present invention, in a SiC complementary metal oxide semiconductor (CMOS) device composed of a first conductive type SiC MOSFET and a second conductive type SiC MOSFET, the first semiconductor graphene layer is located in a conduction channel under a first electrode in the first conductive type SiC MOSFET, and the second semiconductor graphene layer is located in a conduction channel under a second electrode in the second conductive type SiC MOSFET, which helps to improve the mobility of the semiconductor device. Since the first semiconductor graphene layer and the second semiconductor graphene layer have high strength, high thermal conductivity, mobility greater than that of silicon carbide and semiconductor properties, the same mobility of holes and electrons in the conduction channel is ensured, and the uniformity problem of the channel mobility of the first conductive type SiC MOSFET and the second conductive type SiC MOSFET is effectively solved, and the uniformity of the switching speed of the first conductive type channel and the second conductive type channel, the overall efficiency and thermal management efficiency are improved, so that the semiconductor device has a faster response speed.

[0057] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0059] Figure 1 is a schematic structural diagram of a semiconductor device provided according to an embodiment of the present invention;

[0060] Figure 2 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0061] Figure 3-Figure 5 is a cross-sectional view corresponding to each step of a method for manufacturing a semiconductor device provided according to an embodiment of the present invention;

[0062] Figure 6 yes Figure 2 A schematic diagram of the process included in S120 and S130;

[0063] Figure 7 yes Figure 6 The schematic diagram of the process included in S1201;

[0064] Figure 8 yes Figure 6 The schematic diagram of the process included in S1301;

[0065] Fig. 9 yes Figure 7 and Figure 8 Schematic diagram of the structure of the relevant steps in . DETAILED DESCRIPTION

[0066] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0067] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0068] To solve the problem that the channel mobility of NMOS and PMOS is low and the mobility of carriers of NMOS and PMOS is different, the embodiment of the present invention provides the following technical solutions:

[0069] Figure 1 1 is a schematic diagram of the structure of a semiconductor device provided according to an embodiment of the present invention. Figure 1 As shown, the semiconductor device includes: a silicon carbide semiconductor body 100, the silicon carbide semiconductor body 100 includes an electrode setting surface 101, and the silicon carbide semiconductor body 100 is set to a first conductivity type; the silicon carbide semiconductor body 100 also includes a first device region 200 and a second device region 300; a first semiconductor graphene layer 400, located on the electrode setting surface 101 of the first device region 200, for improving the mobility of the semiconductor device, and at the same preset temperature, the mobility of the first semiconductor graphene layer 400 is greater than the mobility of silicon carbide; a second semiconductor graphene layer 500, located on the electrode setting surface 101 of the second device region 300, for improving the mobility of the semiconductor device, and At the same preset temperature, the mobility of the second semiconductor graphene layer 500 is greater than the mobility of silicon carbide; in the semiconductor device, the portion located in the first device area 200 is a first conductivity type silicon carbide metal-oxide semiconductor field effect transistor with a conduction current direction in the first direction, and the portion located in the second device area 300 is a second conductivity type silicon carbide metal-oxide semiconductor field effect transistor with a conduction current direction in the first direction, and the first conductivity type silicon carbide metal-oxide semiconductor field effect transistor and the second conductivity type silicon carbide metal-oxide semiconductor field effect transistor together constitute a silicon carbide complementary metal oxide semiconductor; the first direction is perpendicular to the thickness direction of the silicon carbide semiconductor body 100.

[0070] In the embodiment of the present invention, the silicon carbide semiconductor body 100 may include a substrate and an epitaxial layer, or may include only an epitaxial layer. The epitaxial layer is a semiconductor layer formed by a single epitaxial process, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0071] In an embodiment of the present invention, if the first conductivity type is N-type, the second conductivity type is P-type; if the first conductivity type is P-type, the second conductivity type is N-type. The embodiment of the present invention is described by taking the first conductivity type as N-type as an example. The conductivity type of the silicon carbide semiconductor body 100 is set to N-type. The first conductivity type silicon carbide metal-oxide semiconductor field effect transistor is an N-type silicon carbide metal-oxide semiconductor field effect transistor, and the second conductivity type silicon carbide metal-oxide semiconductor field effect transistor is a P-type silicon carbide metal-oxide semiconductor field effect transistor.

[0072] It should be noted that the mobility of the same semiconductor material will change with the change of temperature. In the embodiment of the present invention, it is defined that at the same preset temperature, the mobility of the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 is greater than the mobility of silicon carbide. That is, at the same preset temperature, the resistance to electron movement in the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 is less than the resistance to movement of carriers in silicon carbide, wherein, in the first device region 200, in the first conductive type silicon carbide metal-oxide semiconductor field effect transistor with the on-current direction in the first direction, under the control of the gate, the on-current flows from the source to the drain through the first semiconductor graphene layer 400. In the second device region 300, in the second conductive type silicon carbide metal-oxide semiconductor field effect transistor with the on-current direction in the first direction, under the control of the gate, the on-current flows from the source to the drain through the second semiconductor graphene layer 500. The provision of the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 significantly increases the channel carrier mobility in the semiconductor device, thereby reducing the on-resistance of the semiconductor device, while ensuring the same hole and electron mobility in the conduction channel.

[0073] It should be noted that the mobility of the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 depends on the growth quality of the material and can be from tens of cm 2 / Vs to 5000cm 2 Preferably, the mobility of the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 at room temperature is greater than or equal to 1000 cm 2 / Vs, even up to 5500cm 2 / Vs. Room temperature is also called normal temperature or general temperature, generally defined as 25 degrees Celsius, sometimes set to 300K (about 27 degrees Celsius). The mobility required by semiconductor devices is only a few tens of cm 2 Therefore, the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 can significantly improve the mobility of the semiconductor device.

[0074] According to the technical solution provided by the embodiment of the present invention, in a SiC complementary metal oxide semiconductor (CMOS) device composed of a first conductive type SiC MOSFET and a second conductive type SiC MOSFET, the first semiconductor graphene layer 400 is located in the conduction channel under the first electrode 602 in the first conductive type SiC MOSFET, which helps to improve the mobility of the semiconductor device, and the second semiconductor graphene layer 500 is located in the conduction channel under the second electrode 702 in the second conductive type SiC MOSFET, which helps to improve the mobility of the semiconductor device. Since the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 have high strength, high thermal conductivity, mobility greater than that of silicon carbide and semiconductor properties, the same mobility of holes and electrons in the conduction channel is ensured, and the uniformity problem of the channel mobility of the first conductive type SiC MOSFET and the second conductive type SiC MOSFET is effectively solved, and the uniformity of the switching speed of the first conductive type channel and the second conductive type channel is improved, and the overall efficiency and thermal management efficiency are improved, so that the semiconductor device has a faster response speed.

[0075] Optional, such as Figure 1 As shown, the band gaps of the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 are greater than or equal to 0.4 eV. Figure 1 As shown, the band gaps of the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 are greater than or equal to 0.6 eV.

[0076] Specifically, since the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 have high strength, high thermal conductivity, mobility greater than that of silicon carbide and semiconductor properties, their band gap is greater than or equal to 0.4 eV, preferably greater than or equal to 0.6 eV, and their mobility is preferably greater than or equal to 1000 cm 2 / Vs, even up to 5500cm 2 / Vs, ensuring the same hole and electron mobility in the conduction channel, effectively solving the uniformity problem of the channel mobility of the first conductivity type SiC MOSFET and the second conductivity type SiC MOSFET, improving the switching speed uniformity of the first conductivity type channel and the second conductivity type channel, the overall efficiency and thermal management efficiency, making the semiconductor device have a faster response speed. Optional, such as Figure 1 As shown, the first device region 200 includes a first region 201 and a well region 202; the first region 201 is set to the first conductivity type and is located on the electrode setting surface 101, and the well region 202 is set to the second conductivity type and is located between the two first regions 201; the second device region 300 includes a second region 301, and the second region 301 is set to the second conductivity type and is located on the electrode setting surface 101; the first semiconductor graphene layer 400 is connected to the two first regions 201; and the second semiconductor graphene layer 500 is connected to the two second regions 301.

[0077] In the embodiment of the present invention, the first region 201 in the first device region 200 is an N+ active region, and the well region 202 is a P-type well region. The first device region 200 also includes a third region 203, wherein the third region 203 is a P+ active region. The first device region 200 also includes a first semiconductor graphene layer 400. The first semiconductor graphene layer 400 is connected to the two first regions 201. The second region 301 in the second device region 300 is a P+ active region. The second device region 300 also includes a fourth region 302. The fourth region 302 is an N+ active region. The second device region 300 also includes a second semiconductor graphene layer 500. The second semiconductor graphene layer 500 is connected to the two second regions 301. The above technical solution clearly gives the specific positions of the semiconductor graphene layers in the first conductive type SiC MOSFET with a first direction of conduction current and the second conductive type SiC MOSFET with a first direction of conduction current in the CMOS planar device.

[0078] In a first conductivity type silicon carbide metal-oxide semiconductor field effect transistor (first conductivity type SiC MOSFET) whose conduction current direction is the first direction, under the control of the gate, the conduction current flows from the source to the drain through the first region 201, the first semiconductor graphene layer 400 and the first region 201. In a second conductivity type silicon carbide metal-oxide semiconductor field effect transistor (second conductivity type SiC MOSFET) whose conduction current direction is the first direction, under the control of the gate, the conduction current flows from the source to the drain through the second region 301, the second semiconductor graphene layer 500 and the second region 301.

[0079] Optional, such as Figure 1 As shown, the first semiconductor graphene layer 400 and the silicon carbide semiconductor body 100 are orderly connected through covalent bonds; and / or, the second semiconductor graphene layer 500 and the silicon carbide semiconductor body 100 are orderly connected through covalent bonds.

[0080] In the embodiment of the present invention, the first semiconductor graphene layer 400 is connected to the silicon carbide semiconductor body 100 by covalent bonding during the growth process, and there is no need to form a bonding layer, which simplifies the preparation process and reduces the preparation cost. The first semiconductor graphene layer 400 is a two-dimensional semiconductor material. The first semiconductor graphene layer 400 and the silicon carbide semiconductor body 100 are orderly bonded by covalent bonds. The first semiconductor graphene layer 400 has a very high mobility. Therefore, the technical solution of forming the first semiconductor graphene layer 400 greatly increases the channel carrier mobility in the semiconductor device, thereby reducing the on-resistance of the semiconductor device.

[0081] The second semiconductor graphene layer 500 is connected to the silicon carbide semiconductor body 100 by covalent bonding during the growth process, and there is no need to form a bonding layer, which simplifies the preparation process and reduces the preparation cost. The second semiconductor graphene layer 500 is a two-dimensional semiconductor material. The second semiconductor graphene layer 500 and the silicon carbide semiconductor body 100 are orderly bonded by covalent bonds. The second semiconductor graphene layer 500 has a very high mobility. Therefore, the technical solution of forming the second semiconductor graphene layer 500 greatly increases the channel carrier mobility in the semiconductor device, thereby reducing the on-resistance of the semiconductor device.

[0082] Since the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 have high strength, high thermal conductivity, mobility greater than that of silicon carbide and semiconductor properties, their band gap is greater than or equal to 0.4 eV, preferably greater than or equal to 0.6 eV, and their mobility is preferably greater than or equal to 1000 cm 2 / Vs, even up to 5500cm 2 / Vs, ensuring the same hole and electron mobility in the conduction channel, effectively solving the uniformity problem of the channel mobility of the first conductivity type SiC MOSFET and the second conductivity type SiC MOSFET, improving the switching speed uniformity of the first conductivity type channel and the second conductivity type channel, the overall efficiency and thermal management efficiency, and making the semiconductor device have a faster response speed.

[0083] Optional, such as Figure 1As shown, the semiconductor device also includes: a first insulating layer 601, located on the electrode setting surface 101; a first electrode 602, located in the first device region 200, and located on the side of the first insulating layer 601 away from the first semiconductor graphene layer 400; a second electrode 702, located in the second device region 300, and located on the side of the first insulating layer 601 away from the second semiconductor graphene layer 500; a third electrode 603 and a fourth electrode 604, located in the first device region 200, and located on the electrode setting surface 101, and respectively connected to the two first regions 201; a fifth electrode 703 and a sixth electrode 704, located in the second device region 300, and located on the electrode setting surface 101, and respectively connected to the two second regions 301.

[0084] Specifically, in the first device region 200, in the first conductive type silicon carbide metal-oxide semiconductor field effect transistor with the on-current direction being the first direction, under the control of the first electrode 602, the on-current flows from the third electrode 603 to the fourth electrode 604 through the first semiconductor graphene layer 400. Exemplarily, the third electrode 603 is the source and the fourth electrode 604 is the drain. In the second device region 300, in the second conductive type silicon carbide metal-oxide semiconductor field effect transistor with the on-current direction being the first direction, under the control of the second electrode 702, the on-current flows from the fifth electrode 703 to the sixth electrode 704 through the second semiconductor graphene layer 500. Exemplarily, the fifth electrode 703 is the source and the sixth electrode 704 is the drain. The provision of the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 significantly increases the channel carrier mobility in the semiconductor device, thereby reducing the on-resistance of the semiconductor device, while ensuring the same hole and electron mobility in the conduction channel, effectively solving the uniformity problem of the channel mobility of the first conductive type SiC MOSFET and the second conductive type SiC MOSFET, improving the switching speed uniformity of the first conductive type channel and the second conductive type channel, the overall efficiency and the thermal management efficiency, so that the semiconductor device has a faster response speed.

[0085] In the embodiment of the present invention, the first insulating layer 601 may be a gate oxide layer. The first electrode 602 may be a polysilicon gate. The second electrode 702 may be a polysilicon gate. The third electrode 603 and the fourth electrode 604 are the source and the drain located in the first device region 200, respectively; the fifth electrode 703 and the sixth electrode 704 are the source and the drain located in the second device region 300, respectively.

[0086] Optional, such as Figure 1 As shown, a second insulating layer 800 is also included to insulate the gate and the source as well as the gate and the drain.

[0087] Optional, Figure 1In the embodiment, the silicon carbide semiconductor body 100 includes a plurality of drift layers stacked in sequence. Figure 1 Since the silicon carbide semiconductor body 100 is of the first conductivity type, which is the same conductivity type as the inversion layer of the second conductivity type SiCMOS, the second conductivity type SiC MOS located in the second device region 300 does not need to be provided with a well region.

[0088] For example, under the same selected room temperature conditions, the maximum room temperature mobility of the first semiconductor graphene layer 400 can reach 5500 cm 2 V -1 s -1 , greatly increasing the channel carrier mobility in the semiconductor device, thereby reducing the on-resistance of the semiconductor device. The room temperature mobility of the second semiconductor graphene layer 500 is the same as that of the first semiconductor graphene layer 400.

[0089] Optionally, based on the above technical solution, refer to Figure 1 , the first semiconductor graphene layer 400 is set to the first conductivity type; and / or, the second semiconductor graphene layer 500 is set to the second conductivity type.

[0090] Specifically, in the first conductivity type SiC MOS device, the first semiconductor graphene layer 400 is set to the first conductivity type, and is the same as the carrier conductivity type in the channel, further increasing the carrier concentration of the device. In the second conductivity type SiC MOS device, the second semiconductor graphene layer 500 is set to the second conductivity type, and is the same as the carrier conductivity type in the channel, further increasing the carrier concentration of the device.

[0091] Optionally, based on the above technical solution, refer to Figure 1 The semiconductor device further includes a first protective layer 401, which is located on a side of the first semiconductor graphene layer 400 away from the silicon carbide semiconductor body 100; and / or further includes a second protective layer 501, which is located on a side of the second semiconductor graphene layer 500 away from the silicon carbide semiconductor body 100.

[0092] Specifically, the first protective layer 401 is a thin film formed by an atomic layer deposition process, which is used to protect the first semiconductor graphene layer 400 away from the surface of the silicon carbide semiconductor body 100, avoiding damage to the first semiconductor graphene layer 400 during epitaxy and formation of subsequent film layers, thereby ensuring that the first semiconductor graphene layer 400 has high mobility, thereby increasing the structural stability of the semiconductor device.

[0093] Optionally, the first protective layer 401 is relatively thin, and the minimum thickness of the first protective layer 401 is 5 nm, which has little effect on the on-resistance of the semiconductor device while protecting the first semiconductor graphene layer 400 away from the surface of the silicon carbide semiconductor body 100 .

[0094] The second protective layer 501 is a thin film formed by an atomic layer deposition process, which is used to protect the second semiconductor graphene layer 500 away from the surface of the silicon carbide semiconductor body 100 to avoid damage to the second semiconductor graphene layer 500 during epitaxy and formation of subsequent film layers, thereby ensuring that the second semiconductor graphene layer 500 has high mobility, thereby increasing the structural stability of the semiconductor device.

[0095] Optionally, the second protective layer 501 is relatively thin, and the minimum thickness of the second protective layer 501 is 5 nm, which has little effect on the on-resistance of the semiconductor device while protecting the second semiconductor graphene layer 500 away from the surface of the silicon carbide semiconductor body 100 .

[0096] Optional, reference Figure 1 The first protective layer 401 includes a gold protective layer or an aluminum oxide protective layer; the second protective layer 501 includes a gold protective layer or an aluminum oxide protective layer.

[0097] Specifically, the gold protective layer or the aluminum oxide protective layer has stable physical and chemical properties, and can protect the first semiconductor graphene layer 400 away from the surface of the silicon carbide semiconductor body 100, and protect the second semiconductor graphene layer 500 away from the surface of the silicon carbide semiconductor body 100, thereby avoiding damage to the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 during epitaxy and formation of subsequent film layers.

[0098] Optional, reference Figure 1 , the number of the first device regions 200 is multiple, and the number of the second device regions 300 is multiple.

[0099] An embodiment of the present invention also provides a method for manufacturing a semiconductor device. Figure 2 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 2 As shown, the method for manufacturing the semiconductor device includes:

[0100] S110, providing a silicon carbide semiconductor body, wherein the silicon carbide semiconductor body includes an electrode setting surface, and the silicon carbide semiconductor body is set to a first conductivity type; the silicon carbide semiconductor body also includes a first device region and a second device region.

[0101] refer to Figure 3, providing a silicon carbide semiconductor body 100, the silicon carbide semiconductor body 100 includes an electrode setting surface 101, and the silicon carbide semiconductor body 100 is set to a first conductivity type; the silicon carbide semiconductor body 100 also includes a first device region 200 and a second device region 300.

[0102] S120, forming a first semiconductor graphene layer on the surface of the electrode, wherein the first semiconductor graphene layer is located in the first device region and is used to improve the mobility of the semiconductor device, and at the same preset temperature, the mobility of the first semiconductor graphene layer is greater than the mobility of silicon carbide.

[0103] refer to Figure 4 A first semiconductor graphene layer 400 is formed on the electrode setting surface 101, the first semiconductor graphene layer 400 is located in the first device region 200, and at the same preset temperature, the mobility of the first semiconductor graphene layer 400 is greater than the mobility of silicon carbide.

[0104] S130, forming a second semiconductor graphene layer on the surface of the electrode, the second semiconductor graphene layer is located in the second device region, and is used to improve the mobility of the semiconductor device, and at the same preset temperature, the mobility of the second semiconductor graphene layer is greater than the mobility of silicon carbide.

[0105] refer to Figure 4 A second semiconductor graphene layer 500 is formed on the electrode setting surface 101, the second semiconductor graphene layer 500 is located in the second device region 300, and at the same preset temperature, the mobility of the second semiconductor graphene layer 500 is greater than the mobility of silicon carbide.

[0106] It should be noted that the mobility of the same semiconductor material will change with the change of temperature. In the embodiment of the present invention, it is defined that at the same preset temperature, the mobility of the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 is greater than the mobility of silicon carbide. That is, at the same preset temperature, the resistance to electron movement in the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 is less than the resistance to movement of carriers in silicon carbide, wherein, in the first device region 200, in the first conductive type silicon carbide metal-oxide semiconductor field effect transistor with the on-current direction in the first direction, under the control of the gate, the on-current flows from the source to the drain through the first semiconductor graphene layer 400. In the second device region 300, in the second conductive type silicon carbide metal-oxide semiconductor field effect transistor with the on-current direction in the first direction, under the control of the gate, the on-current flows from the source to the drain through the second semiconductor graphene layer 500. The provision of the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 significantly increases the channel carrier mobility in the semiconductor device, thereby reducing the on-resistance of the semiconductor device, while ensuring the same hole and electron mobility in the conduction channel.

[0107] It should be noted that the mobility of the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 depends on the growth quality of the material and can be from tens of cm 2 / Vs to 5000cm 2 Preferably, the mobility of the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 at room temperature is greater than or equal to 1000 cm 2 / Vs, even up to 5500cm 2 / Vs. Room temperature is also called normal temperature or general temperature, generally defined as 25 degrees Celsius, sometimes set to 300K (about 27 degrees Celsius). The mobility required by semiconductor devices is only a few tens of cm 2 Therefore, the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 can significantly improve the mobility of the semiconductor device.

[0108] According to the technical solution provided by the embodiment of the present invention, in a SiC complementary metal oxide semiconductor (CMOS) device composed of a first conductive type SiC MOSFET and a second conductive type SiC MOSFET, the first semiconductor graphene layer 400 is located in the conduction channel below the first electrode 602 in the first conductive type SiC MOSFET, which helps to improve the mobility of the semiconductor device, and the second semiconductor graphene layer 500 is located in the conduction channel below the second electrode 702 in the second conductive type SiC MOSFET, which helps to improve the mobility of the semiconductor device. Since the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 have high strength, high thermal conductivity, mobility greater than the mobility of silicon carbide and semiconductor properties, the same mobility of holes and electrons in the conduction channel is ensured, which effectively solves the problem of uniformity of the channel mobility of the first conductive type SiC MOSFET and the second conductive type SiC MOSFET, improves the uniformity of the switching speed of the first conductive type channel and the second conductive type channel, and improves the overall efficiency and thermal management efficiency, so that the semiconductor device has a faster response speed. Optionally, such as Figure 1 As shown, the band gaps of the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 are greater than or equal to 0.4 eV. Figure 1 As shown, the band gaps of the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 are greater than or equal to 0.6 eV.

[0109] Specifically, since the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 have high strength, high thermal conductivity, mobility greater than that of silicon carbide and semiconductor properties, their band gap is greater than or equal to 0.4 eV, preferably greater than or equal to 0.6 eV, and their mobility is preferably greater than or equal to 1000 cm 2 / Vs, ensuring the same hole and electron mobility in the conduction channel, effectively solving the uniformity problem of channel mobility of the first conductivity type SiC MOSFET and the second conductivity type SiC MOSFET, improving the switching speed uniformity of the first conductivity type channel and the second conductivity type channel, the overall efficiency and thermal management efficiency, and making the semiconductor device have a faster response speed.

[0110] In an optional embodiment of the present invention, Figure 6 yes Figure 2 The schematic diagram of the process included in S120 and S130. Figure 6 As shown, S120 forms a first semiconductor graphene layer on the electrode setting surface, including:

[0111] S1201, heating the electrode setting surface to a preset temperature, so that silicon on the electrode setting surface evaporates, thereby forming a first semiconductor graphene layer on the electrode setting surface.

[0112] refer to Figure 4 The electrode setting surface 101 is heated to a preset temperature so that the silicon on the electrode setting surface 101 evaporates, thereby forming a first semiconductor graphene layer 400 on the electrode setting surface 101, wherein the first semiconductor graphene layer 400 and the silicon carbide semiconductor body 100 are connected by covalent bonding.

[0113] Specifically, the preparation of the first semiconductor graphene layer 400 uses a heated electrode setting surface 101. During the heating process, silicon evaporates before carbon, so that the first semiconductor graphene layer 400 is spontaneously crystallized on the surface of the electrode setting surface 101. Among them, the first semiconductor graphene layer 400 is connected to the silicon carbide semiconductor body 100 through covalent bonding during the growth process, and there is no need to form a bonding layer, which simplifies the preparation process and reduces the preparation cost. The first semiconductor graphene layer 400 is a two-dimensional semiconductor material. The first semiconductor graphene layer 400 and the silicon carbide semiconductor body 100 are orderly bonded through covalent bonds. The first semiconductor graphene layer 400 has a very high mobility, thereby greatly increasing the channel carrier mobility in the semiconductor device, thereby reducing the on-resistance of the semiconductor device. And the first semiconductor graphene layer 400 also has the advantages of high strength and high thermal conductivity.

[0114] In an optional embodiment of the present invention, Figure 6 As shown, S130 forming a second semiconductor graphene layer on the electrode setting surface includes:

[0115] S1301, heating the electrode setting surface to a preset temperature, so that silicon on the electrode setting surface evaporates, thereby forming a second semiconductor graphene layer on the electrode setting surface.

[0116] refer to Figure 4 The electrode setting surface 101 is heated to a preset temperature so that the silicon on the electrode setting surface 101 evaporates, thereby forming a second semiconductor graphene layer 500 on the electrode setting surface 101, wherein the second semiconductor graphene layer 500 and the silicon carbide semiconductor body 100 are connected by covalent bonding.

[0117] Specifically, the preparation of the second semiconductor graphene layer 500 uses a heated electrode setting surface 101. During the heating process, silicon evaporates before carbon, so that the second semiconductor graphene layer 500 is spontaneously crystallized on the surface of the electrode setting surface 101. Among them, the second semiconductor graphene layer 500 is connected to the silicon carbide semiconductor body 100 through covalent bonding during the growth process, and there is no need to form a bonding layer, which simplifies the preparation process and reduces the preparation cost. The second semiconductor graphene layer 500 is a two-dimensional semiconductor material. The second semiconductor graphene layer 500 and the silicon carbide semiconductor body 100 are orderly bonded and connected through covalent bonds. The second semiconductor graphene layer 500 has a very high mobility, thereby greatly increasing the channel carrier mobility in the semiconductor device, thereby reducing the on-resistance of the semiconductor device. The second semiconductor graphene layer 500 also has the advantages of high strength and high thermal conductivity.

[0118] Optionally, based on the above technical solution, Figure 7 yes Figure 6 The process diagram included in S1201 is shown in FIG. Figure 7 As shown, S1201 heats the electrode setting surface to a preset temperature so that silicon on the electrode setting surface evaporates, thereby forming a first semiconductor graphene layer on the electrode setting surface, including:

[0119] S12011. Arrange the electrode setting surfaces of the first silicon carbide semiconductor layer and the silicon carbide semiconductor body relative to each other.

[0120] Specifically, refer to Fig. 9 , providing a first silicon carbide semiconductor layer 111 , and arranging the first silicon carbide semiconductor layer 111 and the electrode arrangement surface 101 of the silicon carbide semiconductor body 100 relative to each other.

[0121] S12012. Heat the electrode setting surface to a preset temperature so that the carbon surface of the first silicon carbide semiconductor layer and the electrode setting surface provide a quasi-equilibrium condition established between the carbon surface and the silicon surface at the preset temperature; wherein the electrode setting surface is the silicon surface.

[0122] refer to Fig. 9 , the electrode setting surface 101 of the silicon carbide semiconductor body 100 is heated to a preset temperature so that the carbon surface of the first silicon carbide semiconductor layer 111 and the electrode setting surface 101 provide a quasi-equilibrium condition established between the carbon surface and the silicon surface at the preset temperature; wherein the electrode setting surface 101 is the silicon surface.

[0123] S12013. Evaporating silicon on the electrode setting surface, thereby forming a first semiconductor graphene layer on the electrode setting surface.

[0124] refer to Fig. 9During the heating process, the silicon on the electrode setting surface 101 evaporates before the carbon, so that the first semiconductor graphene layer 400 is spontaneously crystallized on the electrode setting surface 101 .

[0125] Optionally, based on the above technical solution, Figure 8 yes Figure 6 The flow chart of S1301 is shown in FIG. Figure 8 As shown, S1301 heats the electrode setting surface to a preset temperature so that silicon on the electrode setting surface evaporates, thereby forming a second semiconductor graphene layer on the electrode setting surface, including:

[0126] S13011. Arrange the electrode setting surfaces of the second silicon carbide semiconductor layer and the silicon carbide semiconductor body relative to each other.

[0127] Specifically, refer to Fig. 9 , provide a second silicon carbide semiconductor layer 112 , and arrange the second silicon carbide semiconductor layer 112 and the electrode arrangement surface 101 of the silicon carbide semiconductor body 100 relative to each other.

[0128] S13012. Heat the electrode setting surface to a preset temperature so that the carbon surface of the second silicon carbide semiconductor layer and the electrode setting surface provide a quasi-equilibrium condition established between the carbon surface and the silicon surface at the preset temperature; wherein the electrode setting surface is the silicon surface.

[0129] refer to Fig. 9 , the electrode setting surface 101 of the silicon carbide semiconductor body 100 is heated to a preset temperature so that the carbon surface of the second silicon carbide semiconductor layer 112 and the electrode setting surface 101 provide a quasi-equilibrium condition established between the carbon surface and the silicon surface at the preset temperature; wherein the electrode setting surface 101 is the silicon surface.

[0130] S13013, evaporating silicon on the electrode setting surface, thereby forming a second semiconductor graphene layer on the electrode setting surface.

[0131] refer to Fig. 9 During the heating process, the silicon on the electrode setting surface 101 evaporates before the carbon, so that the second semiconductor graphene layer 500 is spontaneously crystallized on the electrode setting surface 101 .

[0132] Specifically, the first semiconductor graphene layer 400 and the second semiconductor graphene layer 500 are connected to the silicon carbide semiconductor body 100 by covalent bonding during the growth process, without the need to form a bonding layer, simplifying the preparation process and reducing the preparation cost. Since the carbon surface of the silicon carbide semiconductor layer and the surface of one side of the silicon carbide semiconductor body 100 provide a quasi-equilibrium condition established between the carbon surface and the silicon surface at a preset temperature, a semiconductor graphene layer with a thickness equal to the thickness of a single layer of carbon atoms can be formed on the surface of one side of the silicon carbide semiconductor body 100. In summary, the essence of the semiconductor graphene layer is a single layer of carbon atoms in the silicon carbide semiconductor body 100, and its thickness is equivalent to the thickness of a single layer of carbon atoms in the silicon carbide epitaxial layer. The thickness of the semiconductor graphene layer is greater than or equal to 0.2nm and less than or equal to 0.3nm, and its average thickness is about 0.25nm. The bonding between the semiconductor graphene layer and the silicon carbide semiconductor body 100 is orderly and periodically arranged, which can ensure that the semiconductor graphene layer is a two-dimensional semiconductor material. The band gap of the semiconductor graphene layer is smaller than the band gap of silicon, and its band gap is greater than or equal to 0.4 eV, preferably greater than or equal to 0.6 eV, and the mobility is preferably greater than or equal to 1000 cm 2 / Vs, even up to 5500cm 2 / Vs or so.

[0133] An embodiment of the present invention provides a power module, comprising a substrate and at least one semiconductor device according to any embodiment of the present invention, wherein the substrate is used to carry the semiconductor device. Therefore, the beneficial effects of the power module including any semiconductor device according to any embodiment of the present invention are not described in detail here.

[0134] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device described in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0135] Therefore, the power conversion circuit includes the beneficial effects of any semiconductor device described in any embodiment of the present invention, which will not be repeated here.

[0136] An embodiment of the present invention also provides a vehicle, which includes a load and the above-mentioned power conversion circuit, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0137] Therefore, the beneficial effects of the vehicle including any of the power conversion circuit packages described in any embodiment of the present invention will not be repeated here.

[0138] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0139] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A silicon carbide semiconductor body, the silicon carbide semiconductor body comprising an electrode setting surface, the silicon carbide semiconductor body being set to a first conductivity type; the silicon carbide semiconductor body further comprising a first device region and a second device region; A first semiconductor graphene layer, located on the electrode setting surface of the first device region, is used to improve the mobility of the semiconductor device, and at the same preset temperature, the mobility of the first semiconductor graphene layer is greater than the mobility of silicon carbide; A second semiconductor graphene layer, located on the electrode setting surface of the second device region, is used to improve the mobility of the semiconductor device, and at the same preset temperature, the mobility of the second semiconductor graphene layer is greater than the mobility of silicon carbide; In the semiconductor device, the portion located in the first device area is a first conductivity type silicon carbide metal-oxide semiconductor field effect transistor whose conduction current direction is a first direction, and the portion located in the second device area is a second conductivity type silicon carbide metal-oxide semiconductor field effect transistor whose conduction current direction is the first direction, and the first conductivity type silicon carbide metal-oxide semiconductor field effect transistor and the second conductivity type silicon carbide metal-oxide semiconductor field effect transistor together constitute a silicon carbide complementary metal oxide semiconductor; the first direction is perpendicular to the thickness direction of the silicon carbide semiconductor body.

2. The semiconductor device according to claim 1, wherein: The band gap of the first semiconductor graphene layer and the second semiconductor graphene layer is greater than or equal to 0.4 eV.

3. The semiconductor device according to claim 2, characterized in that The band gap of the first semiconductor graphene layer and the second semiconductor graphene layer is greater than or equal to 0.6 eV.

4. The semiconductor device according to claim 1, wherein: The first device region includes a first region and a well region; the first region is set to a first conductivity type and is located on the electrode setting surface, and the well region is set to a second conductivity type and is located between the two first regions; the second device region includes a second region, and the second region is set to a second conductivity type and is located on the electrode setting surface; The first semiconductor graphene layer is connected to the two first regions; The second semiconductor graphene layer is connected to the two second regions.

5. The semiconductor device according to claim 1, wherein: The first semiconductor graphene layer and the silicon carbide semiconductor body are orderly connected via covalent bonds; and / or the second semiconductor graphene layer and the silicon carbide semiconductor body are orderly connected via covalent bonds.

6. The semiconductor device according to claim 4, characterized in that The semiconductor device further comprises: A first insulating layer, located on the surface where the electrode is disposed; A first electrode, located in the first device region and located on a side of the first insulating layer away from the first semiconductor graphene layer; A second electrode, located in the second device region and located on a side of the first insulating layer away from the second semiconductor graphene layer; A third electrode and a fourth electrode are located in the first device region and on the electrode setting surface, and are connected to the two first regions respectively; The fifth electrode and the sixth electrode are located in the second device region and on the electrode setting surface, and are connected to the two second regions respectively.

7. The semiconductor device according to claim 1, wherein: The first semiconductor graphene layer is set to a first conductivity type; And / or, the second semiconductor graphene layer is set to a second conductivity type.

8. The semiconductor device according to claim 1, wherein: It also includes a first protective layer, which is located on a side of the first semiconductor graphene layer away from the silicon carbide semiconductor body; And / or, further comprising a second protective layer, wherein the second protective layer is located on a side of the second semiconductor graphene layer away from the silicon carbide semiconductor body.

9. The semiconductor device according to claim 8, characterized in that The first protective layer includes a gold protective layer or an aluminum oxide protective layer; the second protective layer includes a gold protective layer or an aluminum oxide protective layer.

10. The semiconductor device according to claim 1, wherein: The number of the first device regions is plural, and the number of the second device regions is plural.

11. A method for manufacturing a semiconductor device, characterized in that: include: Providing a silicon carbide semiconductor body, the silicon carbide semiconductor body comprising an electrode setting surface, the silicon carbide semiconductor body being set to a first conductivity type; the silicon carbide semiconductor body further comprising a first device region and a second device region; A first semiconductor graphene layer is formed on the surface where the electrode is provided, wherein the first semiconductor graphene layer is located in the first device region and is used to improve the mobility of the semiconductor device, and at the same preset temperature, the mobility of the first semiconductor graphene layer is greater than the mobility of silicon carbide; A second semiconductor graphene layer is formed on the surface where the electrode is provided, the second semiconductor graphene layer is located in the second device region, and is used to improve the mobility of the semiconductor device, and at the same preset temperature, the mobility of the second semiconductor graphene layer is greater than the mobility of silicon carbide; Among them, the part located in the first device area is a first conductivity type silicon carbide metal-oxide semiconductor field effect transistor with a conduction current direction in the first direction, and the part located in the second device area is a second conductivity type silicon carbide metal-oxide semiconductor field effect transistor with a conduction current direction in the first direction. The first conductivity type silicon carbide metal-oxide semiconductor field effect transistor and the second conductivity type silicon carbide metal-oxide semiconductor field effect transistor together constitute a silicon carbide complementary metal oxide semiconductor; the first direction is perpendicular to the thickness direction of the silicon carbide semiconductor body.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: The band gap of the first semiconductor graphene layer and the second semiconductor graphene layer is greater than or equal to 0.4 eV.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: The band gap of the first semiconductor graphene layer and the second semiconductor graphene layer is greater than or equal to 0.6 eV.

14. The method for manufacturing a semiconductor device according to claim 11, wherein: Forming a first semiconductor graphene layer on the electrode setting surface includes: Heating the electrode setting surface to a preset temperature so that silicon on the electrode setting surface evaporates, thereby forming a first semiconductor graphene layer on the electrode setting surface; Forming a second semiconductor graphene layer on the electrode setting surface includes: The electrode setting surface is heated to a preset temperature so that silicon on the electrode setting surface evaporates, thereby forming a second semiconductor graphene layer on the electrode setting surface.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: Heating the electrode setting surface to a preset temperature so that silicon on the electrode setting surface evaporates, thereby forming a first semiconductor graphene layer on the electrode setting surface comprises: Arranging the first silicon carbide semiconductor layer and the electrode arrangement surface of the silicon carbide semiconductor body opposite to each other; The electrode setting surface is heated to a preset temperature so that the carbon surface of the first silicon carbide semiconductor layer and the electrode setting surface provide a quasi-equilibrium condition between the carbon surface and the silicon surface at the preset temperature; wherein the electrode setting surface is a silicon surface; The silicon on the electrode setting surface is evaporated, thereby forming the first semiconductor graphene layer on the electrode setting surface; Heating the electrode setting surface to a preset temperature so that silicon on the electrode setting surface evaporates, thereby forming a second semiconductor graphene layer on the electrode setting surface comprises: Arranging the second silicon carbide semiconductor layer and the electrode arrangement surface of the silicon carbide semiconductor body opposite to each other; The electrode setting surface is heated to a preset temperature so that the carbon surface of the second silicon carbide semiconductor layer and the electrode setting surface provide a quasi-equilibrium condition between the carbon surface and the silicon surface at the preset temperature; wherein the electrode setting surface is a silicon surface; The silicon on the electrode setting surface is evaporated, thereby forming the second semiconductor graphene layer on the electrode setting surface.

16. The method for manufacturing a semiconductor device according to claim 11, wherein: After forming the first semiconductor graphene layer on the electrode setting surface, the method further comprises: Forming a first protective layer on a side of the first semiconductor graphene layer away from the silicon carbide semiconductor body; and / or, After forming a second semiconductor graphene layer on the electrode setting surface, the method further includes: A second protective layer is formed on a side of the second semiconductor graphene layer away from the silicon carbide semiconductor body.

17. A power module, characterized in that: It comprises a substrate and the semiconductor device according to any one of claims 1 to 10, wherein the substrate is used to carry the semiconductor device.

18. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of claims 1 to 10, wherein the semiconductor device is electrically connected to the circuit board.

19. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 18, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

Images