Semiconductor device including electrostatic discharge (ESD) circuit

Abstract

A semiconductor device includes: a first pad configured to receive and transmit a signal; a second pad to which a predetermined reference voltage is input; and an electrostatic protection circuit, and a base region including an emitter region electrically connected to the second pad and doped with a first conductivity type impurity, a base region having a shape surrounding the emitter region in the first direction and the second direction and doped with a second conductivity type impurity different from the first conductivity type impurity, a collector region connected to the first pad and having a shape surrounding the emitter region in the first direction and the second direction, and an impurity region disposed between the collector region and the base region and separated from the collector region and the base region by an element isolation film.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0163581 filed on November 22, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present invention relates to a semiconductor device. Background Art

[0004] The semiconductor device may include a plurality of semiconductor circuits, and a portion of the plurality of semiconductor circuits may include a receiving circuit, a transmitting circuit, etc. for exchanging signals with different external semiconductor devices. The receiving circuit and the transmitting circuit may be connected to a pad for transmitting and receiving signals. In order to protect the semiconductor device from electrostatic discharge (ESD) that may be caused from outside the semiconductor device through the pad, the receiving circuit, the transmitting circuit, etc. may be connected to an ESD protection circuit. In order to effectively protect the semiconductor device, it is necessary to implement an ESD protection circuit that may include an element having a holding voltage higher than the operating voltage of the receiving circuit and the transmitting circuit. Summary of the invention

[0005] An aspect of the inventive concept is to implement a semiconductor device having high ESD resistance using an ESD protection circuit having a holding voltage higher than an operating voltage of the semiconductor circuit.

[0006] According to one aspect of the present invention, a semiconductor device includes: a first well region formed in a substrate and doped with a first conductive type impurity; a second well region formed in the substrate, doped with a second conductive type impurity, and arranged inside the first well region in a first direction parallel to an upper surface of the substrate; a collector region arranged in the first well region and doped with a first conductive type impurity; an impurity region arranged in the first well region and doped with a first conductive type impurity or a second conductive type impurity; an emitter region arranged in the second well region and doped with a first conductive type impurity; a base region arranged in the second well region, doped with a second conductive type impurity, and arranged between the collector region and the emitter region in the first direction; and a plurality of element isolation films arranged between the collector region, the emitter region, and the base region. At least one element isolation film among the plurality of element isolation films is arranged between the impurity region and the collector region.

[0007] According to one aspect of the present invention, a semiconductor device includes: a first pad configured to receive and transmit signals; a second pad to which a predetermined reference voltage is input; and an electrostatic protection unit connected to the first pad and the second pad, and including a plurality of unit elements arranged in a first direction and a second direction parallel to an upper surface of a substrate. Each of the plurality of unit elements includes an emitter region electrically connected to the second pad and doped with a first conductive type impurity, a base region having a shape surrounding the emitter region in the first direction and the second direction and doped with a second conductive type impurity different from the first conductive type impurity, a collector region connected to the first pad and having a shape surrounding the emitter region in the first direction and the second direction, and an impurity region disposed between the collector region and the base region and separated from the collector region and the base region by an element isolation film.

[0008] According to one aspect of the inventive concept, a semiconductor device includes: an NPN transistor, including a collector region doped with N-type impurities and connected to a first pad, a base region doped with P-type impurities, and an emitter region doped with N-type impurities and connected to a second pad; and a diode, connected to the first pad, and including an N-type semiconductor region and a P-type semiconductor region. The collector region is arranged in a first well region doped with N-type impurities, and the base region and the emitter region are arranged in a second well region doped with P-type impurities and surrounded by the first well region. The N-type semiconductor region of the diode includes a first well region, and the P-type semiconductor region of the diode includes an impurity region arranged between the collector region and the base region and doped with P-type impurities. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present inventive concept will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 and Figure 2 is a diagram showing a semiconductor device according to an embodiment;

[0011] Figure 3 is a circuit diagram showing an ESD protection circuit included in a semiconductor device according to an embodiment;

[0012] Figure 4 is a diagram showing a Figure 3 A graph showing the operation of the ESD protection circuit shown in;

[0013] Figure 5 is a diagram showing a Figure 3 A plan view of an NPN transistor included in an ESD protection circuit;

[0014] Figure 6 and Figure 7 is a diagram showing a method according to an example embodiment Figure 3 A cross-sectional view of an NPN transistor included in an ESD protection circuit;

[0015] Figure 8 is a circuit diagram showing an ESD protection circuit included in a semiconductor device according to an embodiment;

[0016] Fig. 9 is a diagram showing a Figure 8 A cross-sectional view of an NPN transistor included in an ESD protection circuit;

[0017] Fig.10 is a circuit diagram showing an ESD protection circuit included in a semiconductor device according to an embodiment;

[0018] Fig.11 is a diagram showing a Fig.10 A cross-sectional view of an NPN transistor included in an ESD protection circuit;

[0019] Fig.12 is a circuit diagram showing an ESD protection circuit included in a semiconductor device according to an embodiment;

[0020] Fig.13 is a diagram showing a Fig.12 A cross-sectional view of an NPN transistor included in an ESD protection circuit;

[0021] Fig.14 is a circuit diagram showing an ESD protection circuit included in a semiconductor device according to an embodiment;

[0022] Figures 15 to 18 is a cross-sectional view showing an NPN transistor included in an ESD protection circuit according to example embodiments;

[0023] Fig.19 is a plan view showing an NPN transistor of an ESD protection circuit included in a semiconductor device according to an embodiment;

[0024] Fig. 20 is a diagram showing a Fig.19 A cross-sectional view of an ESD protection circuit; and

[0025] Fig.21 is a cross-sectional view showing an NPN transistor of an ESD protection circuit included in a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0026] Hereinafter, preferred embodiments will be described with reference to the accompanying drawings.

[0027] Figure 1 and Figure 2 is a diagram showing a semiconductor device according to an embodiment.

[0028] First, refer to Figure 1 , the semiconductor device 10 according to the embodiment may include signal pads 11 and 12, power pads 13 and 14, ESD protection circuits 15 and 16, a core circuit 17, etc. The semiconductor device 10 may exchange signals with different external semiconductor devices through the signal pads 11 and 12. For example, the core circuit 17 may include a transmitting circuit and a receiving circuit connected to the signal pads 11 and 12.

[0029] The core circuit 17 may include a plurality of semiconductor elements. The semiconductor elements included in the core circuit 17 may include various circuits required for the semiconductor device 10 to provide a given function, for example, a central processing unit (CPU), a graphics processing unit (GPU), an image signal processor (ISP), a neural processing unit (NPU), a modem, a cache memory, etc.

[0030] A power supply voltage VDD and a reference voltage (or ground voltage) VSS required for the operation of the core circuit 17 may be input to the power supply pads 13 and 14. For example, the power supply voltage VDD may be input to the first power supply pad 13, and a reference voltage VSS having a level lower than that of the power supply voltage VDD may be input to the second power supply pad 14.

[0031] A high voltage due to static electricity or the like may be applied to at least a portion of the pads 11 to 14 of the semiconductor device 10. For example, under an ESD event condition in which a high voltage is applied to at least one of the signal pads 11 and 12 due to static electricity or the like, when a very large amount of ESD current generated due to the ESD flows into the core circuit 17, the semiconductor element may be damaged. In an embodiment, an ESD event may occur when a subject approaches at least one of the floating pads 11 to 14.

[0032] As described above, in order to prevent damage to the semiconductor element that may occur under ESD event conditions, the semiconductor device 10 may include ESD protection circuits 15 and 16. Each of the ESD protection circuits 15 and 16 may include an NPN transistor connected between one of the signal pads 11 and 12 and the second power pad 14. In addition, each of the ESD protection circuits 15 and 16 may include a diode and / or a metal oxide semiconductor (MOS) transistor connected to the NPN transistor, etc.

[0033] The ESD protection circuits 15 and 16 may provide a path through which current flows into the semiconductor device 10 under ESD event conditions. When the ESD protection circuits 15 and 16 operate normally, current flowing into the signal pads 11 and 12 due to static electricity around the semiconductor device 10 may leak to the second power supply pad 14 through the ESD protection circuits.

[0034] The ESD protection circuits 15 and 16 may have a trigger voltage and a holding voltage determined according to the characteristics of the NPN transistor, and when a voltage higher than the trigger voltage is applied, avalanche breakdown may occur so that the ESD current may leak to the second power supply pad 14. Due to the avalanche breakdown, the voltage may be reduced to have a holding voltage lower than the trigger voltage, and the ESD current may leak to the second power supply pad 14.

[0035] When the difference between the holding voltage and the trigger voltage is large, the ESD protection function of the ESD protection circuits 15 and 16 may not be properly performed. For example, when the difference between the holding voltage and the trigger voltage is large, and the holding voltage is lower than the operating voltage of the semiconductor circuit (e.g., receiving circuit, transmitting circuit, etc.) included in the core circuit 17, a latch-up phenomenon in which the NPN transistors of the ESD protection circuits 15 and 16 continue to be turned on may occur even after the ESD event ends.

[0036] In the embodiment, the latch-up phenomenon described above can be effectively prevented by implementing the ESD protection circuits 15 and 16 in which the difference between the trigger voltage and the holding voltage is not large. For example, in the embodiment, an additional impurity region between the collector region and the base region of the NPN transistor included in the ESD protection circuits 15 and 16 can also be formed to improve the holding voltage characteristics of the NPN transistor and prevent the latch-up phenomenon of the ESD protection circuits 15 and 16.

[0037] Figure 2 2 is a diagram showing a partial region of a semiconductor device 20 according to an embodiment. Figure 2 , the semiconductor device 20 according to the embodiment may include a first pad 21, a second pad 22, an electrostatic protection unit 23, etc. The first pad 21 may be a pad through which a signal is input and / or output, and the second pad 22 may be a pad to which a predetermined reference voltage (eg, a ground voltage) is input.

[0038] The electrostatic protection unit 23 may include a plurality of unit elements 24 arranged in a matrix form. Each of the plurality of unit elements 24 may include an NPN transistor, and the NPN transistor may be connected to at least one of a MOS transistor, a diode, or a resistance element to provide an ESD protection circuit.

[0039] When an ESD event occurs to apply a high voltage to the first pad 21, and the voltage applied to the first pad 21 is higher than the trigger voltage of the ESD protection circuit, the NPN transistor can be turned on. Afterwards, as the voltage is reduced through the NPN transistor to have a holding voltage, the ESD current can flow into the second pad 22, and a large amount of current can be prevented from flowing into the core circuit.

[0040] When the holding voltage of the ESD protection circuit, which may be determined by the characteristics of the NPN transistor, is not high enough, a latch-up phenomenon may occur as described above, affecting the performance of the semiconductor device 20. Two or more electrostatic protection units 23 may be connected between the first pad 21 and the second pad 22 to increase the holding voltage of the ESD protection circuit and alleviate the latch-up phenomenon, but in this case, the integration of the semiconductor device 20 may decrease. In an embodiment, an impurity region adjacent to the collector region of the NPN transistor may be added to provide an ESD protection circuit with a sufficiently high holding voltage while minimizing the increase in the area of ​​the electrostatic protection unit 23 connected between the first pad 21 and the second pad 22.

[0041] Figure 3 is a circuit diagram showing an ESD protection circuit included in a semiconductor device according to an embodiment. Figure 4 is a diagram showing a Figure 3 Graph of the operation of the ESD protection circuit shown in FIG.

[0042] refer to Figure 3 , the ESD protection circuit 30 according to the embodiment may include an NPN transistor BJT (bipolar junction transistor), a resistor element R, a diode DI, a MOS transistor PM, etc. The collector of the NPN transistor BJT may be connected to a first pad P1 through which an input and / or output signal passes, and the emitter of the NPN transistor BJT may be connected to a second pad P2 through which a predetermined reference voltage is input. The reference voltage input to the second pad P2 may be a ground voltage. In addition, the emitter of the NPN transistor BJT may be connected to the base of the NPN transistor BJT through a resistor element R.

[0043] The collector of the NPN transistor BJT may be connected to the cathode of the diode DI, and the MOS transistor PM may be connected between the anode of the diode DI and the second pad P2. The MOS transistor PM may be a P-type MOS (PMOS) transistor, and may be a gate positive MOS (GPPMOS) transistor whose source and gate are connected to each other. In other embodiments described later, at least one of the diode DI or the MOS transistor PM may not be included in the ESD protection circuit 30, and the MOS transistor PM may also be replaced by an N-type MOS (NMOS) transistor.

[0044] In the following, reference will be made to Figure 4 To describe Figure 3 The operation of the ESD protection circuit 30 is shown in FIG.

[0045] refer to Figure 4 , shows an ESD current generated due to an ESD event. When the voltage applied to the first pad P1 increases to a certain level or above due to an ESD event, the ESD current may flow, and a voltage that rapidly increases the ESD current may be defined as a trigger voltage.

[0046] When an ESD event occurs and the voltage of the first pad P1 increases to a trigger voltage or above, the NPN transistor BJT may be turned on, allowing the ESD current to flow to the second pad P2. As the ESD current flows, the voltage may be as Figure 4 As shown in the graph shown in , the ESD current may increase rapidly when the voltage drops to the holding voltage.

[0047] When the difference between the holding voltage and the trigger voltage of the ESD protection circuit 30 is large, and the holding voltage is less than the operating voltage input under normal operation, the NPN transistor BJT may continue to be turned on even after the ESD event ends. Therefore, since a current path may be formed between the first pad P1 and the second pad P2 through the ESD protection circuit 30, the semiconductor device including the ESD protection circuit 30 may not operate normally.

[0048] In an embodiment, the difference between the trigger voltage and the holding voltage in the ESD protection circuit 30 can be reduced by designing the NPN transistor BJT. Therefore, an ESD protection circuit 30 having a sufficiently large holding voltage can be implemented, and an ESD protection circuit 30 suitable for a semiconductor device including a semiconductor circuit having a high operating voltage can be provided. For example, if the operating voltage is 30V, the holding voltage can be higher than the operating voltage, such as Figure 4 Reference Figure 4 , at a trigger voltage of about 37V, the ESD current may be about 0.2A, and at a holding voltage of about 36V, the ESD current may be about 1.9A.

[0049] Figure 5 is a diagram showing a Figure 3 A plan view of an NPN transistor included in an ESD protection circuit. Figure 6 and Figure 7 is a diagram showing a method according to an example embodiment Figure 3 sectional view of an NPN transistor included in an ESD protection circuit.

[0050] First, refer to Figure 5 , according to the embodiment Figure 3 The NPN transistor 100 included in the ESD protection circuit may include a collector region 111, a base region 112, and an emitter region 113. The collector region 111, the base region 112, and the emitter region 113 may be separated from each other by an element isolation film 110. For example, Figure 5 As shown, the base region 112 may be disposed inside the collector region 111 , and the emitter region 113 may be disposed inside the base region 112 .

[0051] The collector region 111 and the emitter region 113 may be doped with first conductivity type impurities, respectively, and the base region 112 may be doped with second conductivity type impurities. For example, the collector region 111 and the emitter region 113 may be doped with N-type impurities, and the base region 112 may be doped with P-type impurities.

[0052] In an embodiment, the impurity region 114 may be disposed between the collector region 111 and the base region 112. Figure 5 and Figure 6 In the depicted embodiment, the impurity region 114 may be doped with second conductivity type impurities.

[0053] Figure 6 is a diagram showing a section taken along line II' Figure 5 Cross-sectional view of an NPN transistor. Figure 6 , an epitaxial layer 102 having a first conductivity type may be formed on the substrate 101, and a first well region 103 and a second well region 105 may be formed in the epitaxial layer 102. An element isolation film 110 may be provided between the first well region 103 and the second well region 105. Figure 3 As described above, the collector region 111 may be connected to a first pad P1 through which a signal is input and / or output, and the emitter region 113 may be connected to a second pad P2 through which a reference voltage is input.

[0054] According to an embodiment, first well region 103 and second well region 105 may be formed in drift regions 104 and 106, respectively, so that NPN transistor 100 can withstand high voltage. First drift region 104 may be doped with first conductive type impurities (e.g., first well region 103), and second drift region 106 may be doped with second conductive type impurities (e.g., second well region 105).

[0055] The collector region 111 and the impurity region 114 may be formed in the first well region 103 , and the base region 112 and the emitter region 113 may be formed in the second well region 105 .

[0056] A diode may be provided by a PN junction of the impurity region 114 and the first well region 103. For example, an N-type semiconductor region connected to the cathode of the diode may include the first well region 103, and a P-type semiconductor region connected to the anode of the diode may include the impurity region 114. It is understood that the cathode of the diode is connected to the collector region 111, and the anode of the diode is connected to the PMOS transistor. For example, the MOS transistor PM has a source terminal and a gate terminal connected to each other and to the collector region 111 through the impurity region 114, and a drain terminal connected to the emitter region 113. Figure 6 In the illustrated embodiment, a high voltage P-well region 107 may be formed below the base region 112 .

[0057] The collector region 111, the base region 112, and the emitter region 113 may be connected to the wiring pattern 130 through the contact parts 120, respectively. Figure 6 The resistance element R may be connected between the wiring patterns 130 respectively connected to the base region 112 and the emitter region 113 , and the wiring pattern 130 connected to the collector region 111 may be connected to a first pad through which an input and / or output signal passes.

[0058] An impurity region 114 doped with impurities of a conductive type different from that of the collector region 111 may be formed in the first well region 103 in which the collector region 111 is formed. The impurity region 114 may be formed to reduce the gain of the NPN transistor 100, and as a result, an effect of increasing the holding voltage may be obtained. Therefore, the holding voltage of the ESD protection circuit including the NPN transistor 100 may be set to be higher than the operating voltage of the core circuit connected to the ESD protection circuit to suppress the latch-up phenomenon of the ESD protection circuit and effectively protect the core circuit.

[0059] The impurity region 114 doped with the second conductive type impurities can provide a diode together with the first well region 103. Therefore, the collector region 111 can be electrically connected to the MOS transistor PM through the diode provided by the impurity region 114 and the first well region 103. In this way, by forming the impurity region 114 to realize the diode connected to the collector region 111, a discharge path can be ensured to protect the core circuit from the influence of negative static electricity.

[0060] refer to Figure 7 The NPN transistor 100A according to the embodiment may further include a dummy gate structure 115 formed on at least a portion of the element isolation film 110. The dummy gate structure 115 may be formed of polysilicon and may be electrically floating without being connected to the contact portion 120, the wiring pattern 130, etc. Figure 7As shown, the dummy gate structure 115 may be provided to change the breakdown voltage of the NPN transistor 100A. For example, the breakdown voltage of the NPN transistor 100A may be increased by the field effect of the dummy gate structure 115.

[0061] refer to Figure 6 and Figure 7 Although not shown, the collector region 111 formed in the first well region 103 may be electrically connected to each other through the contact portion 120 and the wiring pattern 130, respectively, the impurity region 114 formed in the first well region 103 may be electrically connected to each other through the contact portion 120 and the wiring pattern 130, respectively, and the base region 112 formed in the high voltage P well region 107 may be electrically connected to each other through the contact portion 120 and the wiring pattern 130, respectively.

[0062] Figure 8 is a circuit diagram showing an ESD protection circuit included in a semiconductor device according to an embodiment.

[0063] refer to Figure 8 , the ESD protection circuit 40 according to the embodiment may include an NPN transistor BJT, etc. The collector of the NPN transistor BJT may be connected to a first pad P1 through which an input and / or output signal passes, and the emitter of the NPN transistor BJT may be connected to a second pad P2 through which a predetermined reference voltage (e.g., a ground voltage) is input. The reference voltage input to the second pad P2 may be a ground voltage. In addition, the emitter of the NPN transistor BJT may be connected to the base of the NPN transistor BJT through a resistor element R.

[0064] With previous reference Figure 3 The described embodiments are different. Figure 8 In the embodiment shown, the collector of the NPN transistor BJT may not be connected to the diode and may not be connected to the MOS transistor. This may be because the impurity region formed adjacent to the collector region in the NPN transistor BJT may be electrically floating. Fig. 9 This is described in more detail.

[0065] Fig. 9 is a diagram showing a Figure 8 sectional view of an NPN transistor included in an ESD protection circuit.

[0066] refer to Fig. 9, the NPN transistor 200 included in the ESD protection circuit according to the embodiment may include a collector region 211, a base region 212, and an emitter region 213. The collector region 211 and the emitter region 213 may be doped with first conductive type impurities, and the base region 212 may be doped with second conductive type impurities. The first well region 203 in which the collector region 211 is formed and the second well region 205 in which the base region 212 and the emitter region 213 are formed may be separated from each other by an element isolation film 210. As shown in reference Figure 8 As described above, the collector region 211 may be connected to a first pad P1 through which a signal is input and / or output, and the emitter region 213 may be connected to a second pad P2 through which a reference voltage is input.

[0067] Fig. 9 The NPN transistor 200 according to the embodiment shown may have the same Figure 5 and Figure 6 The structure of the NPN transistor 100 described above is similar to that of the NPN transistor 100 described above. For example, an epitaxial layer 202 having a first conductivity type may be formed on the substrate 201, and a first well region 203 and a second well region 205 may be formed in the epitaxial layer 202. The first well region 203 may be formed in the first drift region 204, the second well region 205 may be formed in the second drift region 206, and a high voltage P well region 207 may be formed below the base region 212.

[0068] The collector region 211, the base region 212, and the emitter region 213 may be connected to the wiring pattern 230 through the contact 220. The base region 212 and the emitter region 213 may be connected to each other through the resistance element R, and the wiring pattern 230 connected to the collector region 211 may be connected to the first pad P1 through which a signal is input and / or output.

[0069] The impurity region 214 formed in the first well region 203 together with the collector region 211 and doped with the second conductive type impurities may not be connected to the contact portion 220 and the wiring pattern 230, but may be connected as shown in FIG. Figure 8 As shown floating. Figure 8 As shown in the circuit diagram, Fig. 9 In the illustrated embodiment, the NPN transistor 200 may not be connected to the MOS transistor.

[0070] like Fig. 9 As shown, a dummy gate structure may be added to the NPN transistor 200 in which the impurity region 214 is floating. Figure 7 Similar to the described embodiment, a dummy gate structure may be formed on at least a portion of the element isolation film 210. In this way, a dummy gate structure may be added to change the breakdown voltage of the NPN transistor 200.

[0071] refer to Fig. 9 Although not shown, the collector region 211 formed in the first well region 203 may be electrically connected to each other through the contact portion 220 and the wiring pattern 230, and the base region 212 formed in the high voltage P well region 207 may be electrically connected to each other through the contact portion 220 and the wiring pattern 230, respectively.

[0072] Fig.10 is a circuit diagram showing an ESD protection circuit included in a semiconductor device according to an embodiment.

[0073] refer to Fig.10 , the ESD protection circuit 50 according to the embodiment may include an NPN transistor BJT, a resistor element R, a diode DI, a MOS transistor PM, etc. The collector of the NPN transistor BJT may be connected to a first pad P1 through which an input and / or output signal passes, and the emitter of the NPN transistor BJT may be connected to a second pad P2 through which a predetermined reference voltage is input. The reference voltage input to the second pad P2 may be a ground voltage. In addition, the emitter of the NPN transistor BJT may be connected to the base of the NPN transistor BJT through the resistor element R. The diode DI may be provided by a PN junction of an impurity region and an N-well region formed adjacent to the collector of the NPN transistor BJT.

[0074] exist Fig.10 In the illustrated embodiment, the gate of the MOS transistor PM may be connected to the third pad P3. The third pad P3 may be a pad to which a power supply voltage having a higher level than a reference voltage input to the second pad P2 is input.

[0075] Fig.11 is a diagram showing a Fig.10 sectional view of an NPN transistor included in an ESD protection circuit.

[0076] exist Fig.11 In the embodiment shown, the NPN transistor 300 may have the same Figure 5 and Figure 6 The NPN transistor 100 described above may have a similar structure. For example, an epitaxial layer 302 having a first conductivity type may be formed on a substrate 301, and a first well region 303 and a second well region 305 may be formed in the epitaxial layer 302. The first well region 303 may be formed in a first drift region 304, the second well region 305 may be formed in a second drift region 306, and a high voltage P well region 307 may be below the base region 312.

[0077] The collector region 311 and the impurity region 314 may be formed in the first well region 303. The collector region 311 may be doped with first conductivity type impurities, and the impurity region 314 may be doped with second conductivity type impurities. The base region 312 and the emitter region 313 may be formed in the second well region 305. The base region 312 may be doped with second conductivity type impurities, and the emitter region 313 may be doped with first conductivity type impurities. The first conductivity type impurity may be an N-type impurity, and the second conductivity type impurity may be a P-type impurity.

[0078] The collector region 311, the base region 312, the emitter region 313, and the impurity region 314 may be connected to the wiring pattern 330 through the contact portion 320, respectively. The wiring patterns 330 respectively connected to the base region 312 and the emitter region 313 may be connected to each other through the resistance element R, and the wiring pattern 330 connected to the emitter region 313 may be connected to the second pad P2 for inputting the reference voltage. The wiring pattern 330 connected to the collector region 311 may be connected to the first pad P1 through which the input and / or output signal passes, and the wiring pattern 330 connected to the impurity region 314 may be connected to the MOS transistor PM. The MOS transistor PM may be a P-type MOS (PMOS) transistor. Since the power supply voltage may be input to the gate of the MOS transistor PM, the MOS transistor PM may provide a gate-powered PMOS (GPPMOS) transistor.

[0079] refer to Fig.11 Although not shown, the collector region 311 formed in the first well region 303 may be electrically connected to each other through the contact portion 320 and the wiring pattern 330, respectively, the impurity region 314 formed in the first well region 303 may be electrically connected to each other through the contact portion 320 and the wiring pattern 330, respectively, and the base region 312 formed in the high voltage P well region 307 may be electrically connected to each other through the contact portion 320 and the wiring pattern 330, respectively.

[0080] Fig.12 is a circuit diagram showing an ESD protection circuit included in a semiconductor device according to an embodiment.

[0081] refer to Fig.12 , the ESD protection circuit 60 according to the embodiment may include an NPN transistor BJT, a resistor element R, a diode DI, an external diode EDI, etc. The collector of the NPN transistor BJT may be connected to a first pad P1 through which a signal is input and / or output, and the emitter of the NPN transistor BJT may be connected to a second pad P2 through which a predetermined reference voltage (e.g., a ground voltage) is input. In addition, the emitter of the NPN transistor BJT may be connected to the base of the NPN transistor BJT through the resistor element R.

[0082] The diode DI may be provided by a PN junction of an impurity region and an N-well region formed adjacent to the collector region of the NPN transistor BJT. The cathode of the diode DI may be electrically connected to the collector of the NPN transistor BJT and the first pad P1, and the anode of the diode DI may be electrically connected to the second pad P2 through an external diode EDI. Unlike the diode DI provided by the N-well region and the impurity region included in the NPN transistor BJT, the external diode EDI may be formed separately from the NPN transistor BJT.

[0083] Fig.13 is a diagram showing a Fig.12 sectional view of an NPN transistor included in an ESD protection circuit.

[0084] refer to Fig.13 , the NPN transistor 400 may have the same Figure 5 and Figure 6 The NPN transistor 100 described above may have a similar structure. For example, an epitaxial layer 402 having a first conductivity type may be formed on a substrate 401, and a first well region 403 and a second well region 405 may be formed in the epitaxial layer 402. The first well region 403 may be formed in a first drift region 404, the second well region 405 may be formed in a second drift region 406, and a high voltage P well region 407 may be formed in a corresponding region below the base region 412.

[0085] The collector region 411 and the impurity region 414 may be formed in the first well region 403. The collector region 411 may be doped with first conductivity type impurities, and the impurity region 414 may be doped with second conductivity type impurities. The base region 412 and the emitter region 413 may be formed in the second well region 405. The base region 412 may be doped with second conductivity type impurities, and the emitter region 413 may be doped with first conductivity type impurities. The first conductivity type impurity may be an N-type impurity, and the second conductivity type impurity may be a P-type impurity. The collector region 411, the base region 412, the emitter region 413, and the impurity region 414 may be connected to the wiring pattern 430 through the contact portion 420, respectively.

[0086] A diode may be provided by a PN junction of the impurity region 414 and the first well region 403, and the impurity region 414 providing an anode of the diode may be connected to an external diode EDI through a wiring pattern 430. Fig.13 As shown, the external diode EDI may be formed in a region other than a region where the NPN transistor 400 is formed.

[0087] refer to Fig.13Although not shown, the collector region 411 formed in the first well region 403 may be electrically connected to each other through the contact portion 420 and the wiring pattern 430, respectively, the impurity region 414 formed in the first well region 403 may be electrically connected to each other through the contact portion 420 and the wiring pattern 430, respectively, and the base region 412 formed in the high voltage P well region 407 may be electrically connected to each other through the contact portion 420 and the wiring pattern 430, respectively.

[0088] Fig.14 is a circuit diagram showing an ESD protection circuit included in a semiconductor device according to an embodiment.

[0089] refer to Fig.14 , the ESD protection circuit 70 according to the embodiment may include an NPN transistor BJT, a resistor element R, a diode DI, a MOS transistor NM, etc. The collector and emitter of the NPN transistor BJT may be connected to the first pad P1 and the second pad P2, respectively. As described above, the first pad P1 may be a pad through which an input and / or output signal passes, and the second pad P2 may be a pad for inputting a predetermined reference voltage. The reference voltage input to the second pad P2 may be a ground voltage. In addition, the emitter of the NPN transistor BJT may be connected to the base of the NPN transistor BJT through the resistor element R.

[0090] In an embodiment, the MOS transistor NM may be an NMOS transistor, or a gate-grounded NMOS (GGNMOS) transistor whose gate is connected to the pad P2 .

[0091] For example, the NMOS transistor NM has a drain terminal and a gate terminal connected to each other and to the emitter region 113 , and a source terminal connected to the collector region 111 through the impurity region 114 .

[0092] The diode DI may be provided by a PN junction of an impurity region and an N-well region formed adjacent to the collector of the NPN transistor BJT. The cathode of the diode DI may be electrically connected to the collector of the NPN transistor BJT and the first pad P1, and the anode of the diode DI may be electrically connected to the second pad P2 through the MOS transistor NM.

[0093] Figures 15 to 18 is a cross-sectional view illustrating an NPN transistor included in an ESD protection circuit according to example embodiments.

[0094] Fig.15 It shows Fig.14 FIG. 5 is a cross-sectional view of an NPN transistor 500 included in an ESD protection circuit. Fig.15, an epitaxial layer 502 having a first conductivity type may be formed on a substrate 501, and a first well region 503 and a second well region 505 may be formed in the epitaxial layer 502. The first well region 503 may be formed in a first drift region 504, and the second well region 505 may be formed in a second drift region 506. According to an embodiment, a high voltage P well region 507 may be formed in a portion of the second drift region 506.

[0095] The collector region 511 doped with the first conductive type impurities and the impurity region 514 doped with the second conductive type impurities may be formed in the first well region 503. The base region 512 doped with the second conductive type impurities and the emitter region 513 doped with the first conductive type impurities may be formed in the second well region 505. The first conductive type impurities may be N-type impurities, and the second conductive type impurities may be P-type impurities. The collector region 511, the base region 512, the emitter region 513, and the impurity region 514 may be connected to the contact 520 and the wiring pattern 530.

[0096] A diode may be provided by a PN junction of the impurity region 514 and the first well region 503, and the impurity region 514 providing an anode of the diode may be connected to the MOS transistor NM through the wiring pattern 530. For example, the MOS transistor NM has a drain terminal and a gate terminal connected to each other and to the emitter region 513, and a source terminal connected to the collector region 511 through the impurity region 514.

[0097] refer to Fig.15 Although not shown, the collector region 511 formed in the first well region 503 can be electrically connected to each other through the contact portion 520 and the wiring pattern 530, respectively, the impurity region 514 formed in the first well region 503 can be electrically connected to each other through the contact portion 520 and the wiring pattern 530, respectively, and the base region 512 formed in the high voltage P well region 507 can be electrically connected to each other through the contact portion 520 and the wiring pattern 530, respectively.

[0098] Fig.16 is a cross-sectional view showing an NPN transistor of an ESD protection circuit included in a semiconductor device according to an embodiment.

[0099] refer to Fig.16 , the NPN transistor 600 included in the ESD protection circuit may include an epitaxial layer 602 formed on a substrate 601, and a first well region 603, a second well region 605, a third well region 608, etc. formed in the epitaxial layer 602. The first well region 603 and the third well region 608 may be formed in the first drift region 604, and the second well region 605 may be formed in the second drift region 606. Therefore, as Fig.16As shown, the first well region 603 and the third well region 608 may contact each other in the first drift region 604. The high voltage P well region 607 may be formed in a portion of the second drift region 606. The first drift region 604 may be doped with first conductive type impurities (e.g., the first well region 603), and the second drift region 606 may be doped with second conductive type impurities (e.g., the second well region 605).

[0100] A collector region 611 doped with first conductive type impurities may be formed in the first well region 603. A base region 612 and an emitter region 613 may be formed in the second well region 605, and an impurity region 614 may be formed in the third well region 608. The first conductive type impurities may be N-type impurities, and the second conductive type impurities may be P-type impurities.

[0101] Therefore, in Fig.16 In the embodiment shown, a diode may be provided by a PN junction obtained by contact between the first well region 603 and the third well region 608. In terms of circuit, the cathode of the diode may be electrically connected to the collector region 611, and the anode of the diode may be connected to the MOS transistor PM through the contact 620 and the wiring pattern 630.

[0102] refer to Fig.16 Although not shown, the collector region 611 formed in the first well region 603 can be electrically connected to each other through the contact portion 620 and the wiring pattern 630, respectively, the impurity region 614 formed in the third well region 608 can be electrically connected to each other through the contact portion 620 and the wiring pattern 630, respectively, and the base region 612 formed in the high voltage P well region 607 can be electrically connected to each other through the contact portion 620 and the wiring pattern 630, respectively.

[0103] Fig.17 is a cross-sectional view showing an NPN transistor of an ESD protection circuit included in a semiconductor device according to an embodiment.

[0104] refer to Fig.17 , the NPN transistor 700 included in the ESD protection circuit may include an epitaxial layer 702 formed on a substrate 701, and a first well region 703, a second well region 705, etc. formed in the epitaxial layer 702. Different from the above-mentioned other embodiments, in Fig.17 In the illustrated embodiment, no drift region may be formed between the first well region 703 , the second well region 705 , and the epitaxial layer 702 .

[0105] Except that the drift region is not formed, the structure can be similar to the other embodiments described above. For example, the collector region 711 and the impurity region 714 can be formed in the first well region 703, and the base region 712 and the emitter region 713 can be formed in the second well region 705. The collector region 711 and the emitter region 713 can be doped with N-type impurities, respectively, and the base region 712 and the impurity region 714 can be doped with P-type impurities, respectively. The impurity region 714 can provide a diode through a PN junction with the first well region 703, and can be connected to the MOS transistor PM through the contact portion 720 and the wiring pattern 730.

[0106] refer to Fig.17 Although not shown, the collector region 711 formed in the first well region 703 can be electrically connected to each other through the contact portion 720 and the wiring pattern 730, respectively, the impurity region 714 formed in the first well region 703 can be electrically connected to each other through the contact portion 720 and the wiring pattern 730, respectively, and the base region 712 formed in the second well region 705 can be electrically connected to each other through the contact portion 720 and the wiring pattern 730, respectively.

[0107] Fig.18 is a cross-sectional view showing an NPN transistor of an ESD protection circuit included in a semiconductor device according to an embodiment.

[0108] refer to Fig.18 In the NPN transistor 800 included in the ESD protection circuit, the first well region 803 and the second well region 805 may be formed in the substrate 801 without an epitaxial layer and a drift region. Unlike the epitaxial layer having the first conductivity type included in the NPN transistor in other embodiments, the substrate 801 may have the second conductivity type.

[0109] Except that the epitaxial layer and the drift region are not formed, the structure can be similar to the other embodiments described above. For example, the collector region 811 and the impurity region 814 can be formed in the first well region 803, and the base region 812 and the emitter region 813 can be formed in the second well region 805. The collector region 811 and the emitter region 813 can be doped with N-type impurities, and the base region 812 and the impurity region 814 can be doped with P-type impurities. The impurity region 814 can provide a diode through a PN junction with the first well region 803, and can be connected to the MOS transistor PM through the contact portion 820 and the wiring pattern 830.

[0110] Fig.19 is a plan view showing an NPN transistor included in the ESD protection circuit according to the embodiment.

[0111] refer to Fig.19, the NPN transistor 900 included in the ESD protection circuit may include a collector region 911, a base region 912, and an emitter region 913. The collector region 911, the base region 912, and the emitter region 913 may be separated from each other by an element isolation film 910. The collector region 911 and the emitter region 913 may be doped with first conductive type impurities, respectively, and the base region 912 may be doped with second conductive type impurities. For example, the collector region 911 and the emitter region 913 may be doped with N-type impurities, respectively, and the base region 912 may be doped with P-type impurities.

[0112] refer to Fig.19 The base region 912 may include a first base region 912A surrounding the outside of the emitter region 913 , and a second base region 912B disposed inside the emitter region 913 .

[0113] Fig. 20 is a diagram showing a view taken along line II-II' according to an embodiment. Fig.19 A cross-sectional view of an NPN transistor 900 .

[0114] refer to Fig. 20 , the first base region 912A may be connected to the emitter region 913 through the contact portion 920, the wiring pattern 930, and the first resistance element R1, and the second base region 912B may be connected to the emitter region 913 through the contact portion 920, the wiring pattern 930, and the second resistance element R2. In addition, the high voltage P-well region 907 may be formed under the first base region 912A and the second base region 912B, respectively.

[0115] Other structures may be similar to the other embodiments described above. The first well region 903 and the second well region 905 may be formed on the epitaxial layer 902 formed on the substrate 901, and may be surrounded by drift regions 904 and 906, respectively. The impurity region 914 may be connected to the MOS transistor PM through the contact 920 and the wiring pattern 930, and a diode may be implemented through the impurity region 914 and the first well region 903.

[0116] Fig.21 is a cross-sectional view showing an NPN transistor of an ESD protection circuit according to an embodiment.

[0117] refer to Fig.21 , the NPN transistor 1000 included in the ESD protection circuit may include an epitaxial layer 1002 formed on a substrate 1001, and a first well region 1003, a second well region 1005, etc. formed in the epitaxial layer 1002. A first drift region 1004 may be formed between the first well region 1003 and the epitaxial layer 1002, and a second drift region 1006 may be formed between the second well region 1005 and the epitaxial layer 1002.

[0118] The collector region 1011 and the impurity region 1014 may be formed in the first well region 1003, and the base region 1012 and the emitter region 1013 may be formed in the second well region 1005. Fig.21 In the illustrated embodiment, the collector region 1011, the emitter region 1013, and the impurity region 1014 may be doped with N-type impurities, respectively, and the base region 1012 may be doped with P-type impurities. Since the impurity region 1014 may be doped with N-type impurities, a diode may not be provided by the impurity region 1014. The impurity region 1014 may be connected to the MOS transistor PM through the contact 1020 and the wiring pattern 1030, but depending on the embodiment, the MOS transistor PM may not be connected to the impurity region 1014. In this case, the impurity region 1014 may be directly connected to a pad that supplies a predetermined reference voltage (e.g., a ground voltage).

[0119] The features of each of the above-mentioned embodiments can be selectively applied to each other. Figure 7 The dummy gate structure 115 described may include the Fig. 9 , Fig.11 , Fig.13 , Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig. 20 and Fig.21 In each of the NPN transistors 200, 300, 400, 500, 600, 700, 800, 900 and 1000 of the described embodiments. Figure 6 , Figure 7 , Fig. 9 , Fig.11 , Fig.13 , Fig.15 and Figures 17 to 21 In each of the NPN transistors 100, 100A, 200, 300, 400, 500, 700, 800, 900, and 1000 of the described embodiments, a well region doped with P-type impurities instead of N-type impurities may be formed below the impurity regions 114, 214, 314, 414, 514, 714, 814, 914, and 1014, as shown in FIG. Fig.16 described.

[0120] As in Fig. 20In the embodiment shown, the structure in which the base region 912 is divided into the first base region 912A and the second base region 912B can also be applied to the NPN transistors 100, 100A, 200, 300, 400, 500, 600, 700, 800 and 1000 according to other embodiments. Fig.11 In the illustrated embodiment, the structure in which the power supply voltage VDD is input to the gate of the MOS transistor PM can also be applied to the MOS transistor PM connected to the NPN transistors 100 , 100A, 600 , 700 , 800 , 900 , and 1000 according to other embodiments.

[0121] Various embodiments may overlap and cross-apply. Figure 7 As described above, the element connected to the impurity region 114 of the NPN transistor 100A including the dummy gate structure 115 can be changed to an external diode instead of the MOS transistor PM. In addition, the base region can be divided into a first base region 912A and a second base region 912B, as shown in FIG. Fig. 20 Alternatively, Fig.21 As shown, in the NPN transistor 1000 in which the impurity region 1014 is doped with N-type impurities, a dummy gate structure can be formed on at least a portion of the element isolation film 1010, and the MOS transistor PM can be replaced by an external diode, the power supply voltage VDD can be input to the gate of the MOS transistor PM, or the MOS transistor PM can be omitted and the impurity region 1014 can be electrically floated.

[0122] According to an embodiment, an impurity region may also be provided between the collector region and the base region of the NPN transistor included in the ESD protection circuit to increase the holding voltage of the ESD protection circuit. Therefore, the holding voltage of the ESD protection circuit may be maintained higher than the operating voltage of the semiconductor device to improve the performance of the ESD protection circuit and effectively protect the semiconductor device.

[0123] Various advantages and effects of the present invention are not limited to the above contents and can be more easily understood through the description of specific embodiments.

[0124] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the invention as defined by the appended claims.

Claims

1. A semiconductor device, comprising: A first well region is formed in the substrate and doped with first conductivity type impurities; a second well region formed in the substrate, doped with second conductivity type impurities, and disposed inside the first well region in a first direction parallel to an upper surface of the substrate; a collector region, disposed in the first well region and doped with impurities of the first conductivity type; an impurity region, disposed in the first well region and doped with the first conductivity type impurities or the second conductivity type impurities; an emitter region, disposed in the second well region and doped with impurities of the first conductive type; a base region, disposed in the second well region, doped with the second conductive type impurities, and disposed between the collector region and the emitter region in the first direction; as well as A plurality of element isolation films are provided between the collector region, the emitter region and the base region, Among them, at least one element isolation film among the plurality of element isolation films is provided between the impurity region and the collector region.

2. The semiconductor device according to claim 1, further comprising: The dummy gate structure is disposed on at least one of the plurality of element isolation films and is electrically floating.

3. The semiconductor device according to claim 1, further comprising: A resistance element is connected between the base region and the emitter region.

4. The semiconductor device according to claim 1, further comprising: The metal oxide semiconductor (MOS) transistor has a source terminal connected to the collector region through the impurity region and a drain terminal connected to the emitter region.

5. The semiconductor device according to claim 4, wherein: The MOS transistor is a P-type MOS (PMOS) transistor including a gate terminal connected to the source terminal.

6. The semiconductor device according to claim 4, wherein: The MOS transistor is an N-type MOS (NMOS) transistor including a gate terminal connected to the emitter region.

7. The semiconductor device according to claim 4, wherein: The impurity region is connected to the source terminal of the MOS transistor.

8. The semiconductor device according to claim 1, wherein The impurity region is electrically floating.

9. The semiconductor device according to claim 1, further comprising: A diode includes an anode connected to the impurity region.

10. The semiconductor device according to claim 9, wherein The diode includes a cathode connected to a pad of an input signal.

11. The semiconductor device according to claim 1, wherein The base region comprises: a first base region disposed between the emitter region and the collector region in the first direction, and The second base region is arranged inside the emitter region in the first direction.

12. A semiconductor device comprising: A first pad configured to receive and transmit signals; The second pad is input with a predetermined reference voltage; as well as an electrostatic protection unit connected to the first pad and the second pad and including a plurality of unit elements arranged in a first direction and a second direction parallel to an upper surface of the substrate, Wherein, each of the plurality of unit elements comprises: an emitter region, electrically connected to the second pad and doped with first conductivity type impurities, a base region having a shape surrounding the emitter region in the first direction and the second direction and doped with second conductive type impurities different from the first conductive type impurities, a collector region connected to the first pad and having a shape surrounding the emitter region in the first direction and the second direction, and An impurity region is provided between the collector region and the base region and is separated from the collector region and the base region by an element isolation film.

13. The semiconductor device according to claim 12, wherein: The collector region is doped with impurities of the first conductivity type, and The impurity region is doped with impurities of the second conductivity type.

14. The semiconductor device according to claim 13, wherein: The collector region is disposed in a well region doped with impurities of the first conductive type, and The impurity region is arranged in a well region doped with impurities of the second conductive type.

15. The semiconductor device according to claim 12, wherein: The collector region and the impurity region are doped with the first conductive type impurities, respectively.

16. The semiconductor device according to claim 15, wherein: The collector region and the impurity region are disposed in a well region doped with the first conductive type impurities.

17. A semiconductor device comprising: An NPN transistor including a collector region doped with N-type impurities and connected to the first pad, a base region doped with P-type impurities, and an emitter region doped with N-type impurities and connected to the second pad; as well as a diode connected to the first pad and including an N-type semiconductor region and a P-type semiconductor region, The collector region is arranged in a first well region doped with N-type impurities, and the base region and the emitter region are arranged in a second well region doped with P-type impurities and surrounded by the first well region. Wherein, the N-type semiconductor region of the diode includes the first well region, and The P-type semiconductor region of the diode includes an impurity region disposed between the collector region and the base region and doped with P-type impurities.

18. The semiconductor device according to claim 17, wherein: The impurity region is provided in the first well region together with the collector region.

19. The semiconductor device according to claim 17, wherein: The impurity region is disposed in a third well region that is in contact with the first well region and is doped with P-type impurities.

20. The semiconductor device according to claim 17, wherein The base region includes a first base region disposed between the collector region and the emitter region, and a second base region disposed inside the emitter region.

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