Electrostatic discharge protection structure and electronic equipment

Abstract

The invention relates to an electrostatic discharge protection structure and electronic equipment. The electrostatic discharge protection structure comprises a first conduction region and a second conduction region, the first conduction region comprises a first grid electrode, a first drain electrode and a first source electrode, the first grid electrode is grounded, and a first interval is formed between the first grid electrode and the first drain electrode; the second conduction region is located on the two opposite sides of the first conduction region, the second conduction region comprises a plurality of second grid electrodes, a second drain electrode and a second source electrode, the second grid electrodes are grounded, and the conduction moments of the second conduction region and the first conduction region are the same. By adjusting the conduction moments of the first conduction region and the second conduction region, the conduction moment of the first conduction region is the same as the conduction moment of the second conduction region, so that the plurality of interdigitals of the electrostatic discharge structure can be uniformly conducted, the overall current capability and discharge capability of the device can be improved, and the performance of the device is improved. Voltage overshoot is reduced, and a core circuit is protected from being broken down by high voltage.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an electrostatic discharge protection structure and an electronic device. Background Art

[0002] GGNMOS (Gate-Grounded N-channel Metal-Oxide-Semiconductor Field-EffectTransistor) devices have a simple structure and high process adjustability, so GGNMOS has become the current mainstream ESD (Electrostatic Discharge) protection device. GGNMOS is less affected by parasitic parameters. Under the premise of the same line width, the electric field distribution of the multi-finger GGNMOS is more dispersed and the breakdown voltage is higher.

[0003] However, as the base width of the multi-finger parallel GGNMOS structure increases, the current gain coefficient decreases, making it difficult to turn on the parasitic NPN transistor. As the number of internal parallel fingers increases, the GGNMOS leakage current is limited, making it impossible for multiple fingers to be turned on uniformly, thereby reducing the electrostatic protection capability of the GGNMOS device. Summary of the invention

[0004] The purpose of this application is to provide an electrostatic discharge protection structure and an electronic device, which solves the problem that multiple fingers in the electrostatic discharge protection structure cannot be opened uniformly, and improves the electrostatic protection capability and reliability of the electrostatic discharge protection structure. To achieve the purpose of this application, this application provides the following technical solutions:

[0005] In a first aspect, the present application provides an electrostatic discharge protection structure, comprising:

[0006] A first conductive region, the first conductive region comprising a first gate, and a first drain and a first source located on opposite sides of the first gate, wherein the first gate is grounded, and a first distance is provided between the first gate and the first drain;

[0007] A second conductive region, wherein the second conductive region is located on two opposite sides of the first conductive region, the second conductive region comprises a plurality of second gates, and a second drain and a second source located on two opposite sides of the second gates, the plurality of second gates are arranged at intervals along a first direction parallel to a top surface of the first gate, wherein the second gates are grounded, and the conduction timing of the second conductive region is the same as that of the first conductive region.

[0008] The electrostatic discharge protection structure of the present application, through the gate grounding in the first conduction area and the second conduction area, can be in the case where the voltage between the source and the substrate exceeds the threshold voltage of NMOS, NMOS will enter the conduction state, forming a low impedance path, and discharge the electrostatic discharge current to the ground, thereby protecting the internal circuit. By adjusting the size of the first spacing between the first gate and the first drain, the turn-on voltage of the first conduction area can be adjusted, and then the conduction time of the first conduction area can be adjusted, so that the conduction time of the first conduction area is the same as the conduction time of the second conduction area, and then the uniformity between the multiple interdigits of the electrostatic discharge structure can be turned on, and then the overall current capacity and discharge capacity of the device can be improved, the voltage overshoot can be reduced, and the core circuit can be protected from high voltage breakdown. The on-resistance of the entire structure can be reduced, thereby reducing the voltage drop when discharging the current, ensuring that the voltage of the protected circuit is maintained at a safe level during electrostatic discharge. And the uniform conduction of multiple interdigits can avoid the problem of damage to the electrostatic discharge protection structure due to excessive local temperature, and improve the reliability of the electrostatic discharge protection structure.

[0009] In some embodiments, the second conductive region includes a first conductive portion, a second conductive portion, and a third conductive portion, the second conductive portion is located between the first conductive portion and the third conductive portion, the conductive voltage of the first conductive portion is greater than the conductive voltage of the second conductive portion, and the conductive voltage of the second conductive portion is greater than the conductive voltage of the third conductive portion.

[0010] In some embodiments, the second drain and the second gate of the first conductive portion include a second distance therebetween.

[0011] In some embodiments, the first spacing is associated with a distance between the first gate and the first drain, and the second spacing is associated with a distance between the second gate and the second drain, wherein the first spacing is greater than the second spacing.

[0012] In some embodiments, the second conductive portion includes a capacitor and a first resistor, the first plate of the capacitor is connected to the second gate, and the second plate is connected to the power supply voltage and the second drain, one end of the first resistor is connected to the second gate and the first plate, and the other end of the first resistor is connected to the second source.

[0013] In some embodiments, the second drain of the second conductive portion is connected to the first end of the conductive unit, and the second end of the conductive unit is grounded, wherein the conductive voltage of the conductive unit is a preset conductive voltage.

[0014] In some embodiments, the third conducting portion includes a second resistor, one end of the second resistor is connected to the second gate, and the other end of the second resistor is connected to the second source.

[0015] In some embodiments, nanotubes are also included.

[0016] The nanotubes on the top surfaces of the first source electrode, the second source electrode, the first drain electrode, and the second drain electrode are arranged at intervals along a second direction; the first direction is perpendicular to the second direction.

[0017] In some embodiments, it also includes:

[0018] A substrate, wherein the first gate, the second gate, the first drain, the second drain, the first source and the second source are located on a top surface of the substrate;

[0019] The doped region is located between the first drain and the substrate, and between the second drain and the substrate, and the conductivity type of the doped region is different from the conductivity type of the first drain and the second drain.

[0020] In a second aspect, the present application further provides an electronic device, including:

[0021] The electrostatic discharge protection structure according to any one of the first aspects.

[0022] The electronic device of the present application, through the gate grounding in the first conduction area and the second conduction area, can be in the case where the voltage between the source and the substrate exceeds the threshold voltage of NMOS, NMOS will enter the conduction state, forming a low impedance path, and discharge the electrostatic discharge current to the ground, thereby protecting the internal circuit. By adjusting the size of the first spacing between the first gate and the first drain, the turn-on voltage of the first conduction area can be adjusted, and then the conduction time of the first conduction area can be adjusted, so that the conduction time of the first conduction area is the same as the conduction time of the second conduction area, and then the uniformity between the multiple interdigits of the electrostatic discharge structure can be turned on, and then the overall current capacity and discharge capacity of the device can be improved, the voltage overshoot can be reduced, and the core circuit can be protected from high voltage breakdown. The on-resistance of the entire structure can be reduced, thereby reducing the voltage drop when discharging the current, ensuring that the voltage of the protected circuit is maintained at a safe level during electrostatic discharge. And the uniform conduction of multiple interdigits can avoid the problem of damage to the electrostatic discharge protection structure due to excessive local temperature, and improve the reliability of the electrostatic discharge protection structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0024] Figure 1 is a schematic cross-sectional structure diagram of an electrostatic discharge protection structure provided in an embodiment;

[0025] Figure 2 is a schematic cross-sectional structure diagram of an electrostatic discharge protection structure provided in another embodiment;

[0026] Figure 3 is a schematic cross-sectional structure diagram of an electrostatic discharge protection structure provided in yet another embodiment;

[0027] Figure 4 is a schematic cross-sectional structure diagram of an electrostatic discharge protection structure provided in yet another embodiment;

[0028] Figure 5 is a circuit diagram of an electrostatic discharge protection structure provided in an embodiment;

[0029] Figure 6 is a schematic cross-sectional structure diagram of an electrostatic discharge protection structure provided in an embodiment;

[0030] Figure 7 It is a schematic cross-sectional structure diagram of an electrostatic discharge protection structure provided in another embodiment.

[0031] Description of Reference Numerals

[0032] 10. First conductive region; 101. First gate; 102. First drain; 103. First source; 20. Second conductive region; 201. Second gate; 202. Second drain; 203. Second source; 21. First conductive portion; 22. Second conductive portion; 23. Third conductive portion; 30. Nanotube; 40. Substrate; 50. Doped region. DETAILED DESCRIPTION

[0033] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0035] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0036] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0037] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0038] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0039] GGNMOS (Gate-Grounded N-channel Metal-Oxide-Semiconductor Field-EffectTransistor) devices have a simple structure and high process adjustability, so GGNMOS has become the current mainstream ESD (Electrostatic Discharge) protection device. GGNMOS has the characteristics of being less affected by parasitic parameters. Under the premise of the same line width, the electric field distribution of the multi-finger parallel structure type GGNMOS is more dispersed and the breakdown voltage is higher. However, as the base width of the multi-finger parallel structure type GGNMOS structure increases, the current gain coefficient decreases, which makes it difficult to turn on the parasitic NPN transistor, and as the number of internal parallel fingers increases, the GGNMOS leakage will be limited, making it impossible for multiple fingers to be uniformly turned on, thereby reducing the electrostatic protection capability of the GGNMOS device.

[0040] In conventional technology, the problem of uneven conduction between multiple fingers is usually improved by increasing the distance from the drain end transistor to the gate, adding a metal barrier layer to increase resistance, or using an electrostatic protection ion implantation process.

[0041] However, in the traditional technology, increasing the distance from the drain end transistor of the forked finger to the gate will cause the layout area to increase and the layout utilization to decrease. Adding a metal barrier layer is more of an enhancement of the protection level and the overcurrent capability, but it is difficult to reduce the trigger voltage and cannot solve the problem of non-uniform conduction of GGNMOS. The use of electrostatic protection ion implantation process requires an additional mask layer, which makes the process cumbersome and increases the manufacturing cost.

[0042] The present invention provides an electrostatic discharge protection structure. Figure 1The electrostatic discharge protection structure includes: a first conductive region 10 and a second conductive region 20, wherein the first conductive region 10 includes a first gate 101, and a first drain 102 and a first source 103 located on opposite sides of the first gate 101, wherein the first gate 101 is grounded, and a first distance is included between the first gate 101 and the first drain 102; the second conductive region 20 is located on opposite sides of the first conductive region 10, and the second conductive region 20 includes a plurality of second gates 201, and a second drain 202 and a second source 203 located on opposite sides of the second gate 201, wherein the plurality of second gates 201 are arranged at intervals along a first direction parallel to a top surface of the first gate 101, wherein the second gate 201 is grounded, and the conduction time of the second conductive region 20 is the same as that of the first conductive region 10.

[0043] Exemplarily, the first direction is Figure 1 The first spacing is as follows: Figure 2 The first spacing is equal to the spacing between the first gate 101 and the first drain 102. The first spacing can be adjusted by, but not limited to, adjusting the size of the first gate 101 in the first direction. For example, the larger the size of the first gate 101 in the first direction, the smaller the first spacing.

[0044] For example, the first gate 101 and the second gate 201 may include but are not limited to polysilicon gates. The conductivity type of the first drain 102 and the second drain 202 may include P type or N type. The first drain 102 and the second drain 202 have the same conductivity type.

[0045] It should be noted that the first conductive region 10 is located at Figure 1 In the central area shown in , since the resistance of the substrate 40 of the first conductive region 10 is large, the turn-on voltage of the first conductive region 10 is small, and when other conditions are the same, the turn-on speed of the first conductive region 10 is greater than the turn-on speed of the second conductive region 20. In the embodiment of the present application, the turn-on voltage of the first conductive region 10 can be effectively adjusted by using the first spacing, so that the second conductive region 20 and the first conductive region 10 are turned on at the same time.

[0046] The electrostatic discharge protection structure of the present application, through the grounding of the gate in the first conductive area 10 and the second conductive area 20, can be in the case where the voltage between the source and the substrate 40 exceeds the threshold voltage of the NMOS, the NMOS will enter the on state, forming a low impedance path, and discharge the electrostatic discharge current to the ground, thereby protecting the internal circuit. By adjusting the size of the first spacing between the first gate 101 and the first drain 102, the turn-on voltage of the first conductive area 10 can be adjusted, and then the turn-on time of the first conductive area 10 can be adjusted, so that the turn-on time of the first conductive area 10 is the same as the turn-on time of the second conductive area 20, and then the uniform conduction between the multiple interdigits of the electrostatic discharge structure can be made, and then the overall current capacity and discharge capacity of the device can be improved, the voltage overshoot can be reduced, and the core circuit can be protected from high voltage breakdown. The on-resistance of the entire structure can be reduced, thereby reducing the voltage drop when discharging the current, ensuring that the voltage of the protected circuit is maintained at a safe level during electrostatic discharge. Furthermore, uniform conduction of multiple interdigits can avoid damage to the electrostatic discharge protection structure due to excessively high local temperature, thereby improving the reliability of the electrostatic discharge protection structure.

[0047] In some embodiments, see Figure 1 , Figures 3 to 6 The second conductive region 20 includes a first conductive portion 21, a second conductive portion 22 and a third conductive portion 23. The second conductive portion 22 is located between the first conductive portion 21 and the third conductive portion 23. The on-voltage of the first conductive portion 21 is greater than the on-voltage of the second conductive portion 22. The on-voltage of the second conductive portion 22 is greater than the on-voltage of the third conductive portion 23.

[0048] It should be noted that the distances between the first conductive region 10 and the first conductive portion 21, the second conductive portion 22, and the third conductive portion 23 increase in sequence, so when other conditions are the same, the opening speed of the first conductive portion 21 is greater than the opening speed of the second conductive portion 22, and the opening speed of the second conductive portion 22 is greater than the opening speed of the third conductive portion 23. In the embodiment of the present application, the opening voltages of the first conductive portion 21, the second conductive portion 22, and the third conductive portion 23 are adjusted to achieve the purpose of making the first conductive portion 21, the second conductive portion 22, and the third conductive portion 23 have the same conduction time.

[0049] Exemplarily, the on-voltage of the first conduction section 21 is greater than the on-voltage of the second conduction section 22, and the on-voltage of the second conduction section 22 is greater than the on-voltage of the third conduction section 23, so that the turn-on speed of the first conduction section 21 which is the smallest distance from the first conduction region 10 is smaller than the turn-on speed of the second conduction section 22, and the turn-on speed of the second conduction section 22 is smaller than the turn-on speed of the third conduction section 23 which is the largest distance from the first conduction region 10.

[0050] The electrostatic discharge protection structure in the embodiment of the present application can divide the second conductive area 20 according to different turn-on voltages by setting the second conductive area 20 to the first conductive part 21, the second conductive part 22 and the third conductive part 23, so that each area close to the second conductive area 20 can be turned on at the same time, thereby making the multiple fingers of the electrostatic discharge structure uniformly conductive, thereby improving the reliability of the electrostatic discharge protection structure.

[0051] In some embodiments, see Figure 3 A second distance is provided between the second drain electrode 202 and the second gate electrode 201 of the first conductive portion 21 .

[0052] As an example, the second spacing is Figure 3 The second spacing is equal to the spacing between the second gate 201 and the second drain 202. The second spacing can be adjusted by, but not limited to, adjusting the size of the second gate 201 in the first direction. For example, the larger the size of the second gate 201 in the first direction, the smaller the second spacing.

[0053] The electrostatic discharge protection structure provided in the embodiment of the present application sets a second distance between the second drain 202 and the second gate 201 of the first conductive part 21, which can reduce the width of the transistor NPN base region between the second drain 202 and the third gate, thereby increasing the current gain amplification factor. There is no need to generate more impact ionization hole current to maintain the current of the transistor NPN collector, and the turn-on voltage of the first conductive part 21 can be reduced, thereby increasing the turn-on speed of the first conductive part 21. Therefore, the turn-on time of the first conductive part 21 can be adjusted to match the turn-on time of the first conductive area 10, so that the turn-on time of the first conductive area 10 and the first conductive part 21 are the same, so that the electrostatic discharge protection structure is uniformly turned on, thereby improving the reliability and practicality of the electrostatic discharge protection structure.

[0054] In some embodiments, see Figure 2 and Figure 3 The first spacing is associated with the distance between the first gate 101 and the first drain 102, and the second spacing is associated with the distance between the second gate 201 and the second drain 202, wherein the first spacing is greater than the second spacing.

[0055] Exemplarily, the size of the first spacing and the size of the second spacing can be reasonably set in coordination with each other, so that the turn-on time of the first conductive region 10 is the same as the turn-on time of the first conductive portion 21 .

[0056] In the electrostatic discharge protection structure provided in the embodiment of the present application, the first spacing in the first conductive area 10 is set to be larger than the second spacing in the first conductive portion 21, so that the turn-on voltage of the first conductive area 10 can be larger than the turn-on voltage of the second conductive portion 22, and thus the turn-on speed of the first conductive area 10 can be smaller than the turn-on speed of the first conductive portion 21, so as to compensate for the fact that the time for the current in the electrostatic discharge protection structure to reach the first conductive portion 21 is longer than that to reach the first conductive area 10, so that the turn-on moments of the first conductive area 10 and the second conductive portion 22 are the same, so that the electrostatic discharge protection structure can be turned on uniformly.

[0057] In some embodiments, see Figure 4 and Figure 5 The second conductive portion 22 includes a capacitor and a first resistor R1, the first plate of the capacitor C is connected to the second gate 201, and the second plate is connected to the power supply voltage VDD and the second drain 202, one end of the first resistor is connected to the second gate 201 and the first plate, and the other end of the first resistor is connected to the second source 203.

[0058] Exemplarily, the second plate of the first capacitor is connected to the second drain 202 and the power supply voltage VDD. When the second drain 202 connected to the first capacitor C has an excessive electrostatic discharge current, the second gate 201 can use the capacitance induction of the first capacitor C to obtain a positive voltage, so that the NMOS is in a weak conduction state, thereby causing the hole current to flow from the channel region to the substrate 40, so as to reduce the avalanche current of the turn-on voltage of the second conductive part 22, reduce the turn-on voltage of the second conductive part 22, and increase the turn-on speed of the second conductive part 22. By connecting one end of the first resistor R1 to the second gate 201 and the first plate, and the other end of the first resistor R1 to the second source 203, the current flowing into the second gate 201 when electrostatic discharge occurs can be limited to prevent the gate oxide layer from being broken down.

[0059] The electrostatic discharge protection structure provided in the embodiment of the present application can effectively protect the second conductive part 22 from being broken down by the excessive current generated by electrostatic discharge by setting the first capacitor C and the first resistor R1 in the second conductive part 22, and can reduce the turn-on voltage of the second conductive part 22, so that the turn-on voltage of the second conductive part 22 is lower than the turn-on voltage of the first conductive part 21, thereby making the turn-on speed of the second conductive part 22 greater than the turn-on speed of the first conductive part 21, so that the first conductive part 21 and the second conductive part 22 can be turned on together, thereby improving the conduction uniformity of the electrostatic discharge protection structure and improving the reliability of the electrostatic discharge protection structure.

[0060] In some embodiments, see Figure 5The second drain 202 of the second conductive portion 22 is connected to the first end of the conductive unit NPN, and the second end of the conductive unit NPN is grounded, wherein the conductive voltage of the conductive unit NPN is a preset conductive voltage.

[0061] It should be noted that the conduction unit may include but is not limited to an NPN transistor, the collector of the NPN transistor is connected to the second drain 202, the emitter of the NPN transistor is grounded, and the base of the NPN transistor is connected to one end of the resistor RNWL and then grounded.

[0062] Exemplarily, by connecting the second drain 202 of the second conducting part 22 to the first end of the conducting unit NPN, and grounding the second end of the conducting unit, the conducting unit NPN can be triggered under a very small turn-on voltage. The turn-on voltage of the conducting unit NPN can be set according to the actual situation of the second conducting part 22, so that the turn-on time of the second conducting part 22 is the same as the turn-on time of the first conducting part 21.

[0063] The electrostatic discharge protection structure provided in the embodiment of the present application utilizes the second drain 202 of the second conductive part 22 to be connected to the first end of the conductive unit NPN, and the second end of the conductive unit NPN is grounded, so that the conductive unit can be triggered under a very small start-up voltage, thereby completing the discharge of the electrostatic discharge current, thereby reducing the start-up voltage of the second conductive part 22 and increasing the start-up speed of the second conductive part 22. In addition, the second conductive part 22 can be prevented from being broken down by an excessive current, thereby improving the reliability of the electrostatic discharge protection structure.

[0064] In some embodiments, see Figure 6 The third conducting portion 23 includes a second resistor R2 , one end of the second resistor R2 is connected to the second gate 201 , and the other end of the second resistor R2 is connected to the second source 203 .

[0065] Exemplarily, one end of the second resistor R2 is connected to the second gate 201, and the other end of the second resistor R2 is connected to the second source 203, which can generate a Miller capacitor between the second gate 201 and the second drain 202, thereby reducing the turn-on voltage of the third conductive part 23 and increasing the turn-on speed of the third conductive part 23.

[0066] The electrostatic discharge protection structure provided in the embodiment of the present application can make the turn-on voltage of the third conduction part 23 lower than the turn-on voltage of the second conduction part 22 by setting the second resistor in the third conduction part 23, so that the turn-on speed of the third conduction part 23 can be greater than the turn-on speed of the second conduction part 22, so as to ensure that the first conduction part 21, the second conduction part 22 and the third conduction part 23 are turned on at the same time, thereby improving the conduction uniformity of the second conduction area 20.

[0067] In some embodiments, see Figure 1 The electrostatic discharge protection structure further includes nanotubes 30, and the nanotubes 30 on the top surfaces of the first source 103, the second source 203, the first drain 102 and the second drain 202 are arranged at intervals along the second direction; the first direction is perpendicular to the second direction.

[0068] For example, the types of nanotubes 30 may include but are not limited to single-walled carbon nanotubes 30 and multi-walled carbon nanotubes 30 . The nanotubes 30 may form a conductive path in the polymer matrix, so that static charges are quickly dissipated.

[0069] The electrostatic discharge protection structure provided in the embodiment of the present application can form a conductive path in the polymer matrix by arranging nanotubes 30 on the top surfaces of the first source 103, the second source 203, the first drain 102 and the second drain 202, so that static charge can be dissipated quickly and electrostatic discharge can be prevented from damaging electronic components.

[0070] In some embodiments, see Figure 7 The electrostatic discharge protection structure also includes: a substrate 40, a first gate 101, a second gate 201, a first drain 102, a second drain 202, a first source 103 and a second source 203 are located on the top surface of the substrate 40; a doped region 50 is located between the first drain 102 and the substrate 40, and between the second drain 202 and the substrate 40, and the conductivity type of the doped region 50 is different from the conductivity type of the first drain 102 and the second drain 202.

[0071] Exemplarily, the substrate 40 may include but is not limited to at least one of a silicon substrate 40, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon on insulator (SOI) substrate, a silicon on diamond (SOD) substrate, and a strained layer silicon substrate deposited on a silicon germanium wafer; in the present embodiment, the substrate is a silicon substrate.

[0072] Exemplarily, the conductivity type of the doping region 50 may be P-type or N-type.

[0073] The electrostatic discharge protection structure provided in the embodiment of the present application can reduce the breakdown voltage of the second drain 202 and the first drain 102 by setting the doped region 50 between the second drain 202 and the substrate 40, thereby protecting the internal circuit and preventing the internal circuit from being damaged due to excessive breakdown voltage. Furthermore, the reliability of the electrostatic discharge protection structure can be further improved when the turn-on moments of the first conductive region and the second conductive region are the same.

[0074] It should be noted that the electrostatic discharge protection structure provided in the embodiment of the present application may also include a metal barrier layer and a contact hole, the metal barrier layer is located on the top surface of the substrate 40, and can reduce the on-resistance of the device. The contact hole is located on the top surface of the gate, and can form a path in different dielectric layers to form a current path.

[0075] An embodiment of the present application provides an electronic device, including the electrostatic discharge protection structure in the above embodiment.

[0076] The electrostatic discharge protection structure of the present application, through the grounding of the gate in the first conductive area 10 and the second conductive area 20, can be in the case where the voltage between the source and the substrate 40 exceeds the threshold voltage of the NMOS, the NMOS will enter the on state, forming a low impedance path, and discharge the electrostatic discharge current to the ground, thereby protecting the internal circuit. By adjusting the size of the first spacing between the first gate 101 and the first drain 102, the turn-on voltage of the first conductive area 10 can be adjusted, and then the turn-on time of the first conductive area 10 can be adjusted, so that the turn-on time of the first conductive area 10 is the same as the turn-on time of the second conductive area 20, and then the uniform conduction between the multiple interdigits of the electrostatic discharge structure can be made, and then the overall current capacity and discharge capacity of the device can be improved, the voltage overshoot can be reduced, and the core circuit can be protected from high voltage breakdown. The on-resistance of the entire structure can be reduced, thereby reducing the voltage drop when discharging the current, ensuring that the voltage of the protected circuit is maintained at a safe level during electrostatic discharge. Furthermore, uniform conduction of multiple interdigits can avoid damage to the electrostatic discharge protection structure due to excessively high local temperature, thereby improving the reliability of the electrostatic discharge protection structure.

[0077] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0078] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. An electrostatic discharge protection structure, characterized in that: include: A first conductive region, the first conductive region comprising a first gate, and a first drain and a first source located on opposite sides of the first gate, wherein the first gate is grounded, and a first distance is provided between the first gate and the first drain; A second conductive region, wherein the second conductive region is located on two opposite sides of the first conductive region, the second conductive region comprises a plurality of second gates, and a second drain and a second source located on two opposite sides of the second gates, the plurality of second gates are arranged at intervals along a first direction parallel to a top surface of the first gate, wherein the second gates are grounded, and the conduction timing of the second conductive region is the same as that of the first conductive region.

2. The electrostatic discharge protection structure according to claim 1, characterized in that: The second conductive region includes a first conductive portion, a second conductive portion and a third conductive portion, the second conductive portion is located between the first conductive portion and the third conductive portion, the conductive voltage of the first conductive portion is greater than the conductive voltage of the second conductive portion, and the conductive voltage of the second conductive portion is greater than the conductive voltage of the third conductive portion.

3. The electrostatic discharge protection structure according to claim 2, characterized in that: The second drain and the second gate of the first conductive portion include a second interval therebetween.

4. The electrostatic discharge protection structure according to claim 3, characterized in that: The first spacing is associated with a distance between the first gate and the first drain, and the second spacing is associated with a distance between the second gate and the second drain, wherein the first spacing is greater than the second spacing.

5. The electrostatic discharge protection structure according to claim 2, characterized in that: The second conductive part includes a capacitor and a first resistor, the first plate of the capacitor is connected to the second gate, and the second plate is connected to the power supply voltage and the second drain, one end of the first resistor is connected to the second gate and the first plate, and the other end of the first resistor is connected to the second source.

6. The electrostatic discharge protection structure according to claim 2, characterized in that: The second drain of the second conduction portion is connected to the first end of the conduction unit, and the second end of the conduction unit is grounded, wherein the conduction voltage of the conduction unit is a preset conduction voltage.

7. The electrostatic discharge protection structure according to claim 2, characterized in that: The third conducting portion includes a second resistor, one end of the second resistor is connected to the second gate, and the other end of the second resistor is connected to the second source.

8. The electrostatic discharge protection structure according to claim 1, characterized in that: Also includes nanotubes, The nanotubes on the top surfaces of the first source electrode, the second source electrode, the first drain electrode, and the second drain electrode are arranged at intervals along a second direction; the first direction is perpendicular to the second direction.

9. The electrostatic discharge protection structure according to claim 1, characterized in that: Also includes: A substrate, wherein the first gate, the second gate, the first drain, the second drain, the first source and the second source are located on a top surface of the substrate; The doped region is located between the first drain and the substrate, and between the second drain and the substrate, and the conductivity type of the doped region is different from the conductivity type of the first drain and the second drain.

10. An electronic device, characterized in that: include: The electrostatic discharge protection structure according to any one of claims 1 to 9.

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