Photoelectric integrated semiconductor device and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, in particular to a photoelectric integrated semiconductor device and a preparation method thereof. The semiconductor device comprises a pixel unit and a logic unit which have the same substrate, the pixel unit comprises a transition layer and a light absorption layer located on the transition layer, and the material of the transition layer comprises the material of the light absorption layer; wherein the pixel unit is used for converting near-infrared light absorbed by the light absorption layer into an electric signal and transmitting the electric signal to the logic unit; the logic unit comprises a source-drain structure, and the source-drain structure comprises a transition layer; the logic unit is used for logically processing the electric signals. The semiconductor device provided by the invention has the characteristics of simple structure, convenience in miniaturization and high preparation efficiency.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a photoelectric integrated semiconductor device and a preparation method thereof. Background Art

[0002] As the size of related equipment using semiconductor devices continues to decrease, in order to adapt to smaller devices, such as electronic equipment in the optoelectronic field, the integration of photoelectric sensors continues to increase.

[0003] In the related art, the photoelectric sensor integrates the independent photoelectric conversion unit and the logic processing unit by wire bonding, or designs multiple photoelectric conversion units and logic processing units into a stacked structure, and realizes the integration of multiple units by deploying metal wires and conductive vias in multiple layers. However, this makes the structure of the photoelectric sensor more complex and the reliability is also low. In addition, in order to adapt to light of different wavelengths, the photoelectric sensor will set the required light absorption layer on its substrate. When the substrate and the light absorption layer are made of different types of materials, there will be a lattice mismatch problem, which further affects the reliability of the device. Summary of the invention

[0004] In order to solve the detection technology problems of the above-mentioned prior art photoelectric sensors with complex structures and poor reliability, the present application discloses, on one hand, a photoelectric integrated semiconductor device, which includes a pixel unit and a logic unit having the same substrate;

[0005] The pixel unit includes a transition layer and a light absorbing layer located on the transition layer; the pixel unit is used to convert the near-infrared light absorbed by the light absorbing layer into an electrical signal and transmit it to the logic unit; the material of the transition layer includes the material of the light absorbing layer;

[0006] The logic unit includes a source-drain structure, and the source-drain structure includes a transition layer; the logic unit is used for performing logic processing on the electrical signal.

[0007] Furthermore, the material of the substrate is the first type of material; the material of the light absorption layer is the second type of material; the material of the transition layer includes the first type of material and the second type of material;

[0008] The content of the second type of material in the transition layer gradually decreases along a first direction; the first direction is an extension direction from the light absorbing layer toward the transition layer.

[0009] Further, the first type of material includes silicon;

[0010] The second class of materials includes germanium.

[0011] Furthermore, the transition layer includes a plurality of germanium-silicon layers; in each germanium-silicon layer, the content of silicon accounts for 1 to 99%; the content of germanium accounts for 1 to 99%;

[0012] The germanium content of the germanium silicon layer in the region corresponding to the transition layer gradually decreases along the first direction;

[0013] The thickness of each silicon germanium layer ranges from 1 angstrom to 5 microns.

[0014] Furthermore, a trench isolation structure is provided on two opposite sides of the pixel unit, respectively, and one of the two trench isolation structures is located between the pixel unit and the logic unit;

[0015] The trench isolation structure is filled with an isolation material;

[0016] The isolation material includes silicon oxide or polysilicon.

[0017] Furthermore, the pixel unit also includes an N-type doping layer and a P-type doping layer;

[0018] The N-type doped layer is located at the bottom of the transition layer;

[0019] The P-type doped layer is located on the light absorbing layer.

[0020] Furthermore, a light shielding structure is provided on one side of each trench isolation structure; the light shielding structure is used to block light of a preset wavelength from passing through.

[0021] Furthermore, a light shielding structure is provided between the pixel unit and each trench isolation structure;

[0022] The light shielding structure includes a photonic crystal isolation structure.

[0023] Further, the photonic crystal isolation structure includes a plurality of holes distributed periodically;

[0024] The width of the pores ranges from 50 to 300 nanometers;

[0025] The distance between adjacent holes is 200 to 400 nanometers.

[0026] Furthermore, the thickness of the light absorbing layer ranges from 1 angstrom to 10 micrometers.

[0027] Furthermore, the logic unit is a metal oxide semiconductor field effect transistor.

[0028] In another aspect, the present application further discloses a method for preparing a semiconductor device, which comprises:

[0029] A semiconductor structure is provided; the semiconductor structure includes an initial pixel unit and an initial logic unit having a same substrate; the initial pixel unit includes an N-type doped layer located in the substrate; the initial logic unit includes an N-well or a P-well located in the substrate and a gate structure located on the N-well or the P-well;

[0030] forming transition layers on both sides of the gate structure and the N-type doped layer respectively;

[0031] Ion implantation is performed on the transition layer on both sides of the gate structure to obtain a logic unit;

[0032] A light absorbing layer is formed on the transition layer of the initial pixel unit to obtain a pixel unit; the pixel unit is used to convert near-infrared light absorbed by the light absorbing layer into an electrical signal and transmit it to a logic unit; the logic unit is used to perform logic processing on the electrical signal; the material of the transition layer includes the material of the light absorbing layer.

[0033] Furthermore, transition layers are formed on both sides of the gate structure and the N-type doped layer, respectively, including:

[0034] Using an etching process, two first grooves separated by a preset distance are formed in the area corresponding to the N-well or the P-well; a first groove is provided on both sides of the gate structure;

[0035] Forming a second groove in the N-type doped layer by an etching process;

[0036] While the transition material is deposited in the second groove, the transition material is deposited in the two first grooves to form a transition layer; the height of the transition layer in the first groove ranges from 1 angstrom to 5 microns.

[0037] Furthermore, the semiconductor structure also includes a trench isolation structure;

[0038] A trench isolation structure is respectively provided on two opposite sides of the pixel unit, and one of the two trench isolation structures is located between the pixel unit and the logic unit;

[0039] The trench isolation structure is filled with an isolation material;

[0040] The isolation material includes silicon oxide or polysilicon.

[0041] Furthermore, the method also includes:

[0042] A light shielding structure is formed on one side of each trench isolation structure.

[0043] The semiconductor device provided by the present application includes a pixel unit and a logic unit having the same substrate, wherein the pixel unit includes a transition layer and a light absorption layer located on the transition layer, wherein the pixel unit is used to convert the near-infrared light absorbed by the light absorption layer into an electrical signal and transmit it to the logic unit; the logic unit includes a source-drain structure, and the source-drain structure includes a transition layer; and the logic unit is used to perform logic processing on the electrical signal. Thus, it not only has the advantages of simple structure and convenient miniaturization, but also facilitates the integrated preparation of the pixel unit and the logic unit during the molding process, simplifies the preparation steps, and improves the preparation efficiency. Moreover, the material of the above-mentioned transition layer includes the material of the light absorption layer, thereby effectively improving the lattice mismatch problem between the substrate and the light absorption layer and improving the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0045] Figure 1 is a schematic structural diagram of a semiconductor device provided in an embodiment of the present application;

[0046] Figure 2 is a schematic structural diagram of another semiconductor device provided in an embodiment of the present application;

[0047] Figure 3 is a top view of a pixel unit provided in an embodiment of the present application;

[0048] Figure 4 It is a schematic diagram of a process for preparing a semiconductor device provided in an embodiment of the present application;

[0049] Figure 5 is a schematic structural diagram of a semiconductor structure provided in an embodiment of the present application;

[0050] Figure 6 is a schematic structural diagram of a semiconductor structure having a first groove provided in an embodiment of the present application;

[0051] Figure 7 is a schematic structural diagram of a semiconductor device after a second groove is formed according to an embodiment of the present application;

[0052] Figure 8 is a schematic structural diagram of a semiconductor device after a transition layer is formed, provided in an embodiment of the present application;

[0053] Fig. 9 is a schematic structural diagram of a semiconductor device after an isolation layer is formed, provided in an embodiment of the present application;

[0054] Fig.10 is a schematic structural diagram of a semiconductor device after a third groove is formed according to an embodiment of the present application;

[0055] Fig.11 It is a schematic diagram of the structure of a semiconductor device after a P-type doping layer is formed, as provided in an embodiment of the present application.

[0056] The following is a supplementary description of the attached drawings:

[0057] 1-substrate; 2-pixel unit; 21-transition layer; 22-light absorption layer; 23-N-type doping layer; 24-P-type doping layer; 3-logic unit; 31-source-drain structure; 32-N-well or P-well; 33-gate structure; 34-P-type or N-type layer; 35-sidewall structure; 4-trench isolation structure; 41-first isolation layer; 42-second isolation layer; 5-light shielding structure; 6-conductive via; 7-waveguide layer; 8-isolation layer; 9-first groove; 10-second groove; 11-third groove. DETAILED DESCRIPTION

[0058] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0059] The term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present application. In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "top", "bottom", etc. is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first" and "second" are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may include one or more of the features explicitly or implicitly. Moreover, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here.

[0060] When a numerical range is disclosed herein, the above range is deemed to be continuous and includes the minimum and maximum values ​​of the range, as well as each value between such minimum and maximum values. Further, when a range refers to an integer, each integer between the minimum and maximum values ​​of the range is included. In addition, when multiple ranges are provided to describe features or characteristics, the ranges can be merged. In other words, unless otherwise indicated, all ranges disclosed herein should be understood to include any and all sub-ranges included therein. For example, a specified range from "1 to 10" should be deemed to include any and all sub-ranges between a minimum of 1 and a maximum of 10. Exemplary sub-ranges of ranges 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, etc.

[0061] A photoelectric sensor is a device that can convert light signals into electrical signals based on the photoelectric effect. Its basic working principle is that when light is irradiated on certain substances, the electrons of the substances absorb the energy of photons and produce corresponding electrical effects to detect light signals. This part can be called a pixel unit. After the pixel unit converts the light signal into an electrical signal, a logic operation circuit is required to process the electrical signal. This part of the circuit structure can be called a logic unit. However, in traditional photoelectric sensors, pixel units and logic units are usually stacked in the height direction or integrated by bonding individual devices, which makes the above integration method complicated in preparation process or low in integration.

[0062] To do this, see Figure 1 , Figure 1 It is a structural schematic diagram of a semiconductor device provided by an embodiment of the present application. A semiconductor device with optoelectronic integration is provided, which includes a pixel unit 2 and a logic unit 3 having the same substrate 1, the pixel unit 2 includes a transition layer 21 and a light absorption layer 22 located on the transition layer 21; the pixel unit 2 is used to convert the near-infrared light absorbed by the light absorption layer 22 into an electrical signal and transmit it to the logic unit 3; the logic unit 3 includes a source-drain structure 31, and the source-drain structure 31 includes the transition layer 21; the logic unit 3 is used to perform logic processing on the electrical signal. Since the material of the transition layer 21 includes the material of the light absorption layer 22, the distribution of the material in the transition layer 21 can be adjusted later, which helps to improve the lattice mismatch problem between the light absorption layer 22 and the substrate 1 material or the N-type doped layer 23 in the photodetector, thereby improving the performance of the device. In addition, the above-mentioned pixel unit 2 and logic unit 3 are integrally formed based on semiconductor processing technology, which can greatly simplify the preparation steps, such as the preparation of the transition layer 21, which can be performed simultaneously in the pixel unit 2 and the logic unit 3, and can also further improve the integration of the entire semiconductor device.

[0063] In a feasible embodiment, the material of the substrate 1 is the first type of material; the material of the light absorbing layer 22 is the second type of material; the material of the transition layer 21 includes the first type of material and the second type of material; the content of the second type of material in the transition layer 21 gradually decreases along the first direction, and the content of the first type of material in the transition layer 21 gradually increases along the first direction; the first direction is the extension direction from the light absorbing layer 22 toward the transition layer 21. Thereby, the lattice matching between the substrate and the light absorbing layer can be further improved, thereby improving the device performance.

[0064] In the related art, the above-mentioned pixel unit can be a photodetector. Since silicon has good electrical properties, is compatible with the traditional complementary metal oxide semiconductor (CMOS) process, has low cost and high reliability, the current mainstream photodetector material is mainly silicon. However, the band gap of silicon material is 1.1eV, and the cutoff wavelength of silicon photodetector is about 1100 nanometers. In today's optical fiber communication, 1310 nanometers and 1550 nanometers are the main carrier wavelengths of information. In the field of laser radar, the use of 1550 nanometer near-infrared light can obtain a longer detection distance without harming the human eye. The cutoff wavelength of silicon photodetector is about 1100 nanometers, which cannot realize the light detection of the 1550 nanometer band which is widely used in the field of optical fiber communication and laser radar. For this reason, in a feasible embodiment, the first type of material includes silicon; the second type of material includes germanium. When the first type of material is silicon, the process equipment for preparing the semiconductor device can be compatible with the traditional CMOS process, and has the characteristics of low preparation cost. Of course, the first type of material mentioned above may not be limited to the above silicon as required, and may also include germanium and indium phosphide, etc. For example, when the material of the light absorption layer 22 is germanium, germanium and silicon are semiconductor elements of the same family, the direct band gap of germanium is 0.8eV, and the corresponding photodetector wavelength is around 1550 nanometers. Therefore, this embodiment can realize light absorption in the near-infrared band by forming germanium as the material of the light absorption layer 22 on the silicon substrate 1, and broaden the field of semiconductor devices to which it is applied. And by first setting the transition layer 21 on the silicon substrate 1, the lattice mismatch between germanium and silicon can be effectively reduced. And the transition layer 21 set in the logic unit 3, because it is a germanium silicon stress material, the germanium silicon stress material can generate stress on the silicon substrate, can change the energy band and the effective mass of the carrier, thereby improving the electron mobility of the material, promoting the flow of electrons, so that the device efficiency is improved, that is, the logic operation speed of the logic unit 3 can be effectively improved.

[0065] In order to facilitate understanding of the beneficial effects of the present application, the following description will be made with the first material being silicon and the second material being germanium. It is understandable that the first material and the second material may also be other types of materials (such as germanium and indium phosphide, etc.).

[0066] In a feasible embodiment, the pixel unit 2 further includes an N-type doping layer 23 and a P-type doping layer 24; the N-type doping layer 23 is located at the bottom of the transition layer 21; and the P-type doping layer 24 is located on the light absorbing layer 22. Specifically, the N-type doping layer 23 can be obtained by performing N-type doping on a preset area of ​​the substrate 1. The P-type doping layer 24 is obtained by performing P-type ion implantation from the top surface of the light absorbing layer 22 to perform P-type doping on the light absorbing layer 22. Optionally, the N-type ions corresponding to the N-type doping can be elements corresponding to Group V, such as phosphorus, arsenic or antimony; the P-type ions can include boron ions, boron fluoride ions or indium ions.

[0067] In a feasible embodiment, the transition layer 21 may include several germanium silicon layers; in each germanium silicon layer, the content of silicon is 1-99%, such as 1%, 3%, 5%, 10%, 20%, 30%, 40%, 50%, 70%, 80%, 99%; the content of germanium is 1-99%, such as 1%, 3%, 5%, 10%, 20%, 30%, 40%, 50%, 70%, 80%, 99%; the content of germanium in the region corresponding to the transition layer 21 of the germanium silicon layer gradually decreases along the first direction; the content of silicon in the region corresponding to the transition layer 21 of the germanium silicon layer gradually increases along the first direction, so as to further improve the lattice mismatch between the N-type doped layer 23 and the light absorption layer 22 and improve the device performance. The number of germanium silicon layers can be set as needed, for example, it can be a positive integer such as 1, 2, 3, 4 or 5. Generally, the more the number of germanium silicon layers, the more conducive it is to reduce the lattice mismatch of silicon germanium. Optionally, the thickness of each silicon germanium layer ranges from 1 angstrom to 5 microns, such as 1 angstrom, 1 nanometer, 1 micron, 2 microns, 3 microns, 4 microns, 5 microns, etc.

[0068] In a feasible embodiment, the above-mentioned pixel unit 2 can specifically be a single photon avalanche diode (SPAD). SPAD has become a mainstream photodetector that has attracted widespread attention due to its high sensitivity and picosecond time response. In other embodiments, the pixel unit 2 can also be a photodiode, a four-quadrant detector, etc. Usually, according to the use requirements, SPADs can be arranged into different arrays to form silicon photodiodes (Silicon Photomultiplier, SiPM), in which each SPAD works independently. When the device size becomes smaller, the anti-interference ability of SPADs is weakened, which will cause erroneous light and electrical signal sensing (i.e. optical crosstalk and electrical crosstalk). Therefore, in order to improve the accuracy of detection, please refer to Figure 2 , Figure 2: is a schematic diagram of the structure of a semiconductor device provided by an embodiment of the present application. A trench isolation structure 4 can be provided on opposite sides of the pixel unit 2, and one of the two trench isolation structures 4 is located between the pixel unit 2 and the logic unit 3; the trench isolation structure 4 is filled with an isolation material; the isolation material may include silicon oxide or polysilicon. Thus, the electrical and optical crosstalk problems between the pixel unit 2 and the logic unit 3 can be effectively reduced. It can be understood that in the actual manufacturing process, it is usually a large-scale manufacturing, and a plurality of pixel units 2 and logic units 3 are arrayed on a wafer substrate 1, and a trench isolation structure 4 can be provided between adjacent pixel units 2 or between adjacent logic units 3 or between adjacent pixel units 2 and logic units 3. Although the above-mentioned trench isolation structure 4 has a certain effect of preventing optical crosstalk, there are still certain limitations. For example, for near-infrared light of 1550 nanometers, the above-mentioned trench isolation structure 4 is almost transparent, so that this kind of trench isolation structure 4 can only prevent electrical crosstalk, but cannot prevent optical crosstalk. To this end, in a feasible embodiment, a light shielding structure 5 can be provided on one side of each trench isolation structure 4; since the light shielding structure 5 is used to block the passage of light of a preset wavelength, light shielding of near-infrared light of 1550 nanometers can be achieved.

[0069] In a feasible embodiment, the light shielding structure 5 can be arranged between the trench isolation structure 4 and the logic unit 3, but this arrangement will lose the energy of the photons, which is not conducive to the photons passing through the trench isolation structure 4, thereby reducing the photoelectric conversion efficiency of the pixel unit 2. Therefore, in another feasible embodiment, please refer to Figure 2 A light shielding structure 5 may be provided between the pixel unit 2 and each trench isolation structure 4. For details, please refer to Figure 3 The light shielding structure 5 and the trench isolation structure 4 can be arranged around the pixel unit 2, so as to further improve the device's performance in preventing light and electrical crosstalk. Optionally, the light shielding structure 5 can be a photonic crystal isolation structure, or other structures that can shield light of a preset wavelength.

[0070] Photonic crystal is an artificial periodic dielectric structure. When passing through this structure, the medium has a periodic change in refractive index, which can prevent light waves within a certain wavelength range from propagating in this structure, which is the so-called photonic bandgap or optical bandgap. According to the dimension of the photonic bandgap of the photonic crystal in space, it can be divided into one-dimensional photonic crystals, two-dimensional photonic crystals and three-dimensional photonic crystals. Taking two-dimensional photonic crystals as an example, the usual practice is to generate periodically arranged circular holes in the two-dimensional direction of the flat medium, and fill the circular holes with a material with a refractive index lower than that of the flat medium. The size and spacing of the above circular holes are generally controlled in the range of tens to hundreds of nanometers.

[0071] In a feasible embodiment, the photonic crystal isolation structure includes a plurality of periodically distributed holes; the width of the holes ranges from 50 to 300 nanometers, and the specific width of the holes can be 50 nanometers, 60 nanometers, 80 nanometers, 100 nanometers, 150 nanometers, 200 nanometers and 300 nanometers, etc.; the distance between adjacent holes is 200 to 400 nanometers, and the specific distance between adjacent holes can be 200 nanometers, 220 nanometers, 250 nanometers, 300 nanometers, 350 nanometers, 400 nanometers, etc. The wavelength of light that can be shielded by the photonic crystal isolation structure is jointly determined based on its size and the periodic distribution of the holes. Optionally, the shape of the cross section of the hole can include a circle and a polygon.

[0072] In a feasible embodiment, the thickness of the light absorbing layer 22 ranges from 1 angstrom to 10 microns. Specifically, the thickness of the light absorbing layer 22 can be 1 angstrom, 1 nanometer, 1 micron, 3 microns, 5 microns, 7 microns, 9 microns, 10 microns, etc.

[0073] Please continue reading Figure 2 The pixel unit 2 shown belongs to a SPAD type photodetector, and the light absorption layer 22 can also be called an intrinsic layer. Its working principle is that when the SPAD is biased at a reverse high voltage, the incident near-infrared light is absorbed in the light absorption layer 22, and electron-hole pairs are formed in the depletion region, and an avalanche occurs, realizing the conversion of optical signals to electrical signals. Because the near-infrared wavelength is large, the trench isolation structure 4 can only play the role of electronic isolation, but cannot isolate photons. Therefore, a periodic two-dimensional photonic crystal isolation structure is designed on both sides of the SPAD, which can effectively limit the passage of light within a specific wavelength range, thereby preventing optical crosstalk.

[0074] In a feasible embodiment, the logic unit 3 is a metal oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), which can also be referred to as a MOS tube. Specifically, it can include a P-channel MOS field effect transistor (abbreviated as POMS) and an N-channel MOS field effect transistor (abbreviated as NOMS). Among them, PMOS refers to a MOS tube with an n-type substrate, a p-type channel, and a current transported by the flow of holes, and NMOS refers to a MOS tube with a p-type substrate, an n-type channel, and a current transported by the flow of holes. Please continue to refer to Figure 2, the source-drain structure of the logic unit 3 may specifically include a transition layer and an N-type or P-type layer 34 located on the transition layer. When the logic unit 3 is a PMOS, an N-well is provided in a preset area of ​​the substrate 1, and a source-drain structure 31 is provided on the N-well, that is, a source structure and a drain structure. Each of the source structure and the drain structure includes a transition layer 21 located at the bottom layer, and a P-type layer located on the transition layer 21. When the transition layer 21 is a germanium-silicon stress material, the speed of the PMOS can be effectively improved. A gate structure 33 is provided between the source structure and the drain structure. Since the source structure and the drain structure are not conductive, when a sufficient positive voltage is applied to the source structure (the gate structure is grounded), the surface of the N-well under the gate structure presents a P-type inversion layer, which becomes a channel connecting the source structure and the drain structure. By changing the gate voltage, the hole density in the channel can be changed, thereby changing the resistance of the channel. Similarly, when the logic unit 3 is an NMOS, the main difference between it and the PMOS is that the N well in the PMOS is replaced by a P well, and the P type layer in the PMOS is replaced by an N type layer.

[0075] Please continue reading Figure 2 In this embodiment, staggered waveguide layers 7 and isolation layers 8 may be provided on the substrate 1; wherein the material of the waveguide layer 7 may include silicon nitride or silicon oxide; the material of the isolation layer 8 may include silicon oxide or silicon nitride. Optionally, the thickness of the waveguide layer 7 may be 1 micron to 10 microns, such as 1 micron, 3 microns, 5 microns, 7 microns, 9 microns, 10 microns, etc.; the thickness of the isolation layer 8 may be 1 micron to 10 microns, such as 1 micron, 3 microns, 5 microns, 7 microns, 9 microns, 10 microns, etc. In order to realize signal transmission between multiple units, conductive vias 6 may be reasonably provided between the required layers as needed to realize electrical connection of these layers.

[0076] The optoelectronic integrated semiconductor device provided in the present application integrates the pixel unit 2 and the logic unit 3 on the same surface, taking into account both integration and cost advantages. The transition layer formed simultaneously in the pixel unit 2 and the logic unit 3 can not only reduce the lattice mismatch problem between the light absorption layer 22 and the substrate, but also improve the logic operation speed of the logic unit 3. The introduction of the light shielding structure 5 can effectively prevent light crosstalk and improve the detection quality of the pixel unit 2.

[0077] On the other hand, see Figure 4-11 The present application also discloses a method for preparing a semiconductor device, the method comprising:

[0078] S401: Provide a semiconductor structure (such as Figure 5As shown); the semiconductor structure includes an initial pixel unit 2 and an initial logic unit 3 having the same substrate 1; the initial pixel unit 2 includes an N-type doped layer 23 located in the substrate 1; the initial logic unit 3 includes an N-well or P-well 32 located in the substrate 1 and a gate structure 33 located on the N-well or P-well 32.

[0079] In step S401, the deep trench isolation technology (Front Side Deep Trench Isolation, FDTI) can be specifically used to implement the preparation of the trench isolation structure 4 on both sides of the initial logic unit 3 and the initial pixel unit 2. And the N-type doping layer 23 can be specifically obtained by performing N-type ion implantation on a preset area of ​​the substrate 1, and the N-well or P-well 32 can be specifically obtained by performing N-type ion implantation or P-type ion implantation on a preset area of ​​the substrate 1. Optionally, the trench isolation structure 4 is filled with an isolation material, and the isolation material includes silicon oxide or polycrystalline silicon. Optionally, a sidewall structure 35 is respectively provided on the opposite side surfaces of the gate structure 33 located on the substrate 1. The function of the sidewall structure 35 is to prevent the heavily doped ions from affecting the lightly doped structure during the implantation process. The material of the sidewall structure 35 can be silicon dioxide, organic silicon compound (such as Si(OC 2 H 5 ) 4 ). Among them, deep trench isolation technology is a technology for forming a deep trench isolation structure on the front side of a wafer. Specifically, the process of forming the trench isolation structure 4 can be: etching the front side of the provided wafer to form a plurality of grooves on the substrate. The depth of the groove can be adjusted according to the needs of the device isolation performance. Generally, the depth of the groove can be divided into two types, deep groove and shallow groove. Subsequently, the isolation material can be directly deposited in the groove, or a layer of silicon oxide can be first deposited on the inner surface of the groove, and then the isolation material is filled to further improve the isolation effect. Optionally, the etching process for etching the wafer can select a dry etching process or a wet etching process, which is not limited here.

[0080] The above-mentioned gate structure can be formed by a gate-last process. The specific process can be that a gate dielectric layer is first formed on the substrate, and then a polysilicon layer for making a dummy gate is covered on the gate dielectric layer, and a dummy gate is formed by photolithography and etching. Then, oxynitride sidewalls are sequentially deposited on the semiconductor substrate on which the dummy gate is formed, and the sidewalls are etched by a dry etching process, leaving oxynitride walls in the vertical direction on both sides of the remaining dummy gate, and then an interlayer dielectric layer (ILD, interlayer dielectric) is deposited, and the interlayer dielectric layer is flattened by a chemical mechanical polishing process until the dummy gate is exposed; the dummy gate is removed to form a groove, and then a high dielectric layer is formed inside the groove, and then a metal layer is deposited to fill the groove to form a metal gate. The material of the dummy gate is generally polysilicon and amorphous silicon. Optionally, the material of the gate dielectric layer includes a high dielectric constant material, and the dielectric constant of the high dielectric constant material is greater than 3.9. Optionally, the metal material can be one or more combinations of copper, aluminum, tungsten, chromium, titanium, copper, silver and gold. Optionally, the above-mentioned gate structure can also be prepared by other processes, such as a gate-first process, using interface modulation of high-k dielectric / metal gate, adjusting the effective work function by introducing a dipole layer at the interface, usually using a metal with a work function located in the middle of the bandgap (such as TiN), and adjusting the threshold voltage Vt by depositing different covering layers on (or under) the high-k dielectric.

[0081] In this example, see Figure 5 , a second isolation layer 42 is formed on the top surface of the substrate 1 by using a deposition or epitaxial growth process, and the second isolation layer 42 is used as a gate dielectric layer to control the channel and protect the isolation substrate 1. Optionally, the second isolation layer 42 between the gate structure 33 and the substrate 1 can be made of the same material as the isolation layer 8, such as silicon oxide. Optionally, the thickness of the second isolation layer 42 can be 1 to 4 nanometers, such as 1 nanometer, 1.5 nanometers, 2 nanometers, 3 nanometers, 4 nanometers, etc.

[0082] It is understandable that in the actual manufacturing process, it is usually a large-scale manufacturing, and a plurality of pixel units 2 and logic units 3 are arrayed on a wafer substrate 1, and a trench isolation structure 4 can be set between adjacent pixel units 2 or between adjacent logic units 3, or between adjacent pixel units 2 and logic units 3. Although the above-mentioned trench isolation structure 4 has a certain effect of preventing optical crosstalk, it has certain limitations, such as being almost transparent to near-infrared light of 1550 nanometers, so that this kind of trench isolation structure 4 can only prevent electrical crosstalk, and cannot play a role in preventing optical crosstalk. For this reason, a light shielding structure 5 can also be set on one side of the trench isolation structure 4, and the specific formation process is detailed below.

[0083] S403 : forming transition layers 21 on both sides of the gate structure 33 and the N-type doped layer 23 respectively.

[0084] In a feasible embodiment, the specific implementation of step S403 may include: using an etching process to form two first grooves 9 spaced by a preset distance in the area corresponding to the N-well or P-well 32, so as to obtain Figure 6 The structure shown; a first groove 9 is provided on both sides of the gate structure 33; a second groove 10 is formed in the N-type doped layer 23 by etching process, and the Figure 7 while depositing the transition material in the second groove 10, the transition material is deposited in the two first grooves 9 to form a transition layer 21, and the transition layer 21 is formed. Figure 8 Optionally, the cross section of the first groove 9 can be as follows: Figure 6 The hexagonal shape shown, the first groove 9 with a hexagonal cross section can generate uniaxial compressive stress in the crystal direction

[110] direction on the silicon substrate, split the valence band energy band, reduce the effective mass of the hole in the channel direction, and improve the device speed; it can also be a triangle or a circle, etc., which is not limited here. Optionally, in the process of etching the first groove 9, in order to improve the etching efficiency and the etching accuracy at the same time, the N well or P well 32 can be initially etched by a dry etching process, and after reaching the preset size, further etching is performed by wet anisotropy to obtain the first groove 9 of the required size and shape. Optionally, the etching process of the second groove 10 can be a wet etching process, but in order to improve the etching accuracy, a dry etching process can also be used, which is not limited here. Optionally, the height range of the transition layer 21 in the first groove 9 is 1 angstrom to 5 microns, such as 1 angstrom, 1 nanometer, 1 micron, 2 microns, 3 microns, 4 microns, 5 microns, etc. The aspect ratio of the second groove 10 is 0.01 to 1.

[0085] The steps of depositing the transition layer 21 on both sides of the gate structure 33 and the N-type doped layer 23 in step S403 can be performed simultaneously, thereby improving the preparation efficiency. The deposition process of the transition layer 21 can be molecular beam epitaxy or chemical vapor deposition.

[0086] The specific process of the dry etching process may include: first forming a barrier layer on the substrate. Specifically, the method of forming the barrier layer can be selected according to the material type of the barrier layer. For example, if the barrier layer is a polymer material, spin coating or roll coating can be used, wherein spin coating has the advantage of good controllability, and roll coating has the advantage of high preparation efficiency. If the barrier layer is an inorganic non-metallic material, it can be formed by deposition and other processes. The following takes the barrier layer as a polymer material as an example for explanation. After the barrier layer is formed, the barrier layer is exposed by setting the exposure parameters of the preset conditions and the patterned mask, and then developed (removing the uncured barrier layer) to form a patterned barrier layer. The exposed substrate is etched by using an ion beam or other method to remove the residual barrier layer, and the desired structure can be obtained. The specific process of the above-mentioned wet etching process may include: first forming a barrier layer on the substrate, if the barrier layer is a polymer material, exposing the barrier layer by setting preset exposure parameters and a patterned mask, and then developing (removing the uncured barrier layer) to form a patterned barrier layer, and then etching the exposed substrate portion with a configured etching solution to remove the residual barrier layer to obtain a substrate with a desired structure.

[0087] In this embodiment, as mentioned above, the etching of the first groove 9 includes two parts: first, dry etching is performed to etch a groove with a circular cross-section, and then wet etching is performed to etch a groove with a hexagonal cross-section using anisotropic etching; the etching of the second groove 10 can specifically be performed by dry etching.

[0088] In this embodiment, the transition layer 21 may include several germanium silicon layers; in each germanium silicon layer, the content of silicon is 1-99%, such as 1%, 3%, 5%, 10%, 20%, 30%, 40%, 50%, 70%, 80%, 99%; the content of germanium is 1-99%, such as 1%, 3%, 5%, 10%, 20%, 30%, 40%, 50%, 70%, 80%, 99%; the content of germanium in the region corresponding to the transition layer 21 of the germanium silicon layer gradually decreases along the first direction; the content of silicon in the region corresponding to the transition layer 21 of the germanium silicon layer gradually increases along the first direction, so as to further improve the lattice mismatch between the N-type doped layer 23 and the light absorption layer 22 and improve the device performance. The number of germanium silicon layers can be set as needed, for example, it can be a positive number such as 1, 2, 3, 4 or 5. Generally, the more the number of germanium silicon layers, the more conducive it is to reduce the lattice mismatch of silicon germanium. Optionally, the thickness of each germanium silicon layer ranges from 1 angstrom to 5 microns, such as 1 angstrom, 1 nanometer, 1 micron, 2 microns, 3 microns, 4 microns, 5 microns, etc. Therefore, when the transition layer 21 includes multiple germanium silicon layers, it can be deposited by multiple times of germanium and silicon, and the germanium source (such as GeH 4 ) and silicon sources (such as SiCl4 、SiHCl 3 、SiH 4 ) ratio to adjust the content ratio of germanium and silicon deposited each time.

[0089] S405: Perform ion implantation on the transition layer 21 on both sides of the gate structure 33 to obtain a logic unit 3.

[0090] When the logic unit 3 is a POMS, the ions implanted in step S405 may be P-type ions, and when the logic unit 3 is a NOMS, the ions implanted in step S405 may be N-type ions. N-type ions may be elements corresponding to group V, such as phosphorus, arsenic, or antimony; P-type ions may include boron ions, boron fluoride ions, or indium ions.

[0091] In this embodiment, after step S405, the method further includes: forming an isolation layer 8 on the first isolation layer 41, such as Fig. 9 The structure shown.

[0092] S407: A light absorption layer 22 is formed on the transition layer 21 of the initial pixel unit 2 to obtain the pixel unit 2; the pixel unit 2 is used to convert the near-infrared light absorbed by the light absorption layer 22 into an electrical signal, and transmit it to the logic unit 3; the logic unit 3 is used to perform logic processing on the electrical signal; the material of the transition layer 21 includes the material of the light absorption layer 22.

[0093] In this embodiment, the thickness of the light absorbing layer 22 ranges from 1 angstrom to 10 microns. Specifically, the thickness of the light absorbing layer 22 can be 1 angstrom, 1 nanometer, 1 micron, 3 microns, 5 microns, 7 microns, 9 microns, 10 microns, etc.

[0094] It can be understood that the material of the substrate 1 is the first type of material; the material of the light absorbing layer 22 is the second type of material; the material of the transition layer 21 includes the first type of material and the second type of material; the content of the first type of material in the transition layer 21 gradually increases along the first direction; the first direction is the extension direction from the light absorbing layer 22 toward the transition layer 21. Thus, the lattice matching between the substrate and the light absorbing layer can be further improved, thereby improving the device performance.

[0095] The first type of material includes silicon; the second type of material includes germanium. When the first type of material is silicon, the process equipment for preparing the semiconductor device can be compatible with the traditional COMS process, and has the characteristics of low preparation cost. Of course, the above-mentioned first type of material can be not limited to the above-mentioned silicon as needed, for example, it can also include germanium and indium phosphide. When the material of the light absorption layer 22 is germanium, germanium and silicon are semiconductor elements of the same family, the direct band gap of germanium is 0.8eV, and the corresponding photodetector wavelength is around 1550 nanometers. Therefore, this embodiment can achieve light absorption in the near-infrared band by forming germanium as the material of the light absorption layer 22 on the silicon substrate 1. It broadens the field of semiconductor devices to which it is applied. And by first setting the transition layer 21 on the silicon substrate 1, the lattice mismatch between germanium and silicon can be effectively reduced. And the transition layer 21 set in the logic unit 3, because it is a germanium silicon stress material, the germanium silicon stress material can generate stress on the silicon substrate, can change the energy band and the effective mass of the carrier, thereby improving the electron mobility of the material, promoting the flow of electrons, so that the device efficiency is improved, that is, the logic operation speed of the logic unit 3 can be effectively improved.

[0096] In this embodiment, the process of forming the pixel unit 2 may be to first etch the transition layer 21 in the initial pixel unit 2 and the corresponding area thereon to form the third groove 11, so as to obtain the following: Fig.10 The structure shown in FIG. 1 is then deposited in the third groove 11, and a P-type ion implantation is performed on the top region of the intrinsic layer to form a P-type doped layer 24, and the structure shown in FIG. Fig.11 The structure shown; the remaining undoped intrinsic layer can be referred to as the light absorbing layer 22.

[0097] Since the near-infrared wavelength is relatively large, the trench isolation structure 4 can only play the role of electron isolation but cannot isolate photons. Therefore, in order to achieve the performance of preventing optical crosstalk of the semiconductor device, the method also includes: forming a light shielding structure 5 on one side of each trench isolation structure 4, and continuing to alternately deposit the waveguide layer 7 and the isolation layer 8 on the isolation layer 8 to prepare a conductive through hole 6, so as to obtain Figure 2 The semiconductor device structure shown. The material of the waveguide layer 7 may include silicon nitride or silicon oxide; the material of the isolation layer 8 may include silicon oxide or silicon nitride. Optionally, the thickness of the waveguide layer 7 is 1 micron to 10 microns, such as 1 micron, 3 microns, 5 microns, 7 microns, 9 microns, 10 microns, etc.; the thickness of the isolation layer 8 is 1 micron to 10 microns, such as 1 micron, 3 microns, 5 microns, 7 microns, 9 microns, 10 microns, etc. In order to realize signal transmission between multiple units, conductive vias 6 can be reasonably set between the required layers as needed to realize electrical connection of these layers.

[0098] In this embodiment, the light shielding structure 5 can be disposed between the trench isolation structure 4 and the logic unit 3, but the energy of the photons will be lost, which is not conducive to the photons passing through the trench isolation structure 4, thereby reducing the photoelectric conversion efficiency of the pixel unit 2. For this reason, in another feasible embodiment, please refer to Figure 2 A light shielding structure 5 may be provided between the pixel unit 2 and each trench isolation structure 4. For details, please refer to Figure 3 , the light shielding structure 5 and the trench isolation structure 4 can be arranged around the pixel unit 2, so as to further improve the device's performance in preventing light and electrical crosstalk. Optionally, the light shielding structure 5 can be a photonic crystal isolation structure, or other structures that can shield light of a preset wavelength. Optionally, the photonic crystal isolation structure includes a number of periodically distributed holes; the width of the hole ranges from 50 to 300 nanometers, and the specific width of the hole can be 50 nanometers, 60 nanometers, 80 nanometers, 100 nanometers, 150 nanometers, 200 nanometers and 300 nanometers, etc.; the distance between adjacent holes is 200 to 400 nanometers, and the specific distance between adjacent holes can be 200 nanometers, 220 nanometers, 250 nanometers, 300 nanometers, 350 nanometers, 400 nanometers, etc. The wavelength of light that can be shielded by the photonic crystal isolation structure is jointly determined based on its size and the periodic distribution of the holes. Optionally, the shape of the cross section of the hole can include a circle and a polygon.

[0099] It should be noted that the above-mentioned sequence of the embodiments of the present application is for description only and does not represent the advantages and disadvantages of the embodiments. The above-mentioned specific embodiments of this specification are described. Other embodiments are within the scope of the attached claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0100] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0101] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0102] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A photoelectric integrated semiconductor device, It is characterized in that including a pixel unit and a logic unit having a same substrate; The pixel unit includes a transition layer and a light absorbing layer located on the transition layer; the pixel unit is used to convert the near-infrared light absorbed by the light absorbing layer into an electrical signal and transmit it to the logic unit; the material of the transition layer includes the material of the light absorbing layer; The logic unit includes a source-drain structure, and the source-drain structure includes the transition layer; the logic unit is used to perform logic processing on the electrical signal.

2. The semiconductor device according to claim 1, It is characterized in that The material of the substrate is a first type of material; the material of the light absorbing layer is a second type of material; the material of the transition layer includes the first type of material and the second type of material; The content of the second type of material in the transition layer gradually decreases along a first direction; the first direction is an extension direction from the light absorbing layer toward the transition layer.

3. The semiconductor device according to claim 2, It is characterized in that The first type of material includes silicon; The second type of material includes germanium.

4. The semiconductor device according to claim 3, It is characterized in that The transition layer includes a plurality of germanium silicon layers; in each of the germanium silicon layers, the content of silicon accounts for 1 to 99%; the content of germanium accounts for 1 to 99%; The germanium content of the silicon germanium layer in the region corresponding to the transition layer gradually decreases along the first direction; The thickness of each of the silicon germanium layers is in the range of 1 angstrom to 5 microns.

5. The semiconductor device according to claim 1, It is characterized in that A trench isolation structure is respectively provided on two opposite sides of the pixel unit, and one of the two trench isolation structures is located between the pixel unit and the logic unit; The trench isolation structure is filled with an isolation material; The isolation material includes silicon oxide or polysilicon.

6. The semiconductor device according to claim 5, It is characterized in that The pixel unit further includes an N-type doping layer and a P-type doping layer; The N-type doped layer is located at the bottom of the transition layer; The P-type doping layer is located on the light absorbing layer.

7. The semiconductor device according to claim 5, It is characterized in that A light shielding structure is provided on one side of each of the trench isolation structures; the light shielding structure is used to block the passage of light of a preset wavelength.

8. The semiconductor device according to claim 7, It is characterized in that A light shielding structure is provided between the pixel unit and each of the trench isolation structures; The light shielding structure includes a photonic crystal isolation structure.

9. The semiconductor device according to claim 8, It is characterized in that The photonic crystal isolation structure includes a plurality of holes distributed periodically; The width of the pores ranges from 50 to 300 nanometers; The distance between adjacent holes is 200 to 400 nanometers.

10. The semiconductor device according to claim 4, It is characterized in that The thickness of the light absorbing layer is in the range of 1 angstrom to 10 micrometers.

11. The semiconductor device according to claim 1, It is characterized in that The logic unit is a metal oxide semiconductor field effect transistor.

12. A method for preparing a semiconductor device, It is characterized in that include: A semiconductor structure is provided; the semiconductor structure includes an initial pixel unit and an initial logic unit having a same substrate; The initial pixel unit includes an N-type doped layer located in the substrate; The initial logic unit includes an N-well or a P-well located in the substrate and a gate structure located on the N-well or the P-well; Forming transition layers on both sides of the gate structure and the N-type doping layer respectively; Performing ion implantation on the transition layer on both sides of the gate structure to obtain a logic unit; A light absorbing layer is formed on the transition layer of the initial pixel unit to obtain a pixel unit; the pixel unit is used to convert near-infrared light absorbed by the light absorbing layer into an electrical signal and transmit it to the logic unit; the logic unit is used to perform logic processing on the electrical signal; the material of the transition layer includes the material of the light absorbing layer.

13. The preparation method according to claim 12, It is characterized in that The forming of transition layers on both sides of the gate structure and the N-type doped layer respectively comprises: Using an etching process to form two first grooves spaced apart by a preset distance in a region corresponding to the N-well or the P-well; one first groove is provided on each side of the gate structure; Forming a second groove in the N-type doped layer by an etching process; While the transition material is deposited in the second groove, the transition material is deposited in the two first grooves to form the transition layer; the height of the transition layer in the first groove ranges from 1 angstrom to 5 micrometers.

14. The preparation method according to claim 12, It is characterized in that The semiconductor structure also includes a trench isolation structure; A trench isolation structure is respectively provided on two opposite sides of the pixel unit, and one of the two trench isolation structures is located between the pixel unit and the logic unit; The trench isolation structure is filled with an isolation material; The isolation material includes silicon oxide or polysilicon.

15. The preparation method according to claim 14, It is characterized in that The method further comprises: A light shielding structure is formed on one side of each of the trench isolation structures.

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