Integrated circuit device, method of forming same, and package

Abstract

Various embodiments of the present disclosure are directed to a device including an interconnect structure over a substrate. The bonding structure is over the interconnect structure. The bonding structure includes a first plurality of conductive bonding pads disposed in the first region and a second plurality of conductive bonding pads disposed in the second region. The second region is adjacent to at least one side of the first region. A first pitch of the first plurality of conductive bond pads is less than a second pitch of the second plurality of conductive bond pads. Embodiments of the present disclosure also relate to an integrated circuit device, a method of forming the same, and a package.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to integrated circuit devices, methods of forming the same, and packages thereof. Background Art

[0002] Many modern electronic devices (e.g., smartphones, digital cameras, biomedical imaging devices, automotive imaging devices, etc.) include image sensors. Image sensors include one or more photodetectors (e.g., photodiodes, phototransistors, photoresistors, etc.) configured to absorb incident radiation and output electrical signals corresponding to the incident radiation. Image sensors may include stacked chips to reduce the footprint of each pixel and increase device density. Summary of the invention

[0003] An embodiment of the present disclosure provides an integrated circuit device, comprising: an interconnect structure located on a substrate, and a bonding structure located above the interconnect structure, wherein the bonding structure includes a first plurality of conductive bonding pads arranged in a first region, and a second plurality of conductive bonding pads arranged in a second region, wherein the second region is adjacent to at least one side of the first region, and wherein a first pitch of the first plurality of conductive bonding pads is smaller than a second pitch of the second plurality of conductive bonding pads.

[0004] Another embodiment of the present disclosure provides a package, the package comprising:

[0005] a first integrated circuit (IC) chip, the first integrated circuit (IC) chip comprising a first substrate, a first interconnect structure, and a first bonding structure, wherein the first bonding structure comprises a first plurality of conductive bonding pads disposed in a first region of the first substrate and a second plurality of conductive bonding pads disposed in a second region of the first substrate, wherein the second region is disposed between the first region and an outer edge of the first integrated circuit chip;

[0006] a second integrated circuit chip, the second integrated circuit chip comprising a second substrate, a second interconnect structure, and a second bonding structure located below the first integrated circuit chip; and

[0007] An interface is provided between the first bonding structure and the second bonding structure, wherein a first density of the first plurality of conductive bonding pads is greater than a second density of the second plurality of conductive bonding pads.

[0008] Yet another embodiment of the present disclosure provides a method for forming an integrated circuit device, comprising:

[0009] Forming a first integrated circuit (IC) chip, wherein the first integrated circuit chip includes a first substrate and a first interconnect structure located above the first substrate; forming a first bonding structure above the first interconnect structure, wherein the first bonding structure includes a first plurality of conductive bonding pads located in a first region and a second plurality of conductive bonding pads located in a second region adjacent to the first region, wherein a pitch of the second plurality of conductive bonding pads is greater than a pitch of the first plurality of conductive bonding pads; and bonding the first integrated circuit chip to a second integrated circuit chip, wherein the second integrated circuit chip includes a second substrate and a second bonding structure, wherein a bonding interface is provided between the first bonding structure and the second bonding structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0011] Figure 1A and Figure 1B Various views of some embodiments of a stacked integrated circuit (IC) device including a bonding structure having first conductive bonding pads arranged at a first pitch and second conductive bonding pads arranged at a second pitch different from the first pitch are shown.

[0012] Figure 2A and Figure 2B Shows Figure 1A and Figure 1B Various views of some other embodiments of stacked IC devices.

[0013] Figure 3A and Figure 3B Shows Figure 1A and Figure 1B Various views of some further embodiments of stacked IC devices.

[0014] Figure 4A and Figure 4B Various views of some embodiments of stacked IC devices including a bonding structure having conductive bonding pads with different pitches disposed across a first region, a second region, and a third region are shown.

[0015] FIG. 5A to FIG. 5H Shows Figure 4A and Figure 4B Various cross-sectional views of some other embodiments of stacked IC devices.

[0016] Figure 6Cross-sectional views of some embodiments of stacked IC devices including a bonding structure having first conductive bonding pads arranged at a first pitch and second conductive bonding pads arranged at a second pitch different from the first pitch are shown.

[0017] Figure 7 Cross-sectional views of some embodiments of stacked IC devices including a bonding structure having conductive bonding pads with different pitches disposed across a first region, a second region, and a third region are shown.

[0018] Figure 8 A top view of some embodiments of a bonding structure of an IC chip having conductive bonding pads with different pitches disposed across a first region, a second region, and a third region is shown.

[0019] 9A to 9C Shows Figure 8 Various top views of some embodiments of conductive bonding pads in first, second, and third regions of FIG.

[0020] Fig. 10A Cross-sectional views of some embodiments of a stacked IC device are shown that include a first IC chip, a second IC chip, and a third IC chip that are vertically stacked on each other.

[0021] Fig. 10B Cross-sectional views of some embodiments of a stacked IC device are shown that include a first IC chip, a second IC chip, a third IC chip, and a fourth IC chip that are stacked vertically on each other.

[0022] Figures 11 to 19 Various cross-sectional views of some embodiments of methods of forming a stacked IC device including a bonding structure having conductive bonding pads with different pitches disposed across a plurality of regions are shown.

[0023] Fig. 20 Methods of forming some embodiments of a stacked IC device including a bonding structure having conductive bonding pads with different pitches disposed across a plurality of regions are shown. DETAILED DESCRIPTION

[0024] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the embodiments and / or configurations discussed.

[0025] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0026] A stacked integrated circuit (IC) device may include a first integrated circuit (IC) chip and a second IC chip stacked vertically on each other. The first IC chip includes a first substrate, a first interconnect structure located on the first substrate, and a first bonding structure located on the first interconnect structure. The stacked IC device may be configured as an image sensor so that a plurality of photodetectors are disposed in the first substrate. A transfer transistor may be disposed on the first substrate and configured to transfer accumulated charges from the photodetector. The second IC chip includes a second substrate, a plurality of semiconductor devices located on the second substrate, a second interconnect structure located on the second substrate, and a second bonding structure located on the second interconnect structure. The first bonding structure and the second bonding structure intersect at a bonding interface and facilitate coupling an electrical signal corresponding to the accumulated charges from the photodetector to a plurality of semiconductor devices on the second substrate.

[0027] The first bonding structure can be configured in a variety of different ways. For example, the first bonding structure may include a plurality of conductive bonding pads disposed in a dielectric bonding structure. A first region of the first bonding structure is directly below a plurality of photodetectors, and a plurality of conductive bonding pads are disposed in a second region of the first bonding structure. The second region is disposed around the first region so that the plurality of conductive bonding pads are laterally offset from the plurality of photodetectors. However, in this configuration, the number and complexity of structures of the conductive interconnects in the first interconnect structure are increased to route electrical signals to a second region laterally offset from the plurality of photodetectors. This increases design complexity and manufacturing costs.

[0028] In another embodiment, the first bonding structure may include a first plurality of conductive bonding pads in the first region and a second plurality of conductive bonding pads in the second region. In addition, a plurality of conductive bonding vias may be provided between the first plurality of conductive bonding pads and the first interconnect structure, so that the first bonding structure has two or more layers of conductive bonding structures. However, including a plurality of conductive bonding vias increases the number of conductive structures in the first bonding structure, thereby increasing the manufacturing cost of the first IC chip. In addition, the first plurality of conductive bonding pads and the second plurality of conductive bonding pads are formed with a constant (e.g., uniform) pitch across the first region and the second region. Due to the limitations of the processing tools (e.g., the limitations of the planarization tools), the second plurality of conductive bonding pads in the second region have the same pitch as the first plurality of conductive bonding pads, which may result in a height variation of the upper surface (e.g., bonding surface) of the first bonding structure. As a result, for example, the upper surface of the first bonding structure may not be substantially flat, and / or the total thickness variation (TTV) of the upper surface is relatively high. This may result in gaps and / or bubbles between the first IC chip and the second IC chip across the bonding interface, so that there is a non-bonding area between the first IC chip and the second IC chip. The non-bonding area is an area between the first IC chip and the second IC chip that are not bonded together during the bonding process. Therefore, the bonding adhesion between the first IC chip and the second IC chip is reduced, and the non-bonding area may cause the stacked IC device to fail the wafer acceptance test (WAT) (e.g., due to an open circuit problem between the IC chips), thereby reducing the structural integrity and / or yield of the stacked IC device.

[0029] Therefore, various embodiments of the present application are directed to a stacked IC device having a bonding structure, which is configured to minimize or prevent non-bonding areas between stacked IC chips and reduce design complexity and manufacturing costs. The stacked IC device includes a first IC chip stacked with a second IC chip. The first IC chip includes a first substrate, a plurality of photodetectors located in the first substrate, a first interconnect structure located on the first substrate, and a first bonding structure located on the first interconnect structure. The first bonding structure includes a first plurality of conductive bonding pads disposed in a first region and a second plurality of conductive bonding pads disposed in a second region. The first region is laterally aligned with the plurality of photodetectors, and the second region is adjacent to at least one side of the first region. The first plurality of conductive bonding pads are arranged at a first pitch (e.g., the distance between opposite sides of adjacent conductive bonding pads), and the second plurality of conductive bonding pads are arranged at a second pitch greater than the first pitch. As a result, the first density of the conductive bonding pads in the first region is greater than the second density of the conductive bonding pads in the second region. The conductive bonding pads in the first region have a first pitch and are laterally aligned with the photodetectors, which reduces the complexity of routing electrical signals generated from the accumulated charge at the photodetectors. Therefore, the complexity and / or number of conductive structures in the first interconnect structure may be reduced, thereby reducing manufacturing costs and improving the performance of the first IC chip (eg, by improving transmission efficiency in the first interconnect structure).

[0030] In addition, a second plurality of conductive bonding pads in the second region having a second pitch greater than the first pitch promotes that the upper surface (e.g., bonding surface) of the first bonding structure is substantially flat and / or the first IC chip has a relatively low TTV. For example, limitations of processing tools (e.g., limitations of chemical mechanical planarization (CMP) tools) result in less material being removed at the peripheral region of the first IC chip. The lower second density of the conductive bonding pads in the second region promotes more uniform removal of the conductive bonding pads in the first region and the second region of the first bonding structure. As a result, the upper surface of the first bonding structure is substantially flat, and the formation of voids and / or bubbles along the bonding interface between the first IC chip and the second IC chip is reduced, thereby reducing or preventing the non-bonding area between the first IC chip and the second IC chip. Therefore, the first bonding structure having a first plurality of conductive bonding pads with a first pitch and a second plurality of conductive bonding pads with a second pitch greater than the first pitch improves the overall performance and yield of the stacked IC device.

[0031] Figure 1A and Figure 1B Various views 100a and 100b of some embodiments of stacked IC devices including a bonding structure having first conductive bonding pads arranged at a first pitch and second conductive bonding pads arranged at a second pitch different from the first pitch are shown. Figure 1AA cross-sectional view 100a of some embodiments of a stacked IC device is shown. Figure 1B Shown along Figure 1A A top view 100b of some embodiments of a stacked IC device is taken along line AA′.

[0032] The stacked IC device includes a first IC chip 102 having a first bonding structure 110 and a second IC chip 104 having a second bonding structure 112. The first bonding structure 110 intersects with the second bonding structure 112 at a bonding interface 105. The first IC chip 102 also includes a first substrate 101, a first interconnect structure 122 located between the first substrate 101 and the first bonding structure 110, and a plurality of pixels 130. The plurality of pixels 130 include a plurality of photodetectors 128 disposed in the first substrate 101.

[0033] The first bonding structure 110 includes a first plurality of conductive bonding pads 116 and a second plurality of conductive bonding pads 118 disposed in the first dielectric structure 114. The first plurality of conductive bonding pads 116 are laterally spaced apart in the first region 106 of the first substrate 101, and the second plurality of conductive bonding pads 118 are laterally spaced apart in the second region 108 of the first substrate 102. In some embodiments, the first plurality of conductive bonding pads 116 and / or the second plurality of conductive bonding pads 118 are electrically coupled to the pixels 130 through the first interconnect structure 122. The first interconnect structure 122 includes a first plurality of conductive lines 120 and a first plurality of conductive vias 123.

[0034] The second IC chip 104 includes a second substrate 103, a second interconnect structure 126 between the second substrate 103 and the second bonding structure 112, and a plurality of semiconductor devices 132 disposed on the second substrate 103. In some embodiments, the plurality of semiconductor devices 132 may be or include, for example, pixel devices (e.g., including source follower transistors, selection transistors, reset transistors, etc.), logic devices, capacitors, other suitable semiconductor devices, etc. The second bonding structure 112 is located on the second interconnect structure 126 and is electrically coupled to the plurality of semiconductor devices 132.

[0035] The second bonding structure 112 includes a third plurality of conductive bonding pads 117 and a fourth plurality of conductive bonding pads 119 disposed in the second dielectric structure 124. The third plurality of conductive bonding pads 117 are laterally spaced apart in the first region 106, and the fourth plurality of conductive bonding pads 119 are laterally spaced apart in the second region 108. In some embodiments, the third plurality of conductive bonding pads 117 and / or the fourth plurality of conductive bonding pads 119 are electrically coupled to the plurality of semiconductor devices 132 through the second interconnect structure 126. The second interconnect structure 126 includes a second plurality of conductive lines 121 and a second plurality of conductive vias 125.

[0036] The first plurality of conductive bonding pads 116 and the third plurality of conductive bonding pads 117 are bonded to each other at the bonding interface 105, and the second plurality of conductive bonding pads 118 and the fourth plurality of conductive bonding pads 119 are bonded to each other at the bonding interface 105. Thus, the conductive bonding pads 116 and / or 118 of the first bonding structure 110 and the conductive bonding pads 117 and / or 119 of the second bonding structure 112 facilitate electrical coupling between the first IC chip 102 and the second IC chip 104. In addition, the first dielectric structure 114 and the second dielectric structure 124 are bonded to each other at the bonding interface 105. Thus, the bonding interface 105 includes a dielectric-to-dielectric bonding interface and a conductor-to-conductor bonding interface.

[0037] The first region 106 is directly below the plurality of pixels 130. In some embodiments, the first region 106 is aligned with the central region of the plurality of pixels 130. The second region 108 is adjacent to at least one side of the first region 106. In various embodiments, the second region 108 wraps the first region 106 laterally and is located below the peripheral region of the plurality of pixels 130. In some embodiments, the conductive bonding pads in the first plurality of conductive bonding pads 116 are arranged in an array including a plurality of rows and a plurality of columns. The first plurality of conductive bonding pads 116 are arranged at a first pitch P1. In some embodiments, the first pitch P1 is defined as the distance between the first edge of a single conductive bonding pad in the first plurality of conductive bonding pads 116 and the corresponding second edge of an adjacent conductive bonding pad in the first plurality of conductive bonding pads 116 (e.g., the spacing between the left edges of the conductive bonding pads or the right edges of the conductive bonding pads). Therefore, the first plurality of conductive bonding pads 116 are arranged in the first region 106 at a first density. The conductive bonding pads in the second plurality of conductive bonding pads 118 are arranged at a second pitch P2. In some embodiments, the first pitch P1 is less than the second pitch P2. In various embodiments, the second plurality of conductive bond pads 118 are arranged in the second region 108 at a second density that is less than the first density.

[0038] In various embodiments, a first plurality of conductive bonding pads 116 having a first pitch P1 greater than a second pitch P2 facilitates making the first density relatively large (e.g., greater than the second density). The relatively large first density in the first region 106 directly below the plurality of pixels 130 reduces the complexity of routing the electrical signal of the accumulated charge at the photodetector 128 to the second IC chip 104. As a result, the design complexity is reduced, and the number and / or size of the conductive structures (e.g., wires and / or conductive vias) in the first interconnect structure 122 can be reduced, thereby reducing manufacturing costs. In addition, reducing the number and / or size of the conductive structures in the first interconnect structure 122 reduces the resistance-capacitance (RC) delay in the first IC chip 102. Therefore, the performance of the pixels 130 and the stacked IC device is improved.

[0039] In addition, the second pitch P2 is greater than the first pitch P1 to promote making the second density relatively small (e.g., less than the first density). The relatively small second density alleviates the problems caused by the limitations of the processing tools. For example, the limitations of the processing tools (e.g., the limitations of the CMP tools) may result in less material being removed at the peripheral area of ​​the first IC chip 102. The relatively small second density promotes more uniform removal of the material across the first bonding structure 110 (e.g., the conductive material of the second plurality of conductive bonding pads 118), so that the lower surface (e.g., the bonding surface) of the first bonding structure 100 is substantially flat, and the TTV of the first IC chip 102 is reduced. As a result, the non-bonding area across the bonding interface 105 due to gaps and / or bubbles can be prevented or mitigated. This promotes stronger bonding and better electrical coupling between the first IC chip 102 and the second IC chip 104, thereby improving the yield and overall performance of the stacked IC device.

[0040] In various embodiments, the first bonding structure 110 and the second bonding structure 112 include a single layer or a single level of conductive elements, respectively. For example, the first bonding structure 110 includes a single layer of conductive elements, which includes a first plurality of conductive bonding pads 116 and a second plurality of conductive bonding pads 118 arranged along the same plane. In some embodiments, the bottom surface of the first plurality of conductive bonding pads 116 is coplanar with the bottom surface of the second plurality of conductive bonding pads 118, and the top surface of the first plurality of conductive bonding pads 116 is coplanar with the top surface of the second plurality of conductive bonding pads 118. As a result, the number of conductive elements in the first bonding structure 110 and the second bonding structure 112 can be reduced, thereby reducing manufacturing costs and / or RC delays in stacked IC devices.

[0041] In various embodiments, the second bonding structure 112 has a layout and / or configuration similar or identical to that shown and / or described above with respect to the first bonding structure 110. For example, the third plurality of conductive bonding pads 117 are arranged in the first region 106 at a first pitch P1, and the fourth plurality of conductive bonding pads 119 are arranged in the second region 108 at a second pitch P2. As a result, the complexity of the circuit routing in the second IC chip 104 is reduced, and the TTV of the second IC chip 104 is reduced. Therefore, the second bonding structure 112 having conductive bonding pads of the first pitch P1 and the second pitch P2 reduces design complexity and improves the overall performance of the stacked IC device.

[0042] like Figure 1B As shown, the first plurality of conductive bond pads 116 are arranged in an array including a plurality of rows and a plurality of columns. Figure 1B A first plurality of conductive bonding pads 116 arranged in an array having 4 rows and 4 columns is shown, but this is only a non-limiting example, and the array may include any number of rows and columns. For example, the first plurality of conductive bonding pads 116 may include 1,000,000 or more conductive bonding pads arranged in an array. The second region 108 is adjacent to at least one side of the first region 106. In various embodiments, the second region 108 wraps around the periphery of the first region 106 and is arranged along each side of the first region 106. Therefore, the second region 108 may be annular. In various embodiments, the second plurality of conductive bonding pads 118 are arranged in at least one row or column along the corresponding sides of the first region 106. In a further embodiment, the second plurality of conductive bonding pads 118 are arranged in an array along at least one side of the first region 106.

[0043] In various embodiments, the first plurality of conductive bonding pads 116 are arranged in the first region 106 at a uniform pitch including a first pitch P1. For example, the spacing is substantially the same as the spacing between corresponding outer edges of adjacent conductive bonding pads in the first plurality of conductive bonding pads 116. As used herein, the term "uniform pitch" refers to a substantially uniform pitch across the first plurality of conductive bonding pads 116 within a tolerance due to misalignment errors. In some embodiments, the uniform pitch can have a value that varies by approximately 5% between different pairs of adjacent conductive bonding pads due to misalignment errors (for example, the pitch P1a of the first pair of conductive bonding pads can be between 0.95 times and 1.05 times the pitch P1b of the second pair of conductive bonding pads). The first plurality of conductive bonding pads 116 having a uniform pitch facilitates having the first plurality of conductive bonding pads 116 have a relatively high first density. The relatively high first density reduces the routing of electrical signals to pixels ( Figure 1A 130) and / or the complexity of routing electrical signals from the pixel, thereby reducing the first interconnect structure ( Figure 1AThe design complexity of 122).

[0044] In some embodiments, the second plurality of conductive bonding pads 118 are arranged in the second region 108 at a non-uniform pitch. For example, the spacing between the respective outer edges of adjacent conductive bonding pads in the second plurality of conductive bonding pads 118 may vary across the second region 108. In various embodiments, the minimum pitch in the non-uniform pitches of the second plurality of conductive bonding pads 118 is a second pitch P2 greater than the first pitch P1. In some embodiments, the pitch 138 between adjacent rows in the second plurality of conductive bonding pads 118 is greater than the second pitch P2. In yet further embodiments, the second plurality of conductive bonding pads 118 are arranged in the second region 108 at a uniform pitch including the second pitch P2 (not shown). The second plurality of conductive bonding pads 118 having at least the second pitch P2 facilitates the second plurality of conductive bonding pads 118 to have a second density less than the first density. For example, the number of conductive bonding pads within a first area of ​​the first region 106 is greater than the second number of conductive bonding pads within a second area of ​​the second region 108 (where the first area is equal to the second area). In some embodiments, the number of conductive bonding pads per square millimeter in the first region 106 is greater than the number of conductive bonding pads per square millimeter in the second region 108 .

[0045] The second plurality of conductive bonding pads 118 having a second density mitigates the first IC chip ( Figure 1A 102) and the second IC chip ( Figure 1A 104) between the formation of non-bonded areas, and increase along the bonding interface ( Figure 1A 105), thereby improving the bonding strength of the device yield. For example, limitations of a processing tool (e.g., a CMP tool) may result in uneven removal of material from an outer region of the IC chip. In various embodiments, the problem of uneven material removal may be exacerbated for chips disposed at or around a peripheral region of the semiconductor wafer. The lower second density of the second plurality of conductive bonding pads 118 in the second region 108 mitigates the problems associated with uneven removal of material at the outer region of the IC chip, so that the first IC chip ( Figure 1A Thus, the TTV along the bonding interface ( Figure 1A 105), thereby improving the device yield.

[0046] In some embodiments, each of the first width 140 of each conductive bonding pad in the first plurality of conductive bonding pads 116 and the second width 142 of each conductive bonding pad in the second plurality of conductive bonding pads 118 is less than about 2 micrometers (μm), in a range of about 0.25 to 2 μm, or some other suitable value. In various embodiments, the first width 140 is equal to the second width 142. In further embodiments, the first width 140 is different from the second width 142. In still further embodiments, the area of ​​each conductive bonding pad in the first plurality of conductive bonding pads 116 is equal to or approximately equal to (e.g., equal to within a tolerance of about 5% or less) the area of ​​each conductive bonding pad in the second plurality of conductive bonding pads 118. In some embodiments, the first pitch P1 is less than about 4 μm, in a range of about 0.5 to 4 μm, or some other suitable value. In further embodiments, the second pitch P2 is less than about 10 μm, in a range of about 0.75 to 10 μm, greater than about 4 μm, or some other suitable value.

[0047] Figure 2A and Figure 2B Shows Figure 1A and Figure 1B Various views of some other embodiments of stacked IC devices. Figure 2A A top view 200a of some embodiments of stacked IC devices is shown. Figure 2B Shown along Figure 2A A cross-sectional view 200 b of some embodiments of a stacked IC device is shown taken along line AA′.

[0048] like Figure 2A As shown, in some embodiments, the second region 108 has a first region 106 to the first IC chip ( Figure 2B 102). For example, the second region 108 has a first sub-region 210 with a first length L1, a second sub-region 212 with a second length L2, a third sub-region 214 with a third length L3, and a fourth sub-region 216 with a fourth length L4. The first sub-region 210 is disposed along a first side of the first region 106, the second sub-region 212 is disposed along a second side of the first region 106, the third sub-region 214 is disposed along a third side of the first region 106, and the fourth sub-region 216 is disposed along a fourth side of the first region 106. In some embodiments, the first length L1 is less than the second length L2 and the third length L3, and the fourth length L4 is greater than the second length L2 and the third length L3. In various embodiments, the first sub-region 210 includes a single row of the second plurality of conductive bonding pads 118. In some embodiments, the center of the first region 106 may be located from a plurality of pixels ( Figure 2B130) is laterally offset, wherein the center of the first region 106 is positioned to mitigate the effects of the first interconnect structure ( Figure 2B The complexity of routing electrical signals in 122).

[0049] like Figure 2B As shown, the first bonding structure 110 includes a first bonding dielectric 202, and the first interconnect structure 122 includes a first interconnect dielectric 204. The first plurality of conductive bonding pads 116 and the second plurality of conductive bonding pads 118 are disposed in the first bonding dielectric 202. The first plurality of conductive wires 120 and the first plurality of conductive vias 123 are disposed in the first interconnect dielectric 204. In addition, the second bonding structure 112 includes a second bonding dielectric 206, and the second interconnect structure 126 includes a second interconnect dielectric 208. The third plurality of conductive bonding pads 117 and the fourth plurality of conductive bonding pads 119 are disposed in the second bonding dielectric 206. In addition, the second plurality of conductive wires 121 and the second plurality of conductive vias 125 are disposed in the second interconnect dielectric 208.

[0050] Figure 3A and Figure 3B Shows Figure 2A and Figure 2B Various views of some other embodiments of stacked IC devices. Figure 3A A top view 300a of some embodiments of stacked IC devices is shown. Figure 3B Shown along Figure 3A A cross-sectional view 300b of some embodiments of a stacked IC device is shown taken along line AA′.

[0051] In some embodiments, the second plurality of conductive bonding pads 118 are configured as pseudo conductive bonding pads and are electrically floating. In various embodiments, the entire top surface of each conductive bonding pad in the second plurality of conductive bonding pads 118 directly contacts the first interconnect dielectric 204. Since the second plurality of conductive bonding pads 118 are configured as pseudo conductive bonding pads, the bonding strength along the bonding interface 105 is increased, and the number of conductive structures in the first interconnect structure 122 can be reduced. As a result, the manufacturing cost is reduced and the yield of the stacked IC device is improved. In various embodiments, the fourth plurality of conductive bonding pads 119 are configured as pseudo conductive bonding pads and are electrically floating. In various embodiments, the entire bottom surface of each conductive bonding pad in the fourth plurality of conductive bonding pads 119 directly contacts the second interconnect dielectric 208.

[0052] Figure 4A and Figure 4B Various views of some embodiments of stacked IC devices including a bonding structure having conductive bonding pads with different pitches disposed across a first region, a second region, and a third region are shown. Figure 4A A top view 400a of some embodiments of a stacked IC device is shown. Figure 4B Shown along Figure 4A A cross-sectional view 400b of some embodiments of a stacked IC device is shown taken along line AA′.

[0053] In some embodiments, the first bonding structure 110 further includes a first plurality of external conductive bonding pads 404 arranged in the third region 402 at a third pitch P3. The third pitch P3 is greater than the first pitch P1 and greater than or equal to the second pitch P2. The third region 402 is disposed along at least one side of the second region 108. In some embodiments, the third region 402 extends around the periphery of the second region 108. In further embodiments, the first plurality of external conductive bonding pads 404 are arranged in the third region at a non-uniform pitch, wherein the minimum pitch among the non-uniform pitches of the first plurality of external conductive bonding pads 404 is the third pitch P3. In some embodiments, the pitch between at least one pair of rows in the first plurality of external conductive bonding pads 404 is greater than the third pitch P3. In addition, the first plurality of external conductive bonding pads 404 are arranged along the same plane as the first plurality of conductive bonding pads 116 and the second plurality of conductive bonding pads 118. For example, the bottom surface of the first plurality of external conductive bonding pads 404 is coplanar with the bottom surface of the first plurality of conductive bonding pads 116 and the second plurality of conductive bonding pads 118.

[0054] In various embodiments, the first region 106 and the second region 108 are directly below the plurality of pixels 130, and the third region 402 is disposed at an external region outside the plurality of pixels 130 of the first IC chip 102. In some embodiments, the first plurality of external conductive bonding pads 404 having at least a third pitch P3 greater than the first pitch P1 and the second pitch P2 promote the first plurality of external conductive bonding pads 404 to have a third density less than the first density and less than the second density. For example, the number of conductive bonding pads per square millimeter in the third region 402 is less than the number of conductive bonding pads per square millimeter in the first region 106 and the second region 108. Therefore, the density of the conductive bonding pads in the first bonding structure 110 is discretely reduced by at least two times from the center of the first region 106 to the outer edge of the first bonding structure 100. The first plurality of external conductive bonding pads 404 having a third density less than the first density and the second density further mitigates the formation of a non-bonding region between the first IC chip 102 and the second IC chip 104. As a result, the bonding strength and device yield along the bonding interface 105 are further improved.

[0055] In some embodiments, the first plurality of external conductive bonding pads 404 are configured as pseudo conductive bonding pads and are electrically floating. In various embodiments, the entire top surface of each conductive bonding pad in the first plurality of external conductive bonding pads 404 directly contacts the first interconnect dielectric 204. In addition, the second bonding structure 112 also includes a second plurality of external conductive bonding pads 406 disposed in the third region 402 and disposed around the fourth plurality of conductive bonding pads 119. The second plurality of external conductive bonding pads 406 can be configured as pseudo conductive bonding pads and are electrically floating.

[0056] In some embodiments, the third width 405 of each conductive bonding pad in the first plurality of external conductive bonding pads 404 is about 2 μm, in a range of about 0.25 to 2 μm, or some other suitable value. In various embodiments, the third width 405 is equal to the second width 142 and the first width 140. In further embodiments, the third width 405 is different from the first width 140 and the second width 142. In still further embodiments, the area of ​​each conductive bonding pad in the first plurality of external conductive bonding pads 404 is equal to or approximately equal to (e.g., equal to within a tolerance of about 5% or less) the area of ​​each conductive bonding pad in the first plurality of conductive bonding pads 116 and the second plurality of conductive bonding pads 118. In some embodiments, the third pitch P3 is less than about 15 μm, in a range of about 0.75 to 15 μm, less than about 10 μm, in a range of about 0.75 to 10 μm, or some other suitable value. In some embodiments, each of the conductive bonding pads 116, 118, 404 of the first bonding structure 110 may include, for example, the same material, which may be copper, tungsten, titanium, tantalum, some other conductive material, or any combination of the above materials. In further embodiments, the conductive bonding pads 116, 118, 404 of the first bonding structure 110 may be referred to as conductive bonding contacts, conductive bonding elements, etc.

[0057] In various embodiments, a first ratio (e.g., P1:P2) between the first pitch P1 and the second pitch P2 is in the range of 0.15:5. In further embodiments, a second ratio (e.g., P2:P3) between the second pitch P2 and the third pitch P3 is in the range of 0.10:4.5. In some embodiments, the first ratio is greater than the second ratio. In some embodiments, the conductive bonding pads 116, 118, 404 of the first bonding structure 110 have a first ratio and a second ratio in the above range, which mitigates the formation of a non-bonded area between the first IC chip 102 and the second IC chip 104 and reduces manufacturing complexity.

[0058] FIG. 5A to FIG. 5H Shows Figure 4A and Figure 4BVarious cross-sectional views 500a-500h of some other embodiments of stacked IC devices. FIG. 5A to FIG. 5H Shown along Figure 4A Cross-sectional views 500a - 500h of some embodiments of stacked IC devices taken along line AA′.

[0059] like Figure 5A As shown in the cross-sectional view 500a of FIG. 5 , in some embodiments, the second plurality of conductive bonding pads 118 and the first plurality of outer conductive bonding pads 404 are both configured as dummy conductive bonding pads and are electrically floating.

[0060] like Figure 5B As shown in cross-sectional view 500 b , in some embodiments, lateral surfaces (eg, top surfaces) of the second plurality of conductive bond pads 118 and the first plurality of outer conductive bond pads 404 extend above a bottom surface of the first interconnect dielectric 204 .

[0061] like Figure 5C As shown in the cross-sectional view 500c of FIG. 504, the second plurality of conductive bonding pads 118 are electrically floating. For example, the second plurality of conductive bonding pads 118 are electrically isolated from the conductive structure of the first interconnect structure 122. In a further embodiment, the third region 402 is free of any conductive bonding elements, so that the bottom surface of the first bonding dielectric 202 extends continuously along the top surface of the second bonding dielectric 206 and contacts the top surface of the second bonding dielectric 206 along the entire area of ​​the third region 404. As a result, the manufacturing cost of the stacked IC device is reduced. In some embodiments, the wires 120 and / or the conductive vias 123 of the first interconnect structure 122 are disposed in the third region 402.

[0062] like Figure 5D As shown in the cross-sectional view 500d of FIG. 500, the first plurality of external conductive bonding pads ( Figure 4A and Figure 4B In various embodiments, the third region 402 does not have any conductive bonding elements, so that the bottom surface of the first bonding dielectric 202 extends continuously along the top surface of the second bonding dielectric 206 and contacts the top surface of the second bonding dielectric 206 along the entire area of ​​the third region 402. As a result, the manufacturing cost of the stacked IC device is reduced.

[0063] like Figure 5EAs shown in the cross-sectional view 500e of FIG. 1 , in some embodiments, each of the first plurality of wires and vias 120, 123 and the second plurality of wires and vias 121, 125 includes a first liner layer 502 surrounding a first conductor structure 504. The first liner layer 502 can be or include, for example, one or more of a diffusion barrier layer, an adhesion layer, a seed layer, etc. The first liner layer 502 can be or include, for example, titanium nitride, tantalum nitride, some other conductive material, or any combination of the above materials. The first conductor structure 504 can be or include, for example, aluminum, copper, tungsten, ruthenium, some other conductive material, or any combination of the above materials. In further embodiments, the conductive bonding pads 116, 117, 118, 119, 404, 406 of the first bonding structure 110 and the second bonding structure 112 respectively include a second liner layer 506 and a second conductor structure 508. The second liner layer 506 can be or include, for example, one or more of a diffusion barrier layer, an adhesion layer, a seed layer, etc. The second liner layer 506 may be or include, for example, titanium nitride, tantalum nitride, some other conductive material, or any combination thereof. The second conductor structure 508 may be or include, for example, aluminum, copper, tungsten, ruthenium, some other conductive material, or any combination thereof.

[0064] like Fig. 5F As shown in the cross-sectional view 500f of FIG. 1 , in some embodiments, the centers of the conductive bonding pads 116, 118, 404 of the first bonding structure 110 are laterally offset from the centers of the corresponding conductive bonding pads 117, 119, 406 of the second bonding structure 112 by a lateral distance 510. The lateral distance 510 is non-zero. During the bonding process performed on the first IC chip 102 and the second IC chip 104, the centers of the conductive bonding pads 116, 118, 404 of the first bonding structure 110 can be laterally offset from the centers of the conductive bonding pads 117, 119, 406 of the second bonding structure 112.

[0065] like Figure 5G As shown in the cross-sectional view 500g of FIG. 500b, in some embodiments, the conductive bonding pads 116, 117, 118, 119, 404, 406 of the first bonding structure 110 and the second bonding structure 112 respectively have a trapezoidal shape. In some embodiments, the width of the conductive bonding pads 116, 118, 404 of the first bonding structure 110 continuously decreases from the bottom surface of the first bonding structure 100 in a first direction toward the first substrate 101. In further embodiments, the width of the conductive bonding pads 117, 119, 406 of the second bonding structure 112 continuously decreases from the top surface of the second bonding structure 112 in a second direction toward the second substrate 103.

[0066] like Figure 5HAs shown in the cross-sectional view 500h of FIG. 500h, in some embodiments, the conductive bonding pads 116, 117, 118, 119, 404, 406 of the first bonding structure 110 and the second bonding structure 112 respectively have a trapezoidal shape. In some embodiments, the width of the conductive bonding pads 116, 118, 404 of the first bonding structure 110 continuously increases from the bottom surface of the first bonding structure 100 in a first direction toward the first substrate 101. In further embodiments, the width of the conductive bonding pads 117, 119, 406 of the second bonding structure 112 continuously increases from the top surface of the second bonding structure 112 in a second direction toward the second substrate 103.

[0067] will understand, Figure 1A to Figure 1B , FIG. 2A to FIG. 2B , FIG. 3A to FIG. 3B , FIG. 4A to FIG. 4B and FIG. 5A to FIG. 5H Each of the second bonding structures 112 of the second IC chip 104 in the figure can be configured as and / or have the same layout as the first bonding structure 110 of the first IC chip 102 in the corresponding figure. Therefore, the first bonding structure 110 and the second bonding structure 112 can have a symmetrical layout, which promotes a strong bond between the first IC chip 102 and the second IC chip 104, thereby reducing design complexity and improving device yield.

[0068] Figure 6 A cross-sectional view 600 of some embodiments of a stacked IC device including a bonding structure having first conductive bonding pads arranged at a first pitch and second conductive bonding pads arranged at a second pitch different from the first pitch is shown.

[0069] The stacked IC device includes a first IC chip 102 stacked on a second IC chip 104. The first IC chip 102 includes a first substrate 101, a first interconnect structure 122 located on the first substrate 101, and a first bonding structure 110 located on the first interconnect structure 22. The second IC chip 104 includes a second substrate 103, a second interconnect structure 126 located on the second substrate 103, and a second bonding structure 112 located on the second interconnect structure 126. Each of the first substrate 101 and the second substrate 103 can be or include, for example, silicon, a silicon wafer, single crystal silicon, a CMOS body, silicon germanium, one or more epitaxial layers (e.g., an epitaxial silicon layer), a silicon on insulator (SOI) substrate, or some other type of semiconductor substrate.

[0070] In some embodiments, the second IC chip 104 is configured as an application specific integrated circuit (ASIC) or another suitable device. A plurality of semiconductor devices 132 are arranged on the front side surface 103f of the second substrate 103. For example, a plurality of semiconductor devices 132 can be configured as logic devices, transistors or some other suitable devices. In various embodiments, each of the plurality of semiconductor devices 132 includes a gate electrode on a gate dielectric, a plurality of source / drain regions arranged on opposite sides of the gate electrode, and a well region in the second substrate 103. A shallow trench isolation (STI) structure 602 is arranged in the second substrate 103 and is configured to electrically isolate the semiconductor devices 132 from each other. The second interconnect structure 126 is configured to electrically couple the semiconductor devices 132 to each other and / or electrically couple to the device of the second IC chip 104.

[0071] The first interconnect structure 122 includes a first plurality of conductive lines 120 and a first plurality of conductive vias 123 disposed in a first interconnect dielectric 204. The second interconnect structure 126 includes a second plurality of conductive lines 121 and a second plurality of conductive vias 125 disposed in a second interconnect dielectric 208. Each of the first interconnect dielectric 204 and the second interconnect dielectric 208 may include a plurality of dielectric layers vertically stacked on each other, and the dielectric layers may be, for example, or include silicon dioxide, a low-k dielectric material, an extremely low-k dielectric material, silicon nitride, silicon carbide, etc. The conductive lines 120, 121 and the conductive vias 123, 125 may be, for example, or include aluminum, titanium nitride, tantalum nitride, tungsten, ruthenium, some other conductive material, or any combination of the foregoing materials.

[0072] In some embodiments, the first IC chip 102 is configured as a CMOS imaging chip including a plurality of pixels 130. In various embodiments, the first IC chip 102 is configured as a system on chip (SoC). In further embodiments, the first IC chip 102 includes one or more of a central processing unit (CPU), one or more memory devices, a graphics processing unit (GPU), a digital signal processor (DSP), or some other suitable electronic devices. The first IC chip 102 includes a plurality of photodetectors 128 disposed in a first substrate 101. A plurality of pixel devices 610 are disposed on the first substrate. For example, a plurality of pixel devices 610 may be configured as and / or include transfer transistors, reset transistors, select transistors, source follower transistors, and the like. Each of the pixels 130 includes one or more photodetectors 128 and one or more pixel devices 610.

[0073] The photodetector 128 is configured to absorb incident light (e.g., photons) and generate a corresponding electrical signal corresponding to the incident light. For example, the photodetector 128 can generate electron-hole pairs from the incident light. At least a subset of the pixel devices 610 (e.g., pixel devices configured as transfer transistors) are configured to control a current between the photodetector 128 and a corresponding floating diffusion node (not shown) in the first substrate 101. The pixel device 610 is configured to facilitate reading out an electrical signal corresponding to the incident light received at the photodetector 128 from the plurality of pixels 130.

[0074] A shallow trench isolation (STI) structure 612 is disposed in the first substrate 101. An isolation structure 614 extends into the backside surface 101b of the first substrate 101. The isolation structure 614 is disposed between adjacent photodetectors in the plurality of photodetectors 128. In various embodiments, the isolation structure 614 extends laterally continuously around each photodetector in the plurality of photodetectors 128. The isolation structure 614 increases the electrical isolation between the pixels 130 and increases the optical isolation between the photodetectors 128. The isolation structure 614 may, for example, be or include one or more layers including a conductive material (e.g., aluminum, copper, tungsten, etc.), a dielectric material (e.g., silicon dioxide, aluminum oxide, silicon nitride, etc.), or some other suitable material. An upper dielectric layer 616 is disposed on the backside surface 101b of the first substrate 101. The upper dielectric layer 616 may, for example, be or include silicon dioxide, silicon nitride, silicon carbide, etc. The grid structure 618 is located on the backside surface 101b of the first substrate 101 and includes a plurality of opposing sidewalls defining a plurality of openings above the photodetectors 128. The grid structure 618 is configured to reduce crosstalk between adjacent photodetectors 128, thereby increasing optical isolation.

[0075] An upper dielectric structure 620 is located above the grid structure 618 and fills the opening defined by the opposite sidewalls of the grid structure 618. For example, the upper dielectric structure 620 can be or include an oxide (e.g., silicon dioxide) or some other suitable dielectric material. A plurality of filters 622 are disposed above the plurality of photodetectors 128. Each of the plurality of filters 622 includes a material configured to pass a first wavelength range while blocking a second wavelength range different from the first wavelength range. A plurality of microlenses 624 are located above the filters 622 and are configured to direct incident light toward the photodetectors 128.

[0076] In various embodiments, the first bonding structure 110 includes a first plurality of conductive bonding pads 116 arranged in the first region 106 at a first pitch P1, a second plurality of conductive bonding pads 118 arranged in the second region 108 at a second pitch P2 greater than the first pitch P1, and a first bonding dielectric 202. The first plurality of conductive bonding pads 116 and the second plurality of conductive bonding pads 118 are disposed in the first bonding dielectric 202. The first bonding dielectric 202 includes a first dielectric layer 606a, a second dielectric layer 606b, and a third dielectric layer 606c. The second bonding structure 112 includes a third plurality of conductive bonding pads 117 arranged in the first region 106 at a first pitch P1 and a fourth plurality of conductive bonding pads 119 arranged in the second region 108 at a second pitch P2. The first bonding structure 110 and the second bonding structure 112 intersect each other at a bonding interface 105 including a conductor-to-conductor bond and a dielectric-to-dielectric bond. In various embodiments, the first bonding structure 110 and the second bonding structure 112 including conductive bonding pads with different pitches reduce the complexity of routing electrical signals between the first IC chip 102 and the second IC chip 104. This partially facilitates the scaling feature of the pixel 130, thereby increasing the device density of the stacked IC device and the resolution and / or quality of the image generated from the stacked IC device. In addition, the second pitch P2 is greater than the first pitch P1, which reduces the non-bonding area between the first IC chip 102 and the second IC chip 104, thereby improving the overall performance and yield of the stacked IC device.

[0077] In some embodiments, the conductive bonding pads 116, 117, 118, 119 of the first bonding structure 110 and the second bonding structure 112 may, for example, respectively include copper, tungsten, titanium, tantalum, some other conductive materials, or any combination of the above materials. In a further embodiment, each of the first bonding structure 110 and the second bonding structure 112 includes a single-layer conductive bonding element, thereby reducing the number of conductive structures in the first IC chip 102 and the second IC chip 104. Therefore, the manufacturing cost is reduced. The first dielectric layer 606a may, for example, be or include silicon nitride, silicon carbide, or some other suitable dielectric material. The second dielectric layer 606b may, for example, be or include oxide (e.g., silicon dioxide) or some other suitable dielectric material. The third dielectric layer 606c may, for example, be or include silicon oxynitride, silicon oxycarbide, or some other suitable dielectric material.

[0078] Figure 7 Shows Figure 6 700 of some other embodiments of stacked IC devices, wherein the first bonding structure 110 further includes a first plurality of external conductive bonding pads 404 disposed in a third region 402 adjacent to the second region 108. In some embodiments, the first bonding structure 110 and the second bonding structure 112 may be as follows: Figure 4A , Figure 4B and FIG. 5A to FIG. 5D Any one of the configurations shown and / or described.

[0079] In some embodiments, the first IC chip 102 further includes a plurality of upper bonding elements 702, which extend through the first substrate 101 to one or more conductive structures in the first interconnect structure 122. The upper bonding elements 702 are configured to electrically couple the stacked IC device to another electronic device (not shown). The first plurality of external conductive bonding pads 404 are disposed outside the plurality of photodetectors 128. In various embodiments, the plurality of upper bonding elements 702 are spaced apart in the third region 402 and are directly located above the plurality of external conductive bonding pads 404.

[0080] Figure 8 Shows Figure 4A 800 of some other embodiments of the first bonding structure. The first bonding structure 110 includes a first plurality of conductive bonding pads 116 arranged in the first region 106 at a first pitch P1, a second plurality of conductive bonding pads 118 arranged in the second region 108 at a second pitch P2, and a first plurality of outer conductive bonding pads 404 arranged in the third region 402 at a third pitch P3.

[0081] In some embodiments, the first plurality of conductive bonding pads 116 are arranged in the first region 106 at a first density, the second plurality of conductive bonding pads 118 are arranged in the second region 108 at a second density less than the first density, and the first plurality of outer conductive bonding pads 404 are arranged in the third region 402 at a third density less than the second density. In various embodiments, the area of ​​the first region 106 is greater than the area of ​​the second region 108, and the area of ​​the third region 402 is less than the area of ​​the second region 104.

[0082] 9A to 9C Shows Figure 8 Various top views 900a-900c of some embodiments of conductive bond pads in first, second, and third regions of the device.

[0083] like Fig. 9A As shown in the top view 900a of FIG. 1 , each of the conductive bond pads in the first plurality of conductive bond pads 116 , the second plurality of conductive bond pads 118 , and the first plurality of outer conductive bond pads 404 has a circular shape when viewed from above.

[0084] like Fig. 9BAs shown in the top view 900b, each of the conductive bond pads in the first plurality of conductive bond pads 116, the second plurality of conductive bond pads 118, and the first plurality of outer conductive bond pads 404 has a triangular shape when viewed from above.

[0085] like Fig. 9C As shown in top view 900c, each of the conductive bonding pads in the first plurality of conductive bonding pads 116, the second plurality of conductive bonding pads 118, and the first plurality of outer conductive bonding pads 404 has a polygonal shape (eg, a hexagon, a pentagon, etc.) when viewed from above.

[0086] Fig. 10A A cross-sectional view 1000a of some embodiments of a stacked IC device including a first IC chip, a second IC chip, and a third IC chip, each of which includes one or more bonding structures having conductive bonding pads with different pitches, is shown.

[0087] In some embodiments, the stacked IC device includes a first IC chip 102, a second IC chip 104, and a third IC chip 1002. The second IC chip 104 is disposed between the first IC chip 102 and the third IC chip 1002. In some embodiments, the second IC chip 104 also includes a third bonding structure 1006 disposed on the backside surface 103b of the second substrate 103. In various embodiments, a lower interconnect structure (not shown) is disposed between the backside surface 103b of the second substrate 103 and the third bonding structure 1006. In such an embodiment, the lower interconnect structure is configured to route electrical connections between the third bonding structure 1006 and the structure above (e.g., the second interconnect structure 126 and / or the first IC chip 102). In addition, a first plurality of through-substrate vias (TSVs) 1004 are disposed in the second substrate 103 and are configured to electrically couple the third IC chip 1002 to the second interconnect structure 126. In various embodiments, the first plurality of TSVs 1004 are laterally spaced apart within the third region 402.

[0088] The third IC chip 1002 includes a third substrate 1012, a third interconnect structure 1014 located on a front side surface 1012f of the third substrate 1012, and a fourth bonding structure 1008 located on the third interconnect structure 1014. The third interconnect structure 1014 includes a plurality of conductive lines (not labeled) and a plurality of conductive vias (not labeled). In addition, a second plurality of semiconductor devices 1016 (e.g., transistors) are disposed on the third substrate 1012. A second bonding interface 1010 is disposed between the third IC chip 1002 and the second IC chip 104. In various embodiments, the third bonding structure 1006 is configured as a first bonding structure 110, and the fourth bonding structure 1008 is configured as a second bonding structure 112 (e.g., as Figure 1A to Figure 1B , FIG. 2A to FIG. 2B , FIG. 3A to FIG. 3B , FIG. 4A to FIG. 4B and FIG. 5A to FIG. 5D ). Therefore, the third bonding structure 1006 and the fourth bonding structure 1008 respectively include conductive bonding pads arranged at different pitches across the regions 106, 108, 402, thereby alleviating or preventing non-bonding areas between the second IC chip 104 and the third IC chip 1002. As a result, the overall performance and yield of the stacked IC device are improved. In various embodiments, the external conductive bonding pads 404, 406 in the third bonding structure 1006 and the fourth bonding structure 1008 are electrically coupled to conductive components in the second IC chip 104 and / or the third IC chip 1002 (e.g., coupled to the conductive elements in the TSV 1004 and / or the third interconnect structure 1014).

[0089] Fig. 10B Shows Fig. 10A FIG. 1 is a cross-sectional view 1000 b of some other embodiments of a stacked IC device, wherein the stacked IC device further includes a fourth IC chip located below the third IC chip.

[0090] In some embodiments, the stacked IC device includes a first IC chip 102, a second IC chip 104, a third IC chip 1002, and a fourth IC chip 1018. In some embodiments, the third IC chip 1002 further includes a fifth bonding structure 1022 disposed on a backside surface 1012b of the third substrate 1012. In various embodiments, a second lower interconnect structure (not shown) is disposed between the backside surface 1012b and the fifth bonding structure 1022. A second plurality of TSVs 1020 are disposed in the third substrate 1012 and are configured to electrically couple the fourth IC chip 1018 to the third interconnect structure 1014.

[0091] The fourth IC chip 1018 includes a fourth substrate 1028, a fourth interconnect structure 1030 located on a front side surface 1028f of the fourth substrate 1028, and a sixth bonding structure 1024 located on the fourth interconnect structure 1030. The fourth interconnect structure 1030 includes a plurality of conductive lines (not labeled) and a plurality of conductive vias (not labeled). In addition, a third plurality of semiconductor devices 1032 (e.g., transistors) are disposed on the fourth substrate 1028. A third bonding interface 1026 is disposed between the third IC chip 1002 and the fourth IC chip 1018. In some embodiments, the fifth bonding structure 1022 is configured as the first bonding structure 110, and the sixth bonding structure 1024 is configured as the second bonding structure 112 (e.g., as Figure 1A to Figure 1B , FIG. 2A to FIG. 2B , FIG. 3A to FIG. 3B , FIG. 4A to FIG. 4B and FIG. 5A to FIG. 5D ). Therefore, the fifth bonding structure 1022 and the sixth bonding structure 1024 respectively include conductive bonding pads arranged at different pitches across the regions 106, 108, 402, thereby alleviating or preventing non-bonding areas between the second IC chip 104 and the third IC chip 1002, and improving the overall performance of the stacked IC device. In various embodiments, the external conductive bonding pads 404, 406 in the fifth bonding structure 1022 and the sixth bonding structure 1024 are electrically coupled to conductive components in the third IC chip 1002 and / or the fourth IC chip 1018 (e.g., coupled to the TSV 1004 and / or the conductive elements in the third interconnect structure 1014).

[0092] Figures 11 to 19 Various cross-sectional views 1100-1900 of some embodiments of methods of forming a stacked IC device include a bonding structure having conductive bonding pads with different pitches arranged across a plurality of regions. Figures 11 to 19 1100-1900, but it will be understood that Figures 11 to 19 The structure shown in is not limited to this method, but can be independently independent of this method. Figures 11 to 19 Described as a series of actions, but it will be understood that these actions are not limited, because the order of actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions shown and / or described can be omitted in whole or in part.

[0093] like Fig.11 As shown in the cross-sectional view 1100 of , a first IC structure 1102 is provided or otherwise formed. The first IC structure 1102 includes a first substrate 101, a plurality of photodetectors 128 disposed in the first substrate 101, a plurality of pixel devices 610 located on the first substrate 101, and a first interconnect structure 122 located on the front side surface 101f of the first substrate 101. A shallow trench isolation (STI) structure 612 is disposed in the first substrate 101. The first interconnect structure 122 includes a first plurality of conductive lines 120 and a first plurality of conductive vias 123 disposed in a first interconnect dielectric 204.

[0094] In some embodiments, a plurality of photodetectors 128 are formed in the first substrate 101 by an ion implantation process. A plurality of pixel devices 610 may be formed on the first substrate 101 by one or more deposition processes, one or more ion implantation processes, one or more patterning processes, one or more planarization processes, some other suitable manufacturing processes, or any combination of the above processes. The first plurality of conductive lines 120 and the first plurality of conductive vias 123 may be formed, for example, by one or more single damascene processes, dual damascene processes, or some other suitable manufacturing processes.

[0095] like Fig.12 As shown in the cross-sectional view 1200 of , the first bonding dielectric 202 is formed on the first interconnect structure 122. In some embodiments, the first bonding dielectric 202 includes a first dielectric layer 606a, a second dielectric layer 606b, and a third dielectric layer 606c. Each layer of the first bonding dielectric 202 can be formed by a separate deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or some other suitable growth or deposition process.

[0096] The first dielectric layer 606a can be configured as an etch stop layer and can be, for example, or include silicon nitride, silicon carbide, some other dielectric material, or any combination of the above materials. In some embodiments, the first dielectric layer 606a is formed to a thickness of about 1200 angstroms, a thickness in the range of about 1000 angstroms to 1400 angstroms, or a thickness of some other suitable value. The second dielectric layer 606b can be, for example, or include an oxide such as silicon dioxide or some other dielectric material, and can be formed to a thickness of about 4000 angstroms, a thickness in the range of about 3500 angstroms to 4500 angstroms, or a thickness of some other suitable value. The third dielectric layer 606c can be, for example, or include silicon oxynitride, silicon oxycarbide, some other dielectric material, or any combination of the above materials, and can be formed to a thickness of about 850 angstroms, a thickness in the range of about 700 angstroms to 1000 angstroms, or a thickness of some other suitable value.

[0097] like Fig.13 As shown in the cross-sectional view 1300 of , a patterning process is performed on the first bonding dielectric 202 to form a plurality of openings 1302 in the first bonding dielectric 202. In some embodiments, the patterning process includes: forming a masking layer (not shown) on the first bonding dielectric 202; performing an etching process (e.g., a dry etching process) on the first bonding dielectric 202 according to the masking layer; and performing a removal process to remove the masking layer.

[0098] like Fig.14As shown in the cross-sectional view 1400 of FIG. 1 , a first plurality of conductive bonding pads 116, a second plurality of conductive bonding pads 118, and a first plurality of external conductive bonding pads 404 are formed in the first bonding dielectric 202, thereby forming or defining the first bonding structure 110 on the first interconnect structure 122 and defining the first IC chip 102. In various embodiments, the process for forming the conductive bonding pads 116, 118, 404 of the first bonding structure 110 includes: forming a plurality of openings ( Fig.13 1302) is deposited (e.g., by CVD, PVD, sputtering, electroplating, chemical plating, etc.) with a conductive material (e.g., copper, aluminum, tungsten, etc.), and a planarization process (e.g., chemical mechanical planarization (CMP) process) is performed on the conductive material. In some embodiments, after the planarization process, the top surface of the first bonding dielectric 202 and the top surface of the conductive bonding pads 116, 118, 404 are coplanar and substantially flat, thereby alleviating the subsequent bonding process (e.g., Fig.17 In various embodiments, the process for forming the first bonding structure 110 includes: Figure 12 to Figure 14 The processing steps shown and / or described in .

[0099] In some embodiments, a first plurality of conductive bonding pads 116 are formed in the first region 106 at a first pitch P1, a second plurality of conductive bonding pads 118 are formed in the second region 108 at a second pitch P2, and a first plurality of external conductive bonding pads 404 are formed in the third region 402 at a third pitch P3. In some embodiments, the first pitch P1 is less than the second pitch P2, and the second pitch P2 is less than the third pitch P3. Therefore, the first density of the conductive bonding pads in the first region 106 is greater than the second density of the conductive bonding pads in the second region 108, and the second density is greater than the third density of the conductive bonding pads in the third region 402. The reduced density of the conductive bonding pads from the first region 106 to the third region 402 alleviates problems caused by limitations of processing tools used to perform a planarization process (e.g., reduced removal of material in the outer region of the first IC chip 102). As a result, the top surface of the first bonding structure 110 is substantially flat, and / or the TTV of the first IC chip 102 is relatively low, thereby mitigating the formation of non-bonding areas in subsequent bonding processes. It will be appreciated that although the first engagement structure 110 is shown as being formed as FIG. 4A to FIG. 4B However, the first bonding structure 100 may be formed to be configured as Figure 1A to Figure 1B , FIG. 2A to FIG. 2B , FIG. 3A to FIG. 3B , FIG. 5A to FIG. 5D , Figure 6 , Figure 8 and 9A to 9CThe first engagement structure 110 of any one of the .

[0100] In various embodiments, Fig.13 The patterning process may include performing a first patterning process to define a first subset of openings having a first pitch P1 in the first region 106. Fig.13 1302); performing a second patterning process to define a second subset of openings having a second pitch P2 in the second region 108 ( Fig.13 1302); and performing a third patterning process to define a third subset of openings having a third pitch P3 in the third region 402 ( Fig.13 1302). In some embodiments, each of the first patterning process, the second patterning process, and the third patterning process is performed according to a different masking layer (not shown). For example, the first patterning process is performed according to the first masking layer, the second patterning process is performed according to the second masking layer, and the like.

[0101] like Fig.15 As shown in the cross-sectional view 1500 of FIG. 1 , a second IC structure 1502 is provided or otherwise formed. The second IC structure 1502 includes a second substrate 103, a plurality of semiconductor devices 132 located on the second substrate 103, and a second interconnect structure 126 located on the front side surface 103f of the second substrate 103. The STI structure 602 is disposed in the second substrate 103. The second interconnect structure 126 includes a second plurality of conductive lines 121 and a second plurality of conductive vias 125 disposed in the second interconnect dielectric 208.

[0102] A plurality of semiconductor devices 132 may be formed on the second substrate 103 by one or more deposition processes, one or more ion implantation processes, one or more patterning processes, one or more planarization processes, some other suitable manufacturing processes, or any combination of the above processes. The second plurality of conductive lines 121 and the second plurality of conductive vias 125 may be formed, for example, by one or more single damascene processes, dual damascene processes, or some other suitable manufacturing processes.

[0103] like Fig.16 As shown in the cross-sectional view 1600 of FIG. 1 , a second bonding structure 112 is formed on the second interconnect structure 126, thereby defining a second IC chip 104. In various embodiments, the second bonding structure 112 includes a third plurality of conductive bonding pads 117 arranged at a first pitch P1, a fourth plurality of conductive bonding pads 119 arranged at a second pitch P2, and a second plurality of outer conductive bonding pads 406 arranged at a third pitch P3. In various embodiments, by Figure 12 to Figure 14 for forming a first bonding structure ( Fig.14 The processing step 110) forms a second bonding structure 112.

[0104] like Fig.17 As shown in the cross-sectional view 1700 of FIG. 17 , the first IC chip 102 is flipped over and bonded to the second IC chip 104, so that the bonding interface 105 is disposed between the first bonding structure 110 and the second bonding structure 112. In various embodiments, bonding the first IC chip 102 to the second IC chip 104 includes: aligning the first IC chip 102 with the second IC chip 104, contacting the first bonding structure 110 with the second bonding structure 112, and applying pressure to the first IC chip 102 and / or the second IC chip 104. In some embodiments, the temperature of the first bonding structure 110 and the second bonding structure 112 can be increased to form the bonding interface 105. Since the first bonding structure 110 and the second bonding structure 112 are formed to have a bonding interface 105, the bonding interface 105 can be formed between the first bonding structure 110 and the second bonding structure 112. Fig.14 The different conductive bonding pad densities shown and / or described above mitigate the formation of non-bonded areas between the first IC chip 102 and the second IC chip 104 , thereby improving the yield of stacked IC devices.

[0105] like Fig.18 As shown in the cross-sectional view 1800 of , a thinning process is performed on the first substrate 101, and an isolation structure 614 is formed in the first substrate 101. In some embodiments, the thinning process reduces the thickness of the first substrate 101 and includes performing a mechanical grinding process, a CMP process, etc. An upper dielectric layer 616 is formed on the backside surface 101b of the first substrate 101. A grid structure 618 is formed on the upper dielectric layer 616. The isolation structure 614 is formed to extend through the first substrate 101 and is disposed between adjacent photodetectors in the plurality of photodetectors 128. In addition, an upper dielectric structure 620 is formed above the grid structure 618.

[0106] like Fig.19 As shown in the cross-sectional view 1900 of , a plurality of upper bonding elements 702 are formed, and the upper bonding elements 702 extend through the first substrate 101 to the corresponding conductive structures in the first interconnect structure 122. In some embodiments, forming the plurality of upper bonding elements 702 includes: patterning the backside surface 101b of the first substrate 101 to form a bonding element opening extending to the first interconnect structure 122; depositing a conductive layer in the bonding element opening; and performing an etching process on the conductive layer. In addition, a plurality of filters 622 are formed above the photodetector 128, and a plurality of microlenses 624 are formed on the plurality of filters 622. For example, the plurality of filters 622 can be formed by depositing and patterning corresponding filter layers corresponding to the plurality of filters 622. For example, the microlenses 624 can be formed by depositing a microlens material above the filter 622 and patterning the microlens material to form a plurality of microlenses 624.

[0107] Fig. 20Some embodiments of a method 2000 for forming a stacked IC device are shown, the stacked IC device including a bonding structure having conductive bonding pads with different pitches arranged across multiple regions. Although method 2000 is shown and / or described as a series of actions or events, it will be understood that the method is not limited to the order or actions shown. Therefore, in some embodiments, the actions may be performed in an order different from that shown, and / or may be performed simultaneously. In addition, in some embodiments, the actions or events shown may be subdivided into multiple actions or events, which may be performed at separate times or simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown may be omitted, and other actions or events not shown may be included.

[0108] At act 2002, a plurality of photodetectors are formed within a first substrate of a first IC chip. Fig.11 A cross-sectional view 1100 corresponding to some embodiments of act 2002 is shown.

[0109] At act 2004, a first interconnect structure is formed on a first substrate. Fig.11 Cross-sectional view 1100 corresponding to some embodiments of act 2004 is shown.

[0110] At act 2006, a first bonding structure is formed on the first interconnect structure. The first bonding structure includes a first plurality of conductive bonding pads arranged at a first pitch in a first region and a second plurality of conductive bonding pads arranged at a second pitch greater than the first pitch in a second region, wherein the second region is disposed along at least one side of the first region. Figure 12 to Figure 14 Cross-sectional views 1200 - 1400 corresponding to some embodiments of act 2006 are shown.

[0111] At act 2008, a plurality of semiconductor devices are formed on a second substrate of a second IC chip. Fig.15 Cross-sectional view 1500 corresponding to some embodiments of act 2008 is shown.

[0112] At act 2010, a second interconnect structure is formed on a second substrate. Fig.15 A cross-sectional view 1500 corresponding to some embodiments of act 2010 is shown.

[0113] At act 2012, a second bonding structure is formed on the second interconnect structure. The second bonding structure includes a third plurality of conductive bonding pads arranged at a first pitch and a second plurality of conductive bonding pads arranged at a second pitch. Fig.16 Cross-sectional view 1600 corresponding to some embodiments of act 2012 is shown.

[0114] At act 2014 , the first IC chip is bonded to the second IC chip such that the first bonding structure intersects the second bonding structure at a bonding interface. Fig.17 A cross-sectional view 1700 corresponding to some embodiments of act 2014 is shown.

[0115] At act 2016, a grid structure and a plurality of filters are formed over the backside surface of the first substrate. Fig.18 and Fig.19 Cross-sectional views 1800 and 1900 corresponding to some embodiments of act 2016 are shown.

[0116] Therefore, in some embodiments, the present disclosure relates to a stacked IC device, which includes a first IC chip bonded to a second IC chip, wherein the first IC chip and the second IC chip include a bonding structure, which respectively includes a first plurality of conductive bonding pads arranged at a first pitch and a second plurality of conductive bonding pads arranged at a second pitch greater than the first pitch.

[0117] In some embodiments, the present application provides a device, comprising: an interconnect structure, located on a substrate; a bonding structure, located above the interconnect structure, wherein the bonding structure comprises: a first plurality of conductive bonding pads, arranged in a first region; and a second plurality of conductive bonding pads, arranged in a second region, wherein the second region is adjacent to at least one side of the first region, wherein the first pitch of the first plurality of conductive bonding pads is less than the second pitch of the second plurality of conductive bonding pads. In an embodiment, the first plurality of conductive bonding pads are arranged in an array including a plurality of columns and a plurality of rows. In an embodiment, the second plurality of conductive bonding pads are arranged in one or more rows and / or one or more columns, wherein the first density of the first plurality of conductive bonding pads is greater than the second density of the second plurality of conductive bonding pads. In an embodiment, the first plurality of conductive bonding pads contact the corresponding first wires in the interconnect structure. In an embodiment, the second plurality of conductive bonding pads contact the corresponding second wires in the interconnect structure. In an embodiment, the second plurality of conductive bonding pads are electrically floating, wherein the top surface of the second plurality of conductive bonding pads is offset from the conductive structure in the interconnect structure by a non-zero distance. In an embodiment, the device further comprises a plurality of photodetectors disposed in the substrate, wherein the first region is directly below the plurality of photodetectors. In an embodiment, the substrate further comprises a third region laterally offset from the plurality of photodetectors, wherein the second region is arranged between the first region and the third region, wherein the bonding structure further comprises a third plurality of conductive bonding pads in the third region, wherein a third pitch of the third plurality of conductive bonding pads is greater than or equal to the second pitch. In an embodiment, the substrate further comprises a third region laterally offset from the plurality of photodetectors, wherein the second region is arranged between the first region and the third region, wherein the bonding structure has no conductive bonding structure in the third region.

[0118] In a further embodiment, the present application provides a package, comprising: a first integrated circuit (IC) chip, comprising a first substrate, a first interconnect structure and a first bonding structure, wherein the first bonding structure comprises a first plurality of conductive bonding pads disposed in a first region of the first substrate and a second plurality of conductive bonding pads disposed in a second region of the first substrate, wherein the second region is disposed between the first region and an outer edge of the first IC chip; a second IC chip, comprising a second substrate, a second interconnect structure and a second bonding structure located below the first IC chip; and wherein an interface is disposed between the first bonding structure and the second bonding structure, wherein a first density of the first plurality of conductive bonding pads is greater than a second density of the second plurality of conductive bonding pads. In an embodiment, the first plurality of conductive bonding pads are arranged in the first region with a uniform pitch, and the second plurality of conductive bonding pads are arranged in the second region with a non-uniform pitch, wherein the minimum pitch of the non-uniform pitch is greater than the uniform pitch. In an embodiment, the first bonding structure comprises a single-level conductive element, the single-level conductive element comprising a first plurality of conductive bonding pads and a second plurality of conductive bonding pads, wherein the bottom surface of the first plurality of conductive bonding pads is substantially coplanar with the bottom surface of the second plurality of conductive bonding pads. In an embodiment, the first bonding structure includes a first plurality of pseudo conductive bonding pads disposed in a third region of the first substrate, wherein the second region is spaced between the third region and the first region, wherein the third density of the first plurality of pseudo conductive bonding pads is less than the second density. In an embodiment, the second bonding structure includes a third plurality of conductive bonding pads having a first density located in the first region, a fourth plurality of conductive bonding pads having a second density located in the second region, and a second plurality of pseudo conductive bonding pads having a third density located in the third region. In an embodiment, the first number of conductive bonding pads in the first region is greater than the second number of conductive bonding pads in the second region, and the third number of conductive bonding pads in the third region is less than the second number, wherein the first area of ​​the first region is greater than the second area of ​​the second region, and the third area of ​​the third region is less than the second area. In an embodiment, the second region is spaced between the first region and the third region of the first substrate, wherein the conductive bonding structure in the first bonding structure is completely laterally offset from the third region, and wherein the plurality of conductive wires in the first interconnect structure are laterally spaced apart in the third region.

[0119] In various embodiments, the present application provides a method for forming a device, comprising: forming a first integrated circuit (IC) chip, wherein the first IC chip includes a first substrate and a first interconnect structure located above the first substrate; forming a first bonding structure above the first interconnect structure, wherein the first bonding structure includes a first plurality of conductive bonding pads located in a first region and a second plurality of conductive bonding pads located in a second region adjacent to the first region, wherein the pitch of the second plurality of conductive bonding pads is greater than the pitch of the first plurality of conductive bonding pads; and bonding the first IC chip to a second IC chip, wherein the second IC chip includes a second substrate and a second bonding structure, wherein a bonding interface is provided between the first bonding structure and the second bonding structure. In an embodiment, forming the first bonding structure includes: forming a bonding dielectric on the first interconnect structure; patterning the bonding dielectric to form a plurality of openings in the bonding dielectric; depositing a conductive material in the plurality of openings; and performing a planarization process on the conductive material to define a first plurality of conductive bonding pads and a second plurality of conductive bonding pads, wherein the top surface of the first plurality of conductive bonding pads is coplanar with the top surface of the second plurality of conductive bonding pads. In an embodiment, the first plurality of conductive bonding pads and the second plurality of conductive bonding pads are formed simultaneously with each other. In an embodiment, the method also includes: forming a plurality of photodetectors within a first substrate, wherein the plurality of photodetectors are disposed within a device region of a first IC chip, wherein the first region and the second region are laterally spaced apart within the device region; wherein the first bonding structure includes a third plurality of conductive bonding pads in a third region outside the device region, wherein a pitch of the third plurality of conductive bonding pads is greater than a pitch of the second plurality of conductive bonding pads; and forming an upper bonding element, the upper bonding element extending through the first substrate to the first interconnect structure, wherein the upper bonding element is directly located above at least a portion of the third region.

[0120] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit device comprising: an interconnect structure located on the substrate; A bonding structure is located above the interconnection structure, wherein the bonding structure comprises: a first plurality of electrically conductive bond pads disposed in the first region; and A second plurality of conductive bonding pads are disposed in a second region, wherein the second region is adjacent to at least one side of the first region, wherein a first pitch of the first plurality of conductive bonding pads is smaller than a second pitch of the second plurality of conductive bonding pads.

2. The integrated circuit device according to claim 1, wherein: The first plurality of conductive bond pads are arranged in an array including a plurality of columns and a plurality of rows.

3. The integrated circuit device according to claim 2, wherein: The second plurality of conductive bond pads are arranged in one or more rows and / or one or more columns, wherein a first density of the first plurality of conductive bond pads is greater than a second density of the second plurality of conductive bond pads.

4. The integrated circuit device according to claim 1, wherein: The first plurality of electrically conductive bond pads contact corresponding first conductive lines in the interconnect structure.

5. The integrated circuit device according to claim 4, wherein: The second plurality of conductive bond pads contact corresponding second conductive lines in the interconnect structure.

6. The integrated circuit device according to claim 4, wherein: The second plurality of electrically conductive bond pads are electrically floating, wherein top surfaces of the second plurality of electrically conductive bond pads are offset a non-zero distance from electrically conductive structures in the interconnect structure.

7. The integrated circuit device according to claim 1, further comprising: A plurality of photodetectors are disposed in the substrate, wherein the first region is directly located below the plurality of photodetectors.

8. The integrated circuit device according to claim 7, wherein: The substrate also includes a third region laterally offset from the plurality of photodetectors, wherein the second region is arranged between the first region and the third region, wherein the bonding structure also includes a third plurality of conductive bonding pads located in the third region, wherein a third pitch of the third plurality of conductive bonding pads is greater than or equal to the second pitch.

9. A package comprising: a first integrated circuit (IC) chip comprising a first substrate, a first interconnect structure, and a first bonding structure, wherein the first bonding structure comprises a first plurality of conductive bonding pads disposed in a first region of the first substrate and a second plurality of conductive bonding pads disposed in a second region of the first substrate, wherein the second region is disposed between the first region and an outer edge of the first integrated circuit chip; a second integrated circuit chip comprising a second substrate, a second interconnect structure, and a second bonding structure located below the first integrated circuit chip; and An interface is provided between the first bonding structure and the second bonding structure, wherein a first density of the first plurality of conductive bonding pads is greater than a second density of the second plurality of conductive bonding pads.

10. A method for forming an integrated circuit device, comprising: forming a first integrated circuit (IC) chip, wherein the first integrated circuit chip includes a first substrate and a first interconnect structure located above the first substrate; forming a first bonding structure over the first interconnect structure, wherein the first bonding structure includes a first plurality of conductive bonding pads in a first region and a second plurality of conductive bonding pads in a second region adjacent to the first region, wherein a pitch of the second plurality of conductive bonding pads is greater than a pitch of the first plurality of conductive bonding pads; and The first integrated circuit chip is bonded to a second integrated circuit chip, wherein the second integrated circuit chip includes a second substrate and a second bonding structure, wherein a bonding interface is provided between the first bonding structure and the second bonding structure.

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