Display panel and method of manufacturing the same

Abstract

The invention relates to a display panel and a method of manufacturing the same. The display panel includes: a driving element layer including a pixel driving portion; a light emitting element disposed on the driving element layer, and including: a first electrode; an intermediate layer disposed on the first electrode; and a second electrode disposed on the intermediate layer. The display panel further includes: a pixel defining layer disposed on the driving element layer and including a light emitting opening exposing at least a portion of the first electrode and a groove surrounding the light emitting opening; and a connection electrode disposed on the pixel defining layer and electrically connected to the pixel driving portion and the second electrode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0162965 filed in the Korean Intellectual Property Office on November 22, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display panel having improved contact reliability and a method of manufacturing the display panel. Background Art

[0004] Multimedia electronic devices such as televisions, mobile phones, tablet computers, navigation devices, and gaming devices include a display panel that displays an image. The display panel includes a light-emitting element and a circuit that drives the light-emitting element. The light-emitting element included in the display panel emits light and generates an image in response to a voltage applied to the light-emitting element through the circuit. Research is being conducted on the connection between the light-emitting element and the circuit to improve the reliability of the display panel.

[0005] It will be understood that this background section is intended, in part, to provide a useful background for understanding the present technology. However, this background section may also include ideas, concepts or realizations that were not part of what was known or understood by those skilled in the relevant art prior to the corresponding effective filing date of the subject matter disclosed herein. Summary of the invention

[0006] The present disclosure provides a display panel with improved contact reliability.

[0007] The present disclosure provides a method of manufacturing a display panel having improved contact reliability.

[0008] An embodiment of the present disclosure provides a display panel, which may include: a driving element layer, including a pixel driving unit; a light-emitting element, which is arranged on the driving element layer, and the light-emitting element includes a first electrode, an intermediate layer arranged on the first electrode, and a second electrode arranged on the intermediate layer; a pixel defining layer, which is arranged on the driving element layer, and the pixel defining layer includes a light-emitting opening that exposes at least a portion of the first electrode and a groove surrounding the light-emitting opening; and a connecting electrode, which is arranged on the pixel defining layer and is electrically connected to the pixel driving unit and the second electrode.

[0009] The light emitting element may include a plurality of light emitting elements, the pixel driving unit may include a plurality of pixel driving units, and the connecting electrode may include a plurality of connecting electrodes. The plurality of connecting electrodes may electrically connect the plurality of light emitting elements to the plurality of pixel driving units, respectively. Gaps between adjacent connecting electrodes among the plurality of connecting electrodes may overlap with the groove.

[0010] The connection electrode may include a first edge and a second edge surrounding the first edge, and the second edge may overlap the groove.

[0011] The second electrode may be electrically connected to the connection electrode in a region adjacent to the groove.

[0012] The connection electrode may include a tip portion protruding from an end of the groove, and the connection electrode may overlap the groove of the pixel defining layer in a plan view.

[0013] The second electrode may be electrically connected to the connection electrode at the tip portion.

[0014] A through hole may be further defined through the pixel defining layer, and the connection electrode may be electrically connected to the pixel driving part through the through hole.

[0015] The connection electrode may include: a first connection electrode layer disposed on the pixel defining layer; and a second connection electrode layer disposed on the first connection electrode layer, and the second connection electrode layer may cover the first connection electrode layer.

[0016] The intermediate layer may be disposed on the second connection electrode layer, the second electrode may be disposed on the intermediate layer, and the second electrode may be electrically connected to the second connection electrode layer at the tip portion.

[0017] The display panel may further include a first separation pattern, a second separation pattern, and a third separation pattern. The first separation pattern and the second connection electrode layer may include the same material, the second separation pattern and the intermediate layer may include the same material, and the third separation pattern and the second electrode may include the same material. The first separation pattern, the second separation pattern, and the third separation pattern may be disposed in the groove.

[0018] The first dividing pattern may be electrically connected to the third dividing pattern.

[0019] The connection electrode may include a first connection electrode layer disposed on the pixel defining layer, and the intermediate layer may cover the first connection electrode layer.

[0020] The display panel may further include a first separation pattern and a second separation pattern. The first separation pattern and the intermediate layer may include the same material, and the second separation pattern and the second electrode may include the same material. The first separation pattern and the second separation pattern may be disposed in the groove.

[0021] The pixel defining layer may include a first pixel defining layer portion and a second pixel defining layer portion disposed on the first pixel defining layer portion, the first pixel defining layer portion may be integrated with the second pixel defining layer portion, and the groove may be defined in the second pixel defining layer portion.

[0022] An embodiment of the present disclosure provides a display panel, which may include: a driving element layer including a pixel driving unit; and a light-emitting element disposed on the driving element layer, and the light-emitting element includes a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer. The display panel may also include: a pixel defining layer disposed on the driving element layer, and the pixel defining layer includes a groove formed by removing a portion of the pixel defining layer in a thickness direction of the pixel defining layer; and a connecting electrode disposed on the pixel defining layer, and the connecting electrode includes a tip portion protruding from an end of the groove.

[0023] The pixel defining layer may further include a light emitting opening exposing at least a portion of the first electrode, and the groove may surround the light emitting opening.

[0024] The connection electrode may electrically connect the pixel driving part and the second electrode, and the second electrode may be electrically connected to the connection electrode at the tip portion.

[0025] A through hole may be defined through the pixel defining layer, and the connection electrode may be electrically connected to the pixel driving part through the through hole.

[0026] The light emitting element may include a plurality of light emitting elements, the pixel driving unit may include a plurality of pixel driving units, and the connecting electrode may include a plurality of connecting electrodes. The plurality of connecting electrodes may electrically connect the plurality of light emitting elements to the plurality of pixel driving units, respectively. Gaps between adjacent connecting electrodes among the plurality of connecting electrodes may overlap with the groove.

[0027] The connection electrode may include a first edge and a second edge surrounding the first edge, and the second edge may overlap the groove.

[0028] The connection electrode may include: a first connection electrode layer disposed on the pixel defining layer; and a second connection electrode layer disposed on the first connection electrode layer. The second connection electrode layer may cover the first connection electrode layer, and the second electrode may be electrically connected to the second connection electrode layer at the tip portion.

[0029] The display panel may further include a first separation pattern, a second separation pattern, and a third separation pattern. The first separation pattern and the second connection electrode layer may include the same material, the second separation pattern and the intermediate layer may include the same material, and the third separation pattern and the second electrode may include the same material. The first separation pattern, the second separation pattern, and the third separation pattern may be disposed in the groove, and the first separation pattern may be electrically connected to the third separation pattern.

[0030] The connection electrode may include a first connection electrode layer disposed on the pixel defining layer, and the intermediate layer may cover the first connection electrode layer.

[0031] The display panel may further include a first separation pattern and a second separation pattern. The first separation pattern and the intermediate layer may include the same material, and the second separation pattern and the second electrode may include the same material. The first separation pattern and the second separation pattern may be disposed in the groove.

[0032] The pixel defining layer may include a first pixel defining layer portion and a second pixel defining layer portion disposed on the first pixel defining layer portion. The first pixel defining layer portion may be integrated with the second pixel defining layer portion, and the groove may be defined in the second pixel defining layer portion.

[0033] An embodiment of the present disclosure provides a method for manufacturing a display panel. The method may include: preparing a preliminary display panel, the preliminary display panel including a substrate layer, a driving element layer disposed on the substrate layer, and a pixel defining layer disposed on the driving element layer. The method may also include: depositing a first connection electrode layer on the preliminary display panel; etching a portion of the first connection electrode layer and a portion of the pixel defining layer to form a groove in the pixel defining layer that overlaps with at least a portion of the first connection electrode layer; etching the first connection electrode layer to form a connection electrode; and forming an intermediate layer and a cathode on the connection electrode and the pixel defining layer.

[0034] The method may further include forming a tip portion at an end portion of the first connection electrode layer.

[0035] The method may further include: depositing a second connection electrode layer on the first connection electrode layer; and forming a tip portion at an end of the first connection electrode layer and an end of the second connection electrode layer. The forming the connection electrode may include etching the second connection electrode layer.

[0036] The pixel defining layer may include a first pixel defining layer portion and a second pixel defining layer portion disposed on the first pixel defining layer portion. The first pixel defining layer portion may be integrated with the second pixel defining layer portion, and the groove may be defined in the second pixel defining layer portion.

[0037] According to the above, the light emitting element and the pixel driving unit can stably contact each other, and therefore, the contact reliability between the light emitting element and the pixel driving unit can be improved. As an example, since the connecting electrode can be electrically connected to the cathode of the light emitting element and the pixel driving unit in a relatively wide area rather than at a specific point, the contact reliability can be enhanced. Therefore, external defects caused by contact defects (e.g., spots detected during illumination) can be reduced or eliminated. Therefore, the display quality and manufacturing yield of the display panel can be improved.

[0038] In addition, the lower surface of the connecting electrode and the upper surface of the intermediate connecting electrode can contact each other, and the contact reliability can be improved. Therefore, the size of the through hole through which the connecting electrode is connected to the intermediate connecting electrode can be reduced or minimized. As a result, the size of the light emitting portion and the resolution of the display panel can be increased.

[0039] In addition, the connecting electrode includes a tip portion, and therefore, each of the intermediate layer and the second electrode can be separated at each pixel. Therefore, lateral leakage current can be prevented from occurring between adjacent pixels, and therefore, color mixing and brightness degradation between adjacent pixels can be prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The above and other advantages of the present disclosure will become apparent by referring to the following detailed description when considered in conjunction with the accompanying drawings, in which:

[0041] Figure 1 is a schematic block diagram of a display device according to an embodiment of the present disclosure;

[0042] FIG. 2A to FIG. 2C is a schematic diagram of an equivalent circuit of a pixel according to an embodiment of the present disclosure;

[0043] Figure 3A and Figure 3B is a schematic plan view of a display panel according to an embodiment of the present disclosure;

[0044] FIG. 4A to FIG. 4Dis an enlarged schematic plan view of some areas of a display panel according to an embodiment of the present disclosure;

[0045] Figure 5 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure;

[0046] Fig. 6A is an enlarged schematic cross-sectional view of a region of a display panel according to an embodiment of the present disclosure;

[0047] Figure 6B is an enlarged schematic plan view of a region of a display panel according to an embodiment of the present disclosure;

[0048] Figure 6C is an enlarged schematic cross-sectional view of a region of a display panel according to an embodiment of the present disclosure;

[0049] Figure 7 is an enlarged schematic cross-sectional view of a region of a display panel according to an embodiment of the present disclosure;

[0050] Figure 8 is an enlarged schematic cross-sectional view of a region of a display panel according to an embodiment of the present disclosure;

[0051] Fig. 9 is an enlarged schematic cross-sectional view of a region of a display panel according to an embodiment of the present disclosure;

[0052] FIG. 10A to FIG. 10F is a schematic cross-sectional view showing a process of a method for manufacturing a display panel according to an embodiment of the present disclosure;

[0053] FIG. 11A to FIG. 11C is a schematic cross-sectional view showing a process of a method for manufacturing a display panel according to an embodiment of the present disclosure;

[0054] FIG. 12A to FIG. 12F is a schematic cross-sectional view showing a process of a method of manufacturing a display panel according to an embodiment of the present disclosure; and

[0055] FIG. 13A to FIG. 13C 2 is a schematic cross-sectional view showing a process of a method of manufacturing a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0056] The present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments are shown. However, the present disclosure may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art.

[0057] In the present disclosure, it will be understood that when an element or layer (or region, portion) is referred to as being "on", "connected to" or "coupled to" another element or layer, the element or layer may be directly on, directly connected to or directly coupled to the other element or layer, or intervening elements or layers may be present.

[0058] The same reference numerals always refer to the same elements. In the accompanying drawings, the thickness, proportion and size of the components may be exaggerated in order to effectively describe the technical content. As used herein, the term "and / or" may include any combination and all combinations of one or more related listed items. For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in conjunction or disjunction, and may be understood to be equivalent to "and / or".

[0059] In the specification and claims, for the purpose of its meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of..." For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0060] It will be understood that, although the terms "first", "second", etc. can be used in this article to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below can be referred to as the second element. As used herein, unless the context clearly indicates otherwise, the singular forms "one", "one (kind / person)" and "the (the)" are also intended to include plural forms.

[0061] For ease of description, spatially relative terms such as “under,” “beneath,” “lower,” “over,” and “upper” may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures.

[0062] It will also be understood that when the terms “comprises, comprising,” “has, have, having,” and “include, including,” etc. are used in this specification, they indicate the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0063] The term "overlapping" or "overlapping with..." means that a first object can be above or below or to the side of a second object, and vice versa. Additionally, the term "overlapping" may include stacking, stacking, facing or facing, extending across (extending over), covering or partially covering, or any other suitable term that would be appreciated and understood by a person of ordinary skill in the art.

[0064] Unless otherwise defined or implied, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless explicitly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0065] Figure 1 is a schematic block diagram of a display device DD according to an embodiment of the present disclosure.

[0066] refer to Figure 1 , the display device DD may include a display panel DP, panel drivers SDC, EDC and DDC, a power supply unit PWS and a timing controller TC. The display panel DP may be a light-emitting display panel. The light-emitting display panel may be an organic light-emitting display panel, an inorganic light-emitting display panel or a quantum dot light-emitting display panel. Hereinafter, an organic light-emitting display panel will be described as a representative example of the display panel DP. The panel drivers SDC, EDC and DDC may include a scan driver SDC, an emission driver EDC and a data driver DDC.

[0067] The display panel DP may include scan lines GWL1 to GWLn, GCL1 to GCLn, GIL1 to GILn, GBL1 to GBLn, and GRL1 to GRLn, emission lines ESL1 to ESLn, and data lines DL1 to DLm. The display panel DP may include pixels connected to the scan lines GWL1 to GWLn, GCL1 to GCLn, GIL1 to GILn, GBL1 to GBLn, and GRL1 to GRLn, emission lines ESL1 to ESLn, and data lines DL1 to DLm. Each of "m" and "n" is an integer greater than or equal to 1.

[0068] As an example, a pixel PXij ("i" is an integer greater than or equal to 1 and less than or equal to "n", and "j" is an integer greater than or equal to 1 and less than or equal to "m") positioned to correspond to the i-th horizontal line (or i-th pixel row) and the j-th vertical line (or j-th pixel column) can be connected to the i-th first scan line (or write scan line) GWLi, the i-th second scan line (or compensation scan line) GCLi, the i-th third scan line (or first initialization scan line) GILi, the i-th fourth scan line (or second initialization scan line) GBLi, the i-th fifth scan line (or reset scan line) GRLi, the j-th data line DLj and the i-th emission line ESLi.

[0069] The pixel PXij may include a light emitting element, a transistor, and a capacitor. The pixel PXij may receive a first power voltage VDD, a second power voltage VSS, a third power voltage (or a reference voltage) VREF, a fourth power voltage (or a first initialization voltage) VINT1, a fifth power voltage (or a second initialization voltage) VINT2, and a sixth power voltage (or a compensation voltage) VCOMP from a power supply unit PWS.

[0070] The first power voltage VDD and the second power voltage VSS may have voltage values ​​set to allow current to flow through the light emitting element, and thus light may be emitted from the light emitting element. As an example, the first power voltage VDD may be set to have a voltage level higher than that of the second power voltage VSS.

[0071] The third power voltage VREF may be a voltage for initializing the gate of the driving transistor included in the pixel PXij. The third power voltage VREF may be used to implement a predetermined or selected grayscale using a voltage difference between the third power voltage VREF and the data signal. To this end, the third power voltage VREF may be set to a predetermined or selected voltage within a voltage range of the data signal.

[0072] The fourth power voltage VINT1 may be used to initialize a capacitor included in the pixel PXij. The fourth power voltage VINT1 may be set to a voltage level having a voltage level lower than a voltage level of the third power voltage VREF. As an example, the fourth power voltage VINT1 may be set to a voltage level having a voltage level lower than a voltage level of a voltage difference between the third power voltage VREF and a threshold voltage of the driving transistor, however, the present disclosure should not be limited thereto or thereby.

[0073] The fifth power voltage VINT2 may be used to initialize the cathode of the light emitting element included in the pixel PXij. The fifth power voltage VINT2 may be set to a voltage level lower than the voltage level of the first power voltage VDD or the fourth power voltage VINT1 or may be set to a voltage level similar to or the same as the voltage level of the third power voltage VREF, however, the embodiment should not be limited thereto or thereby. The fifth power voltage VINT2 may be set to a voltage level similar to or the same as the voltage level of the first power voltage VDD.

[0074] The sixth power voltage VCOMP may provide a predetermined or selected current to the driving transistor while compensating for the threshold voltage of the driving transistor.

[0075] Figure 1 A structure in which all of the first power voltage VDD, the second power voltage VSS, the third power voltage VREF, the fourth power voltage VINT1, the fifth power voltage VINT2, and the sixth power voltage VCOMP are provided from the power supply unit PWS is shown, however, the present disclosure should not be limited thereto or thereby. As an example, regardless of the structure of the pixel PXij, both the first power voltage VDD and the second power voltage VSS may be provided, and depending on the structure of the pixel PXij, at least one of the third power voltage VREF, the fourth power voltage VINT1, the fifth power voltage VINT2, and the sixth power voltage VCOMP may not be provided.

[0076] According to the present disclosure, the signal line connected to the pixel PXij may be designed in various ways by considering the structure of the pixel PXij.

[0077] The scan driver SDC may receive a first control signal SCS from the timing controller TC and may provide scan signals to the first to GWLn, second to GCL1 to GCLn, third to GIL1 to GILn, fourth to GBL1 to GBLn, and fifth to GRL1 to GRLn in response to the first control signal SCS.

[0078] The scan signal may be set to have a voltage that allows the transistor to be turned on in response to the scan signal. As an example, the scan signal provided to the P-type transistor may be set to have a logic low level, and the scan signal provided to the N-type transistor may be set to have a logic high level. Hereinafter, the expression "providing a scan signal" may mean providing a scan signal having a logic level that turns on the transistor to the transistor controlled by the scan signal.

[0079] For ease of explanation, Figure 1One scan driver SDC is shown, however, the present disclosure should not be limited thereto or thereby. According to an embodiment, the display device DD may include a plurality of scan drivers to provide scan signals to the first scan lines GWL1 to GWLn, the second scan lines GCL1 to GCLn, the third scan lines GIL1 to GILn, the fourth scan lines GBL1 to GBLn, and the fifth scan lines GRL1 to GRLn.

[0080] The emission driver EDC may provide the emission signals to the emission lines ESL1 to ESLn in response to the second control signal ECS. As an example, the emission signals may be sequentially provided to the emission lines ESL1 to ESLn.

[0081] Each transistor connected to the transmission lines ESL1 to ESLn may be an N-type transistor. The transmission signal provided to the transmission lines ESL1 to ESLn may have a gate-on voltage. The transistor receiving the transmission signal may be turned on when receiving the transmission signal, and may be turned off in other cases.

[0082] The second control signal ECS may include an emission start signal and a clock signal, and the emission driver EDC may be implemented by a shift register that sequentially shifts the emission start signal having a pulse shape using the clock signal to sequentially generate and output emission signals having a pulse shape.

[0083] The data driver DDC may receive the third control signal DCS and the image data RGB from the timing controller TC. The data driver DDC may convert the image data RGB in digital form into analog data signals. The data driver DDC may provide data signals to the data lines DL1 to DLm in response to the third control signal DCS.

[0084] The third control signal DCS may include a data enable signal, a horizontal start signal, and a data clock signal to indicate the output of a valid data signal. As an example, the data driver DDC may include a shift register that shifts the horizontal start signal synchronously with the data clock signal to generate a sampling signal, a latch that latches the image data RGB in response to the sampling signal, a digital-to-analog converter (or decoder) that converts the latched image data RGB (e.g., data in digital form) into a data signal in analog form, and a buffer (or amplifier) ​​that outputs the data signal to the data lines DL1 to DLm.

[0085] The power supply unit PWS may provide the display panel DP with first, second and third power voltages VDD, VSS and VREF to drive the pixels PXij. In addition, the power supply unit PWS may provide the display panel DP with at least one of fourth, fifth and sixth power voltages VINT1, VINT2 and VCOMP.

[0086] As an example, the power supply unit PWS can be connected via a Figure 1 The first power line VDL (reference Figure 2A )、The second power line VSL (reference Figure 2A ), the third power line (or reference voltage line) VRL (reference Figure 2A ), the fourth power line (or the first initialization voltage line) VIL1 (reference Figure 2A ), the fifth power line (or the second initialization voltage line) VIL2 (reference Figure 2A ) and the sixth power line (or compensation voltage line) VCL (reference Figure 2A ) respectively provide a first power voltage VDD, a second power voltage VSS, a third power voltage VREF, a fourth power voltage VINT1, a fifth power voltage VINT2 and a sixth power voltage VCOMP to the display panel DP.

[0087] The power supply unit PWS may be implemented by a power management integrated circuit (IC), however, the present disclosure should not be limited thereto or thereby.

[0088] The timing controller TC may generate a first control signal SCS, a second control signal ECS, a third control signal DCS, and a fourth control signal PCS based on the input image data IRGB, a synchronization signal Sync (e.g., a vertical synchronization signal, a horizontal synchronization signal, etc.), a data enable signal DE, and a clock signal. The first control signal SCS may be applied to the scan driver SDC, the second control signal ECS may be applied to the emission driver EDC, the third control signal DCS may be applied to the data driver DDC, and the fourth control signal PCS may be applied to the power supply unit PWS. The timing controller TC may rearrange the input image data IRGB to correspond to the arrangement of the pixels PXij in the display panel DP, and may generate image data RGB (or frame data).

[0089] The scan driver SDC, the emission driver EDC, the data driver DDC, the power supply unit PWS and / or the timing controller TC may be directly formed in the display panel DP, or may be connected to the display panel DP after being manufactured in a separate driver chip. In addition, at least two of the scan driver SDC, the emission driver EDC, the data driver DDC, the power supply unit PWS and the timing controller TC may be provided in a single driver chip. As an example, the data driver DDC and the timing controller TC may be provided in a single driver chip.

[0090] Although reference is made to Figure 1The display device DD according to the embodiment is described, but the display device DD of the present disclosure should not be limited thereto or thereby. Signal lines can be added or omitted according to the structure of the pixel. In addition, the connection relationship between a pixel and the signal line can be changed. In the case of omitting one of the signal lines, the omitted signal line can be replaced by another signal line.

[0091] Figure 2A , Figure 2B and Figure 2C is a schematic diagram of an equivalent circuit of pixels PXij, PXij-1, and PXij-2 according to an embodiment of the present disclosure. Figure 2A , Figure 2B and Figure 2C An equivalent circuit diagram of pixels PXij, PXij-1 and PXij-2 is shown, and pixels PXij, PXij-1 and PXij-2 are connected to the i-th first scan line GWLi (hereinafter referred to as the write scan line GWLi) and the j-th data line DLj (hereinafter referred to as the data line DLj).

[0092] refer to Figure 2A , the pixel PXij may include a light emitting element LD and a pixel driving unit (part) PDC. The light emitting element LD may be connected to the first power line VDL and the pixel driving unit PDC.

[0093] The pixel driving unit PDC may be connected to the scanning lines GWLi, GCLi, GILi, GBLi and GRLi, the data line DLj, the i-th emission line ESLi and the power lines VDL, VSL, VIL1, VIL2, VRL and VCL. The pixel driving unit PDC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8, a first capacitor C1 and a second capacitor C2. Hereinafter, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 will be described as an N-type transistor, however, the present disclosure should not be limited thereto or thereby. According to an embodiment, some of the first transistor T1 to the eighth transistor T8 may be N-type transistors, and the other transistors of the first transistor T1 to the eighth transistor T8 may be P-type transistors, or each of the first transistor T1 to the eighth transistor T8 may be a P-type transistor, and the present disclosure should not be particularly limited.

[0094] The gate of the first transistor T1 may be connected to the first node N1. The first electrode of the first transistor T1 may be connected to the second node N2, and the second electrode of the first transistor T1 may be connected to the third node N3. The first transistor T1 may be a driving transistor. The first transistor T1 may control a driving current ILD flowing from the first power line VDL to the second power line VSL via the light emitting element LD in response to a voltage of the first node N1. The first power voltage VDD may be set to a voltage having a potential higher than that of the second power voltage VSS.

[0095] In the present disclosure, the expression “a transistor is connected to a signal line” means that one of the source electrode, drain electrode, and gate electrode of the transistor is provided integrally with the signal line or is connected to the signal line via a connecting electrode. In addition, the expression “a transistor is electrically connected to another transistor” means that one of the source electrode, drain electrode, and gate electrode of the one transistor is provided integrally with one of the source electrode, drain electrode, and gate electrode of the other transistor or is connected to one of the source electrode, drain electrode, and gate electrode of the other transistor via a connecting electrode.

[0096] The second transistor T2 may include a gate connected to the write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1. The second transistor T2 may provide a data signal DATA to the first node N1 in response to a write scan signal GW applied thereto via the write scan line GWLi. When the write scan signal GW is applied to the second transistor T2 via the write scan line GWLi, the second transistor T2 may be turned on, and thus, the data line DLj may be electrically connected to the first node N1.

[0097] The third transistor T3 may be connected between the first node N1 and the reference voltage line VRL. The first electrode of the third transistor T3 may receive the reference voltage VREF via the reference voltage line VRL, and the second electrode of the third transistor T3 may be connected to the first node N1. In an embodiment, the gate of the third transistor T3 may receive the reset scan signal GR via the i-th fifth scan line GRLi (hereinafter, referred to as the reset scan line GRLi). The third transistor T3 may be turned on when the reset scan signal GR is applied thereto via the reset scan line GRLi, and may provide the reference voltage VREF to the first node N1.

[0098] The fourth transistor T4 may be connected between the third node N3 and the first initialization voltage line VIL1. The first electrode of the fourth transistor T4 may be connected to the third node N3, and the second electrode of the fourth transistor T4 may be connected to the first initialization voltage line VIL1 through which the first initialization voltage VINT1 is provided. The fourth transistor T4 may be referred to as a first initialization transistor. The gate of the fourth transistor T4 may receive the first initialization scan signal GI via the i-th third scan line GILi (hereinafter, referred to as the first initialization scan line GILi). The fourth transistor T4 may be turned on when the first initialization scan signal GI is provided thereto via the first initialization scan line GILi, and may provide the first initialization voltage VINT1 to the third node N3.

[0099] The fifth transistor T5 may be connected between the compensation voltage line VCL and the second node N2. The first electrode of the fifth transistor T5 may receive the compensation voltage VCOMP via the compensation voltage line VCL, and the second electrode of the fifth transistor T5 may be connected to the second node N2 to be electrically connected to the first electrode of the first transistor T1. The gate of the fifth transistor T5 may receive the compensation scan signal GC via the i-th second scan line GCLi (hereinafter, referred to as the compensation scan line GCLi). The fifth transistor T5 may be turned on when the compensation scan signal GC is provided thereto via the compensation scan line GCLi, and the compensation voltage VCOMP may be provided to the second node N2, and therefore, the threshold voltage of the first transistor T1 may be compensated during the compensation period.

[0100] The sixth transistor T6 may be connected between the first transistor T1 and the light emitting element LD. In detail, the gate of the sixth transistor T6 may receive an emission signal EM via an i-th emission line ESLi (hereinafter, referred to as the emission line ESLi). The first electrode of the sixth transistor T6 may be connected to the cathode of the light emitting element LD via a fourth node N4, and the second electrode of the sixth transistor T6 may be connected to the first electrode of the first transistor T1 via a second node N2. The sixth transistor T6 may be referred to as a first emission control transistor. The sixth transistor T6 may be turned on when an emission signal EM is provided thereto via the emission line ESLi, and therefore, the light emitting element LD may be electrically connected to the first transistor T1.

[0101] The seventh transistor T7 may be connected between the second power line VSL and the third node N3. The first electrode of the seventh transistor T7 may be connected to the second electrode of the first transistor T1 via the third node N3, and the second electrode of the seventh transistor T7 may receive the second power voltage VSS via the second power line VSL. The gate of the seventh transistor T7 may be electrically connected to the emission line ESLi. The seventh transistor T7 may be referred to as a second emission control transistor. The seventh transistor T7 may be turned on when an emission signal EM is provided thereto via the emission line ESLi, and therefore, the second electrode of the first transistor T1 may be electrically connected to the second power line VSL.

[0102] According to an embodiment, the sixth transistor T6 and the seventh transistor T7 may be connected to the same emission line ESLi and may be turned on in response to the same emission signal EM, however, this is merely an example. According to an embodiment, the sixth transistor T6 and the seventh transistor T7 may be turned on independently in response to different signals distinguished from each other. In addition, according to an embodiment, the sixth transistor T6 or the seventh transistor T7 may be omitted from the pixel driving unit PDC.

[0103] The eighth transistor T8 may be connected between the second initialization voltage line VIL2 and the fourth node N4. That is, the eighth transistor T8 may include a gate connected to the i-th fourth scan line GBLi (hereinafter, referred to as the second initialization scan line GBLi), a first electrode connected to the second initialization voltage line VIL2, and a second electrode connected to the fourth node N4. The eighth transistor T8 may be referred to as a second initialization transistor. The eighth transistor T8 may provide a second initialization voltage VINT2 to the fourth node N4 corresponding to the cathode of the light emitting element LD in response to the second initialization scan signal GB applied thereto via the second initialization scan line GBLi. The cathode of the light emitting element LD may be initialized by the second initialization voltage VINT2.

[0104] According to an embodiment, some of the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 may be turned on substantially at the same time in response to the same scan signal. As an example, the eighth transistor T8 and the fifth transistor T5 may be turned on substantially at the same time in response to the same scan signal. As an example, the eighth transistor T8 and the fifth transistor T5 may operate in response to the same compensation scan signal GC. The eighth transistor T8 and the fifth transistor T5 may be turned on and off substantially at the same time in response to the same compensation scan signal GC. The compensation scan line GCLi and the second initialization scan line GBLi may be substantially provided as a single scan line. Therefore, the initialization of the cathode of the light emitting element LD and the compensation of the threshold voltage of the first transistor T1 may be performed at the same timing. However, the present disclosure should not be limited thereto or thereby.

[0105] In addition, according to the present disclosure, the initialization of the cathode of the light emitting element LD and the compensation of the threshold voltage of the first transistor T1 can be performed in response to the same power voltage. As an example, the compensation voltage line VCL and the second initialization voltage line VIL2 can be substantially provided as a single power line. The initialization operation of the cathode and the compensation operation of the driving transistor can be performed using one power voltage, and therefore, the design of the driver can be simplified. However, this is only an example, and the present disclosure should not be particularly limited.

[0106] The first capacitor C1 may be disposed between the first node N1 and the third node N3. The first capacitor C1 may charge a voltage corresponding to a difference between a voltage of the first node N1 and a voltage of the third node N3. The first capacitor C1 may be referred to as a storage capacitor.

[0107] The second capacitor C2 may be disposed between the third node N3 and the second power line VSL. That is, one electrode of the second capacitor C2 may be connected to the second power line VSL receiving the second power voltage VSS, and the other electrode of the second capacitor C2 may be connected to the third node N3. The second capacitor C2 may be charged with a charge corresponding to a voltage difference between the second power voltage VSS and the voltage of the third node N3. The second capacitor C2 may be referred to as a holding capacitor. Compared to the first capacitor C1, the second capacitor C2 may have a higher storage capacity. Therefore, the second capacitor C2 may reduce a voltage change of the third node N3 caused by a voltage change of the first node N1.

[0108] In an embodiment, the light emitting element LD may be connected to the pixel driving unit PDC via a fourth node N4. The light emitting element LD may include an anode connected to the first power line VDL and a cathode opposite to the anode. In an embodiment, the light emitting element LD may be connected to the pixel driving unit PDC via its cathode. That is, according to the pixel PXij, the connection node at which the light emitting element LD is connected to the pixel driving unit PDC may be the fourth node N4, and the fourth node N4 may correspond to the connection node between the first electrode of the sixth transistor T6 and the cathode of the light emitting element LD. Therefore, the potential of the fourth node N4 may correspond to the potential of the cathode of the light emitting element LD.

[0109] In detail, the anode of the light emitting element LD may be connected to the first power line VDL, the first power voltage VDD as a constant voltage may be applied to the anode, and the cathode may be electrically connected to the first transistor T1 via the sixth transistor T6. That is, in an embodiment in which each of the first transistor T1 to the eighth transistor T8 is an N-type transistor, the potential of the third node N3 corresponding to the source of the first transistor T1 may not be directly affected by the characteristics of the light emitting element LD. Therefore, even if the characteristics of the light emitting element LD deteriorate, the influence of the characteristic degradation of the light emitting element LD on the gate-source voltage (Vgs) of the transistor (particularly the driving transistor) constituting the pixel driving unit PDC can be reduced. That is, since the change in the amount of the driving current ILD caused by the characteristic degradation of the light emitting element LD can be reduced, the image retention defect of the display panel caused by the increase in the use time can be reduced, and the life of the display panel can be improved.

[0110] like Figure 2B As shown in FIG. 1 , the pixel PXij-1 may include a pixel driving unit PDC-1 including two transistors T1 and T2 and a first capacitor C1. The pixel driving unit PDC-1 may be connected to the light emitting element LD, the write scan line GWLi, the data line DLj and the second power line VSL. Figure 2B The pixel driving unit PDC-1 shown in FIG. 1 may have a Figure 2A The pixel driving unit PDC shown in FIG. 1 corresponds to a circuit configuration obtained by removing the third transistor T3 to the eighth transistor T8 and the second capacitor C2 .

[0111] Each of the first transistor T1 and the second transistor T2 may be an N-type transistor or a P-type transistor. In an embodiment, each of the first transistor T1 and the second transistor T2 will be described as an N-type transistor.

[0112] The first transistor T1 may include a gate connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The second node N2 may be connected to a first power line VDL, and the third node N3 may be connected to a second power line VSL. The first transistor T1 may be connected to the light emitting element LD via the second node N2, and may be connected to the second power line VSL via the third node N3. The first transistor T1 may be a driving transistor.

[0113] The second transistor T2 may include a gate receiving a write scan signal GW via the write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1. The second transistor T2 may provide a data signal DATA to the first node N1 in response to the write scan signal GW applied thereto via the write scan line GWLi.

[0114] The first capacitor C1 may include an electrode connected to the first node N1 and an electrode connected to the third node N3. The first capacitor C1 may charge a voltage corresponding to the data signal DATA applied to the first node N1.

[0115] The light emitting element LD may include an anode and a cathode. In an embodiment, the anode of the light emitting element LD may be connected to the first power line VDL, and the cathode of the light emitting element LD may be connected to the pixel driving unit PDC-1 via the second node N2. In an embodiment, the cathode of the light emitting element LD may be connected to the first transistor T1. The light emitting element LD may emit light in response to the amount of current flowing through the first transistor T1 of the pixel driving unit PDC-1.

[0116] In an embodiment in which each of the first transistor T1 and the second transistor T2 is an N-type transistor, the cathode of the light emitting element LD is connected to the second node N2 at which the pixel driving unit PDC-1 is located, which may correspond to the drain of the first transistor T1. That is, the change in the gate-source voltage (Vgs) of the first transistor T1 caused by the light emitting element LD can be prevented. Therefore, the change in the amount of the driving current ILD caused by the degradation of the light emitting element LD can be reduced, the image retention defect of the display panel caused by the increase in the use time can be reduced, and the life of the display panel can be improved.

[0117] refer to Figure 2C , the pixel PXij- 2 may include a pixel driving unit PDC- 2 , which includes six transistors T1 , T2 , T3 , T4 a , T5 a , and T6 a and two capacitors C1 and C2 .

[0118] The pixel driving unit PDC-2 can be connected to the light emitting element LD, the write scan line GWLi, the reset scan line GRLi, the compensation scan line GCLi, the i-th first emission line ESL1i (hereinafter referred to as the first emission line ESL1i), the i-th second emission line ESL2i (hereinafter referred to as the second emission line ESL2i), the data line DLj, the first power line VDL, the second power line VSL, the third power line VRL and the initialization voltage line VIL.

[0119] Figure 2C The pixel driving unit PDC-2 shown in FIG. 1 may have a Figure 2A The pixel driving unit PDC shown in FIG. 1 is similar to the circuit configuration obtained by removing the fourth transistor T4 and the fifth transistor T5. Since the pixel driving unit PDC-2 has a smaller Figure 2A The area of ​​the pixel driving unit PDC shown in is reduced, so high resolution can be achieved more easily.

[0120] Each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4a, the fifth transistor T5a and the sixth transistor T6a may be an N-type transistor or a P-type transistor. In an embodiment, as a representative example, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4a, the fifth transistor T5a and the sixth transistor T6a will be described as an N-type transistor.

[0121] The first transistor T1 may include a gate connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The second node N2 may be connected to a first power line VDL, and the third node N3 may be connected to a second power line VSL. The first transistor T1 may be connected to the light emitting element LD via the second node N2, and may be connected to the second power line VSL via the third node N3. The first transistor T1 may be a driving transistor.

[0122] The second transistor T2 may include a gate receiving a write scan signal GW via the write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1. The second transistor T2 may provide a data signal DATA to the first node N1 in response to the write scan signal GW applied thereto via the write scan line GWLi.

[0123] The third transistor T3 may be connected between the first node N1 and the reference voltage line VRL. The first electrode of the third transistor T3 may receive the reference voltage VREF via the reference voltage line VRL, and the second electrode of the third transistor T3 may be connected to the first node N1. In an embodiment, the gate of the third transistor T3 may receive the reset scan signal GR via the reset scan line GRLi. The third transistor T3 may be turned on when the reset scan signal GR is applied thereto via the reset scan line GRLi, and may provide the reference voltage VREF to the first node N1.

[0124] The fourth transistor T4a may be connected between the first transistor T1 and the light emitting element LD. In detail, the gate of the fourth transistor T4a may receive the first emission signal EM1 via the first emission line ESL1i. The first electrode of the fourth transistor T4a may be connected to the cathode of the light emitting element LD via the fourth node N4, and the second electrode of the fourth transistor T4a may be connected to the first electrode of the first transistor T1 via the second node N2. The fourth transistor T4a may be referred to as a first emission control transistor. The fourth transistor T4a may be turned on when the first emission signal EM1 is applied thereto via the first emission line ESL1i, and therefore, the light emitting element LD may be electrically connected to the first transistor T1.

[0125] The fifth transistor T5a may be connected between the second power line VSL and the third node N3. The first electrode of the fifth transistor T5a may be connected to the second electrode of the first transistor T1 via the third node N3, and the second electrode of the fifth transistor T5a may receive the second power voltage VSS via the second power line VSL. The gate of the fifth transistor T5a may be electrically connected to the second emission line ESL2i. The fifth transistor T5a may be referred to as a second emission control transistor. The fifth transistor T5a may be turned on when the second emission signal EM2 is applied thereto via the second emission line ESL2i, and therefore, the second electrode of the first transistor T1 may be electrically connected to the second power line VSL.

[0126] In an embodiment, the fourth transistor T4a and the fifth transistor T5a may be connected to a first emission line ESL1i and a second emission line ESL2i, respectively, and may be turned on in response to a first emission signal EM1 and a second emission signal EM2, respectively, which are distinguished from each other. That is, the fourth transistor T4a and the fifth transistor T5a may be turned on independently, however, this is only an example. As an example, the fourth transistor T4a and the fifth transistor T5a may be connected to the same emission line and may be controlled by the same emission signal. In addition, the fourth transistor T4a or the fifth transistor T5a may be omitted from the pixel driving unit PDC-2.

[0127] The sixth transistor T6a may be connected between the initialization voltage line VIL and the fourth node N4. That is, the sixth transistor T6a may include a gate connected to the compensation scan line GCLi, a first electrode connected to the initialization voltage line VIL, and a second electrode connected to the fourth node N4. The sixth transistor T6a may be referred to as an initialization transistor. The sixth transistor T6a may provide an initialization voltage VINT to the fourth node N4 corresponding to the cathode of the light emitting element LD in response to a compensation scan signal GC applied thereto via the compensation scan line GCLi. The cathode of the light emitting element LD may be initialized by the initialization voltage VINT.

[0128] The first capacitor C1 may be disposed between the first node N1 and the third node N3. The first capacitor C1 may charge a voltage corresponding to a difference between a voltage of the first node N1 and a voltage of the third node N3. The first capacitor C1 may be referred to as a storage capacitor.

[0129] The second capacitor C2 may be disposed between the third node N3 and the second power line VSL. That is, one electrode of the second capacitor C2 may be connected to the second power line VSL to which the second power voltage VSS is applied, and the other electrode of the second capacitor C2 may be connected to the third node N3. The second capacitor C2 may be charged with a charge corresponding to a voltage difference between the second power voltage VSS and the voltage of the third node N3. The second capacitor C2 may be referred to as a holding capacitor.

[0130] The light emitting element LD may include an anode and a cathode. In an embodiment, the anode of the light emitting element LD may be connected to the first power line VDL, and the cathode of the light emitting element LD may be connected to the pixel driving unit PDC-2 via the fourth node N4. In an embodiment, the cathode of the light emitting element LD may be connected to the first transistor T1 via the fourth transistor T4a. The light emitting element LD may emit light in response to the amount of current flowing through the first transistor T1 of the pixel driving unit PDC-2.

[0131] In an embodiment in which each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4a, the fifth transistor T5a, and the sixth transistor T6a is an N-type transistor, the potential of the third node N3 corresponding to the source of the first transistor T1 as a driving transistor may not be directly affected by the characteristics of the light emitting element LD. Therefore, even if the light emitting element LD deteriorates, the influence of the degradation of the light emitting element LD on the gate-source voltage (Vgs) of the transistor (particularly the driving transistor) constituting the pixel driving unit PDC-2 can be reduced. That is, since the change in the amount of the driving current ILD caused by the degradation of the light emitting element LD can be reduced, the image retention defect of the display panel caused by the increase in the use time can be reduced, and the life of the display panel can be improved.

[0132] Figure 2A , Figure 2B and Figure 2C The circuits of the pixel driving units PDC, PDC-1 and PDC-2 according to the embodiments of the present disclosure are shown, and the number and arrangement of transistors and the number and arrangement of capacitors can be designed in various ways as long as the circuit is connected to the cathode of the light emitting element LD in the display panel.

[0133] Figure 3A and Figure 3B Schematic plan view of a display panel DP according to an embodiment of the present disclosure. Figure 3A and Figure 3B Some components are omitted in each of the above. Figure 3A and Figure 3B The present disclosure is described.

[0134] refer to Figure 3A , the display panel DP may include a display area DA and a peripheral area (or non-display area) NDA. The display area DA may include a light emitting portion EP.

[0135] The light emitting portion EP may be a pixel PXij (refer to Figure 1 ) an area where light is emitted. In detail, each of the light emitting portions EP may correspond to a light emitting opening OP-PDL (refer to Figure 5 ).

[0136] The peripheral area NDA may be defined as being adjacent to the display area DA. In an embodiment, the peripheral area NDA may have a shape surrounding an edge of the display area DA, however, this is merely an example. According to an embodiment, the peripheral area NDA may be defined as being adjacent to one side of the display area DA, or the peripheral area NDA may be omitted.

[0137] In an embodiment, a scan driver SDC and a data driver DDC may be mounted on the display panel DP. The scan driver SDC may be disposed in the display area DA, and the data driver DDC may be disposed in the peripheral area NDA. The scan driver SDC may overlap at least some of the light emitting portions EP disposed in the display area DA in a plan view. Since the scan driver SDC is disposed in the display area DA, the size of the peripheral area NDA may be reduced compared to the size of the peripheral area of ​​a conventional display panel in which the scan driver is disposed in the peripheral area, and therefore, a narrow frame of the display device may be easily realized.

[0138] and Figure 3AUnlike the scan driver SDC shown in , the scan driver SDC may be provided in two parts distinguished from each other. The two scan drivers SDC may be respectively disposed at the left and right sides of the display area DA and may be spaced apart from each other. According to an embodiment, three or more scan drivers SDC may be adopted, but the number of the scan drivers SDC should not be particularly limited.

[0139] Figure 3A A representative example of the display panel DP is shown, and the data driver DDC may also be disposed in the display area DA. In the case where the data driver DDC is disposed in the display area DA, some of the light emitting parts EP arranged in the display area DA may overlap with the data driver DDC in a plan view.

[0140] According to an embodiment, the data driver DDC may be provided in a separate driving chip formed independently from the display panel DP and may be connected to the display panel DP, however, this is merely an example. According to an embodiment, the data driver DDC may be formed through the same process as the scan driver SDC to form the display panel DP, and the embodiment should not be limited thereto or thereby.

[0141] refer to Figure 3B , the display panel DP may have a length in the first direction DR1 that is longer than a length in the second direction DR2. The display panel DP may include pixels PX11 to PXnm arranged in n rows by m columns in the display area DA. In an embodiment, the display panel DP may include scan drivers SDC1 and SDC2. The scan drivers SDC1 and SDC2 may include a first scan driver SDC1 and a second scan driver SDC2 that are spaced apart from each other in the first direction DR1.

[0142] The first scan driver SDC1 may be connected to some scan lines among the scan lines GL1 to GLn, and the second scan driver SDC2 may be connected to other scan lines among the scan lines GL1 to GLn. As an example, the first scan driver SDC1 may be connected to odd-numbered scan lines among the scan lines GL1 to GLn, and the second scan driver SDC2 may be connected to even-numbered scan lines among the scan lines GL1 to GLn.

[0143] For ease of explanation, Figure 3B The pads PD of the data lines DL1 to DLm are shown. The pads PD may be placed at the ends of the data lines DL1 to DLm. The data lines DL1 to DLm may be connected to a data driver (refer to Figure 3A data driver DDC).

[0144] According to the present disclosure, the pads PD may be arranged in areas of the peripheral area NDA that are spaced apart from each other, and the display area DA is interposed between the areas of the peripheral area NDA. As an example, some of the pads PD may be arranged in an upper portion of the display panel DP adjacent to the first scan line GL1 among the scan lines GL1 to GLn, and other pads of the pads PD may be arranged in a lower portion of the display panel DP adjacent to the last scan line GLn among the scan lines GL1 to GLn. In an embodiment, pads of the pads PD connected to odd-numbered data lines may be arranged in an upper portion, and pads of the pads PD connected to even-numbered data lines may be arranged in a lower portion.

[0145] Although not shown in the figure, the display panel DP may include a plurality of upper data drivers connected to the pads PD arranged in the upper portion and a plurality of lower data drivers connected to the pads PD arranged in the lower portion, however, these are merely examples. According to an embodiment, the display panel DP may include one upper data driver connected to the pads PD arranged in the upper portion and one lower data driver connected to the pads PD arranged in the lower portion. According to an embodiment, the pads PD may be arranged only in one side portion and may be connected to a single data driver, and the present disclosure should not be particularly limited.

[0146] In addition, as referenced Figure 3A As described, Figure 3B The scan driver and / or the data driver of the display panel DP may be disposed in the display area DA, and thus, some of the light emitting parts arranged in the display area DA may overlap with the scan driver and / or the data driver in a plan view.

[0147] FIG. 4A to FIG. 4D is a display panel DP according to an embodiment of the present disclosure (see Figure 1 ) are enlarged schematic plan views of some areas.

[0148] Figure 4A The light emitting units UT11, UT12, UT21 and UT22 are shown arranged in two rows by two columns. Figure 4A The light-emitting parts arranged in the first row Rk may include light-emitting parts constituting the light-emitting units UT11 arranged in the first row and the first column and the light-emitting units UT12 arranged in the first row and the second column, and the light-emitting parts arranged in the second row Rk+1 may include light-emitting parts constituting the light-emitting units UT21 arranged in the second row and the first column and the light-emitting units UT22 arranged in the second row and the second column.

[0149] Each of the light emitting portions EP1, EP2, and EP3 may correspond to a light emitting opening OP-PDL (refer to Figure 5). That is, each of the light emitting parts EP1, EP2, and EP3 may be a region from which the light emitting element emits light. The light emitting parts EP1, EP2, and EP3 may correspond to a region provided through the display panel DP (reference Figure 1 ) is a unit of an image displayed. In more detail, each of the light emitting parts EP1, EP2 and EP3 may correspond to an area defined by a light emitting opening OP-PDL described later (particularly, an area defined by a lower portion of the light emitting opening OP-PDL).

[0150] The light emitting parts EP1, EP2 and EP3 may include a first light emitting part EP1, a second light emitting part EP2 and a third light emitting part EP3. The first light emitting part EP1, the second light emitting part EP2 and the third light emitting part EP3 may emit light having different colors from each other. As an example, the first light emitting part EP1 may emit red light, the second light emitting part EP2 may emit green light, and the third light emitting part EP3 may emit blue light, however, the combination of the colors of the first light emitting part EP1, the second light emitting part EP2 and the third light emitting part EP3 should not be limited thereto or thereby. In addition, at least two of the light emitting parts EP1, EP2 and EP3 may emit light having the same color. For example, the first light emitting part EP1, the second light emitting part EP2 and the third light emitting part EP3 may all emit blue light or white light.

[0151] Among the first light emitting part EP1, the second light emitting part EP2, and the third light emitting part EP3, the third light emitting part EP3 displaying an image corresponding to the light emitted by the third light emitting element may include two sub-light emitting parts EP31 and EP32 spaced apart from each other in the second direction DR2, however, this is merely an example. According to an embodiment, the third light emitting part EP3 may be provided in a single pattern formed as a single body like the first light emitting part EP1 and the second light emitting part EP2, or at least one of the first light emitting part EP1 and the second light emitting part EP2 may include sub-light emitting parts spaced apart from each other, and the present disclosure should not be particularly limited.

[0152] The light-emitting parts arranged in the first row Rk may include the first light-emitting part EP1, the second light-emitting part EP2 and the third light-emitting part EP3 constituting the light-emitting unit UT11 arranged in the first row and the first column, and the first light-emitting part EP1, the second light-emitting part EP2 and the third light-emitting part EP3a constituting the light-emitting unit UT12 arranged in the first row and the second column, and the light-emitting parts arranged in the second row Rk+1 may include the first light-emitting part EP1, the second light-emitting part EP2 and the third light-emitting part EP3a constituting the light-emitting unit UT21 arranged in the second row and the first column, and the first light-emitting part EP1, the second light-emitting part EP2 and the third light-emitting part EP3 constituting the light-emitting unit UT22 arranged in the second row and the second column.

[0153] The light emitting parts constituting the light emitting units UT11 arranged in the first row and the first column may have substantially the same shape as the light emitting parts constituting the light emitting units UT22 arranged in the second row and the second column. In addition, the light emitting parts constituting the light emitting units UT12 arranged in the first row and the second column may have substantially the same shape as the light emitting parts constituting the light emitting units UT21 arranged in the second row and the first column. The light emitting parts constituting the light emitting units UT11 arranged in the first row and the first column may have a shape different from the shape of the light emitting parts constituting the light emitting units UT12 arranged in the first row and the second column. As an example, some of the light emitting parts arranged in the first row Rk may have a shape symmetrical with respect to the shape of some of the light emitting parts arranged in the second row Rk+1.

[0154] Relative to an axis approximately parallel to the first direction DR1, the third light emitting portion EP3a of the light emitting unit UT21 arranged in the second row and the first column and the third light emitting portion EP3 of the light emitting unit UT11 arranged in the first row and the first column may have a linearly symmetrical shape and arrangement, and relative to an axis approximately parallel to the first direction DR1, the third light emitting portion EP3 of the light emitting unit UT22 arranged in the second row and the second column and the third light emitting portion EP3a of the light emitting unit UT12 arranged in the first row and the second column may have a linearly symmetrical shape and arrangement, however, the present disclosure should not be limited to or thereby.

[0155] Figure 4B The light emitting parts arranged in a row are shown. For ease of explanation, Figure 4B The second electrodes EL2_1 , EL2_2 , and EL2_3 , the pixel driving units PDC1 , PDC2 , and PDC3 , the first, second, and third connection electrodes CNE1 , CNE2 , and CNE3 , and the groove GV are shown. Figure 4CThe groove GV, the light emitting parts EP1, EP2 and EP3 disposed in the area defined by the groove GV among the components of the display panel DP (see FIG. Figure 4B ), and connecting electrodes CNE1, CNE2 and CNE3.

[0156] refer to Figure 4B and Figure 4C , the second electrodes EL2_1, EL2_2 and EL2_3 may be separated from each other by the groove GV and may be electrically disconnected from each other. In an embodiment, the light emitting unit UT11 may include three light emitting portions EP1, EP2 and EP3. Therefore, the light emitting unit UT11 may include three second electrodes EL2_1, EL2_2 and EL2_3 (hereinafter referred to as the first cathode EL2_1, the second cathode EL2_2 and the third cathode EL2_3), three pixel driving units PDC1, PDC2 and PDC3, and three connection electrodes CNE1, CNE2 and CNE3, however, this is only an example. The number and arrangement of the light emitting portions included in the light emitting unit UT11 may be designed in various ways, and the present disclosure should not be particularly limited.

[0157] The first pixel driving unit PDC1, the second pixel driving unit PDC2, and the third pixel driving unit PDC3 may be electrically connected to the first light emitting element LD1, the second light emitting element LD2, and the third light emitting element LD3 including the first light emitting part EP1, the second light emitting part EP2, and the third light emitting part EP3, respectively. In the present disclosure, the expression that component A is connected to component B may mean not only the case where component A is directly and physically connected to component B, but also the case where component A is electrically connected to component B.

[0158] In addition, if Figure 4B As shown in FIG. 1 , each of the regions defining the first pixel driving unit PDC1, the second pixel driving unit PDC2, and the third pixel driving unit PDC3 in a plan view may correspond to a pixel driving unit PDC (refer to FIG. 1 ) including a light emitting element configured to drive a pixel. Figure 2A ) units of transistors and capacitors.

[0159] The first pixel driving unit PDC1, the second pixel driving unit PDC2 and the third pixel driving unit PDC3 may be sequentially arranged in the first direction DR1. The arrangement positions and shapes of the first pixel driving unit PDC1, the second pixel driving unit PDC2 and the third pixel driving unit PDC3 may be designed independently of the positions and shapes of the first light emitting part EP1, the second light emitting part EP2 and the third light emitting part EP3.

[0160] As an example, the first pixel driving unit PDC1, the second pixel driving unit PDC2, and the third pixel driving unit PDC3 may be placed at a position different from the area divided by the groove GV (i.e., the position where the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 are placed), or may be designed to have a shape and size different from the shape and size of the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3. According to an embodiment, the first pixel driving unit PDC1, the second pixel driving unit PDC2, and the third pixel driving unit PDC3 may be placed to overlap with the positions where the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3 are placed, respectively, and may be designed to have a shape and size similar to the shape and size of the area divided by the groove GV (i.e., the shape and size of the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3).

[0161] In an embodiment, each of the first pixel driving unit PDC1, the second pixel driving unit PDC2 and the third pixel driving unit PDC3 may have a rectangular shape, each of the first light-emitting portion EP1, the second light-emitting portion EP2 and the third light-emitting portion EP3 may have a size smaller than that of the first pixel driving unit PDC1, the second pixel driving unit PDC2 and the third pixel driving unit PDC3 and a shape different from that of the first pixel driving unit PDC1, the second pixel driving unit PDC2 and the third pixel driving unit PDC3, and the first cathode EL2_1, the second cathode EL2_2 and the third cathode EL2_3 may be placed at a position overlapping with the first light-emitting portion EP1, the second light-emitting portion EP2 and the third light-emitting portion EP3, and may have an atypical shape.

[0162] Accordingly, if Figure 4B As shown in , the first pixel driving unit PDC1 can be placed at a position overlapping with the first light-emitting part EP1, the second light-emitting part EP2 and a part of another light-emitting unit adjacent to the first light-emitting part EP1 and the second light-emitting part EP2. The second pixel driving unit PDC2 can be placed at a position overlapping with the first light-emitting part EP1, the second light-emitting part EP2 and the third cathode EL2_3. The third pixel driving unit PDC3 can be placed at a position overlapping with the third light-emitting part EP3, however, these are merely examples. According to an embodiment, the arrangement position and shape of the first pixel driving unit PDC1, the second pixel driving unit PDC2 and the third pixel driving unit PDC3 can be designed independently of the position and shape of the light-emitting parts EP1, EP2 and EP3, and should not be particularly limited.

[0163] The light emitting unit UT11 may include a first connection electrode CNE1, a second connection electrode CNE2, and a third connection electrode CNE3. The first connection electrode CNE1 may electrically connect the first light emitting element LD1 in which the first light emitting portion EP1 is formed (or in which the first light emitting portion EP1 is defined) to the first pixel driving unit PDC1, the second connection electrode CNE2 may electrically connect the second light emitting element LD2 in which the second light emitting portion EP2 is formed to the second pixel driving unit PDC2, and the third connection electrode CNE3 may electrically connect the third light emitting element LD3 in which the third light emitting portion EP3 is formed to the third pixel driving unit PDC3.

[0164] In detail, the first, second, and third connection electrodes CNE1, CNE2, and CNE3 may electrically connect the first, second, and third cathodes EL2_1, EL2_2, and EL2_3 with the first, second, and third pixel driving units PDC1, PDC2, and PDC3 in one-to-one correspondence.

[0165] Each of the first, second, and third connection electrodes CNE1, CNE2, and CNE3 may be disposed on a pixel defining layer PDL (refer to FIG. 1 ) described later. Figure 5 ). Each of the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 may have a ring shape surrounding a corresponding light emitting portion among the first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3. In the embodiment, as a representative example, each of the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 may have a closed loop shape, however, the embodiment should not be limited thereto or thereby. As an example, at least one of the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 may have an open loop shape in which a portion thereof is cut.

[0166] Since the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 have a ring shape, the degree of freedom of connection positions of the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 to the first pixel driving unit PDC1, the second pixel driving unit PDC2, and the third pixel driving unit PDC3 can be improved. As an example, the first connection electrode CNE1 can be connected to the first pixel driving unit PDC1 via the first connection portion CE1, the second connection electrode CNE2 can be connected to the second pixel driving unit PDC2 via the second connection portion CE2, and the third connection electrode CNE3 can be connected to the third pixel driving unit PDC3 via the connection line CN3. That is, the connection line that is additionally connected to the first connection electrode CNE1 and the second connection electrode CNE2 can be omitted.

[0167] The connection line CN3 may electrically connect the third pixel driving unit PDC3 to the third light emitting element LD3 of the third light emitting part EP3. In detail, the connection line CN3 may correspond to the light emitting element LD (refer to Figure 2A )Connect to Figure 2A Pixel drive unit PDC, Figure 2B Pixel driver unit PDC-1 or Figure 2C The node where the pixel driving unit PDC-2 is located (reference Figure 2A The fourth node N4, Figure 2B The second node N2 or Figure 2C The fourth node N4).

[0168] The connection line CN3 may include a third connection portion CE3 and a driving connection portion CD3. The third connection portion CE3 may be provided at one end of the connection line CN3, and the driving connection portion CD3 may be provided at the other end of the connection line CN3.

[0169] The driving connection portion CD3 may be a portion of the connection line CN3 connected to the pixel driving unit PDC3. In an embodiment, the driving connection portion CD3 may be connected to an electrode of a transistor of the pixel driving unit PDC3. In detail, the driving connection portion CD3 may be connected to Figure 2A The drain of the sixth transistor T6 shown in Figure 2B The drain of the first transistor T1 shown in Figure 2C , and the drain of the fourth transistor T4a shown in . Therefore, the position of the driving connection part CD3 may correspond to the position of the transistor of the pixel driving unit that is physically connected to the connection line CN3. The third connection part CE3 may be a portion of the connection line CN3 connected to the third light emitting element LD3. In an embodiment, the third connection part CE3 may be connected to the third connection electrode CNE3.

[0170] The first connection electrode CNE1 may include a first edge EG11 surrounding at least a portion of the first light emitting portion EP1 and a second edge EG12 surrounding the first edge EG11. The second connection electrode CNE2 may include a first edge EG21 surrounding at least a portion of the second light emitting portion EP2 and a second edge EG22 surrounding the first edge EG21. The third connection electrode CNE3 may include a first edge EG31 surrounding at least a portion of the third light emitting portion EP3 and a second edge EG32 surrounding the first edge EG31.

[0171] The first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 may be arranged to be spaced apart from each other. As an example, the gaps GP1, GP2, and GP3 between the connection electrodes adjacent to each other among the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 may overlap with the groove GV. As an example, the first edge EG11 of the first connection electrode CNE1, the first edge EG21 of the second connection electrode CNE2, and the first edge EG31 of the third connection electrode CNE3 may not overlap with the groove GV, and the second edge EG12 of the first connection electrode CNE1, the second edge EG22 of the second connection electrode CNE2, and the second edge EG32 of the third connection electrode CNE3 may overlap with the groove GV.

[0172] The first connection portion CE1, the second connection portion CE2, and the third connection portion CE3 may be disposed at positions that do not overlap with the first light emitting portion EP1, the second light emitting portion EP2, and the third light emitting portion EP3 in a plan view. As an example, a light emitting opening OP-PDL (refer to Figure 5 ) and a through hole OP-P (reference Figure 5 ).

[0173] The through hole OP-P may include a first through hole OP-P1, a second through hole OP-P2, and a third through hole OP-P3. The first connection portion CE1, the second connection portion CE2, and the third connection portion CE3 may be arranged corresponding to the first through hole OP-P1, the second through hole OP-P2, and the third through hole OP-P3, respectively. The light-emitting opening OP-PDL may include a first light-emitting opening OP-PDL1, a second light-emitting opening OP-PDL2, and a third light-emitting opening OP-PDL3. The first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3 may be defined to correspond to the first light-emitting opening OP-PDL1, the second light-emitting opening OP-PDL2, and the third light-emitting opening OP-PDL3, respectively. Therefore, the first connection portion CE1, the second connection portion CE2, and the third connection portion CE3 may be arranged at a position spaced apart from the first light-emitting portion EP1, the second light-emitting portion EP2, and the third light-emitting portion EP3.

[0174] The first link electrode CNE1, the second link electrode CNE2, and the third link electrode CNE3 may be disposed on the pixel defining layer PDL (refer to Figure 5 In a plan view, the first connection electrode CNE1 may surround the first light emitting opening OP-PDL1, the second connection electrode CNE2 may surround the second light emitting opening OP-PDL2, and the third connection electrode CNE3 may surround the third light emitting opening OP-PDL3.

[0175] The transistor TR (refer to FIG. 1 ) of the third pixel driving unit PDC3 as the connection line CN3 Figure 5 ) The driving connection portion CD3 of the portion connected to the connection line CN3 may be defined at a position not overlapping with the third connection portion CE3 in a plan view, and may be disposed at a position overlapping with the third light emitting portion EP3. Since the third cathode EL2_3 is connected to the third pixel driving unit PDC3 via the connection line CN3, restrictions on the design of the third pixel driving unit PDC3 due to the position or shape of the third light emitting portion EP3 may be reduced, and the degree of freedom of circuit design may be improved.

[0176] The first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 may be connected to the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3. As an example, the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 may be connected to the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3, respectively, in an area adjacent to the groove GV.

[0177] In addition, the connection area in which the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 are connected to the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 may surround at least a portion of the first light emitting opening OP-PDL1, the second light emitting opening OP-PDL2, and the third light emitting opening OP-PDL3, respectively. The first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 may be connected to the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 in an area adjacent to the groove GV, and each of the connection areas may be defined to be adjacent to the groove GV. That is, the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 may not be connected to the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 at a specific point, but may be connected to the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 in a relatively large (relatively wide) area (for example, in an area having a shape similar to that of each of the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3). That is, the size of the connection area may be increased, and thus, the connection between the first cathode EL2_1, the second cathode EL2_2, and the third cathode EL2_3 and the first connection electrode CNE1, the second connection electrode CNE2, and the third connection electrode CNE3 may be stable.

[0178] Figure 4D The groove GV, the light emitting parts EP1, EP2 and EP3, and the first electrode EL1 are shown.

[0179] refer to Figure 4D , also refer to Figure 3A , light emitting element LD (reference Figure 5 ) may be commonly disposed in the light emitting parts EP1, EP2, and EP3. That is, the anode EL1 may have a single main layer throughout the display area DA, and thus, the anode EL1 may overlap the groove GV. According to an embodiment, the anodes EL1 of the light emitting elements LD may be formed as conductive patterns independent of each other and may be electrically connected to each other via other conductive layers, and thus, the anode EL1 may be disposed not to overlap the groove GV.

[0180] As described above, the first power voltage VDD (reference Figure 2A ) is applied to the anode EL1, and a common voltage may be applied to all light emitting parts. The anode EL1 may be connected to a first power line VDL (reference line VDL) providing a first power voltage VDD in the peripheral area NDA. Figure 2A) or may be connected to the first power line VDL (reference Figure 2A ), and the embodiments should not be limited thereto or thereby.

[0181] An opening may be defined by the anode EL1, and the opening may penetrate the anode EL1. The opening defined by the anode EL1 may be defined not to overlap with the light emitting portion EP (refer to Figure 3A ) and may be defined as substantially overlapping the groove GV. The opening may facilitate discharge of an organic layer (eg, the sixth insulating layer 60 (refer to Figure 5 Therefore, since the gas from the organic layer disposed under the light emitting element LD is sufficiently exhausted in the manufacturing process of the display panel DP, the gas generated from the organic layer after the manufacturing process is completed can be reduced, and thus, the degradation rate of the light emitting element LD can be reduced.

[0182] Figure 5 is a schematic cross-sectional view of a display panel DP according to an embodiment of the present disclosure. Figure 5 Shown along Figure 4C A cross-sectional view taken along line II'.

[0183] refer to Figure 5 , also refer to Figure 3A and Figure 4C The display panel DP may include a base layer BS, a driving element layer DDL, a light emitting element layer LDL, an encapsulation layer ECL, and a sensing layer ISL, however, this is only an example. According to an embodiment, the display panel DP may not include the sensing layer ISL.

[0184] The driving element layer DDL may include insulating layers 10, 20, 30, 40, 50, and 60 disposed on the base layer BS and conductive patterns and semiconductor patterns disposed between the insulating layers 10, 20, 30, 40, 50, and 60. The conductive patterns and semiconductor patterns disposed between the insulating layers 10, 20, 30, 40, 50, and 60 may form a pixel driving unit PDC. For convenience of explanation, Figure 5 A cross section of a portion of a region in which one light emitting portion is provided is shown.

[0185] The base layer BS may provide a base surface on which the pixel driving unit PDC is disposed. The base layer BS may be a rigid substrate or a flexible substrate that is bendable, foldable or rollable. The base layer BS may be a glass substrate, a metal substrate or a polymer substrate, however, the embodiment should not be limited thereto or thereby. According to an embodiment, the base layer BS may be an inorganic layer, an organic layer or a composite material layer.

[0186] The base layer BS may have a multi-layer structure. The base layer BS may include a first polymer resin layer, a silicon oxide (SiO x ) layer, an amorphous silicon (a-Si) layer disposed on the silicon oxide layer, and a second polymer resin layer disposed on the amorphous silicon (a-Si) layer. x ) layer and the amorphous silicon (a-Si) layer can be referred to as a substrate barrier layer.

[0187] Each of the first polymer resin layer and the second polymer resin layer may include a polyimide resin. In addition, each of the first polymer resin layer and the second polymer resin layer may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a perylene resin. In the present disclosure, as used herein, the term "X-type resin" refers to a resin containing an X functional group.

[0188] The insulating layer, the conductive layer, and the semiconductor layer disposed on the base layer BS may be formed by coating and deposition processes. The insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by several photolithography processes, and thus, a hole may be defined through the insulating layer, or a semiconductor pattern, a conductive pattern, and a signal line may be formed.

[0189] The driving element layer DDL may include first, second, third, fourth, fifth, and sixth insulating layers 10, 20, 30, 40, 50, and 60, which are sequentially stacked on the base layer BS, and a pixel driving unit PDC. Figure 5 One transistor TR and two capacitors C1 and C2 of the pixel driving unit PDC are shown.

[0190] The transistor TR may correspond to a transistor connected to the light emitting element LD via the intermediate connection electrode CN and the connection electrode CNE, that is, connected to a node ( 100 ) corresponding to the cathode of the light emitting element LD. Figure 2A The fourth node N4, Figure 2B The second node N2 or Figure 2C In detail, the transistor TR may correspond to Figure 2A The sixth transistor T6, Figure 2B The first transistor T1 or Figure 2C Although not shown in the figure, other transistors constituting the pixel driving unit PDC may have the same Figure 5The structure of the transistor TR shown in FIG. 1 (hereinafter, referred to as the connecting transistor TR) is substantially the same as that of FIG. 1 , however, this is merely an example. According to an embodiment, other transistors constituting the pixel driving unit PDC may have a structure different from that of the connecting transistor TR and should not be particularly limited.

[0191] The first insulating layer 10 may be disposed on the base layer BS. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the first insulating layer 10 may have a single-layer structure of a silicon oxide layer. The insulating layer described later may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The inorganic layer may include at least one of the above materials, however, the embodiment should not be limited thereto or thereby.

[0192] The first insulating layer 10 may cover the lower conductive layer BCL. That is, the display panel DP may further include a lower conductive layer BCL overlapping the connection transistor TR. The lower conductive layer BCL may prevent the potential caused by the polarization phenomenon of the base layer BS from exerting an influence on the connection transistor TR. In addition, the lower conductive layer BCL may block light incident into the connection transistor TR from the lower side of the lower conductive layer BCL. At least one of an inorganic barrier layer and a buffer layer may be further disposed between the lower conductive layer BCL and the base layer BS.

[0193] The lower conductive layer BCL may include a reflective metal material and a metal nitride. As an example, the lower conductive layer BCL may include titanium (Ti), molybdenum (Mo), an alloy including molybdenum (Mo), aluminum (Al), an alloy including aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), and copper (Cu).

[0194] In an embodiment, the lower conductive layer BCL may be connected to the source of the connection transistor (or transistor) TR via the source electrode pattern W1. The lower conductive layer BCL may be synchronized with the source of the transistor TR, however, this is merely an example. According to an embodiment, the lower conductive layer BCL may be connected to the gate of the transistor TR and synchronized with the gate of the transistor TR. According to an embodiment, the lower conductive layer BCL may be connected to another electrode to independently receive a constant voltage or a pulse signal. According to an embodiment, the lower conductive layer BCL may be provided in an isolated form isolated from other conductive patterns. The lower conductive layer BCL may be provided in various forms and should not be particularly limited.

[0195] The connection transistor TR may be disposed on the first insulating layer 10. The connection transistor TR may include a semiconductor pattern SP and a gate electrode GE. The semiconductor pattern SP may be disposed on the first insulating layer 10. The semiconductor pattern SP may include an oxide semiconductor. As an example, the oxide semiconductor may include a transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ), etc., however, the material used for the semiconductor pattern SP should not be limited thereto or thereby. As an example, the semiconductor pattern SP may include amorphous silicon or polycrystalline silicon (such as low temperature polycrystalline silicon).

[0196] The semiconductor pattern SP may include a source region SR, a drain region DR, and a channel region CR that are distinguished from each other according to the degree of conductivity. The channel region CR may overlap with the gate electrode GE in a plan view. The source region SR and the drain region DR may be spaced apart from each other, and the channel region CR is interposed between the source region SR and the drain region DR. In the case where the semiconductor pattern SP is an oxide semiconductor, each of the source region SR and the drain region DR may be a reduction region. Therefore, compared with the channel region CR, the source region SR and the drain region DR may have a relatively high content of reduction metal. According to an embodiment, in the case where the semiconductor pattern SP is polysilicon, each of the source region SR and the drain region DR may be a highly doped region.

[0197] The source region SR and the drain region DR may have relatively high conductivity compared to the channel region CR. The source region SR may correspond to a source electrode of the connection transistor TR, and the drain region DR may correspond to a drain electrode of the connection transistor TR. Figure 5 As shown in FIG, the connection transistor TR may further include a source electrode pattern W1 and a drain electrode pattern W2 separated from each other and connected to the source region SR and the drain region DR, respectively. In detail, each of the source electrode pattern W1 and the drain electrode pattern W2 may be connected to a pixel driving unit PDC (refer to FIG. Figure 2A ), pixel driver unit PDC-1 (reference Figure 2B ) and pixel driver unit PDC-2 (reference Figure 2C ) are formed integrally with the wires, however, the embodiments should not be limited to or thereby.

[0198] The second insulating layer 20 may overlap with the pixel in common and may cover the semiconductor pattern SP. The second insulating layer 20 may be an inorganic layer and / or an organic layer and may have a single-layer structure or a multi-layer structure. The second insulating layer 20 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, the second insulating layer 20 may have a single-layer structure of a silicon oxide layer.

[0199] The gate electrode GE may be disposed on the second insulating layer 20. The gate electrode GE may correspond to the gate of the connection transistor TR. In addition, the gate electrode GE may be disposed on the semiconductor pattern SP, however, this is only an example. According to an embodiment, the gate electrode GE may be disposed under the semiconductor pattern SP, and the embodiment should not be particularly limited.

[0200] The gate electrode GE may include titanium (Ti), silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu) or alloys thereof, aluminum nitride (AlN), and tungsten nitride (WN), however, embodiments should not be particularly limited.

[0201] The third insulating layer 30 may be disposed on the gate electrode GE. The third insulating layer 30 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure.

[0202] Among the conductive patterns W1, W2, CPE1, CPE2, and CPE3, the first capacitor electrode CPE1 and the second capacitor electrode CPE2 may form a first capacitor C1. The first capacitor electrode CPE1 and the second capacitor electrode CPE2 may be spaced apart from each other with the first insulating layer 10 and the second insulating layer 20 interposed therebetween.

[0203] According to an embodiment, the first capacitor electrode CPE1 and the lower conductive layer BCL may be provided integrally with each other. In addition, the second capacitor electrode CPE2 may be provided integrally with the gate electrode GE.

[0204] The third capacitor electrode CPE3 may be disposed on the third insulating layer 30. The third capacitor electrode CPE3 may be spaced apart from the second capacitor electrode CPE2, with the third insulating layer 30 interposed between the third capacitor electrode CPE3 and the second capacitor electrode CPE2, and the third capacitor electrode CPE3 may overlap with the second capacitor electrode CPE2 in a plan view. The third capacitor electrode CPE3 and the second capacitor electrode CPE2 may form a second capacitor C2.

[0205] The fourth insulating layer 40 may be disposed on the third insulating layer 30 and / or the third capacitor electrode CPE3. The fourth insulating layer 40 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multi-layer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0206] The source electrode pattern W1 and the drain electrode pattern W2 may be disposed on the fourth insulating layer 40. The source electrode pattern W1 may be connected to the source region SR of the connection transistor TR via the first contact hole CNT1, and the source electrode pattern W1 and the source region SR of the semiconductor pattern SP may serve as the source of the connection transistor TR. The drain electrode pattern W2 may be connected to the drain region DR of the connection transistor TR via the second contact hole CNT2, and the drain electrode pattern W2 and the drain region DR of the semiconductor pattern SP may serve as the drain of the connection transistor TR. The fifth insulating layer 50 may be disposed on the source electrode pattern W1 and the drain electrode pattern W2.

[0207] The intermediate connection electrode CN may be disposed on the fifth insulating layer 50. The intermediate connection electrode CN may electrically connect the pixel driving unit PDC to the light emitting element LD. That is, the intermediate connection electrode CN may electrically connect the connection transistor TR to the light emitting element LD. The intermediate connection electrode CN may be a connection node connecting the pixel driving unit PDC to the light emitting element LD. That is, the intermediate connection electrode CN may correspond to Figure 2A The fourth node N4 shown in FIG. 1 may correspond to Figure 2B The second node N2 shown in Figure 2C The fourth node N4 is shown in .

[0208] The intermediate connection electrode CN may include a first layer L1, a second layer L2, and a third layer L3 sequentially stacked in the third direction DR3. The second layer L2 may include a material different from that of the first layer L1. The second layer L2 may include a material different from that of the third layer L3. The second layer L2 may have a thickness relatively thicker than that of the first layer L1. The second layer L2 may have a thickness relatively thicker than that of the third layer L3. The second layer L2 may include a material having high conductivity. As an example, the second layer L2 may include aluminum (Al).

[0209] The sixth insulating layer 60 may be disposed on the intermediate connection electrode CN. The sixth insulating layer 60 may be disposed on the fifth insulating layer 50 and may cover at least a portion of the intermediate connection electrode CN. Each of the fifth insulating layer 50 and the sixth insulating layer 60 may be an organic layer. As an example, each of the fifth insulating layer 50 and the sixth insulating layer 60 may include a general polymer such as polystyrene (PS), benzocyclobutene (BCB), hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer (such as polyimide), an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, or a blend thereof.

[0210] The sixth insulating layer 60 may be provided with a through hole OP-60 defined in the sixth insulating layer 60 to expose at least a portion of the intermediate connection electrode CN. The intermediate connection electrode CN may be connected to the connection electrode CNE via a portion exposed by the sixth insulating layer 60 and not covered by the sixth insulating layer 60, and thus may be electrically connected to the light emitting element LD. That is, the intermediate connection electrode CN and the connection electrode CNE may electrically connect the connection transistor TR to the light emitting element LD. According to an embodiment, the sixth insulating layer 60 may be omitted, or a plurality of sixth insulating layers 60 may be provided in the display panel DP, however, the embodiment should not be particularly limited. In the case where the sixth insulating layer 60 is omitted, the intermediate connection electrode CN may also be omitted.

[0211] According to the embodiment, since the lower surface of the connection electrode CNE contacts the upper surface of the middle connection electrode CN, the contact reliability can be improved. Therefore, the size of the through holes OP-P and OP-60 required to connect the connection electrode CNE and the middle connection electrode CN can be reduced. Therefore, the size and resolution of the light emitting portion of the display panel DP can be easily increased.

[0212] The light emitting element layer LDL may be disposed on the driving element layer DDL. The light emitting element layer LDL may include a pixel defining layer PDL and a light emitting element LD.

[0213] The pixel defining layer PDL may be an organic layer. As an example, the pixel defining layer PDL may include a general polymer such as polystyrene (PS), benzocyclobutene (BCB), hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer (such as polyimide), an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, or a blend thereof.

[0214] The pixel defining layer PDL may have light absorption characteristics. For example, the pixel defining layer PDL may have a black color. That is, the pixel defining layer PDL may include a black colorant. The black colorant may include a black dye or a black pigment. The black colorant may include carbon black, a metal material (such as chromium) or an oxide thereof. The pixel defining layer PDL may correspond to a light blocking pattern having a light blocking characteristic.

[0215] The pixel defining layer PDL may be provided with an opening OP-PDL (hereinafter, referred to as a light emitting opening OP-PDL) defined in the pixel defining layer PDL to expose at least a portion of the first electrode EL1. A plurality of light emitting openings OP-PDL may be provided, and the light emitting openings OP-PDL may correspond to the light emitting elements LD, respectively. All components of the light emitting element LD may overlap with each other in the light emitting openings OP-PDL, and the light emitting openings OP-PDL may correspond to an area where light emitted from the light emitting element LD is substantially displayed. Therefore, the first light emitting portion EP1 (refer to Figure 4A ) may substantially correspond to the shape of the light emitting opening OP-PDL in a plan view.

[0216] The connection electrode CNE may be disposed on the pixel definition layer PDL. The connection electrode CNE may electrically connect the pixel driving unit PDC to the light emitting element LD. That is, the pixel driving unit PDC may be electrically connected to the light emitting element LD through the intermediate connection electrode CN and the connection electrode CNE. The connection electrode CNE may correspond to Figure 4A The first connection electrode CNE1 shown in FIG. Figure 4A ) and the third connection electrode CNE3 (reference Figure 4A ) can have a structure similar to that of the connection electrode CNE.

[0217] The connection electrode CNE may include a first edge EG1c adjacent to the light emitting opening OP-PDL and a second edge EG2c surrounding the first edge EG1c. The second electrode EL2 of the light emitting element LD may contact the connection electrode CNE in a region adjacent to the second edge EG2c. That is, the second electrode EL2 and the connection electrode CNE may be connected to each other in a region adjacent to the groove GV.

[0218] The connection electrode CNE may include a transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ) etc., however, the material used for the connection electrode CNE should not be limited thereto or thereby.

[0219] The connection electrode CNE may have a first light emitting portion EP1 (refer to Figure 4A ) is formed. Therefore, the degree of freedom in designing the position where the connection electrode CNE is connected to the light emitting element LD and the degree of freedom in designing the position where the connection electrode CNE is connected to the pixel driving unit PDC can be improved.

[0220] In addition, since the lower surface of the connection electrode CNE contacts the upper surface of the intermediate connection electrode CN, the contact reliability can be improved. Therefore, the size of the through holes OP-P and OP-60 required to connect the connection electrode CNE with the intermediate connection electrode CN can be reduced. Therefore, the size and resolution of the light emitting portion of the display panel DP can be easily increased.

[0221] The groove GV may be defined in the pixel defining layer PDL to surround the light emitting opening OP-PDL. The groove GV may be formed by removing a portion of the pixel defining layer PDL in a thickness direction (e.g., a third direction DR3) of the pixel defining layer PDL. The groove GV may overlap a gap between two connection electrodes CNE adjacent to each other and disposed on the pixel defining layer PDL.

[0222] A portion of the connection electrode CNE may protrude from the end of the groove GV toward the center of the groove GV. The portion of the connection electrode CNE may be defined as a tip portion TP. That is, the connection electrode CNE may include a tip portion TP. Since the tip portion TP protrudes toward the groove GV, the connection electrode CNE may partially overlap with the groove GV in a plan view. The second electrode EL2 of the light emitting element LD and the connection electrode CNE may be connected to each other at the tip portion TP or may contact each other at the tip portion TP.

[0223] According to an embodiment, the second electrode EL2 and the functional layer FNL may be deposited and formed in common throughout the pixels using an open mask. A portion of the functional layer FNL may include an organic layer. In the case of forming the organic layer in common, a lateral leakage current may occur due to the organic layer provided in common throughout the pixels adjacent to each other, and as a result, color mixing and brightness defects may occur between the pixels adjacent to each other. In the present disclosure, the expression "lateral leakage current" indicates a current flowing in a direction intersecting with a third direction DR3 (i.e., a direction in which an image is displayed) corresponding to the stacking direction of the light emitting element LD, rather than a current flowing in the third direction DR3. The lateral leakage current may indicate a current flowing in a direction substantially parallel to a plane defined by the first direction DR1 and the second direction DR2.

[0224] According to the present disclosure, each of the intermediate layer IML and the second electrode EL2 can be divided into a plurality of parts by the tip portion TP of the connection electrode CNE, and the plurality of parts can be respectively arranged in a plurality of pixels to prevent lateral leakage current from occurring between pixels adjacent to each other. Therefore, the occurrence of lateral leakage current can be prevented, and the occurrence of color mixing between pixels adjacent to each other and the degradation of brightness can be prevented. The tip portion TP of the connection electrode CNE can have a closed line shape relative to each of the plurality of light-emitting parts, and therefore, each of the second electrode EL2 and the functional layer FNL can be divided into a plurality of parts corresponding to the plurality of light-emitting parts, respectively. That is, each of the second electrode EL2 and the intermediate layer IML can be electrically independent between pixels adjacent to each other.

[0225] The tip portion TP may have a reverse tapered shape. That is, the tapered angle between the lower surface of the connection electrode CNE and the side surface of the connection electrode CNE may be an obtuse angle, however, this is merely an example. The tapered angle may be set in various ways as long as the second electrode EL2 is electrically disconnected in each pixel by the tip portion TP of the connection electrode CNE. As an example, in the connection electrode CNEa (reference Figure 7 ) only includes the first connection electrode layer LL1 (reference Figure 7 ), the tapered angle between the lower surface of the connection electrode CNEa and the side surface of the connection electrode CNEa may be an acute angle or a right angle.

[0226] The dummy pattern DMP may be disposed in the groove GV. The tip portion TP of the connection electrode CNE may be connected to a portion of the connection electrode CNE (eg, the second connection electrode layer LL2 (reference Fig. 6A )), the second electrode EL2 and the functional layer FNL are separated to form a dummy pattern DMP, however, this is only an example. FIG. 6A to FIG. 9 This is described in detail.

[0227] The through hole OP-P may be defined through the pixel defining layer PDL and may be spaced apart from the light emitting opening OP-PDL. A plurality of through holes OP-P may be provided, and the through holes OP-P may be respectively arranged corresponding to the light emitting elements LD. The through hole OP-P defined through the pixel defining layer PDL may have a size greater than that of the through hole OP-60 defined through the sixth insulating layer 60. The connection electrode CNE may be arranged in the through hole OP-P and the through hole OP-60 and may be connected to the intermediate connection electrode CN. That is, the connection electrode CNE may be connected to the pixel driving unit PDC via the through hole OP-P and the through hole OP-60.

[0228] The light emitting element LD may include a first electrode EL1 , an intermediate layer IML, and a second electrode EL2 .

[0229] The first electrode EL1 may be a semi-transmissive electrode, a transmissive electrode, or a reflective electrode. According to an embodiment, the first electrode EL1 may include a reflective layer formed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include a material selected from indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ) and aluminum-doped zinc oxide (AZO). For example, the first electrode EL1 may have a stack structure of ITO / Ag / ITO.

[0230] In an embodiment, the first electrode EL1 may be an anode of the light emitting element LD. That is, the first electrode EL1 may be connected to the first power line VDL (reference Figure 2A ), and can receive a first power voltage VDD (reference Figure 2A The first electrode EL1 may be located in the display area DA (refer to Figure 3A or Figure 3B ) is connected to the first power line VDL, or may be connected to the first power line VDL in the peripheral area NDA. In the case where the first electrode EL1 is connected to the first power line VDL in the peripheral area NDA, the first power line VDL may be provided in the peripheral area NDA (reference Figure 3A or Figure 3B ), and the first electrode EL1 may extend to the peripheral area NDA.

[0231] exist Figure 5 In the cross-sectional view of FIG. 1 , the first electrode EL1 overlaps with the light emitting opening OP-PDL and does not overlap with the groove GV, however, the embodiment should not be limited thereto or thereby. Figure 4D As described above, the first electrodes EL1 of the light emitting elements LD may be provided integrally with each other and may have a mesh shape or a lattice shape in which openings are defined in some regions. That is, the first electrode EL1 may have a variety of shapes as long as the light emitting elements LD receive the same first power voltage VDD through their first electrodes EL1, however, the embodiment should not be limited thereto or thereby.

[0232] The intermediate layer IML may be disposed between the first electrode EL1 and the second electrode EL2. The intermediate layer IML may include a light emitting layer EML and a functional layer FNL having a size greater than that of the light emitting layer EML. The light emitting element LD may include the intermediate layer IML having various structures and should not be particularly limited. As an example, the functional layer FNL may include a plurality of layers, or may include two or more layers spaced apart from each other, with the light emitting layer EML interposed between the two or more layers.

[0233] The light emitting layer EML may include an organic light emitting material. According to an embodiment, the light emitting layer EML may include an inorganic light emitting material or may include a layer obtained by mixing an organic light emitting material with an inorganic light emitting material. In an embodiment, the light emitting layers EML respectively included in the light emitting portions EP adjacent to each other may include light emitting materials showing different colors from each other. As an example, the light emitting layer EML included in each light emitting portion EP may emit light having at least one color of blue, red, and green, however, the embodiment should not be limited thereto or thereby. According to an embodiment, the light emitting layer EML commonly provided in the light emitting portion EP may include a light emitting material showing the same color. The light emitting layer EML may provide blue light or white light.

[0234] The functional layer FNL may be disposed between the first electrode EL1 and the second electrode EL2. In detail, the functional layer FNL may include a first intermediate functional layer disposed between the first electrode EL1 and the light-emitting layer EML and a second intermediate functional layer disposed between the second electrode EL2 and the light-emitting layer EML. According to an embodiment, the first intermediate functional layer or the second intermediate functional layer may be omitted. In an embodiment, the light-emitting layer EML may be inserted into the functional layer FNL. That is, the light-emitting layer EML may be disposed between the first intermediate functional layer and the second intermediate functional layer.

[0235] The functional layer FNL may control the movement of charges between the first electrode EL1 and the second electrode EL2. As an example, the first intermediate functional layer may include a hole injection / transport material and / or an electron injection / transport material. The second intermediate functional layer may include at least one of an electron blocking layer, a hole transport layer, a hole injection layer, a hole blocking layer, an electron transport layer, an electron injection layer, and a charge generation layer.

[0236] The second electrode EL2 may be disposed on the intermediate layer IML. As described above, the second electrode EL2 may be electrically connected to the pixel driving unit PDC via the connection electrode CNE. In an embodiment, the second electrode EL2 may be electrically connected to the connection transistor TR via the connection electrode CNE.

[0237] The encapsulation layer ECL may be disposed on the light emitting element layer LDL. The encapsulation layer ECL may cover the light emitting element LD and the groove GV. The encapsulation layer ECL may include a first inorganic layer IL1, an organic layer OL, and a second inorganic layer IL2 that are sequentially stacked.

[0238] However, the present disclosure should not be limited to this or thereby. According to an embodiment, the encapsulation layer ECL may also include a plurality of inorganic layers and a plurality of organic layers. As an example, the encapsulation layer ECL may include a first encapsulation layer instead of the first inorganic layer. The first encapsulation layer may include a sub-encapsulation layer. At least one of the sub-encapsulation layers may include an organic material. As an example, the first encapsulation layer may include a first sub-encapsulation layer, a second sub-encapsulation layer, and a third sub-encapsulation layer, the first sub-encapsulation layer and the third sub-encapsulation layer may include an inorganic material, and the second sub-encapsulation layer may include an organic material. Even if a gap is formed in the first sub-encapsulation layer as an inorganic material layer, the gap may be filled by the second sub-encapsulation layer. The first encapsulation layer may smoothly cover the groove GV defined in the pixel defining layer PDL and the tip portion TP of the connecting electrode CNE. Therefore, the protective function of the encapsulation layer ECL protecting the light-emitting element LD may be improved. However, the present disclosure should not be limited to this or thereby, and the encapsulation layer ECL may be a glass substrate.

[0239] The first inorganic layer IL1 and the second inorganic layer IL2 may protect the light emitting element LD from moisture and oxygen outside the display panel DP, and the organic layer OL may protect the light emitting element LD from foreign matter such as dust particles remaining in the process of forming the first inorganic layer IL1. The first inorganic layer IL1 and the second inorganic layer IL2 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic layer OL may include an acrylic organic layer, however, the embodiment should not be particularly limited.

[0240] The sensing layer ISL may sense external input. The sensing layer ISL may be formed on the encapsulation layer ECL through a continuous process. The sensing layer ISL may be directly disposed on the encapsulation layer ECL. In the present disclosure, the expression "the sensing layer ISL is directly disposed on the encapsulation layer ECL" means that there is no intermediate element between the sensing layer ISL and the encapsulation layer ECL. That is, no separate bonding member may be disposed between the sensing layer ISL and the encapsulation layer ECL, however, this is merely an example. According to an embodiment, the sensing layer ISL may be provided after being formed separately, and may be coupled to the display panel DP through a bonding member, and the embodiment should not be limited thereto or thereby.

[0241] The sensing layer ISL may include a conductive layer and an insulating layer. The conductive layer may include a first sensing conductive layer MTL1 and a second sensing conductive layer MTL2, and the insulating layer may include a first sensing insulating layer 71, a second sensing insulating layer 72, and a third sensing insulating layer 73. However, this is merely an example, and the number of insulating layers should not be particularly limited.

[0242] Each of the first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 may have a single layer structure or a multilayer structure of a plurality of layers stacked in the third direction DR3. The first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 may include an inorganic layer. The inorganic layer may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The first sensing insulating layer 71, the second sensing insulating layer 72, and the third sensing insulating layer 73 may include an organic layer. The organic layer may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

[0243] The first sensing conductive layer MTL1 may be disposed between the first sensing insulating layer 71 and the second sensing insulating layer 72, and the second sensing conductive layer MTL2 may be disposed between the second sensing insulating layer 72 and the third sensing insulating layer 73. A portion of the second sensing conductive layer MTL2 may be connected to the first sensing conductive layer MTL1 via a contact hole CNT formed through the second sensing insulating layer 72. Each of the first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may have a single-layer structure or a multi-layer structure in which a plurality of layers are stacked in the third direction DR3.

[0244] The sensing conductive layer having a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or indium zinc tin oxide (IZTO). In addition, the transparent conductive layer may include a conductive polymer (such as poly (3,4-ethylenedioxythiophene) (PEDOT)), a metal nanowire or graphene, etc.

[0245] The sensing conductive layer having a multi-layer structure may include a metal layer. The metal layer may have a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti). The sensing conductive layer having a multi-layer structure may include at least one metal layer and at least one transparent conductive layer.

[0246] The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may form a sensor to sense an external input in the sensing layer ISL. The sensor may be driven by a capacitive method (e.g., a mutual capacitance method or a self-capacitive method), however, this is merely an example. According to an embodiment, the sensor may be driven by a resistive film method, an ultrasonic method, or an infrared method instead of a capacitive method, and the embodiment should not be particularly limited.

[0247] Each of the first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may include a transparent conductive oxide, or may have a metal mesh shape formed of an opaque conductive material. The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may include various materials and various shapes as long as the visibility of the image displayed by the display panel DP is not deteriorated.

[0248] Fig. 6A is a display panel DP according to an embodiment of the present disclosure (refer to Figure 5 ) is an enlarged schematic cross-sectional view of a region. Fig. 6A yes Figure 5 An enlarged cross-sectional view of area AA'.

[0249] refer to Figure 5 and Fig. 6A , the connection electrode CNE may include a first connection electrode layer LL1 disposed on the pixel defining layer PDL and a second connection electrode layer LL2 disposed on the first connection electrode layer LL1. The second connection electrode layer LL2 may cover the first connection electrode layer LL1. As an example, the second connection electrode layer LL2 may cover the upper surface and the side surface S_LL1 of the first connection electrode layer LL1. Therefore, the side surface S_LL1 of the first connection electrode layer LL1 may not be exposed to the outside. The end of the first connection electrode layer LL1 and the end of the second connection electrode layer LL2 covering the end of the first connection electrode layer LL1 may form a tip portion TP of the connection electrode CNE.

[0250] The second connection electrode layer LL2 may be patterned through the end of the first connection electrode layer LL1, and a portion of the second connection electrode layer LL2 may be disposed in the groove GV. Since the second connection electrode layer LL2 is disposed on the first connection electrode layer LL1 and patterned on the first connection electrode layer LL1, the connection electrode CNE may have a reverse tapered shape. As an example, the tapered angle between the lower surface of the first connection electrode layer LL1 and the side surface S_LL1 of the first connection electrode layer LL1 may be an acute angle or a right angle. Since the second connection electrode layer LL2 is patterned through the protruding end of the first connection electrode layer LL1, the second connection electrode layer LL2 may smoothly cover the side surface S_LL1 of the first connection electrode layer LL1, and the tip portion TP of the connection electrode CNE may have a reverse tapered shape.

[0251] The first connection electrode layer LL1 and the second connection electrode layer LL2 may include a transparent conductive oxide (TCO), such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ) etc., however, the materials used for the first connection electrode layer LL1 and the second connection electrode layer LL2 should not be limited thereto or thereby.

[0252] The intermediate layer IML may be disposed on the second connection electrode layer LL2. The intermediate layer IML may cover an upper surface of the second connection electrode layer LL2 and a portion of a side surface S_LL2 of the second connection electrode layer LL2. The intermediate layer IML may be patterned by the tip portion TP of the connection electrode CNE, and a portion of the intermediate layer IML may be disposed in the groove GV.

[0253] The second electrode EL2 may be disposed on the intermediate layer IML. The second electrode EL2 may cover the upper surface and the side surface S_IML of the intermediate layer IML. The second electrode EL2 may be patterned by the tip portion TP of the connection electrode CNE, and a portion of the second electrode EL2 may be disposed in the groove GV. The second electrode EL2 may be connected to the second connection electrode layer LL2 or may be in contact with the second connection electrode layer LL2. As an example, at the tip portion TP of the connection electrode CNE, the end portion of the second electrode EL2 and the portion of the end portion of the second connection electrode layer LL2 that is not covered by the intermediate layer IML may be connected to each other or may be in contact with each other.

[0254] The dummy pattern DMP may be disposed in the groove GV. The dummy pattern DMP may include a first partition pattern PP1, a second partition pattern PP2, and a third partition pattern PP3.

[0255] The first separation pattern PP1 may include the same material as the second connection electrode layer LL2. The first separation pattern PP1 may be formed substantially simultaneously with the second connection electrode layer LL2 through a single process and may be separated from the second connection electrode layer LL2 by an end portion of the first connection electrode layer LL1.

[0256] The second separation pattern PP2 may include the same material as the intermediate layer IML. The second separation pattern PP2 may be formed substantially simultaneously with the intermediate layer IML through a single process, and may be separated from the intermediate layer IML by the tip portion TP of the connection electrode CNE.

[0257] The third partition pattern PP3 may include the same material as the second electrode EL2. The third partition pattern PP3 may be formed substantially simultaneously with the second electrode EL2 through a single process and may be separated from the second electrode EL2 by the tip portion TP of the connection electrode CNE. The first partition pattern PP1 may be electrically connected to the third partition pattern PP3 in the groove GV.

[0258] Figure 6B is a display panel DP according to an embodiment of the present disclosure (refer to Figure 3A ), and Figure 6C is a display panel DP according to an embodiment of the present disclosure (refer to Figure 3A ) is an enlarged schematic cross-sectional view of a region. Figure 6B yes Figure 3A an enlarged plan view of area XX', and Figure 6C is along Figure 6B An enlarged schematic cross-sectional view taken along line YY'. Figure 6B and Figure 6C An outer portion of the display panel DP is shown.

[0259] refer to FIG. 6A to FIG. 6C , also refer to Figure 2A The connection electrode CNE may not be disposed in the display area DA of the display panel DP (refer to Figure 3A ) and non-display area NDA (reference Figure 3A ) at the boundary between the display area DA and the non-display area NDA. That is, a portion of the tip portion TP of the connection electrode CNE may not be formed in the outer portion of the display panel DP. In other embodiments of the present invention, the tip portion N_TP of the connection electrode CNE (hereinafter, referred to as the outer tip portion N_TP) formed in the outer portion of the display panel DP may be formed adjacent to the region in which the light-emitting parts EP1, EP2, and EP3 are disposed, and may not be formed in the region in which the light-emitting parts EP1, EP2, and EP3 are not disposed. The outer groove N_GV may be formed in the region in which the outer tip portion N_TP is not formed. The outer groove N_GV may be formed along the boundary between the display area DA and the non-display area NDA. The outer groove N_GV may have a shape connected to the groove GV formed between the light-emitting parts EP1, EP2, EP3.

[0260] The outer dummy pattern N_DMP may be disposed in the outer groove N_GV. The outer dummy pattern N_DMP may include a first outer partition pattern N_PP1, a second outer partition pattern N_PP2, and a third outer partition pattern N_PP3.

[0261] The first outer partition pattern N_PP1 may include the same material as the second connection electrode layer LL2. The first outer partition pattern N_PP1 may be formed substantially simultaneously with the second connection electrode layer LL2 through a single process and may be separated from the second connection electrode layer LL2 by an end portion of the first connection electrode layer LL1. The first outer partition pattern N_PP1 may be connected to the first partition pattern PP1 and may be provided integrally with the first partition pattern PP1.

[0262] The second outer separation pattern N_PP2 may include the same material as the intermediate layer IML. The second outer separation pattern N_PP2 may be formed substantially simultaneously with the intermediate layer IML by a single process and may be separated from the intermediate layer IML by the outer tip portion N_TP of the connection electrode CNE. The second outer separation pattern N_PP2 may be connected to the second separation pattern PP2 and may be provided integrally with the second separation pattern PP2.

[0263] The third outer partition pattern N_PP3 may include the same material as the second electrode EL2. The third outer partition pattern N_PP3 may be formed substantially simultaneously with the second electrode EL2 by a single process and may be separated from the second electrode EL2 by the outer tip portion N_TP of the connection electrode CNE. The third outer partition pattern N_PP3 may be connected to the third partition pattern PP3 and may be provided integrally with the third partition pattern PP3.

[0264] The first power voltage VDD as a constant voltage may be applied to the third outer partition pattern N_PP3. The first outer partition pattern N_PP1 may be electrically connected to the third outer partition pattern N_PP3 in the outer groove N_GV, and thus, the first power voltage VDD may be applied to the first outer partition pattern N_PP1. Since the outer groove N_GV has a shape connected to the groove GV formed between the light emitting parts EP1, EP2, and EP3, the first power voltage VDD may be applied to the first and third partition patterns PP1 and PP3 disposed in the groove GV.

[0265] According to an embodiment, when the first power voltage VDD as a constant voltage is applied to the first separation pattern PP1 and the first outer separation pattern N_PP1 , noise coupling caused by the first separation pattern PP1 and the first outer separation pattern N_PP1 may be reduced or removed.

[0266] Figure 7 is an enlarged schematic cross-sectional view of a region of a display panel according to an embodiment of the present disclosure. Figure 7 yes Figure 5 An enlarged cross-sectional view of the area AA'. Figure 7 In the same / similar reference numerals, Figures 1 to 6C, and thus, detailed description of the same elements will be omitted.

[0267] refer to Figure 5 and Figure 7 The connection electrode CNEa may be disposed on the pixel defining layer PDL. The connection electrode CNEa may be electrically connected to the pixel driving unit PDC and the light emitting element LD. The connection electrode CNEa may include a first connection electrode layer LL1 disposed on the pixel defining layer PDL. That is, the connection electrode CNEa may have a Fig. 6A The connection electrode CNE removes the second connection electrode layer LL2 (reference Fig. 6A ). The end of the first connection electrode layer LL1 may form a tip portion TPa of the connection electrode CNEa. The tapered angle between the lower surface of the connection electrode CNEa and the side surface of the connection electrode CNEa may be an acute angle or a right angle. However, the present disclosure should not be limited thereto or thereby, and the tip portion TPa may have a reverse tapered shape.

[0268] The intermediate layer IML may be disposed on the first connection electrode layer LL1. The intermediate layer IML may cover an upper surface of the first connection electrode layer LL1 and a portion of a side surface S_LL1 of the first connection electrode layer LL1. The intermediate layer IML may be patterned by the tip portion TPa of the connection electrode CNEa, and a portion of the intermediate layer IML may be disposed in the groove GV.

[0269] The second electrode EL2 may be disposed on the intermediate layer IML. The second electrode EL2 may cover the upper surface and the side surface S_IML of the intermediate layer IML. The second electrode EL2 may be patterned by the tip portion TPa of the connection electrode CNEa, and a portion of the second electrode EL2 may be disposed in the groove GV. The second electrode EL2 may be connected to the first connection electrode layer LL1 or may be in contact with the first connection electrode layer LL1. As an example, at the tip portion TPa of the connection electrode CNEa, the end of the second electrode EL2 may be connected to a portion of an end of the first connection electrode layer LL1 that is not covered by the intermediate layer IML or may be in contact with a portion of an end of the first connection electrode layer LL1 that is not covered by the intermediate layer IML.

[0270] The dummy pattern DMPa may be disposed in the groove GV. The dummy pattern DMPa may include a first partition pattern PP1a and a second partition pattern PP2a.

[0271] The first separation pattern PP1a may include the same material as the intermediate layer IML. The first separation pattern PP1a may be formed substantially simultaneously with the intermediate layer IML through a single process, and may be separated from the intermediate layer IML by the tip portion TPa of the connection electrode CNEa.

[0272] The second separation pattern PP2a may include the same material as the second electrode EL2. The second separation pattern PP2a may be formed substantially simultaneously with the second electrode EL2 through a single process, and may be separated from the second electrode EL2 by the tip portion TPa of the connection electrode CNEa.

[0273] Figure 8 is an enlarged schematic cross-sectional view of a region of a display panel according to an embodiment of the present disclosure. Figure 8 yes Figure 5 An enlarged cross-sectional view of the area AA'. Figure 8 In the same / similar reference numerals, Figures 1 to 7 , and thus, detailed description of the same elements will be omitted.

[0274] refer to Figure 5 and Figure 8 , the pixel defining layer PDLa may include a first pixel defining layer portion PDL1 and a second pixel defining layer portion PDL2. The first pixel defining layer portion PDL1 and the second pixel defining layer portion PDL2 may be formed by a single process and may have a single body. The first pixel defining layer portion PDL1 may be disposed on the sixth insulating layer 60, and the second pixel defining layer portion PDL2 may be disposed on the first pixel defining layer portion PDL1. The first pixel defining layer portion PDL1 may correspond to Fig. 6A The second pixel defining layer portion PDL2 may have a shape protruding from the first pixel defining layer portion PDL1 in a thickness direction (eg, third direction DR3). A groove GV may be defined in the second pixel defining layer portion PDL2.

[0275] The connection electrode CNEb may be disposed on the pixel defining layer PDLa. The connection electrode CNEb may electrically connect the pixel driving unit PDC to the light emitting element LD. The connection electrode CNEb may include a first connection electrode layer LL1a disposed on the pixel defining layer PDLa and a second connection electrode layer LL2a disposed on the first connection electrode layer LL1a. The second connection electrode layer LL2a may cover the first connection electrode layer LL1a. As an example, the second connection electrode layer LL2a may cover the upper surface and the side surface S_LL1a of the first connection electrode layer LL1a. Therefore, the side surface S_LL1a of the first connection electrode layer LL1a may not be exposed to the outside. The end of the first connection electrode layer LL1a and the end of the second connection electrode layer LL2a covering the end of the first connection electrode layer LL1a may form a tip portion TPb of the connection electrode CNEb.

[0276] The second connection electrode layer LL2a may be patterned through the end of the first connection electrode layer LL1a, and a portion of the second connection electrode layer LL2a may be disposed in the groove GV. Since the second connection electrode layer LL2a is disposed on the first connection electrode layer LL1a and patterned on the first connection electrode layer LL1a, the connection electrode CNEb may have a reverse tapered shape. As an example, the tapered angle between the lower surface of the first connection electrode layer LL1a and the side surface S_LL1a of the first connection electrode layer LL1a may be an acute angle or a right angle. Since the second connection electrode layer LL2a is patterned through the protruding end of the first connection electrode layer LL1a, the second connection electrode layer LL2a may smoothly cover the side surface S_LL1a of the first connection electrode layer LL1a, and the tip portion TPb of the connection electrode CNEb may have a reverse tapered shape. In addition, since the pixel defining layer PDLa includes the second pixel defining layer portion PDL2 protruding from the first pixel defining layer portion PDL1 , the tip portion TPb of the connection electrode CNEb may have a reverse tapered shape by a slope of the second pixel defining layer portion PDL2 .

[0277] The first connection electrode layer LL1a and the second connection electrode layer LL2a may include a transparent conductive oxide (TCO), such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ) etc., however, the materials used for the first connection electrode layer LL1a and the second connection electrode layer LL2a should not be limited thereto or thereby.

[0278] The intermediate layer IML may be disposed on the second connection electrode layer LL2a. The intermediate layer IML may cover an upper surface of the second connection electrode layer LL2a and a portion of a side surface S_LL2a of the second connection electrode layer LL2a. The intermediate layer IML may be patterned by the tip portion TPb of the connection electrode CNEb, and a portion of the intermediate layer IML may be disposed in the groove GV.

[0279] The second electrode EL2 may be disposed on the intermediate layer IML. The second electrode EL2 may cover the upper surface and the side surface S_IML of the intermediate layer IML. The second electrode EL2 may be patterned by the tip portion TPb of the connection electrode CNEb, and a portion of the second electrode EL2 may be disposed in the groove GV. The second electrode EL2 may be connected to the second connection electrode layer LL2a or may be in contact with the second connection electrode layer LL2a. As an example, at the tip portion TPb of the connection electrode CNEb, the end of the second electrode EL2 may be connected to a portion of an end of the second connection electrode layer LL2a that is not covered by the intermediate layer IML or may be in contact with a portion of an end of the second connection electrode layer LL2a that is not covered by the intermediate layer IML.

[0280] The dummy pattern DMPb may be disposed in the groove GV. The dummy pattern DMPb may include a first partition pattern PP1, a second partition pattern PP2, and a third partition pattern PP3. The first partition pattern PP1, the second partition pattern PP2, and the third partition pattern PP3 may be respectively Fig. 6A The first, second and third partition patterns PP1, PP2 and PP3 are substantially the same.

[0281] Fig. 9 is an enlarged schematic cross-sectional view of a region of a display panel according to an embodiment of the present disclosure. Fig. 9 yes Figure 5 An enlarged cross-sectional view of the area AA'. Fig. 9 In the same / similar reference numerals, Figures 1 to 8 For the same / similar elements in the present invention, detailed description of the same elements will be omitted.

[0282] refer to Figure 5 and Fig. 9 , the pixel defining layer PDLa may include a first pixel defining layer portion PDL1 and a second pixel defining layer portion PDL2. The connection electrode CNEc may be disposed on the pixel defining layer PDLa. The connection electrode CNEc may electrically connect the pixel driving unit PDC to the light emitting element LD. The connection electrode CNEc may include a first connection electrode layer LL1a disposed on the pixel defining layer PDLa. That is, the connection electrode CNEc may have a Figure 8 The second connection electrode layer LL2a (reference Figure 8) is obtained by a structure obtained by a first connection electrode layer LL1a. The end of the first connection electrode layer LL1a may form a tip portion TPc of the connection electrode CNEc. The tapered angle between the lower surface of the connection electrode CNEc and the side surface of the connection electrode CNEc may be an acute angle or a right angle, however, the present disclosure should not be limited thereto or thereby. According to an embodiment, the tip portion TPc may have a reverse tapered shape. As an example, since the pixel defining layer PDLa includes a second pixel defining layer portion PDL2 protruding from the first pixel defining layer portion PDL1, the tip portion TPc of the connection electrode CNEc may have a reverse tapered shape by the slope of the second pixel defining layer portion PDL2.

[0283] The intermediate layer IML may be disposed on the first connection electrode layer LL1a. The intermediate layer IML may cover the upper surface and the side surface S_LL1a of the first connection electrode layer LL1a. The intermediate layer IML may be patterned by the tip portion TPc of the connection electrode CNEc, and a portion of the intermediate layer IML may be disposed in the groove GV.

[0284] The second electrode EL2 may be disposed on the intermediate layer IML. The second electrode EL2 may cover the upper surface and the side surface S_IML of the intermediate layer IML. The second electrode EL2 may be patterned by the tip portion TPc of the connection electrode CNEc, and a portion of the second electrode EL2 may be disposed in the groove GV. The second electrode EL2 may be connected to the first connection electrode layer LL1a or may be in contact with the first connection electrode layer LL1a. As an example, at the tip portion TPc of the connection electrode CNEc, the end of the second electrode EL2 may be connected to a portion of an end of the first connection electrode layer LL1a that is not covered by the intermediate layer IML or may be in contact with a portion of an end of the first connection electrode layer LL1a that is not covered by the intermediate layer IML.

[0285] The dummy pattern DMPc may be disposed in the groove GV. The dummy pattern DMPc may include a first partition pattern PP1a and a second partition pattern PP2a. The first partition pattern PP1a and the second partition pattern PP2a may be respectively Figure 7 The first partition patterns PP1a and the second partition patterns PP2a are substantially identical.

[0286] FIG. 10A to FIG. 10F is a schematic cross-sectional view showing a process of a method for manufacturing a display panel according to an embodiment of the present disclosure. FIG. 10A to FIG. 10F In the same / similar reference numerals, Figures 1 to 9 , and therefore, detailed description of the same elements will be omitted. FIG. 10A to FIG. 10F The display panel manufactured by the manufacturing method shown in Fig. 6A The display panel shown in .

[0287] According to the present disclosure, a method for manufacturing a display panel may include: preparing a preliminary display panel including a base layer, a driving element layer arranged on the base layer, and a pixel defining layer arranged on the driving element layer; depositing a first connecting electrode layer on the preliminary display panel; etching a portion of the first connecting electrode layer and a portion of the pixel defining layer to form a groove in the pixel defining layer that overlaps with a portion of the first connecting electrode layer; etching the first connecting electrode layer to form a connecting electrode; and forming an intermediate layer and a cathode on the connecting electrode and the pixel defining layer.

[0288] refer to Fig. 10A The manufacturing method of the display panel may include preparing a preliminary display panel DP_I and depositing a first connection electrode layer LL1. The preliminary display panel DP_I may include a base layer BS, a driving element layer DDL disposed on the base layer BS, and a pixel defining layer PDL disposed on the driving element layer DDL.

[0289] The base layer BS can provide a base surface, a pixel driving unit PDC (reference Figure 5 ) is disposed on the substrate surface. The driving element layer DDL may be formed by a conventional manufacturing process of a circuit element, in which an insulating layer, a conductive layer, and a semiconductor layer are formed by coating and deposition processes, and the insulating layer, the semiconductor layer, and the conductive layer are selectively patterned by photolithography and etching processes to form semiconductor patterns, conductive patterns, and signal lines. The driving element layer DDL may include a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, a fourth insulating layer 40, a fifth insulating layer 50, and a sixth insulating layer 60 sequentially stacked on the substrate layer BS (refer to Figure 5 ) and pixel driving unit PDC.

[0290] A pixel defining layer PDL may be formed on the driving element layer DDL. A light emitting opening OP-PDL (refer to Figure 5 ) and through hole OP-P (reference Figure 5 )'s pixel defining layer PDL.

[0291] The first connection electrode layer LL1 may be deposited on the preliminary display panel DP_I. The deposition of the first connection electrode layer LL1 may be performed by a process of depositing a conductive material. The conductive material used to form the first connection electrode layer LL1 may include a transparent conductive oxide (TCO), such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3) etc., however, the material used for the first connection electrode layer LL1 should not be limited thereto or thereby.

[0292] The manufacturing method of the display panel may include forming a first photoresist layer PR1. The first photoresist layer PR1 may be formed on the first connection electrode layer LL1. The first photoresist layer PR1 may be formed by forming a preliminary photoresist layer on the first connection electrode layer LL1 and patterning the preliminary photoresist layer using a photomask. Through the patterning process, the first photoresist layer PR1 through which the first optical opening OP_PR1 is defined may be formed.

[0293] refer to Fig. 10B and Fig. 10C , the method of manufacturing the display panel may include forming a groove GV of the pixel defining layer PDL, the groove GV overlapping a portion of the first connection electrode layer LL1.

[0294] refer to Fig. 10B , the formation of the groove GV of the pixel defining layer PDL may include etching a portion of the first connection electrode layer LL1. The etching process for the first connection electrode layer LL1 may be a wet etching process. The portion of the first connection electrode layer LL1 may be removed by the wet etching process, and thus, a first opening OP_LL1 may be formed through the first connection electrode layer LL1. The first opening OP_LL1 may overlap with the first light opening OP_PR1 of the first photoresist layer PR1. The end of the first connection electrode layer LL1 that defines the first opening OP_LL1 may have a tapered shape. As an example, the tapered angle between the lower surface of the first connection electrode layer LL1 and the side surface of the first connection electrode layer LL1 may be an acute angle or a right angle, however, the embodiment should not be limited to this or thereby.

[0295] refer to Fig. 10C , the formation of the groove GV of the pixel defining layer PDL may include etching a portion of the pixel defining layer PDL. The etching process for the pixel defining layer PDL may be a dry etching process. The portion of the pixel defining layer PDL may be removed by the dry etching process, and the groove GV may be formed in the pixel defining layer PDL. The groove GV may overlap with the first opening OP_LL1 of the first connection electrode layer LL1 and the first optical opening OP_PR1 of the first photoresist layer PR1. The groove GV may overlap with a portion of the first connection electrode layer LL1. That is, the portion of the first connection electrode layer LL1 may protrude from the end of the groove GV to the center of the groove GV.

[0296] refer to Fig. 10D The manufacturing method of the display panel may include: removing the first photoresist layer PR1 (reference Fig. 10C); depositing a second connection electrode layer LL2; and forming a tip portion TP.

[0297] The second connection electrode layer LL2 may be deposited on the first connection electrode layer LL1. The deposition of the second connection electrode layer LL2 may be performed by a process of depositing a conductive material. The conductive material used to form the second connection electrode layer LL2 may include a transparent conductive oxide (TCO), such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ), etc., however, the material for the second connection electrode layer LL2 should not be limited thereto or thereby. The tip portion TP may be defined by an end portion of the first connection electrode layer LL1 and an end portion of the second connection electrode layer LL2 covering the end portion of the first connection electrode layer LL1.

[0298] The second connection electrode layer LL2 may be patterned by an end portion of the first connection electrode layer LL1, and a portion of the second connection electrode layer LL2 may be disposed in the groove GV. A portion of the second connection electrode layer LL2 separated from the second connection electrode layer LL2 by an end portion of the first connection electrode layer LL1 may be defined as a first partition pattern PP1. The first partition pattern PP1 may include the same material as the second connection electrode layer LL2, and the first partition pattern PP1 may be formed substantially simultaneously with the second connection electrode layer LL2 through a single process.

[0299] The manufacturing method of the display panel may include forming a second photoresist layer PR2. The second photoresist layer PR2 may be formed on the second connection electrode layer LL2. The second photoresist layer PR2 may be formed by forming a preliminary photoresist layer on the second connection electrode layer LL2 and patterning the preliminary photoresist layer using a photomask. Through the patterning process, the second photoresist layer PR2 may be formed, and the second photoresist layer PR2 may overlap the groove GV.

[0300] refer to Fig. 10E , the manufacturing method of the display panel may include etching the first connection electrode layer LL1 and the second connection electrode layer LL2 to form the connection electrode CNE. The etching process for the first connection electrode layer LL1 and the second connection electrode layer LL2 may be a wet etching process. The first connection electrode layer LL1 that is not in contact with the second photoresist layer PR2 (reference Fig. 10D ) overlapped with the second connection electrode layer LL2 and the second photoresist layer PR2 (reference Fig. 10DThe first connection electrode layer LL1 and the second connection electrode layer LL2 that remain and overlap with the second photoresist layer PR2 may form a connection electrode CNE. The second photoresist layer PR2 may be removed.

[0301] refer to Fig.10F , the manufacturing method of the display panel may include forming an intermediate layer IML and a second electrode EL2 (or cathode) on the connection electrode CNE and the pixel defining layer PDL. The formation of the intermediate layer IML and the formation of the second electrode EL2 may be performed by a deposition process.

[0302] The intermediate layer IML may be patterned by the tip portion TP of the connection electrode CNE, and a portion of the intermediate layer IML may be disposed in the groove GV. A portion of the intermediate layer IML separated from the intermediate layer IML by the tip portion TP of the connection electrode CNE may be defined as a second separation pattern PP2. The second separation pattern PP2 may include the same material as the intermediate layer IML, and the second separation pattern PP2 may be formed substantially simultaneously with the intermediate layer IML through a single process.

[0303] The second electrode EL2 may be patterned by the tip portion TP of the connection electrode CNE, and a portion of the second electrode EL2 may be disposed in the groove GV. A portion of the second electrode EL2 separated from the second electrode EL2 by the tip portion TP of the connection electrode CNE may be defined as a third separation pattern PP3. The third separation pattern PP3 may include the same material as the second electrode EL2, and the third separation pattern PP3 may be formed substantially simultaneously with the second electrode EL2 by a single process. The first separation pattern PP1, the second separation pattern PP2, and the third separation pattern PP3 may form a dummy pattern DMP.

[0304] FIG. 11A to FIG. 11C is a schematic cross-sectional view showing a process of a method for manufacturing a display panel according to an embodiment of the present disclosure. FIG. 11A to FIG. 11C In the same / similar reference numerals, Figures 1 to 10F , and therefore, detailed description of the same elements will be omitted. FIG. 11A to FIG. 11C The display panel manufactured by the manufacturing method shown in Figure 7 The display panel shown in .

[0305] refer to FIG. 11A to FIG. 11C The manufacturing method of the display panel may include: preparing a preliminary display panel DP_I (reference Fig. 10A ); depositing a first connection electrode layer LL1; and forming a groove GV of the pixel defining layer PDL to overlap a portion of the first connection electrode layer LL1. Preliminary display panel DP_I (reference Fig. 10A), the deposition of the first connection electrode layer LL1, and the formation of the groove GV of the pixel defining layer PDL overlapping with a portion of the first connection electrode layer LL1 may be related to FIG. 10A to FIG. 10C The preparation of the preliminary display panel DP_I, the deposition of the first connection electrode layer LL1, and the formation of the groove GV of the pixel defining layer PDL overlapping a portion of the first connection electrode layer LL1 are substantially the same.

[0306] refer to Fig.11A , the manufacturing method of the display panel may include: forming a tip portion TPa; and removing the first photoresist layer PR1 (reference Fig. 10C ) Then, a second photoresist layer PR2 is formed. The tip portion TPa may be defined by an end portion of the first connection electrode layer LL1.

[0307] A second photoresist layer PR2 may be disposed on the first connection electrode layer LL1. The second photoresist layer PR2 may be formed by forming a preliminary photoresist layer on the first connection electrode layer LL1 and patterning the preliminary photoresist layer using a photomask. Through the patterning process, a second photoresist layer PR2 overlapping the groove GV may be formed.

[0308] refer to Fig. 11B , the manufacturing method of the display panel may include etching the first connection electrode layer LL1 to form the connection electrode CNEa. The etching process for the first connection electrode layer LL1 may be a wet etching process. The first connection electrode layer LL1 that is not in contact with the second photoresist layer PR2 (reference Fig.11A ), and the first connection electrode layer LL1 that remains and overlaps with the second photoresist layer PR2 may form the connection electrode CNEa. The second photoresist layer PR2 may be removed.

[0309] refer to Fig. 11C , the method for manufacturing a display panel may include forming an intermediate layer IML and a second electrode EL2 (or cathode) on the connection electrode CNEa and the pixel defining layer PDL. The formation of the intermediate layer IML and the formation of the second electrode EL2 may be performed by a deposition process.

[0310] The intermediate layer IML may be patterned by the tip portion TPa of the connection electrode CNEa, and a portion of the intermediate layer IML may be disposed in the groove GV. A portion of the intermediate layer IML separated from the intermediate layer IML by the tip portion TPa of the connection electrode CNEa may be defined as a first separation pattern PP1a. The first separation pattern PP1a may include the same material as the intermediate layer IML, and the first separation pattern PP1a may be formed substantially simultaneously with the intermediate layer IML through a single process.

[0311] The second electrode EL2 may be patterned by the tip portion TPa of the connection electrode CNEa, and a portion of the second electrode EL2 may be disposed in the groove GV. A portion of the second electrode EL2 separated from the second electrode EL2 by the tip portion TPa of the connection electrode CNEa may be defined as a second separation pattern PP2a. The second separation pattern PP2a may include the same material as the second electrode EL2, and the second separation pattern PP2a may be formed substantially simultaneously with the second electrode EL2 by a single process. The first separation pattern PP1a and the second separation pattern PP2a may form a dummy pattern DMPa.

[0312] FIG. 12A to FIG. 12F is a schematic cross-sectional view showing a process of a method for manufacturing a display panel according to an embodiment of the present disclosure. FIG. 12A to FIG. 12F In the same / similar reference numerals, Figures 1 to 11C , and therefore, detailed description of the same elements will be omitted. FIG. 12A to FIG. 12F The display panel manufactured by the manufacturing method shown in Figure 8 The display panel shown in .

[0313] refer to Fig. 12A , the manufacturing method of the display panel may include: preparing a preliminary display panel DPa_I; and depositing a first connection electrode layer LL1a. The preliminary display panel DPa_I may include a base layer BS, a driving element layer DDL disposed on the base layer BS, and a pixel defining layer PDLa disposed on the driving element layer DDL.

[0314] A pixel defining layer PDLa may be formed on the driving element layer DDL. A preliminary pixel defining layer may be deposited on the driving element layer DDL, and the preliminary pixel defining layer may be selectively patterned by photolithography and etching processes, and thus, a pixel defining layer PDLa including a first pixel defining layer portion PDL1 and a second pixel defining layer portion PDL2 having a shape protruding from the first pixel defining layer portion PDL1 may be formed. The first pixel defining layer portion PDL1 and the second pixel defining layer portion PDL2 may be formed by a single process and may have a single body. In the process of forming the pixel defining layer PDLa, a halftone mask may be used, however, the method of forming the pixel defining layer PDLa should not be limited thereto or thereby. Furthermore, a light emitting opening OP-PDL (refer to Figure 5 ) and through hole OP-P (reference Figure 5 ).

[0315] The first connection electrode layer LL1a may be deposited on the preliminary display panel DPa_I. In detail, the first connection electrode layer LL1a may be deposited on the first pixel defining layer portion PDL1 and the second pixel defining layer portion PDL2 of the pixel defining layer PDLa. The deposition of the first connection electrode layer LL1a may be performed by a process of depositing a conductive material. The conductive material for forming the first connection electrode layer LL1a may include a transparent conductive oxide (TCO), such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ) etc., however, the material used for the first connection electrode layer LL1a should not be limited thereto or thereby.

[0316] The manufacturing method of the display panel may include forming a first photoresist layer PR1. The first photoresist layer PR1 may be formed on the first connection electrode layer LL1a. The first photoresist layer PR1 may be formed by forming a preliminary photoresist layer on the first connection electrode layer LL1a and patterning the preliminary photoresist layer using a photomask. Through the patterning process, the first photoresist layer PR1 through which the first optical opening OP_PR1 is defined may be formed.

[0317] refer to Fig. 12B and Fig. 12C , the method for manufacturing a display panel may include forming a groove GV of the pixel defining layer PDLa, the groove GV overlapping a portion of the first connection electrode layer LL1a.

[0318] refer to Fig. 12B , the formation of the groove GV of the pixel defining layer PDLa may include etching a portion of the first connection electrode layer LL1a. The etching process for the first connection electrode layer LL1a may be a wet etching process. The portion of the first connection electrode layer LL1a may be removed by the etching process, and thus, a first opening OP_LL1a may be formed through the first connection electrode layer LL1a. The first opening OP_LL1a may overlap with the first light opening OP_PR1 of the first photoresist layer PR1. The end of the first connection electrode layer LL1a that defines the first opening OP_LL1a may have a tapered shape. As an example, the tapered angle between the lower surface of the first connection electrode layer LL1a and the side surface of the first connection electrode layer LL1a may be an acute angle or a right angle, however, the present disclosure should not be limited to or thereby.

[0319] refer to Fig. 12C, the formation of the groove GV of the pixel defining layer PDLa may include etching a portion of the pixel defining layer PDLa. The etching process for the pixel defining layer PDLa may be a dry etching process. The portion of the pixel defining layer PDLa may be removed by the etching process, and thus, a groove GV may be formed in the pixel defining layer PDLa. The groove GV may overlap with the first opening OP_LL1a of the first connection electrode layer LL1a and the first optical opening OP_PR1 of the first photoresist layer PR1. The groove GV may overlap with a portion of the first connection electrode layer LL1a. That is, the portion of the first connection electrode layer LL1a may protrude from the end of the groove GV to the center of the groove GV.

[0320] refer to Fig.12D The manufacturing method of the display panel may include: removing the first photoresist layer PR1 (reference Fig. 12C ); depositing a second connection electrode layer LL2a; and forming a tip portion TPb.

[0321] The second connection electrode layer LL2a may be deposited on the first connection electrode layer LL1a. The deposition of the second connection electrode layer LL2a may be performed by a process of depositing a conductive material. The conductive material used to form the second connection electrode layer LL2a may include a transparent conductive oxide (TCO), such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ), etc., however, the material for the second connection electrode layer LL2a should not be limited thereto or thereby. The tip portion TPb may be defined by an end portion of the first connection electrode layer LL1a and an end portion of the second connection electrode layer LL2a covering the end portion of the first connection electrode layer LL1a.

[0322] According to the present disclosure, since the second connection electrode layer LL2a is patterned by the protruding end of the first connection electrode layer LL1a, the second connection electrode layer LL2a can smoothly surround the side surface S_LL1a of the first connection electrode layer LL1a (see Figure 8 ), and connect electrode CNEb (see Figure 8 ) may have a reverse tapered shape. In addition, since the pixel defining layer PDLa includes the second pixel defining layer portion PDL2 protruding from the first pixel defining layer portion PDL1, the tip portion TPb of the connection electrode CNEb may have a reverse tapered shape due to the slope of the second pixel defining layer portion PDL2.

[0323] The second connection electrode layer LL2a may be patterned by an end portion of the first connection electrode layer LL1a, and a portion of the second connection electrode layer LL2a may be disposed in the groove GV. A portion of the second connection electrode layer LL2a separated from the second connection electrode layer LL2a by an end portion of the first connection electrode layer LL1a may be defined as a first partition pattern PP1. The first partition pattern PP1 may include the same material as the second connection electrode layer LL2a, and the first partition pattern PP1 may be formed substantially simultaneously with the second connection electrode layer LL2a by a single process.

[0324] The manufacturing method of the display panel may include forming a second photoresist layer PR2. The second photoresist layer PR2 may be formed on the second connection electrode layer LL2a. The second photoresist layer PR2 may be formed by forming a preliminary photoresist layer on the second connection electrode layer LL2a and patterning the preliminary photoresist layer using a photomask. Through the patterning process, the second photoresist layer PR2 overlapping the groove GV may be formed.

[0325] refer to Fig.12E , the manufacturing method of the display panel may include etching the first connection electrode layer LL1a and the second connection electrode layer LL2a to form the connection electrode CNEb. The etching process for the first connection electrode layer LL1a and the second connection electrode layer LL2a may be a wet etching process. The first connection electrode layer LL1a that is not in contact with the second photoresist layer PR2 (reference Fig.12D ) overlapped with the second connection electrode layer LL2a and the second photoresist layer PR2 (reference Fig.12D The first connection electrode layer LL1a and the second connection electrode layer LL2a remaining and overlapping with the second photoresist layer PR2 may form a connection electrode CNEb. The second photoresist layer PR2 may be removed.

[0326] refer to Fig.12F , the manufacturing method of the display panel may include forming an intermediate layer IML and a second electrode EL2 (or cathode) on the connection electrode CNEb and the pixel defining layer PDLa. Each of the formation of the intermediate layer IML and the formation of the second electrode EL2 may be performed by a deposition process.

[0327] The intermediate layer IML may be patterned by the tip portion TPb of the connection electrode CNEb, and a portion of the intermediate layer IML may be disposed in the groove GV. A portion of the intermediate layer IML separated from the intermediate layer IML by the tip portion TPb of the connection electrode CNEb may be defined as a second separation pattern PP2. The second separation pattern PP2 may include the same material as the intermediate layer IML, and the second separation pattern PP2 may be formed substantially simultaneously with the intermediate layer IML through a single process.

[0328] The second electrode EL2 may be patterned by the tip portion TPb of the connection electrode CNEb, and a portion of the second electrode EL2 may be disposed in the groove GV. A portion of the second electrode EL2 separated from the second electrode EL2 by the tip portion TPb of the connection electrode CNEb may be defined as a third separation pattern PP3. The third separation pattern PP3 may include the same material as the second electrode EL2, and the third separation pattern PP3 may be formed substantially simultaneously with the second electrode EL2 by a single process. The first separation pattern PP1, the second separation pattern PP2, and the third separation pattern PP3 may form a dummy pattern DMPb.

[0329] FIG. 13A to FIG. 13C is a schematic cross-sectional view showing a process of a method for manufacturing a display panel according to an embodiment of the present disclosure. FIG. 13A to FIG. 13C In the same / similar reference numerals, Figures 1 to 12F , and therefore, detailed description of the same elements will be omitted. FIG. 13A to FIG. 13C The display panel manufactured by the manufacturing method shown in Fig. 9 The display panel shown in .

[0330] refer to FIG. 13A to FIG. 13C The manufacturing method of the display panel may include: preparing a preliminary display panel DPa_I (reference Fig. 12A ); depositing a first connection electrode layer LL1a; and forming a groove GV of the pixel defining layer PDLa to overlap a portion of the first connection electrode layer LL1a. Preliminary display panel DPa_I (reference Fig. 12A ), the deposition of the first connection electrode layer LL1a, and the formation of a groove GV of the pixel defining layer PDLa overlapping a portion of the first connection electrode layer LL1a may be performed with FIG. 12A to FIG. 12C The preparation of the preliminary display panel DPa_I, the deposition of the first connection electrode layer LL1a, and the formation of the groove GV of the pixel defining layer PDLa overlapping a portion of the first connection electrode layer LL1a are substantially the same.

[0331] refer to Fig.13A The manufacturing method of the display panel may include: removing the first photoresist layer PR1 (reference Fig. 12C ); forming a tip portion TPc; and forming a second photoresist layer PR2. The tip portion TPc may be defined by an end portion of the first connection electrode layer LL1a.

[0332] According to the present disclosure, since the pixel defining layer PDLa includes the second pixel defining layer portion PDL2 protruding from the first pixel defining layer portion PDL1 , the tip portion TPc of the connection electrode CNEc may have a reverse tapered shape due to the slope of the second pixel defining layer portion PDL2 .

[0333] A second photoresist layer PR2 may be formed on the first connection electrode layer LL1a. The second photoresist layer PR2 may be formed by forming a preliminary photoresist layer on the first connection electrode layer LL1a and patterning the preliminary photoresist layer using a photomask. Through the patterning process, a second photoresist layer PR2 overlapping the groove GV may be formed.

[0334] refer to Fig. 13B The method for manufacturing a display panel may include etching the first connection electrode layer LL1a to form a connection electrode CNEc. The etching process for the first connection electrode layer LL1a may be a wet etching process. The first connection electrode layer LL1a that is not in contact with the second photoresist layer PR2 (reference Fig.13A ), and the first connection electrode layer LL1a remaining and overlapping with the second photoresist layer PR2 may form the connection electrode CNEc. The second photoresist layer PR2 may be removed.

[0335] refer to Fig. 13C , the manufacturing method of the display panel may include forming an intermediate layer IML and a second electrode EL2 (or cathode) on the connection electrode CNEc and the pixel defining layer PDLa. Each of the formation of the intermediate layer IML and the formation of the second electrode EL2 may be performed by a deposition process.

[0336] The intermediate layer IML may be patterned by the tip portion TPc of the connection electrode CNEc, and a portion of the intermediate layer IML may be disposed in the groove GV. A portion of the intermediate layer IML separated from the intermediate layer IML by the tip portion TPc of the connection electrode CNEc may be defined as a first separation pattern PP1a. The first separation pattern PP1a may include the same material as the intermediate layer IML, and the first separation pattern PP1a may be formed substantially simultaneously with the intermediate layer IML through a single process.

[0337] The second electrode EL2 may be patterned by the tip portion TPc of the connection electrode CNEc, and a portion of the second electrode EL2 may be disposed in the groove GV. A portion of the second electrode EL2 separated from the second electrode EL2 by the tip portion TPc of the connection electrode CNEc may be defined as a second separation pattern PP2a. The second separation pattern PP2a may include the same material as the second electrode EL2, and the second separation pattern PP2a may be formed substantially simultaneously with the second electrode EL2 by a single process. The first separation pattern PP1a and the second separation pattern PP2a may form a dummy pattern DMPc.

[0338] Although the embodiments of the present disclosure have been described, it is understood that the present disclosure should not be limited to these embodiments, but a person skilled in the art may make various changes and modifications within the spirit and scope of the present disclosure. Therefore, the disclosed subject matter should not be limited to the embodiments described herein.

Claims

1. A display panel, wherein: The display panel comprises: A driving element layer, including a pixel driving unit; A light emitting element is disposed on the driving element layer, and the light emitting element includes: a first electrode; an intermediate layer, disposed on the first electrode; and A second electrode is disposed on the intermediate layer; a pixel defining layer disposed on the driving element layer, wherein the pixel defining layer includes a light emitting opening exposing at least a portion of the first electrode and a groove surrounding the light emitting opening; and A connection electrode is disposed on the pixel defining layer, and the connection electrode is electrically connected to the pixel driving unit and the second electrode.

2. The display panel according to claim 1, wherein: The light emitting element comprises a plurality of light emitting elements, The pixel driving unit includes a plurality of pixel driving units. The connecting electrode comprises a plurality of connecting electrodes, The plurality of connection electrodes electrically connect the plurality of light emitting elements to the plurality of pixel driving units, respectively, and A gap between mutually adjacent connection electrodes among the plurality of connection electrodes overlaps the groove.

3. The display panel according to claim 1, wherein: The connecting electrode comprises: first edge; and a second edge surrounding said first edge, and The second edge overlaps the groove.

4. The display panel according to claim 1, wherein: The second electrode is electrically connected to the connection electrode in a region adjacent to the groove.

5. The display panel according to claim 1, wherein: The connection electrode includes a tip portion protruding from an end of the groove, and In a plan view, the connection electrode overlaps the groove of the pixel defining layer.

6. The display panel according to claim 5, wherein: The second electrode is electrically connected to the connection electrode at the tip portion.

7. The display panel according to claim 5, wherein: A through hole is further defined through the pixel defining layer, and The connection electrode is electrically connected to the pixel driving section through the through hole.

8. The display panel according to claim 5, wherein: The connecting electrode comprises: A first connection electrode layer is disposed on the pixel defining layer; and a second connection electrode layer, disposed on the first connection electrode layer, and The second connection electrode layer covers the first connection electrode layer.

9. The display panel according to claim 8, wherein: The intermediate layer is arranged on the second connection electrode layer, The second electrode is disposed on the intermediate layer, and The second electrode is electrically connected to the second connection electrode layer at the tip portion.

10. The display panel according to claim 8, wherein: The display panel further includes: a first partition pattern; a second partition pattern; and A third partition pattern, wherein The first separation pattern and the second connection electrode layer include the same material, The second partition pattern and the intermediate layer include the same material, The third partition pattern and the second electrode include the same material, and The first partition pattern, the second partition pattern, and the third partition pattern are disposed in the groove.

11. The display panel according to claim 10, wherein: The first dividing pattern is electrically connected to the third dividing pattern.

12. The display panel according to claim 1, wherein: The connection electrode includes a first connection electrode layer disposed on the pixel defining layer, and The intermediate layer covers the first connecting electrode layer.

13. The display panel according to claim 12, wherein: The display panel further includes: a first partition pattern; and The second partition pattern, wherein The first partition pattern and the intermediate layer include the same material, The second partition pattern and the second electrode include the same material, and The first partition pattern and the second partition pattern are disposed in the groove.

14. The display panel according to claim 1, wherein: The pixel defining layer comprises: a first pixel defining layer portion; and A second pixel defining layer portion is disposed on the first pixel defining layer portion, the first pixel defining layer portion is integrated with the second pixel defining layer portion, and the groove is defined in the second pixel defining layer portion.

15. A display panel, wherein: The display panel comprises: A driving element layer, including a pixel driving unit; A light emitting element is disposed on the driving element layer, and the light emitting element includes: a first electrode; an intermediate layer, disposed on the first electrode; and A second electrode is disposed on the intermediate layer; a pixel defining layer disposed on the driving element layer, wherein the pixel defining layer includes a groove formed by removing a portion of the pixel defining layer in a thickness direction of the pixel defining layer; and A connection electrode is disposed on the pixel defining layer, and includes a tip portion protruding from an end of the groove.

16. The display panel according to claim 15, wherein: The pixel defining layer further includes a light emitting opening exposing at least a portion of the first electrode, and The groove surrounds the light emitting opening.

17. The display panel according to claim 15, wherein: The connecting electrode electrically connects the pixel driving unit to the second electrode, and The second electrode is electrically connected to the connection electrode at the tip portion.

18. The display panel according to claim 15, wherein: defining a through hole through the pixel defining layer, and The connection electrode is electrically connected to the pixel driving section through the through hole.

19. The display panel according to claim 15, wherein: The light emitting element comprises a plurality of light emitting elements, The pixel driving unit includes a plurality of pixel driving units. The connecting electrode comprises a plurality of connecting electrodes, The plurality of connection electrodes electrically connect the plurality of light emitting elements to the plurality of pixel driving units, respectively, and A gap between mutually adjacent connection electrodes among the plurality of connection electrodes overlaps the groove.

20. The display panel according to claim 15, wherein: The connecting electrode comprises: first edge; and a second edge surrounding said first edge, and The second edge overlaps the groove.

21. The display panel according to claim 15, wherein: The connecting electrode comprises: A first connection electrode layer is disposed on the pixel defining layer; and a second connection electrode layer, arranged on the first connection electrode layer; The second connection electrode layer covers the first connection electrode layer, and The second electrode is electrically connected to the second connection electrode layer at the tip portion.

22. The display panel according to claim 21, wherein: The display panel further includes: a first partition pattern; a second partition pattern; and A third partition pattern, wherein The first separation pattern and the second connection electrode layer include the same material, The second partition pattern and the intermediate layer include the same material, The third partition pattern and the second electrode include the same material, The first partition pattern, the second partition pattern, and the third partition pattern are disposed in the groove, and The first dividing pattern is electrically connected to the third dividing pattern.

23. The display panel according to claim 15, wherein: The connection electrode includes a first connection electrode layer disposed on the pixel defining layer, and The intermediate layer covers the first connecting electrode layer.

24. The display panel according to claim 23, wherein: The display panel further includes: a first partition pattern; and The second partition pattern, wherein The first partition pattern and the intermediate layer include the same material, The second partition pattern and the second electrode include the same material, and The first partition pattern and the second partition pattern are disposed in the groove.

25. The display panel according to claim 15, wherein: The pixel defining layer comprises: a first pixel defining layer portion; and A second pixel defining layer portion is disposed on the first pixel defining layer portion, the first pixel defining layer portion is integrated with the second pixel defining layer portion, and the groove is defined in the second pixel defining layer portion.

26. A method for manufacturing a display panel, wherein: The method comprises: A preliminary display panel is prepared, the preliminary display panel comprising: Base layer; a driving element layer, disposed on the base layer; and A pixel defining layer, disposed on the driving element layer; depositing a first connection electrode layer on the preliminary display panel; etching a portion of the first connection electrode layer and a portion of the pixel defining layer to form a groove in the pixel defining layer that overlaps at least a portion of the first connection electrode layer; etching the first connection electrode layer to form a connection electrode; and An intermediate layer and a cathode are formed on the connection electrode and the pixel defining layer.

27. The method according to claim 26, wherein: The method further comprises: A tip portion is formed at an end portion of the first connection electrode layer.

28. The method according to claim 26, wherein: The method further comprises: depositing a second connection electrode layer on the first connection electrode layer; and forming a tip portion at an end portion of the first connection electrode layer and an end portion of the second connection electrode layer, Wherein, forming the connecting electrode includes etching the second connecting electrode layer.

29. The method according to claim 26, wherein: The pixel defining layer comprises: a first pixel defining layer portion; and A second pixel defining layer portion is disposed on the first pixel defining layer portion, the first pixel defining layer portion is integrated with the second pixel defining layer portion, and the groove is defined in the second pixel defining layer portion.

Images